Submicron grid electrode etching method based on etching compensation and power modulation
By combining a two-step etching method with initial linewidth compensation of photoresist lines, precise control and low damage of submicron gates are achieved, solving the problems of etching accuracy and damage in existing etching schemes, and improving device performance and process stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2026-01-30
- Publication Date
- 2026-05-08
AI Technical Summary
Existing etching methods are difficult to achieve precise pattern transfer of submicron gates, and high-energy ion bombardment causes device performance damage, resulting in poor process repeatability and stability.
A two-step etching method is adopted. First, the main groove shape is formed by rapid etching at high power, and then fine trimming is performed at low power. Combined with the initial linewidth compensation of the photoresist lines to compensate for the outward expansion, the submicron gate can be precisely controlled and damage reduced.
Precise control of the submicron gate was achieved, reducing damage to the barrier layer and channel, improving the device's saturation output current and RF performance, and enhancing process repeatability and stability.
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Figure CN122002876A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor process technology, specifically relating to a submicron gate etching method based on etch compensation and power modulation. Background Technology
[0002] With the rapid development of fifth-generation (5G) and future wireless communication technologies toward millimeter-wave bands (such as Ka-band and Q-band), the performance requirements for core radio frequency power devices are becoming increasingly stringent.
[0003] Gallium nitride high electron mobility transistors (GaN HEMTs) are core components of high-power devices in the millimeter-wave band due to their excellent wide bandgap characteristics, such as high breakdown electric field, high electron saturation velocity, and outstanding thermal stability. The frequency characteristics of these devices are closely related to the gate length; the shorter the gate length, the higher the cutoff frequency. Therefore, achieving submicron gates of 0.1 micrometers and below is a key technology for millimeter-wave GaN devices.
[0004] GaN and AlGaN surfaces contain numerous surface states, such as dangling bonds and defects. When devices operate under high-voltage (high-drain-voltage) switching conditions, these surface states trap electrons in the channel, forming dummy gates. This depletes the underlying two-dimensional electron gas (2DEG), leading to a sharp increase in on-resistance and a decrease in output current—a phenomenon known as current collapse. Silicon nitride (SiN) passivation dielectric layers passivate the dangling bonds on the GaN surface through chemical bonds (primarily Si-N bonds), significantly reducing the surface state density. This prevents electrons from being trapped by surface states, greatly mitigating current collapse and ensuring the dynamic performance and output power of the device under high-frequency, high-power switching conditions. Based on this passivation scheme, the passivation dielectric layer needs to be etched to fabricate gate trenches, providing the necessary conditions for subsequent gate metal fabrication.
[0005] Currently, there are two main etching methods for forming gate trenches: Option 1 employs a fixed-parameter F-based plasma etching process. This approach typically sets a fixed set of parameters, including RF source power, RF bias power, chamber pressure, and gas flow rate, for a single etching process. For example, using a higher bias power (e.g., 200 watts or more) can ensure etching perpendicularity, but this can exacerbate plasma damage; conversely, using a lower power can mitigate damage, but this can lead to problems such as excessively slow etching rates, poor anisotropy, and undesirable sidewall morphology.
[0006] Option two employs atomic layer etching (ALE). Through self-limiting surface reactions, such as modification-removal cycles, atomic-level precision etching and extremely low damage are achieved. ALE is considered the ultimate solution for achieving ultra-low damage, nanometer-level precision gate trench etching, but it faces challenges such as complex processes, demanding equipment, and slow etching rates.
[0007] However, existing etching methods have the following drawbacks: due to the significant lateral etching caused by fixed low-power etching, the difference between the lithographic line size and the final gate size, i.e., the etching outward expansion, is large, making it impossible to achieve precise pattern transfer of submicron gates and resulting in inaccurate size control; high-energy ions continuously bombard the bottom of the gate trench, causing irreversible damage to the underlying AlGaN barrier layer and two-dimensional electron gas channel, thus degrading device performance; in order to balance etching rate and damage, a single parameter set needs to be precisely optimized, resulting in small process tolerance, poor repeatability, and poor stability; although ALE etching has a slow etching rate and can achieve lower damage, it has high time costs and low process efficiency for etching the passivation dielectric layer. Summary of the Invention
[0008] To address the aforementioned problems in the prior art, this invention provides a submicron gate etching method based on etch compensation and power modulation. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a submicron gate etching method based on etching compensation and power modulation, comprising the following steps: A sample is provided, the sample comprising a passivation dielectric layer and photoresist located on the passivation dielectric layer; The photoresist in the gate region is patterned to form photoresist lines, wherein the initial linewidth of the photoresist lines is smaller than the length of the target gate. Under the first etching parameters, the passivation dielectric layer of the gate region is etched in the first stage using the photoresist lines, etching to the interior of the passivation dielectric layer; Under the second etching parameters, the passivation dielectric layer of the gate region is further etched in a second stage until a submicron-level gate trench is formed. The etching power in the second etching parameters is less than the etching power in the first etching parameters, and the length of the gate trench is equal to the length of the target gate.
[0009] In one embodiment of the present invention, the sample further includes a substrate and a heterojunction structure, wherein the heterojunction structure, the passivation dielectric layer and the photoresist are sequentially stacked on the substrate.
[0010] In one embodiment of the present invention, the method for determining the initial linewidth of the photoresist lines is as follows: An experimental sample is provided, the experimental sample comprising an experimental passivation dielectric layer and an experimental photoresist located on the experimental passivation dielectric layer; An electron beam lithography machine is used to expose experimental photoresist to form a photoresist line group. Several lines in the photoresist line group have different line widths, and some of them have line widths that are less than, greater than, or equal to the target gate. Under the first etching parameters, the photoresist line group is used to etch the experimental passivation medium layer, and a number of etching lines are formed in the experimental passivation medium layer under the same etching target depth and the same etching time. The actual width of the etched lines is measured, and the line width of the photoresist line with the same width as the length of the target gate is selected as the initial line width.
[0011] In one embodiment of the present invention, the length of the target gate is 95-105 nm, and correspondingly, the initial linewidth is 70-80 nm.
[0012] In one embodiment of the present invention, the etching power in the first etching parameter is 200-1000W.
[0013] In one embodiment of the present invention, the first etching parameters include: upper electrode power of 250W, lower electrode power of 40W, CF4 gas flow rate of 50sccm, and chamber pressure of 5mT.
[0014] In one embodiment of the present invention, the etching power in the second etching parameter is 50-100W.
[0015] In one embodiment of the present invention, the second etching parameters include: upper electrode power of 80W, lower electrode power of 10W, CF4 gas flow rate of 50sccm, and chamber pressure of 5mT.
[0016] In one embodiment of the present invention, the depth ratio of the first stage etching to the second stage etching is 9:1.
[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention sets the initial linewidth of the photoresist lines to be smaller than the length of the target gate, which can optimally compensate for the outward expansion in subsequent etching steps; the etching power of the second stage is set to be lower than that of the first stage. The high-power etching provides strong ion-directed bombardment, with good anisotropy, which can quickly and vertically etch away most of the gate trench depth to form the main trench shape. The low-power etching effectively repairs the plasma damage caused by the high-power stage, significantly reducing the damage to the barrier layer and the two-dimensional electron gas in the channel, thereby potentially improving the saturated output current, transconductance, and RF performance of the device and mitigating the current collapse effect; through the combination of etching compensation and high-power rapid prototyping with low-power fine trimming, the actual size of the submicron gate is effectively controlled, achieving precise control of the submicron gate size with minimal damage to the barrier layer, high pattern fidelity, and simultaneously achieving high precision and low damage; 2. The method of the present invention is based on conventional ICP etching equipment, without the need to introduce special hardware, and is easy to implement and integrate into existing processes. The two-step strategy expands the process window, improves process repeatability and stability, and has good process compatibility. Attached Figure Description
[0018] Figure 1 A schematic flowchart of a submicron gate etching method based on etching compensation and power modulation is provided for an embodiment of the present invention. Figures 2a-2d A schematic diagram illustrating a submicron gate etching method based on etching compensation and power modulation, provided in an embodiment of the present invention; Figures 3a-3b This is a comparison diagram of the surface roughness of the barrier layer in the gate trench prepared by the etching method of this invention and the conventional method. Detailed Implementation
[0019] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0020] Example 1 The present invention aims to solve the problems of etching accuracy and device performance damage when using inductively coupled plasma (ICP) etching machines to fabricate submicron (e.g., 0.1 micron) gates for GaN HEMTs.
[0021] Please see Figure 1 and Figures 2a-2d , Figure 1 This is a schematic flowchart of a submicron gate etching method based on etch compensation and power modulation, provided in an embodiment of the present invention. Figures 2a-2d This is a schematic diagram illustrating a submicron gate etching method based on etch compensation and power modulation, provided in an embodiment of the present invention. This etching method, through etch compensation and power modulation strategies, simultaneously achieves high-precision (minimizing etch spread) and low-damage (protective barrier layer) GaN HEMT submicron gate fabrication without sacrificing the etch rate. The specific steps include: S1. Provide a sample, which includes a passivation dielectric layer and photoresist on the passivation dielectric layer.
[0022] In one specific embodiment, the sample includes a substrate, a heterojunction structure, a passivation dielectric layer PL, and photoresist. The heterojunction structure, the passivation dielectric layer PL, and the photoresist are sequentially stacked on the substrate. The heterojunction structure includes an AlGaN / GaN heterojunction epitaxial layer formed by a GaN channel layer and an AlGaN barrier layer, such as... Figure 2a As shown. In other embodiments, the sample can also be other GaN HEMT structures including a passivation dielectric layer and photoresist.
[0023] S2. Pattern the photoresist in the gate region to form photoresist lines, such as... Figure 2b As shown in the figure. The initial linewidth of the photoresist lines is smaller than the length of the target gate.
[0024] Specifically, the initial linewidth of the photoresist lines is determined through single-step process experiments. The determination method is as follows: An experimental sample is provided, comprising an experimental passivation dielectric layer and experimental photoresist on the experimental passivation dielectric layer. An electron beam lithography machine is used to expose the experimental photoresist to form a photoresist line group. Several lines in the photoresist line group have different linewidths, including those less than, greater than, and equal to the target gate linewidth. Under the first etching parameters, the photoresist line group is used to etch the experimental passivation dielectric layer, forming several etched lines in the experimental passivation dielectric layer at the same etching target depth and the same etching time. The actual width of several etched lines is measured, and the linewidth of the photoresist line with the same width as the target gate length is selected as the initial linewidth.
[0025] Taking a target gate length of 100nm as an example, the method for determining the initial linewidth of the photoresist lines includes: using an electron beam lithography machine to expose the experimental photoresist on the experimental passivation dielectric layer to form a group of photoresist lines ranging from 60nm to 150nm; under the first etching parameters, using ICP etching to etch a 120nm thick silicon nitride passivation dielectric layer, forming several etch lines in the experimental passivation dielectric layer under the same etching target depth and the same etching time; using AFM to measure the actual width of several etch lines, obtaining the etching expansion of different submicron gates under the first etching parameters. By comparison, it was found that when the width of the photoresist lines is 70-80nm, the actual width of the etch lines corresponds to 95-105nm, which is basically consistent with the target gate size of 100nm. Therefore, the 70-80nm photoresist linewidth can optimally compensate for the expansion in subsequent etching steps.
[0026] S3. Under the first etching parameters, the passivation dielectric layer PL in the gate region is etched in the first stage using photoresist lines, etching down to the interior of the passivation dielectric layer PL, such as... Figure 2c As shown.
[0027] Specifically, within the etching chamber, the first stage of high-power main etching is performed using the first etching parameters. The core of this stage is high radio frequency (RF) bias power, supplemented by appropriate pressure and gas flow rate; here, RF bias power refers to the upper electrode power, for example, 200-1000W. The purpose of this stage is to rapidly and vertically etch away most of the gate trench depth, etching into the interior of the passivation dielectric layer PL, forming the main trench shape. Because the high bias provides strong ion-directed bombardment, the etching anisotropy is good, but the etching damage at the bottom is greater.
[0028] In one specific embodiment, the etching power (upper electrode power) in the first etching parameters is 200-1000W. For example, the first etching parameters include: upper electrode power of 250W, lower electrode power of 40W, CF4 gas flow rate of 50 sccm, and chamber pressure of 5 mT.
[0029] S4. Under the second etching parameters, the passivation dielectric layer PL in the gate region continues to be etched in the second stage until a submicron-level gate trench is formed, such as... Figure 2d As shown, the etching power in the second etching parameter is less than the etching power in the first etching parameter, and the length of the gate trench is equal to the length of the target gate.
[0030] Specifically, without interrupting the process, when the depth of the first-stage etching reaches 90% of the target depth (i.e., the ratio of the first-stage etching depth to the second-stage etching depth is 9:1), the etching parameters are immediately switched to the second etching parameters for low-power fine etching until a submicron-level gate trench is formed. The core of this stage is to significantly reduce the RF bias power (e.g., reducing the upper electrode power to 50-100W), while fine-tuning other parameters, such as appropriately reducing the lower electrode power, to perform low-damage etching on the remaining passivation dielectric layer PL. This low-power, gentle etching allows for low-damage etching of the remaining passivation dielectric layer PL, thus reducing barrier damage.
[0031] In one specific embodiment, the etching power (upper electrode power) in the second etching parameters is 50-100W. For example, the second etching parameters include: upper electrode power of 80W, lower electrode power of 10W, CF4 gas flow rate of 50 sccm, and chamber pressure of 5 mT.
[0032] This embodiment decomposes the etching process into two stages with different functions and parameters, and matches them with the initial width of the specific photoresist lines. Finally, based on the etching compensation to obtain a precise submicron gate length, it can ensure that the outward expansion is reduced to improve process efficiency and that there is low damage to the barrier layer surface. In the end, a high-quality gate with precise dimensions and minimal damage to the barrier layer is prepared.
[0033] This embodiment implements the above method on an ICP etching machine from Naura Technology Group, using CF4 etching gas, and ultimately obtains a gate trench with good flatness. Please refer to [link to documentation]. Figures 3a-3b , Figures 3a-3b This is a comparison diagram of the surface roughness of the barrier layer in the gate trench prepared by the etching method of this invention and the conventional method. Figure 3a The etching method of this invention includes the following etching parameters: the first stage etching parameters are: the upper electrode power is 250W and the lower electrode power is 40W; the second etching parameters include: the upper electrode power is 80W and the lower electrode power is 10W. Figure 3bThe traditional etching method uses an upper electrode power of 250W and a lower electrode power of 40W. The barrier layer surface produced by this method has numerous particles and poor flatness, with a root mean square surface roughness of 0.657. In contrast, the barrier layer surface produced by this invention exhibits significantly better flatness, with a root mean square surface roughness as low as 0.173.
[0034] In this embodiment, the initial linewidth of the photoresist lines is set to be smaller than the length of the target gate, which can optimally compensate for the outward expansion in subsequent etching steps. The etching power of the second stage is set to be lower than that of the first stage. The high-power etching provides strong ion-directed bombardment, with good anisotropy, which can quickly and vertically etch away most of the gate trench depth to form the main trench shape. The low-power etching effectively repairs the plasma damage caused by the high-power stage, significantly reducing the damage to the barrier layer and the two-dimensional electron gas in the channel. This is expected to improve the saturated output current, transconductance, and RF performance of the device and mitigate the current collapse effect. Through the combination of etching compensation and high-power rapid prototyping with low-power fine trimming, the actual size of the submicron gate is effectively controlled, achieving precise control of the submicron gate size with minimal damage to the barrier layer and high pattern fidelity, simultaneously achieving high precision and low damage.
[0035] The method in this embodiment is based on conventional ICP etching equipment, requiring no special hardware, and is easy to implement and integrate into existing processes. The two-step strategy expands the process window, improves process repeatability and stability, and has good process compatibility.
[0036] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A submicron gate etching method based on etch compensation and power modulation, characterized in that, Including the following steps: A sample is provided, the sample comprising a passivation dielectric layer and photoresist located on the passivation dielectric layer; The photoresist in the gate region is patterned to form photoresist lines, wherein the initial linewidth of the photoresist lines is smaller than the length of the target gate. Under the first etching parameters, the passivation dielectric layer of the gate region is etched in the first stage using the photoresist lines, etching to the interior of the passivation dielectric layer; Under the second etching parameters, the passivation dielectric layer of the gate region is further etched in a second stage until a submicron-level gate trench is formed. The etching power in the second etching parameters is less than the etching power in the first etching parameters, and the length of the gate trench is equal to the length of the target gate.
2. The submicron gate etching method based on etch compensation and power modulation according to claim 1, characterized in that, The sample also includes a substrate and a heterojunction structure, wherein the heterojunction structure, the passivation dielectric layer, and the photoresist are sequentially stacked on the substrate.
3. The submicron gate etching method based on etch compensation and power modulation according to claim 1, characterized in that, The method for determining the initial linewidth of the photoresist lines is as follows: An experimental sample is provided, the experimental sample comprising an experimental passivation dielectric layer and an experimental photoresist located on the experimental passivation dielectric layer; An electron beam lithography machine is used to expose experimental photoresist to form a photoresist line group. Several lines in the photoresist line group have different line widths, and some of them have line widths that are less than, greater than, or equal to the target gate. Under the first etching parameters, the photoresist line group is used to etch the experimental passivation medium layer, and a number of etching lines are formed in the experimental passivation medium layer under the same etching target depth and the same etching time. The actual width of the etched lines is measured, and the line width of the photoresist line with the same width as the length of the target gate is selected as the initial line width.
4. The submicron gate etching method based on etch compensation and power modulation according to claim 1, characterized in that, The target gate has a length of 95-105 nm, and the corresponding initial linewidth is 70-80 nm.
5. The submicron gate etching method based on etch compensation and power modulation according to claim 1, characterized in that, The etching power in the first etching parameter is 200-1000W.
6. The submicron gate etching method based on etch compensation and power modulation according to claim 5, characterized in that, The first etching parameters include: upper electrode power of 250W, lower electrode power of 40W, CF4 gas flow rate of 50sccm, and chamber pressure of 5mT.
7. The submicron gate etching method based on etch compensation and power modulation according to claim 1, characterized in that, The etching power in the second etching parameter is 50-100W.
8. The submicron gate etching method based on etch compensation and power modulation according to claim 7, characterized in that, The second etching parameters include: upper electrode power of 80W, lower electrode power of 10W, CF4 gas flow rate of 50sccm, and chamber pressure of 5mT.
9. The submicron gate etching method based on etch compensation and power modulation according to claim 1, characterized in that, The depth ratio of the first stage etching to the second stage etching is 9:1.