Manufacturing method of backside illuminated image sensor

Abstract

The invention provides a manufacturing method of a back-illuminated image sensor, which comprises the following steps of: sequentially etching a dielectric layer exposed in a first opening and a substrate at the bottom of the first opening by taking a patterned first photoresist layer as a mask to form a second opening, and etching the dielectric layer in an exposed logic region to form a grounding hole, the second opening (the growth window used for forming the metal bonding pad) and the grounding hole are formed in the same etching step, that is, the second opening and the grounding hole can be formed through one layer of mask, so that two layers of masks are saved, the number of masks in the forming process of the metal bonding pad and the grounding structure is reduced, and the process cost is reduced. Correspondingly, the metal bonding pad and the grounding structure can be formed in the same process step, so that the process steps are reduced, and the process cost is further reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a back-illuminated image sensor. Background Technology

[0002] CMOS (Complementary Metal Oxide Semiconductor) image sensors convert optical signals into electrical signals, which are then further converted into digital signals via readout circuitry. In existing back-illuminated image sensors, metal pads need to be formed in the substrate of the input / output area to achieve electrical connections between the metal interconnect structures, and ground via structures need to be formed in the substrate of the logic area to electrically connect the metal grid to the substrate, thereby achieving grounding. However, in the process of forming metal pads and ground via structures, a first mask is typically used to form metal pad openings (growth windows for metal pad formation) in the substrate of the input / output region. Then, a metal material layer is deposited and etched to form metal pads within the openings. Next, a protective layer (e.g., silicon oxide) is deposited, covering the metal pads and the substrate of the logic region. Due to the presence of the metal pad openings, the thickness difference on the protective layer surface is significant. Therefore, a second mask is needed to thin the protective layer on the substrate to facilitate subsequent chemical mechanical polishing (CMP) processes. Next, CMP is performed on the protective layer. Then, a third mask is used to form ground vias in the protective layer above the logic region substrate. Finally, a metal material layer is deposited in the ground vias and etched to form a ground structure. This manufacturing method requires three masks to form the metal pad openings and ground vias, making the process complex and costly. Summary of the Invention

[0003] The purpose of this invention is to provide a method for manufacturing a back-illuminated image sensor to reduce the masking required during the formation of metal pads and grounding structures.

[0004] To achieve the above objectives, the present invention provides a method for manufacturing a back-illuminated image sensor, comprising:

[0005] A substrate is provided having an input / output region, a logic region, and a pixel region, the logic region being located between the input / output region and the pixel region, and a metal interconnect structure being formed in the substrate of the input / output region, wherein the substrate of the input / output region has a first opening, the first opening being located above the metal interconnect structure;

[0006] A dielectric layer is formed, which covers the sidewalls and bottom of the first opening and the substrate;

[0007] A patterned first photoresist layer is formed on the dielectric layer, the patterned first photoresist layer exposing the dielectric layer at the bottom of the first opening and a portion of the dielectric layer on the logic region;

[0008] Using the patterned first photoresist layer as a mask, the dielectric layer exposed in the first opening and the substrate at the bottom of the first opening are sequentially etched to form a second opening. The second opening exposes a portion of the metal interconnect structure, and the dielectric layer of the exposed logic region is etched to form a ground hole. The ground hole exposes a portion of the substrate of the logic region.

[0009] Remove the patterned first photoresist layer;

[0010] A metal pad and a grounding structure are formed, wherein the metal pad fills the second opening and a portion of the first opening and is electrically connected to the metal interconnect structure, and the grounding structure fills the grounding hole and is electrically connected to the substrate.

[0011] Optionally, the method for forming the metal pads and the grounding structure includes:

[0012] A first metal material layer and a second metal material layer are formed sequentially. The first metal material layer covers the sidewalls and bottom of the first opening, the sidewalls of the second opening, and the sidewalls and bottom of the grounding hole, and covers the substrate. The second metal material layer covers the first metal material layer.

[0013] The second metal material layer in the first opening is etched to form the metal pad, the sidewall of the metal pad is spaced from the first metal material layer in the sidewall of the first opening, and the second metal material layer on the substrate is removed while the second metal material layer in the grounding hole is retained to form the grounding structure.

[0014] Optionally, the method for etching the second metal material layer in the first opening and removing the second metal material layer on the substrate includes:

[0015] A patterned second photoresist layer is formed on the second metal material layer, the patterned second photoresist layer exposing a portion of the second metal material layer in the first opening and exposing the second metal material layer on the substrate;

[0016] Using the patterned second photoresist layer as a mask, a dry etching process is employed to etch the second metal material layer exposed in the first opening, and the second metal material layer on the substrate is removed; and,

[0017] Remove the patterned second photoresist layer.

[0018] Optionally, the first metal material layer is made of tungsten, the second metal material layer is made of aluminum, and the dielectric layer is made of silicon oxide.

[0019] Optionally, after forming the metal pads and the grounding structure, the method for manufacturing the back-illuminated image sensor further includes:

[0020] The first metal material layer on the substrate of the logic region is etched to form a first metal grid, and the first metal material layer on the substrate of the pixel region is etched to form a second metal grid, and the first metal material layer on the substrate of the input / output region is removed, wherein the grounding structure is electrically connected to the substrate through the first metal grid.

[0021] Optionally, the method for etching the first metal material layer includes:

[0022] A hard mask layer is formed, which covers the first metal material layer, the metal pads, and the grounding structure;

[0023] A patterned third photoresist layer is formed on the hard mask layer, the patterned third photoresist layer exposing a portion of the hard mask layer in the pixel area and the hard mask layer on the substrate in the input / output area;

[0024] Using the patterned third photoresist layer as a mask, the hard mask layer is etched to form a patterned hard mask layer. The patterned hard mask layer exposes a portion of the first metal material layer in the pixel area and exposes the first metal material layer on the substrate of the input / output area.

[0025] Using the patterned third photoresist layer and the patterned hard mask layer as masks, the exposed first metal material layer is etched using a dry etching process to form the first metal grid and the second metal grid, and the first metal material layer on the substrate of the input / output area is removed; and the patterned third photoresist layer is removed.

[0026] Optionally, a deep trench isolation structure is formed in the substrate of the pixel region, the dielectric layer covers the deep trench isolation structure, and the second metal grid is located above the deep trench isolation structure.

[0027] Optionally, after forming the first metal grid and the second metal grid, the method for manufacturing the back-illuminated image sensor further includes:

[0028] A patterned fourth photoresist layer is formed, the patterned photoresist layer exposing the patterned hard mask layer on the metal pads;

[0029] Using the patterned fourth photoresist layer as a mask, the exposed patterned hard mask layer is etched to expose the top surface of the metal pads; and,

[0030] Remove the patterned fourth photoresist layer.

[0031] Optionally, the dielectric layer may be etched using a dry etching process.

[0032] Optionally, the substrate includes a support substrate, an interlayer dielectric layer, and a device substrate stacked sequentially from bottom to top. The metal interconnect structure is formed in the interlayer dielectric layer. The device substrate has a first surface and a second surface disposed opposite to each other. The interlayer dielectric layer is formed on the second surface of the device substrate. The dielectric layer is formed on the first surface of the device substrate. The first opening is formed in the device substrate and penetrates the device substrate.

[0033] In the manufacturing method of the back-illuminated image sensor provided by this invention, a second opening is formed by sequentially etching the dielectric layer exposed in the first opening and the substrate at the bottom of the first opening using a patterned first photoresist layer as a mask, and then etching the dielectric layer of the exposed logic region to form a grounding via. That is, the second opening (the growth window for forming the metal pad) and the grounding via are formed in the same etching step. In other words, the second opening and the grounding via can be formed with a single mask, thus saving two mask layers and reducing the number of masks required in the formation of the metal pad and grounding structure, thereby reducing process costs. Correspondingly, the metal pad and grounding structure can be formed in the same process step, thereby reducing process steps and further reducing process costs. Attached Figure Description

[0034] Figure 1 This is a schematic flowchart of the manufacturing method of the back-illuminated image sensor provided in an embodiment of the present invention;

[0035] Figures 2 to 12 This is a schematic diagram of the structure formed in the manufacturing method of the back-illuminated image sensor provided in the embodiment of the present invention;

[0036] The reference numerals in the attached figures are explained as follows:

[0037] 100 - Substrate; 100A - Input / output area; 100B - Logic area; 100C - Pixel area; 101 - Supporting substrate; 102 - Interlayer dielectric layer; 103 - Device substrate; 104 - Metal interconnect structure; 105 - Deep trench isolation structure;

[0038] 110 - First opening;

[0039] 120 - Dielectric layer; 121 - Second opening;

[0040] 130 - Patterned first photoresist layer;

[0041] 140 - Grounding hole;

[0042] 150 - First metal material layer; 151 - First metal grid; 152 - Second metal grid;

[0043] 160 - Second metal material layer; 161 - Metal pad; 162 - Grounding structure;

[0044] 170 - Hard mask layer; 171 - Patterned hard mask layer. Detailed Implementation

[0045] The manufacturing method of the back-illuminated image sensor proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0046] Figure 1 This is a schematic flowchart of the manufacturing method of the back-illuminated image sensor provided in an embodiment of the present invention.

[0047] like Figure 1 As shown, the manufacturing method of the back-illuminated image sensor provided in this embodiment includes:

[0048] Step S1: Provide a substrate having an input / output area, a logic area, and a pixel area, wherein the logic area is located between the input / output area and the pixel area, and a metal interconnect structure is formed in the substrate of the input / output area, wherein the substrate of the input / output area has a first opening, and the first opening is located above the metal interconnect structure;

[0049] Step S2: Form a dielectric layer that covers the sidewalls and bottom of the first opening and covers the substrate;

[0050] Step S3: A patterned first photoresist layer is formed on the dielectric layer, the patterned first photoresist layer exposing the dielectric layer at the bottom of the first opening and a portion of the dielectric layer on the logic region;

[0051] Step S4: Using the patterned first photoresist layer as a mask, the dielectric layer exposed in the first opening and the substrate at the bottom of the first opening are etched sequentially to form a second opening. The second opening exposes a portion of the metal interconnect structure, and the dielectric layer of the exposed logic region is etched to form a ground hole. The ground hole exposes a portion of the substrate of the logic region.

[0052] Step S5: Remove the patterned first photoresist layer;

[0053] Step S6: Form a metal pad and a grounding structure, wherein the metal pad fills the second opening and part of the first opening and is electrically connected to the metal interconnect structure, and the grounding structure fills the grounding hole and is electrically connected to the substrate.

[0054] Figures 2 to 12 This is a schematic diagram of the structure formed in the manufacturing method of the back-illuminated image sensor provided in the embodiment of the present invention. The following will be combined with... Figures 2 to 12 The manufacturing method of the back-illuminated image sensor provided in this embodiment will be described in more detail.

[0055] refer to Figure 2 As shown, in step S1, a substrate 100 is provided, the substrate 100 having an input / output area 100A, a logic area 100B and a pixel area 100C, the logic area 100B being located between the input / output area 100A and the pixel area 100C, a metal interconnect structure 104 being formed in the substrate 100 of the input / output area 100A, wherein the substrate 100 of the input / output area 100A has a first opening 110, the first opening 110 being located above the metal interconnect structure 104.

[0056] Specifically, the substrate 100 includes a support substrate 101, an interlayer dielectric layer 102, and a device substrate 103 stacked sequentially from bottom to top. The support substrate 101 and the device substrate 103 can be any suitable substrate material known to those skilled in the art for fabricating image sensors, such as semiconductor materials like Si, SiGe, SiGeC, SiC, GaAs, InAs, or InP. In this embodiment, both the support substrate 101 and the device substrate 103 are made of silicon. The support substrate 101 and the device substrate 103 are bonded together using a bonding process.

[0057] like Figure 2As shown, the metal interconnect structure 104 is formed within the interlayer dielectric layer 102, meaning the metal interconnect structure 104 is buried within the interlayer dielectric layer 102. The interlayer dielectric layer 102 can be a single-layer structure or a multilayer film stacked structure. In some exemplary embodiments, the material of the interlayer dielectric layer 102 may include at least one of a low-k dielectric material, a high-k dielectric material, silicon oxide, and silicon nitride. The low-k dielectric material has a k value below 3.0, and the high-k dielectric material has a k value greater than 7.0.

[0058] The device substrate 103 has a first surface and a second surface disposed opposite to each other, and the interlayer dielectric layer 102 is formed on the second surface of the device substrate 103. The second surface of the device substrate 103 also forms a photodiode array (not shown) located in the pixel region 100C, and the interlayer dielectric layer 102 also buries the photodiode array therein.

[0059] In this embodiment, a deep trench isolation structure 105 is formed in the substrate 100 of the pixel region 100C. The deep trench isolation structure 105 can block electronic crosstalk generated between subsequently formed metal grids. Specifically, the deep trench isolation structure 105 extends from the first surface of the device substrate 103 in the substrate 100 into the device substrate 103. The top surface of the deep trench isolation structure 105 can be flush with the first surface of the device substrate 103, or the top surface of the deep trench isolation structure 105 can be higher than the first surface of the device substrate 103. In this embodiment, the example of the top surface of the deep trench isolation structure 105 being higher than the first surface of the device substrate 103 is used for illustration.

[0060] Specifically, the method for forming the deep trench isolation structure 105 includes: first, forming a patterned mask layer on the substrate 100, the patterned mask layer exposing the area on the substrate 100 of the pixel region 100C where the deep trench isolation structure 105 is to be formed, wherein the patterned mask layer can be a patterned photoresist layer; then, etching the exposed substrate 100 of the pixel region 100C using the patterned mask layer as a mask to form a deep trench; next, sequentially filling the deep trench with a high dielectric constant material layer and a protective layer to form the deep trench isolation structure 105. The high dielectric constant material layer can be, for example, hafnium oxide, aluminum oxide, or tantalum oxide, and can be formed using chemical vapor deposition (CVD) or physical vapor deposition (PVD). The protective layer contains silicon oxide and can be formed using chemical vapor deposition.

[0061] Next, as Figure 2As shown, a first opening 110 is formed in the substrate 100 of the input / output region 100A, and the first opening 110 is located above the metal interconnect structure 104. Exemplarily, firstly, a patterned photoresist layer is formed on the substrate 100 (i.e., the second surface of the device substrate 103), exposing the area in the substrate 100 of the input / output region 100A where metal pads 161 are predetermined to be formed; then, using the patterned photoresist layer as a mask, a dry etching process is employed to etch the exposed substrate 100 to form the first opening 110; subsequently, the patterned photoresist layer is removed.

[0062] Next, proceed to step S2, referring to... Figure 3 As shown, a dielectric layer 120 is formed, which covers the sidewalls and bottom of the first opening 110 and the substrate 100. The dielectric layer 120 also covers the deep trench isolation structure 105.

[0063] In this embodiment, the dielectric layer 120 is made of silicon oxide and can be formed by chemical vapor deposition.

[0064] Next, proceed to step S3, refer to... Figure 4 As shown, a patterned first photoresist layer 130 is formed, which exposes the dielectric layer 120 at the bottom of the first opening 110 and a portion of the dielectric layer 120 of the logic region 100B. Specifically, the patterned first photoresist layer 130 covers the top surface of the first dielectric layer 120 on the sidewall of the first opening 110, the dielectric layer 120 of the pixel region 100C, and a portion of the dielectric layer 120 of the logic region 100B. The patterned first photoresist layer 130 serves as a mask for forming the grounding via 140 and the first opening 110 during subsequent etching processes.

[0065] An exemplary method for forming a patterned first photoresist layer 130 includes: firstly, forming a photoresist layer on the dielectric layer 120; then, sequentially exposing and developing the photoresist layer to form a patterned first photoresist layer 130, the patterned first photoresist layer 130 having a first groove and a second groove, the first groove exposing the dielectric layer 120 at the bottom of the first opening 110, and the second groove exposing a portion of the dielectric layer 120 of the logic region 100B.

[0066] Next, proceed to step S4, refer to... Figure 5As shown, using the patterned first photoresist layer 130 as a mask, the dielectric layer 120 exposed in the first opening 110 and the substrate 100 at the bottom of the first opening 110 are sequentially etched to form a second opening 121. The dielectric layer 120 of the exposed logic region 100B is then etched to form a grounding via 140, which exposes a portion of the substrate 100 of the logic region 100B. The second opening 121 and the first opening 110 serve as growth windows for the subsequent formation of the metal pad 161, and the grounding via 140 serves as a growth window for the subsequent formation of the grounding structure 162.

[0067] Specifically, a dry etching process can be used to sequentially etch the dielectric layer 120 exposed in the first opening 110 and the substrate 100 at the bottom of the first opening 110 to form the second opening 121. The width of the second opening 121 is smaller than the width of the first opening 110 to reduce the contact area between the first metal material layer 150 subsequently filled in the second opening 121 and adjacent components or the first metal material layer 150 filled in the first opening 110, thereby reducing the risk of short circuits. The substrate 100 at the bottom of the first opening 110 refers to the interlayer dielectric layer 102 in the substrate 100, that is, the portion between the metal interconnect structure 104 in the interlayer dielectric layer 102 and the device substrate 103. In other words, the process of forming the second opening includes sequentially etching the dielectric layer 120 and the interlayer dielectric layer 102 at the bottom of the first opening 110 until the top surface of the metal interconnect structure 104 is exposed.

[0068] While etching the dielectric layer 120 exposed in the first opening 110 and the substrate 100 at the bottom of the first opening 110, the dielectric layer 120 of the exposed logic region 100B is also etched to form a grounding via 140. The grounding via 140 is a through-hole, meaning that the grounding via 140 penetrates the dielectric layer 120, thereby exposing a portion of the substrate 100 of the logic region 100B, specifically exposing a portion of the first surface of the device substrate 103 in the substrate 100 of the logic region 100B. Since the bottom of the grounding via 140 is the substrate 100 (specifically, the device substrate 103 within the substrate 100), there is a high etching selectivity between the device substrate 103 and the dielectric layer 120 during the etching process. Therefore, the surface of the substrate 100 (i.e., the first surface of the device substrate 103) that stops at the bottom of the grounding via 140 can be etched, thereby reducing or avoiding damage to the substrate 100.

[0069] Since the second opening 121 (the growth window for forming the metal pad 161) and the grounding hole 140 are formed in the same etching step, that is, the second opening 121 and the grounding hole 140 can be formed with just one mask (the first patterned photoresist layer). Compared with the prior art, which uses three masks to form the growth window and grounding hole of the metal pad, two masks can be saved, thereby reducing the number of masks used in the formation process of the metal pad 161 and the grounding structure 162, and thus reducing the process cost.

[0070] Next, proceed to step S5, refer to... Figure 6 As shown, the patterned first photoresist layer 130 is removed. This can be done by dry stripping, such as plasma oxidation or decomposition; or by wet stripping, such as a wet cleaning process.

[0071] In this embodiment, after the patterned first photoresist layer 130 is removed, the remaining dielectric layer 120 is exposed.

[0072] Next, proceed to step S6, refer to... Figure 8 As shown, a metal pad 161 and a ground structure 162 are formed. The metal pad 161 fills the second opening 121 and part of the first opening 110 and is electrically connected to the metal interconnect structure 104. The ground structure 162 fills the ground hole 140 and is electrically connected to the substrate 100.

[0073] Specifically, the method for forming the metal pad 161 and the grounding structure 162 includes: firstly, as... Figure 7 As shown, a first metal material layer 150 and a second metal material layer 160 are formed sequentially. The first metal material layer 150 covers the sidewalls and bottom of the first opening 110, the sidewalls of the second opening 121, and the sidewalls and bottom of the grounding via 140, and also covers the substrate 100. The second metal material layer 160 covers the first metal material layer 150. The second metal material layer 160 is used to fabricate metal pads 161 and grounding structures 162. Thus, the second metal material layer 160 used to fabricate metal pads 161 and grounding structures 162 can be deposited in the same process step, thereby simplifying the process flow and reducing the number of process steps.

[0074] Furthermore, since the second metal material layer 160 used to prepare the metal pad 161 and the ground structure 162 is in the same process step, there is no need to deposit a protective layer to cover the metal pad, and therefore no subsequent protective layer thinning and chemical mechanical polishing processes are required. Compared with the prior art method of forming the metal pad and ground structure by depositing two metal material layers separately, this embodiment can save the mask required for thinning the protective layer and reduce the number of process steps in the process of preparing the metal pad 161 and the ground structure 162, thereby further reducing the process cost.

[0075] In this embodiment, the material of the first metal material layer 150 includes tungsten, and the material of the second metal material layer 160 includes aluminum. The first metal material layer 150 and the second metal material layer 160 can be formed by physical vapor deposition.

[0076] Then, as Figure 8 As shown, the second metal material layer 160 in the first opening 110 is etched to form the metal pad 161. The sidewall of the metal pad 161 is spaced from the first metal material layer 150 on the sidewall of the first opening 110. The second metal material layer 160 on the substrate 100 is removed, while the second metal material layer 160 in the grounding via 140 is retained to form the grounding structure 162. By using the same etching process to form both the metal pad 161 and the grounding structure 162, they can be formed in the same process step, thereby reducing the number of process steps and further lowering the process cost.

[0077] Specifically, the method for etching the second metal material layer 160 in the first opening 110 and removing the second metal material layer 160 on the substrate 100 includes: firstly forming a patterned second photoresist layer (not shown) on the second metal material layer 160, the patterned second photoresist layer exposing a portion of the second metal material layer 160 in the first opening 110 and exposing the second metal material layer 160 on the substrate 100; then, using the patterned second photoresist layer as a mask, etching the exposed second metal material layer 160 in the first opening 110 using a dry etching process to form a metal pad 161, and removing the second metal material layer 160 on the substrate 100; and finally, removing the patterned second photoresist layer to expose the first metal material layer 150.

[0078] After that, as Figure 10As shown, the first metal material layer 150 on the substrate 100 of the logic region 100B is etched to form a first metal grid 151, and the first metal material layer 150 on the substrate 100 of the pixel region 100C is etched to form a second metal grid 152, and the first metal material layer 150 on the substrate 100 of the input / output region 100A is removed, wherein the grounding structure 162 is electrically connected to the substrate 100 through the first metal grid 151.

[0079] Specifically, the method for etching the first metal material layer 150 includes: firstly, as... Figure 9 As shown, a hard mask layer 170 is formed, which covers the first metal material layer 150, the metal pad 161, and the ground structure 162. The hard mask layer 170 completely covers the metal pad 161, meaning it covers the top surface of the metal pad 161 and fills the area (or gap) between the sidewall of the metal pad 161 and the first metal material layer 150. In this embodiment, the material of the hard mask layer 170 comprises silicon oxide.

[0080] Then, a patterned third photoresist layer is formed on the hard mask layer 170, which exposes a portion of the hard mask layer 170 of the pixel region 100C. Specifically, it may expose a portion of the hard mask layer 170 located on the substrate 100 between adjacent deep trench isolation structures 105, so that the subsequently formed second metal grid is located above the deep trench isolation structures 105 and exposes the hard mask layer 170 on the substrate 100 of the input / output region 100A.

[0081] Next, as Figure 10 As shown, using the patterned third photoresist layer as a mask, the hard mask layer 170 is etched to form a patterned hard mask layer 171. The patterned hard mask layer 171 exposes a portion of the first metal material layer 150 of the pixel region 100C, that is, exposes the first metal material layer 150 on the substrate 100 region between adjacent deep trench isolation structures 105, and exposes the first metal material layer 150 on the substrate 100 of the input / output region 100A. In other words, the patterned third photoresist layer covers the first metal material layer 150 of the logic region 100B and covers the first metal material layer 150 of the pixel region 100C located above the deep trench isolation structure 105.

[0082] Next, as Figure 11As shown, using the patterned third photoresist layer and the patterned hard mask layer 171 as masks, a dry etching process is employed to etch the exposed first metal material layer 150 to form the first metal grid 151 and the second metal grid 152, and then remove the first metal material layer 150 on the substrate 100 of the input / output region 100A. The second metal grid 152 is located above the deep trench isolation structure 105, and the second metal grid 152 is isolated from the deep trench isolation structure 105 by a dielectric layer. Afterwards, the patterned third photoresist layer is removed.

[0083] In this embodiment, the first metal grid 151 and the second metal grid 152 are electrically connected (not shown). A color filter can then be formed between the first metal grid 151 and the second metal grid 152, as well as between two adjacent second metal grids 152. The color filter can cover both the first metal grid 151 and the second metal grid 152. When incident light passes through the color filter, the first metal grid 151 and the second metal grid 152 act as an isolation layer, effectively preventing stray light from entering adjacent pixels and optimizing the light path, reducing scattering and reflection of light within the device, thereby improving light efficiency. Furthermore, since both the first metal grid 151 and the second metal grid 152 are made of tungsten, it helps reduce crosstalk between pixels.

[0084] Next, a patterned fourth photoresist layer is formed, which exposes the patterned hard mask layer 171 on the metal pad 161; as Figure 12 As shown, using the patterned fourth photoresist layer as a mask, the exposed patterned hard mask layer 171 is etched to expose the top surface of the metal pad 161. By exposing the top surface of the metal pad 161, the metal pad 161 can be electrically connected to external circuits or devices during subsequent processes or tests. Afterward, the patterned fourth photoresist layer is removed.

[0085] In summary, in the back-illuminated image sensor manufacturing method provided in this embodiment of the invention, by using a patterned first photoresist layer as a mask, the dielectric layer exposed in the first opening and the substrate at the bottom of the first opening are sequentially etched to form a second opening, and the dielectric layer of the exposed logic region is etched to form a grounding via. That is, the second opening (the growth window for forming the metal pad) and the grounding via are formed in the same etching step. In other words, the second opening and the grounding via can be formed with a single mask, thus saving two mask layers and reducing the number of masks required in the formation of the metal pad and grounding structure, thereby reducing process costs. Correspondingly, the metal pad and grounding structure can be formed in the same process step, thereby reducing process steps and further reducing process costs.

[0086] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

[0087] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

Claims

1. A method for manufacturing a back-illuminated image sensor, characterized in that, include: A substrate is provided having an input / output region, a logic region, and a pixel region, the logic region being located between the input / output region and the pixel region, and a metal interconnect structure being formed in the substrate of the input / output region, wherein the substrate of the input / output region has a first opening, the first opening being located above the metal interconnect structure; A dielectric layer is formed, which covers the sidewalls and bottom of the first opening and the substrate; A patterned first photoresist layer is formed on the dielectric layer, the patterned first photoresist layer exposing the dielectric layer at the bottom of the first opening and a portion of the dielectric layer on the logic region; Using the patterned first photoresist layer as a mask, the dielectric layer exposed in the first opening and the substrate at the bottom of the first opening are sequentially etched to form a second opening. The second opening exposes a portion of the metal interconnect structure, and the dielectric layer of the exposed logic region is etched to form a ground hole. The ground hole exposes a portion of the substrate of the logic region. Remove the patterned first photoresist layer; A metal pad and a grounding structure are formed, wherein the metal pad fills the second opening and a portion of the first opening and is electrically connected to the metal interconnect structure, and the grounding structure fills the grounding hole and is electrically connected to the substrate.

2. The method for manufacturing a back-illuminated image sensor as described in claim 1, characterized in that, The method of forming the metal pads and the grounding structure includes: A first metal material layer and a second metal material layer are formed sequentially. The first metal material layer covers the sidewalls and bottom of the first opening, the sidewalls of the second opening, and the sidewalls and bottom of the grounding hole, and covers the substrate. The second metal material layer covers the first metal material layer. The second metal material layer in the first opening is etched to form the metal pad, the sidewall of the metal pad is spaced from the first metal material layer in the sidewall of the first opening, and the second metal material layer on the substrate is removed while the second metal material layer in the grounding hole is retained to form the grounding structure.

3. The method for manufacturing a backside illumination type image sensor according to claim 2, wherein The methods for etching the second metal material layer in the first opening and removing the second metal material layer on the substrate include: A patterned second photoresist layer is formed on the second metal material layer, the patterned second photoresist layer exposing a portion of the second metal material layer in the first opening and exposing the second metal material layer on the substrate; Using the patterned second photoresist layer as a mask, a dry etching process is employed to etch the second metal material layer exposed in the first opening, and the second metal material layer on the substrate is removed; and, Remove the patterned second photoresist layer.

4. The method for manufacturing a back-illuminated image sensor as described in claim 2, characterized in that, The first metal material layer is made of tungsten, the second metal material layer is made of aluminum, and the dielectric layer is made of silicon oxide.

5. The method for manufacturing a back-illuminated image sensor as described in claim 2, characterized in that, After forming the metal pads and the grounding structure, the method for manufacturing the back-illuminated image sensor further includes: The first metal material layer on the substrate of the logic region is etched to form a first metal grid, and the first metal material layer on the substrate of the pixel region is etched to form a second metal grid, and the first metal material layer on the substrate of the input / output region is removed, wherein the grounding structure is electrically connected to the substrate through the first metal grid.

6. The method for manufacturing a back-illuminated image sensor as described in claim 5, characterized in that, The method for etching the first metal material layer includes: A hard mask layer is formed, which covers the first metal material layer, the metal pads, and the grounding structure; A patterned third photoresist layer is formed on the hard mask layer, the patterned third photoresist layer exposing a portion of the hard mask layer in the pixel area and the hard mask layer on the substrate in the input / output area; Using the patterned third photoresist layer as a mask, the hard mask layer is etched to form a patterned hard mask layer. The patterned hard mask layer exposes a portion of the first metal material layer in the pixel area and exposes the first metal material layer on the substrate of the input / output area. Using the patterned third photoresist layer and the patterned hard mask layer as masks, the exposed first metal material layer is etched using a dry etching process to form the first metal grid and the second metal grid, and the first metal material layer on the substrate of the input / output area is removed; and the patterned third photoresist layer is removed.

7. The method for manufacturing a back-illuminated image sensor as described in claim 5 or 6, characterized in that, A deep trench isolation structure is formed in the substrate of the pixel area, the dielectric layer covers the deep trench isolation structure, and the second metal grid is located above the deep trench isolation structure.

8. The method for manufacturing a back-illuminated image sensor as described in claim 6, characterized in that, After forming the first metal grid and the second metal grid, the method for manufacturing the back-illuminated image sensor further includes: A patterned fourth photoresist layer is formed, the patterned photoresist layer exposing the patterned hard mask layer on the metal pads; Using the patterned fourth photoresist layer as a mask, the exposed patterned hard mask layer is etched to expose the top surface of the metal pads; and, Remove the patterned fourth photoresist layer.

9. The method for manufacturing a back-illuminated image sensor as described in claim 1, characterized in that, The dielectric layer is etched using a dry etching process.

10. The method for manufacturing a back-illuminated image sensor as described in claim 1, characterized in that, The substrate includes a support substrate, an interlayer dielectric layer, and a device substrate stacked sequentially from bottom to top. The metal interconnect structure is formed in the interlayer dielectric layer. The device substrate has a first surface and a second surface disposed opposite to each other. The interlayer dielectric layer is formed on the second surface of the device substrate. The dielectric layer is formed on the first surface of the device substrate. The first opening is formed in the device substrate and penetrates the device substrate.

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