Solar cell, preparation method thereof and photovoltaic module

By optimizing the design of the doped layer and isolation region on the back of the BC cell, and adopting a closed pattern and a scale-like undulating structure of the heavily doped region, the problem of carrier recombination center on the back of the BC cell was solved, thereby improving the cell performance and efficiency.

CN122002969APending Publication Date: 2026-05-08TIANJIN ZHONGHUAN SEMICON CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
TIANJIN ZHONGHUAN SEMICON CO LTD
Filing Date
2026-02-11
Publication Date
2026-05-08

AI Technical Summary

Technical Problem

In the back structure of BC batteries, carrier recombination is severe, especially at the edges of the passivation film structure at the interface between the N and P regions and the isolation region, where the carrier recombination center is caused by etching, which affects battery performance.

Method used

A first polar doped layer and a second polar doped layer are disposed on a semiconductor substrate. The first polar doped layer surrounds the second polar doped layer to form a closed pattern. Spacing portions and heavily doped regions are disposed at the edge of the substrate. Combined with a scaly undulating structure and a grid-like distribution, the arrangement of the doped layers and the design of the isolation region are optimized.

Benefits of technology

It effectively reduces carrier recombination, improves the open-circuit voltage and conversion efficiency of the battery, enhances the mechanical strength of the battery edge and the carrier collection capability, and reduces power loss under metal electrode failure.

✦ Generated by Eureka AI based on patent content.

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Abstract

The invention provides a solar cell, a preparation method thereof and a photovoltaic module, and relates to the technical field of photovoltaic cells. The semiconductor substrate comprises a first surface and a second surface which are oppositely arranged, the first surface is provided with a first polarity doping layer, a second polarity doping layer and an isolation region, and the doping types of the first polarity doping layer and the second polarity doping layer are different; wherein the first polarity doping layer is arranged around the second polarity doping layer, and the outer contour boundary of the first polarity doping layer is continuously arranged along the edge of the first surface to form a closed pattern. The first polarity doping layers are continuously arranged in a surrounding mode, it is guaranteed that all the doping layers existing in the edge area of the cell are of the same doping type, the periodic arrangement structure of the back face is optimized, the length of the isolation area is reduced, carrier recombination caused by the electrode area and the isolation area interface is reduced, and therefore the cell performance is improved.
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Description

Technical Field

[0001] This invention relates to the field of photovoltaic cell technology, and in particular to a solar cell and its preparation method, and a photovoltaic module. Background Technology

[0002] The back structure of the BC battery achieves zero shading on the front side by interdigitating the P-type and N-type doped regions, maximizing the utilization of incident light. At the same time, the tunneling contact passivation structure significantly reduces carrier recombination losses and improves open-circuit voltage. As a high-efficiency battery, the BC battery has gradually become the mainstream product in the market.

[0003] In mainstream passivation contact technologies, the electron-selective contact region (N-region) of a solar cell is formed by depositing a doped layer containing a dielectric layer and an n-type dopant on the substrate, while the hole-selective contact region (P-region) is formed by depositing a doped layer containing a dielectric layer and a p-type dopant on the substrate.

[0004] BC cells have N-regions and P-regions periodically alternating on the back side, as well as an isolation region between them. In the BC cell manufacturing process, the dielectric layer and doped layer on the surface of the isolation region need to be removed by laser etching, chemical etching, etc., to ensure that the N and P regions do not directly contact each other and cause problems such as leakage and carrier recombination. Therefore, the passivation contact film layer containing dielectric and doped layers covering the surface of the N or P region has a fracture cross section at the interface where it meets the isolation region.

[0005] Studies have shown that carrier recombination at this interface is quite severe. Published literature indicates that the edge of the passivation film structure at this interface is over-etched during subsequent laser and chemical etching processes, leading to local passivation failure and micro-depressions, thus becoming carrier recombination centers. The carrier recombination situation in different regions of the BC battery surface was characterized using reverse saturation current densities J01 and J02. Tests revealed that although this interface accounts for less than 20% of the total area, it accounts for 60.6% of the total J02. Therefore, when designing the pattern on the back of the BC battery, it is necessary not only to consider the area ratio and spacing of the N and P regions, but also to consider how to reduce the length of the selective region and isolation region interface through optimization of the surface pattern arrangement.

[0006] In view of this, the present invention is hereby proposed. Summary of the Invention

[0007] The purpose of this invention is to provide a solar cell, a method for its preparation, and a photovoltaic module.

[0008] In order to achieve the above-mentioned objectives of the present invention, the following technical solution is adopted: In a first aspect, the present invention provides a solar cell, comprising a semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface disposed opposite to each other, the first surface being provided with a first polar doped layer, a second polar doped layer and an isolation region, and the first polar doped layer and the second polar doped layer having different doping types. The first polar doped layer surrounds the second polar doped layer, and the outer contour boundary of the first polar doped layer is continuously arranged along the edge of the first surface to form a closed pattern. The first polar doped layer has a gap between at least two parallel edges of the first surface.

[0009] Furthermore, the first polar doped layer has a spacer between at least two parallel edges of the first surface, wherein the semiconductor substrate is rectangular, and the spacer is disposed on two parallel edges of the first surface, or three edges of the first surface, or four edges of the first surface.

[0010] Furthermore, the width w of the interval is 1~50 μm.

[0011] Furthermore, on the first surface of the semiconductor substrate, the first polar doped layer and the second polar doped layer are arranged at intervals; wherein, the isolation region is disposed between the first polar doped layer and the second polar doped layer.

[0012] Furthermore, the outer contour boundary of the first polar doped layer has a serrated morphology extending from the first polar doped layer to the edge of the first surface.

[0013] Furthermore, a scale-like undulating structure is provided on the substrate surface between the outer contour boundary of the first polar doped layer and the edge of the first surface.

[0014] Furthermore, the distance difference d between the peaks and troughs of the sawtooth morphology and the edge of the first surface is 2~20 μm.

[0015] Furthermore, the scaly undulating structure has at least one layer distributed along the thickness direction of the substrate, preferably two or more layers.

[0016] Furthermore, when the scale-like undulating structure has two or more layers distributed along the thickness direction of the substrate, the scale-like undulating structure is distributed in a gradient along the thickness direction of the substrate; wherein, in the direction intersecting with the edge of the first surface, the size d1 of the undulating structure in the region close to the first surface from the first polar doped layer to the edge of the first surface is less than the size d2 of the undulating structure in the region far from the first surface.

[0017] Furthermore, the dimension d1 of the undulating structure in the region near the first surface from the first polar doped layer toward the edge of the first surface is 50 to 95% of the dimension d2 of the undulating structure in the region away from the first surface.

[0018] Furthermore, the first polar doped layer is distributed in a continuous grid structure to form a mesh region enclosed by the grid; wherein, the second polar doped layer is disposed in the mesh region, and the isolation region is disposed between the first polar doped layer and the second polar doped layer.

[0019] Furthermore, the shape of the mesh area includes any one of the following: circle, rectangle, regular polygon, and irregular polygon.

[0020] Furthermore, the distance between the centers of two adjacent mesh openings is 0.05~5 mm.

[0021] Furthermore, the ratio of the perimeter of a single mesh opening to the area of ​​the mesh opening is (0.01~5):1.

[0022] Furthermore, in a single mesh, the area ratio between the second polar doped layer and the isolation region is (2~100):1.

[0023] Furthermore, the total area of ​​the second polar doped layer accounts for 5 to 50% of the total area of ​​the first surface; the total area of ​​the isolation region accounts for 0.1 to 10% of the total area of ​​the first surface.

[0024] Furthermore, the outer contour boundary of the first polar doped layer is disposed adjacent to the edge of the first surface of the semiconductor substrate.

[0025] Furthermore, a heavily doped region is provided between the outer contour boundary of the first polar doped layer and the edge of the first surface; wherein the doping concentration of the heavily doped region is greater than the doping concentration of the semiconductor substrate.

[0026] Furthermore, the ratio of the doping concentration of the heavily doped region to the doping concentration of the semiconductor substrate is (10~100):1.

[0027] Furthermore, the semiconductor substrate is made of any one of silicon, germanium, gallium arsenide, and gallium nitride.

[0028] Furthermore, the semiconductor substrate includes an N-type doped substrate or a P-type doped substrate, preferably an N-type doped substrate.

[0029] Furthermore, the initial doping concentration of the semiconductor substrate is 1 E14 atm.cm. -3 ~1 E16 atm.cm -3.

[0030] Furthermore, the doping element in the N-type doped substrate includes any one or a combination of at least two of phosphorus, arsenic, antimony, and bismuth.

[0031] Furthermore, the doping elements in the P-type doped substrate include any one or a combination of at least two of boron, aluminum, gallium, and indium.

[0032] Furthermore, the materials of the first polar doped layer and the second polar doped layer each independently include any one of polycrystalline silicon, amorphous silicon, and silicon carbide.

[0033] Furthermore, when the first polar doped layer is a P-type doped layer, the second polar doped layer is an N-type doped layer; when the first polar doped layer is an N-type doped layer, the second polar doped layer is a P-type doped layer.

[0034] Furthermore, the concentration of the N-type doped layer is 1 E20~1 E21 atm.cm. -3 The concentration of the p-type doped layer is 1 E19~1 E20 atm.cm. -3 .

[0035] Furthermore, the doping elements in the N-type doped layer include any one or a combination of at least two of phosphorus, arsenic, antimony, and bismuth.

[0036] Furthermore, the doping elements in the P-type doped layer include any one or a combination of at least two of boron, aluminum, gallium, and indium.

[0037] Furthermore, a passivation layer is provided on the surface of the first polar doped layer, the second polar doped layer, and the isolation region; and a passivation layer is provided on the second surface.

[0038] Furthermore, the passivation layer is made of any one or a combination of at least two of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, and titanium oxide.

[0039] Furthermore, the thickness of the passivation layer is 1~100 nm.

[0040] Furthermore, a first electrode and a second electrode are also disposed on the first surface; wherein the first electrode forms an electrical contact with the first polar doped layer, and the second electrode forms an electrical contact with the second polar doped layer.

[0041] In a second aspect, the present invention provides a method for preparing a solar cell as described in the first aspect, comprising: The first polar doped layer is prepared on the first surface of the semiconductor substrate; Remove the first polar doped layer at the location of the second polar doped layer and the isolation region; The second polar doped layer is prepared on the first surface; The second polar doped layer is removed from the area covered by the isolation region and the first polar doped layer to obtain the solar cell.

[0042] Furthermore, after the step of removing the second polar doped layer at the location of the isolation region and the coverage area of ​​the first polar doped layer, and before obtaining the solar cell, the method further includes: first preparing a passivation layer on the surface of the first polar doped layer, the second polar doped layer and the isolation region, and then preparing a passivation layer on the second surface.

[0043] Thirdly, the present invention provides a photovoltaic module, the photovoltaic module comprising the solar cell as described in the first aspect.

[0044] Compared with the prior art, the present invention has the following beneficial effects: (1) The first polar doped layer of the solar cell of the present invention connects the various regions of the cell into a whole, so that even if the metal electrode fails and cannot output the charge carriers, the charge carriers in any part of the cell can be transmitted to the adjacent electrode through the doped layer, thereby effectively reducing the power loss in the case of partial metal electrode failure. (2) The solar cell of the present invention reduces the interface length between the carrier selective region and the isolation region, while increasing the area of ​​the carrier selective region with excellent passivation effect; thus, it improves the overall passivation effect on the back of the cell, reduces carrier recombination, and improves the open circuit voltage Uoc and conversion efficiency of the cell. (3) The solar cell of the present invention ensures that all the doped layers adjacent to the edge of the substrate are first polar doped layers, and there is a gap of a certain width between the boundary of the doped layer and the edge of the substrate. A heavily doped region is provided in the substrate in the gap region. The doping type of the heavily doped region is the same as that of the first polar doped layer. The field passivation effect of the first polar doped layer and the heavily doped region can increase the carrier collection efficiency in the edge region of the cell. Attached Figure Description

[0045] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the planar structure of a solar cell provided in Embodiment I of the present invention.

[0047] Figure 2 This is a schematic diagram of the planar structure of a solar cell provided in Embodiment II of the present invention.

[0048] Figure 3 This is a schematic diagram of the planar structure of a solar cell provided in Embodiment III of the present invention.

[0049] Figure 4 This is a schematic diagram of a planar structure of a solar cell with a heavily doped region according to an embodiment of the present invention.

[0050] Figure 5 This is a partial cross-sectional schematic diagram of a solar cell provided according to an embodiment of the present invention.

[0051] Figure 6 A partial planar structure diagram and a cross-sectional diagram of the edge of a solar cell provided in an embodiment of the present invention.

[0052] Figure 7 This is a schematic diagram of the planar structure of a solar cell provided in a proportional embodiment of the present invention.

[0053] Wherein, 10 is a semiconductor substrate, 11 is a first polar doped layer, 12 is a second polar doped layer, 13 is an isolation region, 14 is the edge of the first surface, 15 is the outer contour boundary of the first polar doped layer, 16 is a heavily doped region, and 17 is a spacer. Detailed Implementation

[0054] Unless otherwise defined herein, the scientific and technical terms used in conjunction with this invention shall have the meanings commonly understood by one of ordinary skill in the art. The meaning and scope of terms shall be clear; however, in any case of potential ambiguity, the definitions provided herein shall prevail over any dictionary or foreign definitions. In this application, unless otherwise stated, the use of "or" means "and / or". Furthermore, the use of the term "comprising" and other forms is non-limiting.

[0055] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] Firstly, such as Figure 1 , Figure 2 and Figure 3As shown, the present invention provides a solar cell, the solar cell including a semiconductor substrate 10, the semiconductor substrate 10 including a first surface and a second surface disposed opposite to each other, the first surface being provided with a first polar doped layer 11, a second polar doped layer 12 and an isolation region 13, and the first polar doped layer 11 and the second polar doped layer 12 having different doping types. The first polar doped layer 11 is disposed around the second polar doped layer 12, and the outer contour boundary 15 of the first polar doped layer is continuously disposed along the edge 14 of the first surface to form a closed pattern. Among them, such as Figure 4 As shown, the first polar doped layer 11 has a spacer 17 between at least two parallel edges of the first surface.

[0057] It should be noted that the first polar doped layer of the solar cell described in this invention is disposed around the second polar doped layer, and the outer contour boundary of the first polar doped layer is continuously disposed along the edge of the first surface to form a closed pattern, which ensures that the polarity of the doped layer at the edge of the first surface is the same, reduces the length of the isolation region in the edge region of the solar cell, and the solar cell structure optimizes the back periodic arrangement structure, reduces the length of the isolation region in the internal region, reduces the carrier recombination of the cell, thereby improving the cell performance.

[0058] As an optional implementation, the semiconductor substrate 10 is rectangular, and the spacing portion 17 is disposed on two parallel edges of the first surface, or three edges of the first surface, or four edges of the first surface.

[0059] As an optional implementation, the width w of the spacing portion 17 is 1~50 μm, for example, it can be 1 μm, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm, 22 μm, 24 μm, 26 μm, 28 μm, 30 μm, 32 μm, 34 μm, 36 μm, 38 μm, 40 μm, 42 μm, 44 μm, 46 μm, 48 μm, 50 μm, etc.

[0060] It should be noted that, relative to the center region of the semiconductor substrate, the edge of the semiconductor substrate inevitably suffers damage and defects due to frequent friction and collision with tooling fixtures during the manufacturing process, which leads to increased carrier recombination at the edge. The spacer can reduce the recombination of carriers in the polar doped layer region by defects at the edge, thereby improving battery efficiency.

[0061] As an optional implementation method, such as Figure 1 , Figure 2 and Figure 3As shown, on the first surface of the semiconductor substrate, the first polar doped layer 11 and the second polar doped layer 12 are arranged at intervals; wherein, the isolation region 13 is disposed between the first polar doped layer 11 and the second polar doped layer 12, and the isolation region 13 has no doped layer region.

[0062] It should be noted that, in the solar cell of the present invention, the first polar doped layer and the second polar doped layer are arranged at intervals along the first surface of the substrate, and the isolation region is disposed between the first polar doped layer and the second polar doped layer. The isolation region prevents the first polar doped layer and the second polar doped layer from directly contacting each other, thus preventing carrier recombination. It spatially isolates the first polar doped layer and the second polar doped layer to ensure electrical insulation, avoid leakage, and effectively prevent direct contact between regions of different polarities, thus preventing leakage and carrier recombination. This structure ensures the electrical independence of selective contact, improves the back passivation quality, reduces the interface recombination rate, and enhances the open-circuit voltage and conversion efficiency.

[0063] As an optional implementation method, such as Figure 6 As shown, the outer contour boundary 15 of the first polar doped layer has a serrated shape extending from the edge of the first polar doped layer toward the first surface.

[0064] As an optional implementation method, such as Figure 6 As shown, a scale-like undulating structure is provided on the substrate surface between the outer contour boundary 15 of the first polar doped layer and the edge 14 of the first surface.

[0065] It should be noted that the sawtooth structure on the outer contour edge of the first polar doped layer of the present invention reduces the stress at the boundary of the outer contour of the first polar doped layer, preventing the edge region of the first polar doped layer from bursting or cracking due to stress concentration; the scale-like undulating structure between the outer contour boundary of the first polar doped layer and the edge of the first surface increases the effective surface area of ​​the substrate and increases the light absorption efficiency. Furthermore, in practical applications, the temperature of the module fluctuates by tens of degrees. Due to the different coefficients of thermal expansion between the solar cell and the encapsulation material, there is an interaction force between the solar cell and the encapsulation material during the thermal expansion and contraction process. The edge area of ​​the solar cell is more prone to damage because the direction of the force is inconsistent. Compared with the planar structure, the scaly undulating structure of the edge area of ​​the silicon wafer can disperse the direction of the force, avoid the fragmentation and damage of the substrate edge material caused by local force, and enhance the mechanical strength of the substrate edge.

[0066] As an optional implementation, the distance difference d between the peaks and troughs of the sawtooth morphology and the edge of the first surface is 2~20 μm, for example, it can be 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 8 μm, 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm, etc.; wherein, the highest point of the protrusion of the sawtooth morphology is the peak, and the lowest point of the depression is the trough.

[0067] It should be noted that the size of the serrated structure at the outer contour edge of the first polar doped layer described in this invention needs to be within a certain range. If the structure size is too small, it cannot effectively buffer the stress concentration caused by stress changes in the doped layer, while if the size is too large, it will reduce the coverage area of ​​the edge of the first polar doped layer, reduce the carrier collection capacity, and damage the electrical performance of the solar cell.

[0068] As an optional implementation, the scaly undulating structure has at least one layer distributed along the thickness direction of the substrate, for example, it can be 1 layer, 2 layers, 3 layers, 4 layers, 5 layers, 6 layers, 7 layers, 8 layers, 9 layers, 10 layers, etc.

[0069] In a preferred embodiment, the scaly undulating structure has two or more layers distributed along the thickness direction of the substrate.

[0070] It should be noted that the scaly undulation structure described in this invention is distributed in multiple layers along the thickness direction of the substrate, which can further increase the effective area of ​​the battery surface and improve the light absorption efficiency; at the same time, the multi-layered scaly undulation along the thickness direction of the substrate forms a light trapping structure, which has a lower reflectivity than a plane, further improving the light absorption efficiency of the battery.

[0071] As an optional implementation, when the scale-like undulating structure has two or more layers distributed along the thickness direction of the substrate, the scale-like undulating structure is distributed in a gradient along the thickness direction of the substrate; wherein, in the direction intersecting with the edge of the first surface, the size d1 of the undulating structure in the region close to the first surface from the first polar doped layer to the edge of the first surface is less than the size d2 of the undulating structure in the region far from the first surface.

[0072] In a preferred embodiment, the dimension d1 of the undulating structure in the region near the first surface from the first polar doped layer toward the edge of the first surface is 50-95% of the dimension d2 of the undulating structure in the region away from the first surface, for example, it can be 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, etc.

[0073] It should be noted that the size of the undulating structure near the first surface of the scale-like undulating structure described in this invention is smaller than that of the undulating structure away from the first surface, and the ratio of the two sizes is maintained within a certain range. This structural design can maximize the light-trapping effect of the light-trapping structure and reduce the surface reflectivity. At the same time, the size of the scale-like undulating structure near the edge of the silicon wafer is larger, providing higher mechanical strength to the edge of the cell.

[0074] As an optional implementation method, such as Figure 1 , Figure 2 and Figure 3 As shown, the first polar doped layer 11 is distributed in a continuous grid structure, forming a mesh region enclosed by the grid; wherein, the second polar doped layer 12 is disposed in the mesh region, and the isolation region 13 is disposed between the first polar doped layer 11 and the second polar doped layer 12.

[0075] It should be noted that the first polar doped layer is distributed in a continuous mesh structure. As a whole without obvious dividing boundaries, there is at least one carrier transport path between any two points in the first polar doped layer. The area traversed by this path exists only in the first polar doped layer. Spatially, this path does not pass through or cross the second polar doped layer or the isolation region. The current between any two points on the mesh structure (i.e., the plane covered by the polar region) can be transmitted through the path within the mesh structure without needing to pass through or cross another polar region or isolation region. In planar representation, a continuous connecting line can be found between any two points on the mesh structure, and any point on this connecting line is within the closed plane formed by the edge of the mesh structure. The continuous mesh structure reduces the design length of the isolation region and reduces carrier recombination caused by the interface between the polar region and the isolation region. Meanwhile, the mesh structure is continuously arranged close to the edge of the battery, so that all the doped layers in the edge region of the battery are of the same doping type; a heavily doped region is set between the outer contour boundary of the mesh structure and the edge of the battery, and the doping type is the same as that of the mesh structure; the heavily doped region increases the carrier collection efficiency at the edge of the battery and improves the battery performance.

[0076] As an optional implementation, the shape of the mesh area includes any one of the following: circle, rectangle, regular polygon, and irregular polygon.

[0077] As an optional implementation, the spacing between the centers of two adjacent mesh openings is 0.05 to 5 mm, for example, it can be 0.5 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 3.5 mm, 4 mm, 4.5 mm, 5 mm, etc.

[0078] As an optional implementation, the ratio of the perimeter of a single mesh opening to the area of ​​the mesh opening is (0.01~5):1, for example, it can be 0.01:1, 0.05:1, 0.1:1, 0.5:1, 1:1, 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, etc.

[0079] It should be noted that, depending on design requirements or actual manufacturing processes, the mesh shape of the mesh structure includes, but is not limited to, circular, rectangular, and irregular polygonal shapes; the size of the mesh and the spacing between the meshes affect the series resistance, fill factor, and conversion efficiency of the battery; the optimal parameter range needs to be obtained through design and experimental verification based on the substrate resistivity, the doping concentration of the first polar doped layer and the second polar doped layer, as shown above.

[0080] As an optional implementation, in a single mesh, the area ratio between the second polar doped layer and the isolation region is (2~100):1, for example, it can be 2:1, 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, 40:1, 45:1, 50:1, 55:1, 60:1, 70:1, 80:1, 90:1, 100:1, etc.

[0081] As an optional implementation, the total area of ​​the second polar doped layer accounts for 5% to 50% of the total area of ​​the first surface, for example, it can be 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, etc.

[0082] As an optional implementation, the total area of ​​the isolation zone accounts for 0.1% to 10% of the total area of ​​the first surface, for example, it can be 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, etc.

[0083] As an optional implementation method, such as Figure 1 , Figure 2 and Figure 3 As shown, the outer contour boundary 15 of the first polar doped layer is disposed adjacent to the edge 14 of the first surface of the semiconductor substrate.

[0084] As an optional implementation method, such as Figure 1 As shown, the first polar doped layer 11 is distributed in a continuous grid structure, forming a mesh region surrounded by the grid, and the mesh region has a segmented and regional structure; that is, the second polar doped layer 12 has a segmented and regional structure.

[0085] As an optional implementation method, such as Figure 2As shown, the first polar doped layer 11 is distributed in a continuous grid structure, forming a mesh region surrounded by the grid, and the mesh region has a discrete distribution structure; that is, the second polar doped layer 12 has a discrete distribution structure.

[0086] As an optional implementation method, such as Figure 3 As shown, the first polar doped layer 11 is distributed in a continuous grid structure, forming a mesh region surrounded by the grid, and the mesh region has an extended continuous structure; that is, the second polar doped layer 12 has an extended continuous structure.

[0087] As an optional implementation method, such as Figure 4 As shown, a heavily doped region 16 is provided between the outer contour boundary 15 of the first polar doped layer and the edge 14 of the first surface.

[0088] As an optional implementation, the doping concentration of the heavily doped region is greater than the doping concentration of the semiconductor substrate.

[0089] As an optional implementation, the ratio of the doping concentration of the heavily doped region to the doping concentration of the semiconductor substrate is (10~100):1, for example, it can be 10:1, 20:1, 30:1, 40:1, 50:1, 60:1, 70:1, 80:1, 90:1, 100:1, etc.

[0090] It should be noted that a heavily doped region is provided between the outer contour boundary of the first polar doped layer and the edge of the substrate. The doping type of the heavily doped region is the same as that of the first polar doped layer, and the surface doping concentration is significantly higher than that of the original doping concentration of the substrate. A high-low junction is formed between the heavily doped region and the substrate, thereby improving the carrier collection in the edge region and improving the battery performance.

[0091] As an optional implementation, the semiconductor substrate 10 is made of any one of silicon, germanium, gallium arsenide, and gallium nitride.

[0092] As an optional implementation, the semiconductor substrate 10 includes an N-type doped substrate or a P-type doped substrate.

[0093] In a preferred embodiment, the semiconductor substrate 10 is an N-type doped substrate.

[0094] It should be noted that the semiconductor substrate is preferably an N-type doped substrate, because it has a higher minority carrier lifetime and carrier diffusion length, which can effectively reduce recombination loss and improve the photoelectric conversion efficiency and stability of the device.

[0095] As an optional implementation, the initial doping concentration of the semiconductor substrate 10 is 1 E14 atm.cm. -3 ~1E16 atm.cm -3For example, it could be 1 E14 atm.cm -3 2 E14 atm.cm -3 3 E14 atm.cm -3 4 E14atm.cm -3 5 E14 atm.cm -3 6 E14 atm.cm -3 7 E14 atm.cm -3 8 E14 atm.cm -3 9 E14atm.cm -3 1 E15 atm.cm -3 2 E15 atm.cm -3 3 E15 atm.cm -3 4 E15 atm.cm -3 5 E15atm.cm -3 6 E15 atm.cm -3 7 E15 atm.cm -3 8 E15 atm.cm -3 9 E15 atm.cm -3 1 E16atm.cm -3 wait.

[0096] As an optional implementation, the doping element in the N-type doped substrate includes any one or a combination of at least two of phosphorus, arsenic, antimony, and bismuth.

[0097] As an optional implementation, the doping element in the P-type doped substrate includes any one or a combination of at least two of boron, aluminum, gallium, and indium.

[0098] As an optional implementation, the materials of the first polar doped layer 11 and the second polar doped layer 12 may each independently include any one of polycrystalline silicon, amorphous silicon, and silicon carbide.

[0099] As an optional implementation, when the first polar doped layer 11 is a P-type doped layer, the second polar doped layer 12 is an N-type doped layer.

[0100] As an optional implementation, when the first polar doped layer 11 is an N-type doped layer, the second polar doped layer 12 is a P-type doped layer.

[0101] As an optional implementation, the concentration of the N-type doped layer is 1 E20~1 E21 atm.cm. -3 For example, it could be 1 E20 atm.cm -3 2 E20 atm.cm-3 3 E20 atm.cm -3 4 E20 atm.cm -3 5 E20 atm.cm -3 6E20 atm.cm -3 7 E20 atm.cm -3 8 E20 atm.cm -3 9 E20 atm.cm -3 1 E21atm.cm -3 wait.

[0102] As an optional implementation, the concentration of the p-type doped layer is 1 E19~1 E20 atm.cm. -3 For example, it could be 1 E19 atm.cm -3 2 E19 atm.cm -3 3 E19 atm.cm -3 4 E19 atm.cm -3 5 E19 atm.cm -3 6E19 atm.cm -3 7 E19 atm.cm -3 8 E19 atm.cm -3 9 E19 atm.cm -3 1 E20 atm.cm -3 wait.

[0103] As an optional implementation, the doping element in the N-type doped layer includes any one or a combination of at least two of phosphorus, arsenic, antimony, and bismuth.

[0104] As an optional implementation, the doping element in the P-type doped layer includes any one or a combination of at least two of boron, aluminum, gallium, and indium.

[0105] As an optional implementation method, such as Figure 5 As shown, the boundary between the isolation region 13 and the first polar doped layer 11 and the second polar doped layer 12 can be a regular straight line, a circle or an arc; or this boundary can be an irregular curve, etc.

[0106] As an optional implementation, a passivation layer is provided on the surface of the first polar doped layer 11, the second polar doped layer 12, and the isolation region 13.

[0107] As an optional implementation, the second surface is provided with a passivation layer.

[0108] As an optional implementation, the material of the passivation layer includes any one or a combination of at least two of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, and titanium oxide.

[0109] As an optional implementation, the thickness of the passivation layer is 1~100 nm, for example, it can be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 12 nm, 14 nm, 16 nm, 18 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, etc.

[0110] As an optional implementation, a first electrode and a second electrode are also disposed on the first surface.

[0111] As an optional implementation, the first electrode forms an electrical contact with the first polar doped layer 11.

[0112] As an optional implementation, the second electrode forms an electrical contact with the second polar doped layer 12.

[0113] In a second aspect, the present invention provides a method for preparing a solar cell as described in the first aspect, comprising: The first polar doped layer is prepared on the first surface of the semiconductor substrate; Remove the first polar doped layer at the location of the second polar doped layer and the isolation region; The second polar doped layer is prepared on the first surface; The second polar doped layer is removed from the area covered by the isolation region and the first polar doped layer to obtain the solar cell.

[0114] As an optional implementation, after the step of removing the second polar doped layer at the location covered by the isolation region and the first polar doped layer, and before obtaining the solar cell, the method further includes: first preparing a passivation layer on the surface of the first polar doped layer, the second polar doped layer, and the isolation region, and then preparing a passivation layer on the second surface.

[0115] In some embodiments of the present invention, the present invention provides a method for preparing a solar cell as described in the first aspect, the method comprising: (A) The first polar doped layer is prepared on the first surface of the semiconductor substrate; (B) Perform a first patterning process on the intermediate cell obtained in step (A) to remove the first polar doped layer at the location of the second polar doped layer and the isolation region; (C) Prepare the second polar doped layer on the first surface of the intermediate cell obtained in step (B); (D) Perform a second patterning process on the intermediate cell obtained in step (C) to remove the second polar doped layer at the location of the isolation region and the area covered by the first polar doped layer.

[0116] As an optional implementation, a cleaning process is included before step (A), which includes texturing and / or polishing the semiconductor substrate.

[0117] As an optional implementation, in step (A), the first polar doped layer can be formed by deposition methods such as PECVD, LPCVD, and PVD; the doping method of the first polar doped layer can be formed by gas source thermal diffusion, solid source coating thermal diffusion, or in-situ doping.

[0118] As an optional implementation, in step (B), the first patterning process can be carried out by methods such as laser etching, alkaline etching, acid etching, photoresist mask + chemical etching, etc.

[0119] As an optional implementation, in step (C), the second polar doped layer can be formed by deposition methods such as PECVD, LPCVD, and PVD; the doping method of the second polar doped layer can be formed by gas source thermal diffusion, solid source coating thermal diffusion, or in-situ doping.

[0120] As an optional implementation, in step (D), the second patterning process can be carried out by methods such as laser etching, alkaline etching, acid etching, photoresist mask + chemical etching, etc.

[0121] As an optional implementation, step (D) is followed by step (E) to prepare a passivation layer: first, a passivation layer is prepared on the surface of the first polar doped layer, the second polar doped layer and the isolation region, and then a passivation layer is prepared on the second surface.

[0122] As an optional implementation, step (E) is followed by step (F) of preparing electrodes: preparing a first electrode and a second electrode on the first surface, such that the first electrode forms an electrical contact with the first polar doped layer, and the second electrode forms an electrical contact with the second polar doped layer.

[0123] Thirdly, the present invention provides a photovoltaic module, the photovoltaic module comprising the solar cell as described in the first aspect.

[0124] The present invention will be further illustrated by the following examples. Unless otherwise specified, the materials in the examples are prepared according to existing methods or purchased directly from the market.

[0125] Example 1 This embodiment provides a solar cell, such as Figure 1 As shown, the semiconductor substrate includes a first surface and a second surface disposed opposite to each other. A first polar doped layer, a second polar doped layer, and an isolation region are disposed on the first surface, and the first polar doped layer and the second polar doped layer have different doping types. The first polar doped layer surrounds the second polar doped layer, and the outer contour boundary of the first polar doped layer is continuously disposed along the edge of the first surface to form a closed pattern. On the first surface of the semiconductor substrate, the first polar doped layer and the second polar doped layer are arranged at intervals. The isolation region is disposed between the first polar doped layer and the second polar doped layer.

[0126] The first polar doped layer 11 has a spacer between its two parallel edges and the first surface; the semiconductor substrate is rectangular, and the spacer is disposed on the four edges of the first surface; the width w of the spacer is 15 μm.

[0127] The outer contour boundary of the first polar doped layer has a serrated morphology extending from the first polar doped layer to the edge of the first surface, and a scale-like undulating structure is provided on the substrate surface between the outer contour boundary of the first polar doped layer and the edge of the first surface; the distance difference between the peak and trough of the serrated morphology to the edge of the first surface is 7 μm; the scale-like undulating structure is distributed in two layers along the thickness direction of the substrate; and the scale-like undulating structure is gradient distributed along the thickness direction of the substrate; wherein, the dimension d1 of the undulating structure in the region near the first surface from the first polar doped layer to the edge of the first surface is 60% of the dimension d2 of the undulating structure in the region away from the first surface.

[0128] The first polar doped layer is distributed in a continuous grid structure, forming a mesh region enclosed by the grid; the second polar doped layer is disposed in the mesh region, and the isolation region is disposed between the first polar doped layer and the second polar doped layer; the first polar doped layer 11 is distributed in a continuous grid structure, forming a mesh region enclosed by the grid, and the mesh region has a segmented and regional structure; that is, the second polar doped layer 12 has a segmented and regional structure. The mesh area is rectangular in shape, with each rectangular mesh being 0.55 mm wide and 10 mm long. The center-to-center distance between two adjacent rectangular meshes is 1.05 mm along the width direction and 11 mm along the length direction. The meshes are arranged in an array on the first surface according to these dimensions. In a single rectangular mesh, the area ratio between the second polar doped layer and the isolation region is 4.5:1. The total area of ​​the second polar doped layer accounts for 42.9% of the total area of ​​the first surface; the total area of ​​the isolation region accounts for 9.5% of the total area of ​​the first surface. The outer contour boundary of the first polar doped layer is disposed adjacent to the edge of the first surface of the semiconductor substrate; a heavily doped region is disposed between the outer contour boundary of the first polar doped layer and the edge of the first surface; wherein the ratio of the doping concentration of the heavily doped region to the doping concentration of the semiconductor substrate is 50:1. The semiconductor substrate is made of silicon, is an N-type doped substrate, and has an initial doping concentration of 4E14 atm.cm. -3 The N-type doped substrate contains phosphorus as the dopant; and both the first and second polar doped layers are made of polycrystalline silicon, with the first polar doped layer being an N-type doped layer and the second polar doped layer being a P-type doped layer; the concentration of the N-type doped layer is 3 E20 atm / cm². -3 The concentration of the p-type doped layer is 5 E19 atm.cm. -3 The N-type doped layer is doped with phosphorus, and the P-type doped layer is doped with boron.

[0129] The first polar doped layer, the second polar doped layer, and the isolation region are all provided with passivation layers; and the second surface is provided with a passivation layer; the passivation layer consists of an aluminum oxide layer with a thickness of 5 nm and a silicon nitride layer with a thickness of 85 nm from the inside out.

[0130] The first surface is further provided with a first electrode and a second electrode; wherein the first electrode forms an electrical contact with the first polar doped layer, and the second electrode forms an electrical contact with the second polar doped layer.

[0131] The method for preparing a solar cell described in this embodiment includes: (1) The semiconductor substrate is texturized; (2) The first polar doped layer is prepared on the first surface of the semiconductor substrate described in step (1); wherein the first polar doped layer is formed by LPCVD deposition and the doping method of the first polar doped layer is gas source thermal diffusion; the process parameters of LPCVD deposition include: deposition temperature 650℃, deposition time 90 min, and the process parameters of gas source thermal diffusion include: diffusion temperature 910℃, diffusion time 150 min. (3) Perform a first patterning process on the intermediate battery cell obtained in step (2) to remove the first polar doped layer at the location of the second polar doped layer and the isolation region; wherein, the first patterning process can be performed by laser etching + alkaline solution etching method; laser etching removes the silicon oxide layer on the surface of the second polar doped layer and the isolation region, and then alkaline solution etching removes the lower first polar doped layer; the process parameters of laser etching include: laser pulse width 15 ps, laser frequency 10 MHz, laser power 20 W, scanning speed 50 m / s; the alkaline solution is a KOH solution with a concentration of 2.5 wt%, and the solution temperature is 48℃; (4) The second polar doped layer is prepared on the first surface of the intermediate cell obtained in step (3); wherein the second polar doped layer is formed by LPCVD deposition and the doping method of the first polar doped layer is gas source thermal diffusion; the process parameters of LPCVD deposition include: deposition temperature 650℃, deposition time 70 min, and the process parameters of gas source thermal diffusion include: diffusion temperature 860℃, diffusion time 120 min. (5) Perform a second patterning process on the intermediate battery cell obtained in step (4) to remove the second polar doped layer on the area covered by the isolation region and the first polar doped layer; wherein, the second patterning process can be performed by laser etching + alkaline solution etching method; laser etching removes the silicon oxide layer on the surface of the first polar doped layer and the isolation region, and then alkaline solution etching removes the lower second polar doped layer; the process parameters of laser etching include: laser pulse width 15 ps, laser frequency 10 MHz, laser power 20 W, scanning speed 50 m / s; the alkaline solution is a KOH solution with a concentration of 2.5 wt% and a solution temperature of 48℃; (6) A passivation layer is prepared on the surface of the first polar doped layer, the second polar doped layer and the isolation region of the intermediate battery cell obtained in step (5); (7) A passivation layer is prepared on the second surface of the intermediate battery cell obtained in step (6).

[0132] (8) A first electrode and a second electrode are prepared on the first surface of the intermediate cell obtained in step (7), so that the first electrode forms an electrical contact with the first polar doped layer and the second electrode forms an electrical contact with the second polar doped layer, thereby obtaining the solar cell.

[0133] Example 2 This embodiment provides a solar cell, such as Figure 2 As shown, the semiconductor substrate includes a first surface and a second surface disposed opposite to each other. A first polar doped layer, a second polar doped layer, and an isolation region are disposed on the first surface, and the first polar doped layer and the second polar doped layer have different doping types. The first polar doped layer surrounds the second polar doped layer, and the outer contour boundary of the first polar doped layer is continuously disposed along the edge of the first surface to form a closed pattern. On the first surface of the semiconductor substrate, the first polar doped layer and the second polar doped layer are arranged at intervals. The isolation region is disposed between the first polar doped layer and the second polar doped layer.

[0134] The first polar doped layer 11 has a spacer between its two parallel edges and the first surface; the semiconductor substrate is rectangular, and the spacer is disposed on the four edges of the first surface; the width w of the spacer is 15 μm.

[0135] The outer contour boundary of the first polar doped layer has a serrated morphology extending from the first polar doped layer to the edge of the first surface, and a scale-like undulating structure is provided on the substrate surface between the outer contour boundary of the first polar doped layer and the edge of the first surface; the distance difference between the peak and trough of the serrated morphology to the edge of the first surface is 7 μm; the scale-like undulating structure is distributed in two layers along the thickness direction of the substrate; and the scale-like undulating structure is gradient distributed along the thickness direction of the substrate; wherein, the dimension d1 of the undulating structure in the region near the first surface from the first polar doped layer to the edge of the first surface is 60% of the dimension d2 of the undulating structure in the region away from the first surface.

[0136] The first polar doped layer is distributed in a continuous grid structure, forming a mesh region enclosed by the grid; the second polar doped layer is disposed in the mesh region, and the isolation region is disposed between the first polar doped layer and the second polar doped layer; the first polar doped layer 11 is distributed in a continuous grid structure, forming a mesh region enclosed by the grid, and the mesh region has a discrete distribution structure; that is, the second polar doped layer 12 has a discrete distribution structure. The mesh area is rectangular in shape, with each rectangular mesh having a width of 0.1 mm and a length of 0.2 mm. The center-to-center distance between two adjacent rectangular meshes is 0.8 mm along the width direction and 0.35 mm along the length direction. The meshes are arranged in an array on the first surface according to these dimensions. In a single rectangular mesh, the area ratio between the second polar doped layer and the isolation region is 7:1. The total area of ​​the second polar doped layer accounts for 7% of the total area of ​​the first surface; the total area of ​​the isolation region accounts for 1% of the total area of ​​the first surface. The outer contour boundary of the first polar doped layer is disposed adjacent to the edge of the first surface of the semiconductor substrate; a heavily doped region is disposed between the outer contour boundary of the first polar doped layer and the edge of the first surface; wherein the ratio of the doping concentration of the heavily doped region to the doping concentration of the semiconductor substrate is 50:1. The semiconductor substrate is made of silicon, is an N-type doped substrate, and has an initial doping concentration of 4E14 atm.cm. -3 The N-type doped substrate contains phosphorus as the dopant; and both the first and second polar doped layers are made of polycrystalline silicon, with the first polar doped layer being an N-type doped layer and the second polar doped layer being a P-type doped layer; the concentration of the N-type doped layer is 3 E20 atm / cm². -3 The concentration of the p-type doped layer is 5 E19 atm.cm. -3 The N-type doped layer is doped with phosphorus, and the P-type doped layer is doped with boron.

[0137] The first polar doped layer, the second polar doped layer, and the isolation region are all provided with passivation layers; and the second surface is provided with a passivation layer; the passivation layer consists of an aluminum oxide layer with a thickness of 5 nm and a silicon nitride layer with a thickness of 85 nm from the inside out.

[0138] The first surface is further provided with a first electrode and a second electrode; wherein the first electrode forms an electrical contact with the first polar doped layer, and the second electrode forms an electrical contact with the second polar doped layer.

[0139] The method for preparing a solar cell described in this embodiment includes: (1) The semiconductor substrate is texturized; (2) The first polar doped layer is prepared on the first surface of the semiconductor substrate described in step (1); wherein the first polar doped layer is formed by LPCVD deposition and the doping method of the first polar doped layer is gas source thermal diffusion; the process parameters of LPCVD deposition include: deposition temperature 650℃, deposition time 90 min, and the process parameters of gas source thermal diffusion include: diffusion temperature 910℃, diffusion time 150 min. (3) Perform a first patterning process on the intermediate battery cell obtained in step (2) to remove the first polar doped layer at the location of the second polar doped layer and the isolation region; wherein, the first patterning process can be performed by laser etching + alkaline solution etching method; laser etching removes the silicon oxide layer on the surface of the second polar doped layer and the isolation region, and then alkaline solution etching removes the lower first polar doped layer; the process parameters of laser etching include: laser pulse width 15 ps, laser frequency 10 MHz, laser power 20 W, scanning speed 50 m / s; the alkaline solution is a KOH solution with a concentration of 2.5 wt%, and the solution temperature is 48℃; (4) The second polar doped layer is prepared on the first surface of the intermediate cell obtained in step (3); wherein the second polar doped layer is formed by LPCVD deposition and the doping method of the first polar doped layer is gas source thermal diffusion; the process parameters of LPCVD deposition include: deposition temperature 650℃, deposition time 70 min, and the process parameters of gas source thermal diffusion include: diffusion temperature 860℃, diffusion time 120 min. (5) Perform a second patterning process on the intermediate battery cell obtained in step (4) to remove the second polar doped layer on the area covered by the isolation region and the first polar doped layer; wherein, the second patterning process can be performed by photoresist mask + chemical etching; positive photoresist is used to ensure development accuracy, the isolation region is designed to be 5 μm wide, and a KOH solution with a concentration of 2.5 wt% is used at a solution temperature of 48°C to etch and remove the lower layer to obtain the second polar doped layer, forming the isolation region while exposing the first polar doped layer; (6) A passivation layer is prepared on the surface of the first polar doped layer, the second polar doped layer and the isolation region of the intermediate cell obtained in step (5); (7) A passivation layer is prepared on the second surface of the intermediate battery cell obtained in step (6).

[0140] (8) A first electrode and a second electrode are prepared on the first surface of the intermediate cell obtained in step (7), so that the first electrode forms an electrical contact with the first polar doped layer and the second electrode forms an electrical contact with the second polar doped layer, thereby obtaining the solar cell.

[0141] Example 3 This embodiment provides a solar cell, such as Figure 2 As shown, the semiconductor substrate includes a first surface and a second surface disposed opposite to each other. A first polar doped layer, a second polar doped layer, and an isolation region are disposed on the first surface, and the first polar doped layer and the second polar doped layer have different doping types. The first polar doped layer surrounds the second polar doped layer, and the outer contour boundary of the first polar doped layer is continuously disposed along the edge of the first surface to form a closed pattern. On the first surface of the semiconductor substrate, the first polar doped layer and the second polar doped layer are arranged at intervals. The isolation region is disposed between the first polar doped layer and the second polar doped layer.

[0142] The first polar doped layer 11 has a spacer between its two parallel edges and the first surface; the semiconductor substrate is rectangular, and the spacer is disposed on the four edges of the first surface; the width w of the spacer is 15 μm.

[0143] The outer contour boundary of the first polar doped layer has a serrated morphology extending from the first polar doped layer to the edge of the first surface, and a scale-like undulating structure is provided on the substrate surface between the outer contour boundary of the first polar doped layer and the edge of the first surface; the distance difference between the peak and trough of the serrated morphology to the edge of the first surface is 7 μm; the scale-like undulating structure is distributed in two layers along the thickness direction of the substrate; and the scale-like undulating structure is gradient distributed along the thickness direction of the substrate; wherein, the dimension d1 of the undulating structure in the region near the first surface from the first polar doped layer to the edge of the first surface is 60% of the dimension d2 of the undulating structure in the region away from the first surface.

[0144] The first polar doped layer is distributed in a continuous grid structure, forming a mesh region enclosed by the grid; the second polar doped layer is disposed in the mesh region, and the isolation region is disposed between the first polar doped layer and the second polar doped layer; the first polar doped layer 11 is distributed in a continuous grid structure, forming a mesh region enclosed by the grid, and the mesh region has an extended continuous structure; that is, the second polar doped layer 12 has an extended continuous structure. The mesh area is rectangular in shape, with each rectangular mesh having a width of 0.55 mm and a length of 175 mm. The center-to-center distance between two adjacent rectangular meshes along the width direction is 1.05 mm. The meshes are arranged in an array on the first surface according to the above dimensions. In a single rectangular mesh, the area ratio between the second polar doped layer and the isolation region is 4.5:1. The total area of ​​the second polar doped layer accounts for 45% of the total area of ​​the first surface; the total area of ​​the isolation region accounts for 8% of the total area of ​​the first surface. The outer contour boundary of the first polar doped layer is disposed adjacent to the edge of the first surface of the semiconductor substrate; a heavily doped region is disposed between the outer contour boundary of the first polar doped layer and the edge of the first surface; wherein the ratio of the doping concentration of the heavily doped region to the doping concentration of the semiconductor substrate is 50:1. The semiconductor substrate is made of silicon, is an N-type doped substrate, and has an initial doping concentration of 4 E14 atm.cm. -3 The N-type doped substrate contains phosphorus as the dopant; and both the first and second polar doped layers are made of polycrystalline silicon, with the first polar doped layer being an N-type doped layer and the second polar doped layer being a P-type doped layer; the concentration of the N-type doped layer is 3 E20 atm / cm². -3 The concentration of the p-type doped layer is 5 E19 atm.cm. -3 The N-type doped layer is doped with phosphorus, and the P-type doped layer is doped with boron.

[0145] The first polar doped layer, the second polar doped layer, and the isolation region are all provided with passivation layers; and the second surface is provided with a passivation layer; the passivation layer consists of an aluminum oxide layer with a thickness of 5 nm and a silicon nitride layer with a thickness of 85 nm from the inside out.

[0146] The first surface is further provided with a first electrode and a second electrode; wherein the first electrode forms an electrical contact with the first polar doped layer, and the second electrode forms an electrical contact with the second polar doped layer.

[0147] The method for preparing a solar cell described in this embodiment includes: (1) The semiconductor substrate is texturized; (2) The first polar doped layer is prepared on the first surface of the semiconductor substrate described in step (1); wherein the first polar doped layer is formed by LPCVD deposition and the doping method of the first polar doped layer is gas source thermal diffusion; the process parameters of LPCVD deposition include: deposition temperature 650℃, deposition time 90 min, and the process parameters of gas source thermal diffusion include: diffusion temperature 910℃, diffusion time 150 min. (3) Perform a first patterning process on the intermediate battery cell obtained in step (2) to remove the second polar doped layer and the first polar doped layer at the location of the isolation region; wherein, the first patterning process can be performed by laser etching + alkaline solution etching method; laser etching removes the silicon oxide layer on the surface of the second polar doped layer and the isolation region, and then alkaline solution etching removes the lower first polar doped layer; the process parameters of laser etching include: laser pulse width 15 ps, laser frequency 10 MHz, laser power 20 W, scanning speed 50 m / s; the alkaline solution is a KOH solution with a concentration of 2.5 wt%, and the solution temperature is 48℃; (4) The second polar doped layer is prepared on the first surface of the intermediate cell obtained in step (3); wherein the second polar doped layer is formed by LPCVD deposition and the doping method of the first polar doped layer is gas source thermal diffusion; the process parameters of LPCVD deposition include: deposition temperature 650℃, deposition time 70 min, and the process parameters of gas source thermal diffusion include: diffusion temperature 860℃, diffusion time 120 min. (5) Perform a second patterning process on the intermediate battery cell obtained in step (4) to remove the second polar doped layer on the area covered by the isolation region and the first polar doped layer; wherein, the first patterning process can be performed by laser etching + alkaline solution etching method; laser etching removes the silicon oxide layer on the surface of the first polar doped layer and the isolation region, and then alkaline solution etching removes the lower second polar doped layer; the process parameters of laser etching include: laser pulse width 15 ps, laser frequency 10 MHz, laser power 20 W, scanning speed 50 m / s; the alkaline solution is a KOH solution with a concentration of 2.5 wt% and a solution temperature of 48℃; (6) A passivation layer is prepared on the surface of the first polar doped layer, the second polar doped layer and the isolation region of the intermediate cell obtained in step (5); (7) A passivation layer is prepared on the second surface of the intermediate battery cell obtained in step (6).

[0148] (8) A first electrode and a second electrode are prepared on the first surface of the intermediate cell obtained in step (7), so that the first electrode forms an electrical contact with the first polar doped layer and the second electrode forms an electrical contact with the second polar doped layer, thereby obtaining the solar cell.

[0149] Example 4 This embodiment provides a solar cell, which differs from Embodiment 1 only in that the ratio of the doping concentration of the heavily doped region to the doping concentration of the semiconductor substrate is 10, while the other steps are the same as in Embodiment 1.

[0150] Example 5 This embodiment provides a solar cell, which differs from Embodiment 1 only in that the surface doping concentration of the heavily doped region is 100 times the original doping concentration of the semiconductor substrate, while the other steps are the same as in Embodiment 1.

[0151] Example 6 This embodiment provides a solar cell, which differs from Embodiment 1 only in that the heavily doped region is not provided, and no doped layer is provided between the outer contour boundary of the first polar doped layer and the edge of the first surface. The other steps are the same as in Embodiment 1.

[0152] Example 7 This embodiment provides a solar cell, which differs from Embodiment 1 only in that the width w of the spacing portion is 1 μm, while the other steps are the same as in Embodiment 1.

[0153] Example 8 This embodiment provides a solar cell, which differs from Embodiment 1 only in that the width w of the spacing portion is 50 μm, while the other steps are the same as in Embodiment 1.

[0154] Example 9 This embodiment provides a solar cell, which differs from Embodiment 1 only in that the width w of the spacing portion is 0.5 μm, while the other steps are the same as in Embodiment 1.

[0155] Example 10 This embodiment provides a solar cell, which differs from Embodiment 1 only in that the width w of the spacing portion is 100 μm, while the other steps are the same as in Embodiment 1.

[0156] Comparative Example 1 This comparative example provides a solar cell, which differs from Example 1 only in that the first polar doped layer is no longer arranged around the second polar doped layer, but the first polar doped layer and the second polar doped layer are arranged in a traditional interdigitated shape, and the polarity of the doped layers arranged on the surfaces of the opposite first edge and second edge regions is different. The other steps are the same as in Example 1.

[0157] Comparative Example 2 This comparative example provides a solar cell, differing from Example 1 only in that the outer contour boundary of the first polar doped layer is discontinuously arranged along the edge of the first surface, forming a non-closed pattern; the outermost ring of the first polar doped layer's grid has openings of 0.55 mm (e.g., ...). Figure 7 (As shown), the other steps are the same as in Example 1.

[0158] Test Example 1 Test samples: solar cells provided in Examples 1-10 and solar cells provided in Comparative Examples 1-2.

[0159] Test method: Standard test conditions (STC): Light intensity: 1000 W / m 2 ; Spectrum: AM1.5; Temperature: 25℃.

[0160] The test results are shown in Table 1 below: Table 1

[0161] As shown in Table 1, the continuous mesh doped layer on the back side of the back-contact solar cell of the present invention connects all regions of the cell into a whole. This allows any part of the cell, even if the metal electrode fails and cannot output charge carriers, to at least transmit charge carriers to the adjacent electrode region through the doped layer, thereby effectively reducing power loss in the event of partial metal electrode failure. At the same time, it also reduces the interface length between the charge carrier selective region and the isolation region, while increasing the area of ​​the charge carrier selective region with excellent passivation effect. Therefore, it improves the overall passivation effect of the back side of the cell, reduces charge carrier recombination, and improves the open-circuit voltage Uoc and conversion efficiency of the cell.

[0162] As shown by the comparison between Examples 1 and Examples 4-5, in the solar cell of the present invention, a heavily doped region of the same type as the doped layer is provided between the outer contour boundary of the first polar doped layer and the edge of the substrate, which can effectively improve the conversion efficiency and open-circuit voltage of the cell. However, its performance gain is extremely sensitive to the concentration of heavy doping. Experimental data show that the performance is optimal when the heavy doping concentration is about 20 times that of the original substrate doping concentration; if the concentration is too low (e.g., 10 times), the gain effect is not obvious; if the concentration is too high (e.g., 100 times), it will introduce too many defects, leading to increased carrier recombination, which will damage the cell performance. Therefore, there exists an optimal range of heavy doping concentration to maximize performance.

[0163] As shown by the comparison between Examples 1 and 6, setting a heavily doped region of the same type as the first polar doped layer between the outer contour boundary of the first polar doped layer and the edge of the substrate can effectively improve the carrier collection efficiency of the battery edge region through the field passivation effect, reduce recombination losses, and thus significantly improve the open-circuit voltage and overall conversion efficiency of the battery. This technical feature has a positive effect on improving device performance.

[0164] As shown by the comparison of Examples 1, 7-8 and 9-10, the width of the gap between the first polar doped layer and the edge of the first surface needs to be maintained within a reasonable range. If the gap width is too low, it cannot effectively isolate the edge region of the silicon wafer, resulting in increased carrier recombination and affecting the Uoc and FF of the battery. If the gap width is too large, the area of ​​the polar doped layer becomes smaller, reducing the collection efficiency of carriers and affecting the Uoc and Isc of the battery, resulting in a decrease in battery efficiency.

[0165] As shown by the comparison between Example 1 and Comparative Example 1, the core difference between Example 1 (the first polar doped layer is arranged in a continuous grid pattern and surrounds the second polar doped layer) and Comparative Example 1 (the traditional interdigitated arrangement) lies in the arrangement of the back doped layer. The structure in which the first polar doped layer continuously surrounds the second polar doped layer can reduce the total length of the interface between the selective region and the isolation region, reduce the severe carrier recombination loss at the interface, and optimize the back electric field distribution and carrier transport path, thereby effectively improving the overall passivation effect and photoelectric conversion performance of the battery.

[0166] As shown by the comparison between Example 1 and Comparative Example 2, maintaining the continuity and closure of the outer contour boundary of the first polar doped layer along the substrate edge is crucial. This design ensures that the doping type is completely consistent in the cell edge region, effectively reducing edge recombination and enhancing the continuity of carrier lateral transport. Once the contour is interrupted, even a tiny opening will destroy this integrity, leading to a decrease in passivation effect and electrical performance.

[0167] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A solar cell, characterized in that, The semiconductor substrate includes a first surface and a second surface disposed opposite to each other. A first polar doped layer, a second polar doped layer and an isolation region are disposed on the first surface, and the first polar doped layer and the second polar doped layer have different doping types. The first polar doped layer surrounds the second polar doped layer, and the outer contour boundary of the first polar doped layer is continuously arranged along the edge of the first surface to form a closed pattern. The first polar doped layer has a gap between at least two parallel edges of the first surface.

2. The solar cell according to claim 1, characterized in that, The outer contour boundary of the first polar doped layer has a serrated shape extending from the edge of the first polar doped layer toward the first surface. And / or, the substrate surface between the outer contour boundary of the first polar doped layer and the edge of the first surface is provided with a scale-like undulating structure; And / or, the distance difference d between the peaks and troughs of the sawtooth morphology and the edge of the first surface is 2~20 μm; And / or, the scaly undulating structure has at least one layer distributed along the thickness direction of the substrate; And / or, when the scale-like undulating structure has two or more layers distributed along the thickness direction of the substrate, the scale-like undulating structure is distributed in a gradient along the thickness direction of the substrate; wherein, in the direction intersecting with the edge of the first surface, the size d1 of the undulating structure in the region close to the first surface from the first polar doped layer to the edge of the first surface is less than the size d2 of the undulating structure in the region far from the first surface. And / or, the dimension d1 of the undulating structure in the region near the first surface from the first polar doped layer toward the edge of the first surface is 50 to 95% of the dimension d2 of the undulating structure in the region away from the first surface.

3. The solar cell according to claim 1 or 2, characterized in that, The first polar doped layer is distributed in a continuous grid structure to form a mesh region enclosed by the grid; wherein, the second polar doped layer is disposed in the mesh region, and the isolation region is disposed between the first polar doped layer and the second polar doped layer; And / or, the shape of the mesh area includes any one of the following: circle, rectangle, regular polygon, and irregular polygon; And / or, the spacing between the centers of two adjacent mesh openings is 0.05~5 mm; And / or, the ratio of the perimeter of a single mesh opening to the area of ​​the mesh opening is (0.01~5):1; And / or, in a single mesh, the area ratio between the second polar doped layer and the isolation region is (2~100):1; And / or, the total area of ​​the second polar doped layer accounts for 5 to 50% of the total area of ​​the first surface; the total area of ​​the isolation region accounts for 0.1 to 10% of the total area of ​​the first surface.

4. The solar cell according to claim 1, characterized in that, The outer contour boundary of the first polar doped layer is disposed adjacent to the edge of the first surface of the semiconductor substrate; And / or, a heavily doped region is provided between the outer contour boundary of the first polar doped layer and the edge of the first surface; wherein, the doping concentration of the heavily doped region is greater than the doping concentration of the semiconductor substrate; And / or, the ratio of the doping concentration of the heavily doped region to the doping concentration of the semiconductor substrate is (10~100):

1.

5. The solar cell according to claim 1, characterized in that, The semiconductor substrate is made of any one of silicon, germanium, gallium arsenide, and gallium nitride. And / or, the semiconductor substrate includes an N-type doped substrate or a P-type doped substrate; And / or, the initial doping concentration of the semiconductor substrate is 1 E14 atm.cm. -3 ~1 E16 atm.cm -3 ; And / or, the doping element in the N-type doped substrate includes any one or a combination of at least two of phosphorus, arsenic, antimony, and bismuth; And / or, the doping elements in the P-type doped substrate include any one or a combination of at least two of boron, aluminum, gallium, and indium.

6. The solar cell according to claim 1, characterized in that, The materials of the first polar doped layer and the second polar doped layer each independently include any one of polycrystalline silicon, amorphous silicon, and silicon carbide; And / or, when the first polar doped layer is a P-type doped layer, the second polar doped layer is an N-type doped layer; when the first polar doped layer is an N-type doped layer, the second polar doped layer is a P-type doped layer. And / or, the concentration of the N-type doped layer is 1 E20~1 E21 atm.cm -3 The concentration of the p-type doped layer is 1 E19~1 E20 atm.cm. -3 ; And / or, the doping elements in the N-type doped layer include any one or a combination of at least two of phosphorus, arsenic, antimony, and bismuth; And / or, the doping elements in the P-type doped layer include any one or a combination of at least two of boron, aluminum, gallium, and indium.

7. The solar cell according to claim 1, characterized in that, A passivation layer is provided on the surface of the first polar doped layer, the second polar doped layer, and the isolation region; and a passivation layer is provided on the second surface. And / or, the material of the passivation layer includes any one or a combination of at least two of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, and titanium oxide; And / or, the thickness of the passivation layer is 1~100 nm; And / or, a first electrode and a second electrode are further disposed on the first surface; wherein the first electrode forms an electrical contact with the first polar doped layer, and the second electrode forms an electrical contact with the second polar doped layer.

8. A method for preparing a solar cell according to any one of claims 1 to 7, characterized in that, include: The first polar doped layer is prepared on the first surface of the semiconductor substrate; Remove the first polar doped layer at the location of the second polar doped layer and the isolation region; The second polar doped layer is prepared on the first surface; The second polar doped layer is removed from the area covered by the isolation region and the first polar doped layer to obtain the solar cell.

9. The method for preparing a solar cell according to claim 8, characterized in that, After the step of removing the second polar doped layer at the location of the isolation region and the coverage area of ​​the first polar doped layer, and before obtaining the solar cell, the method further includes: first preparing a passivation layer on the surface of the first polar doped layer, the second polar doped layer and the isolation region, and then preparing a passivation layer on the second surface.

10. A photovoltaic module, characterized in that, The photovoltaic module includes a solar cell as described in any one of claims 1 to 7 or a solar cell obtained by the preparation method as described in any one of claims 8 or 9.