Solder thickness determination method and device, electronic equipment, chip and storage medium

Abstract

The invention relates to a solder thickness determination method and device, electronic equipment, a chip and a storage medium, and belongs to the technical field of semiconductors. The method comprises the steps that a target packaging type of the power semiconductor is determined, thickness information of a composition structure with a fixed height in the power semiconductor is determined according to the target packaging type, the target height of the power semiconductor is determined, and the target height is the distance between a specified surface in the power semiconductor and a welded surface of a radiator. The specified surface is the surface farthest from the welded surface in the power semiconductor under the target packaging type, and the solder thickness of the solder layer is determined according to the target height and thickness information. Nondestructive detection of the thickness of the solder layer of the power semiconductor module can be realized, a product does not need to be cut open to observe the thickness of the solder layer, the phenomenon that the detection module is scrapped due to monitoring is avoided, the detection cost is reduced, the detection time efficiency is improved, large-scale sampling or full-amount detection can be performed due to nondestructive detection, and the detection efficiency is improved. And the overall production quality can be ensured.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method, apparatus, electronic device, chip, and storage medium for determining solder thickness. Background Technology

[0002] The core function of a power semiconductor module is to convert the direct current (DC) from a high-voltage battery into alternating current (AC) to drive the motor. During operation, the module draws a large current, generating significant heat, which must be dissipated by a heat sink within the module. In related technologies, the heat sink is typically connected to the power semiconductor module via soldering. However, the solder thickness often affects product performance and lifespan. For example, excessively thick solder results in high thermal resistance and low product performance, while insufficiently thick solder leads to high stress, making it prone to thermal stress cracking over long-term use, resulting in poor thermal conductivity and performance degradation. Therefore, the solder thickness of power semiconductor modules is a key concern, and non-destructive testing of solder thickness has become a research hotspot. Summary of the Invention

[0003] This disclosure provides a method, apparatus, electronic device, chip, and storage medium for determining solder thickness, to at least achieve non-destructive testing of solder thickness in power semiconductor modules.

[0004] The technical solution disclosed herein is as follows: According to a first aspect of the present disclosure, a method for determining solder thickness is provided, applicable to a power semiconductor module, the power semiconductor module comprising: a heat sink, a solder layer, and a power semiconductor, wherein the solder layer is used to fix the power semiconductor to the heat sink, the method comprising: Determine the target package type for the power semiconductor module; Based on the target package type, determine the thickness information of the constituent structure with a fixed height in the power semiconductor; Determine the target height of the power semiconductor, wherein the target height is the distance between a specified surface of the power semiconductor and the surface of the heat sink to be soldered, and the specified surface is the surface of the power semiconductor that is furthest from the surface to be soldered under the target package type; The solder thickness of the solder layer is determined based on the target height and the thickness information.

[0005] According to a second aspect of the present disclosure, a solder thickness determining apparatus is provided, suitable for a power semiconductor module, the power semiconductor module comprising: a heat sink, a solder layer, and a power semiconductor, the solder layer being used to fix the power semiconductor to the heat sink, the apparatus comprising: The first determining module is configured to determine the target package type of the power semiconductor; The second determining module is configured to determine the thickness information of the constituent structure with a fixed height in the power semiconductor according to the target package type. The third determining module is configured to determine the target height of the power semiconductor, wherein the target height is the distance between a specified surface in the power semiconductor module and the surface of the heat sink to be welded, and the specified surface is the surface of the power semiconductor in the target package type that is farthest from the surface to be welded; The fourth determining module is configured to determine the solder thickness of the solder layer based on the target height and the thickness information.

[0006] According to a third aspect of the present disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the solder thickness determination method described in the first to third aspects of the present disclosure.

[0007] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided that stores computer program instructions thereon, which, when executed by a processor, implement the steps of the solder thickness determination method described in the first to third aspects of the present disclosure.

[0008] According to a fifth aspect of the present disclosure, a chip is provided, the chip including an interface circuit and a processing circuit coupled to each other, the interface circuit being used to input or output signals, and the processing circuit being configured to implement the steps of the solder thickness determination method described in the first to third aspects of the present disclosure.

[0009] According to a sixth aspect of the present disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the solder thickness determination method described in the first to third aspects of the present disclosure.

[0010] The technical solutions provided by the embodiments of this disclosure have at least the following beneficial effects: This invention enables non-destructive testing of solder layer thickness in power semiconductor modules, eliminating the need to cut the product to observe the solder layer thickness. This avoids the phenomenon of modules being scrapped due to testing issues, thereby reducing testing costs and improving testing efficiency. Moreover, because it is non-destructive testing, it allows for large-scale sampling or full-scale testing, ensuring overall production quality. Furthermore, during online module production, fluctuations in raw material prices, equipment, and process parameters may occur, leading to variations in solder thickness. This invention allows for online detection of solder layer thickness, effectively monitoring and reporting these fluctuations during online module production. This prevents the scrapping of large batches of modules due to these fluctuations, reducing product scrap rates and saving resources and costs.

[0011] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0013] Figure 1 This is a schematic flowchart illustrating a method for determining solder thickness according to an exemplary embodiment.

[0014] Figure 1a This is a schematic diagram of the structure of a power semiconductor module according to an exemplary embodiment.

[0015] Figure 1b This is a schematic diagram of the structure of another power semiconductor module according to an exemplary embodiment.

[0016] Figure 1c This is a schematic diagram of the structure of another power semiconductor module according to an exemplary embodiment.

[0017] Figure 1d This is a schematic diagram of the structure of another power semiconductor module according to an exemplary embodiment.

[0018] Figure 2 This is a flowchart illustrating another method for determining solder thickness according to an exemplary embodiment.

[0019] Figure 2a This is a schematic diagram of the structure of another power semiconductor module according to an exemplary embodiment.

[0020] Figure 3 This is a flowchart illustrating another solder thickness determination method according to another exemplary embodiment.

[0021] Figure 3a This is a schematic diagram of the structure of another power semiconductor module according to an exemplary embodiment.

[0022] Figure 4 This is a process intention of another solder thickness determination method illustrated according to another exemplary embodiment.

[0023] Figure 4a This is a schematic diagram of the structure of another power semiconductor module according to an exemplary embodiment.

[0024] Figure 5 This is a flowchart illustrating another solder thickness determination method according to another exemplary embodiment.

[0025] Figure 5a This is a structural layout diagram of a power semiconductor surface according to an exemplary embodiment.

[0026] Figure 6 This is a schematic diagram of a solder thickness determination device according to an exemplary embodiment.

[0027] Figure 7 This is a schematic diagram of the structure of an electronic device according to an exemplary embodiment.

[0028] Figure 8 This is a schematic diagram of the structure of a chip according to an exemplary embodiment. Detailed Implementation

[0029] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0030] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0031] The core function of a power semiconductor module is to convert the direct current (DC) from a high-voltage battery into alternating current (AC) to power the drive motor. During operation, the power semiconductor module draws a large current, generating significant heat. This heat must be dissipated by a heat sink within the module. In related technologies, the heat sink is typically connected to the power semiconductor module via soldering. The thickness of the solder layer significantly impacts product performance and lifespan. For example, excessively thick solder results in high thermal resistance and low product performance, while insufficiently thick solder leads to high welding stress, making it prone to thermal stress cracking over long-term use, resulting in poor thermal conductivity and performance degradation. Therefore, the solder layer thickness is a critical concern.

[0032] In related technologies, destructive testing of power semiconductor modules, such as cutting open the product to observe the solder layer thickness, renders the product unusable. This method is costly, suitable only for small-scale sampling, and cannot guarantee overall production quality. Therefore, in the field of power semiconductor module manufacturing, how to perform non-destructive testing of the solder layer thickness has become a research hotspot.

[0033] The following description, with reference to the accompanying drawings, outlines a method, apparatus, electronic device, chip, and storage medium for determining the solder thickness of a power semiconductor module according to embodiments of the present disclosure.

[0034] Figure 1 This is a schematic flowchart illustrating a method for determining solder thickness according to an exemplary embodiment.

[0035] It should be noted that the entity executing the solder thickness determination method of this disclosure is a hardware device with data processing capabilities and / or the necessary software to drive the hardware device. For example, it can be executed by the solder thickness determination device of this disclosure, which can be configured in any electronic device to execute the solder thickness determination method of this disclosure.

[0036] In any embodiment of this application, the electronic device may include a terminal, product testing equipment, product testing platform, host computer, chip, product testing service, and server, etc. Optionally, the terminal may be a user device, personal computer, etc. Optionally, the server may be a cloud server, a distributed system server, or a server combined with blockchain, etc.

[0037] In any embodiment of this application, the chip can be integrated into an electronic device. The chip includes a Central Processing Unit (CPU), an Image Signal Processing (ISP), an Application-Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Field-Programmable Gate Array (FPGA), a System-on-Chip (SOC), a Reduced Instruction Set Computer (RISC), etc., which will not be listed here.

[0038] like Figure 1a As shown, the power semiconductor module includes a heat sink 1, a solder layer 2, and a power semiconductor 3. The power semiconductor 3 is a functional component that converts DC to AC current. The heat sink 1 provides mounting and heat dissipation for it. The solder layer 2 is used to fix the power semiconductor 3 to the heat sink 1 and provides a heat conduction path for the power semiconductor 3. Uniform solder thickness in the solder layer 2 is a key indicator for ensuring balanced connection and heat dissipation. For example, if the solder layer is too thick, the thermal resistance is high, resulting in insufficient heat dissipation, limiting the current carrying capacity of the power semiconductor, and degrading its performance. Conversely, if the solder layer is too thin, the stress is high, posing a risk of durability cracking.

[0039] In some embodiments, the heat sink 1 may be one or more of the following materials: aluminum, aluminum alloy, copper, copper alloy, aluminum silicon carbide (AlSiC), diamond copper, graphite copper, diamond aluminum, graphite aluminum, plastic, etc., which are suitable for various heat dissipation structure solutions.

[0040] In some embodiments, the power semiconductor 3 may be a silicon (Si)-based or silicon carbide (SiC)-based semiconductor device, suitable for various semiconductor packaging forms.

[0041] In some embodiments, the solder used in solder layer 2 can be any solder, such as tin (Sn) based solder, indium (In) based solder, lead (Pb) based solder, copper (Cu) based solder, silver (Ag) based solder, etc.

[0042] In some embodiments, such as Figure 1b and 1cAs shown, the power semiconductor 3 may include a substrate 31 and a molding compound 32, the molding compound 32 being used to encapsulate the substrate 31. A chip is fixed on the substrate 31, and the molding compound 32 is used to encapsulate the substrate 31. Optionally, the substrate 31 is a ceramic substrate.

[0043] In some embodiments, such as Figure 1d As shown, the power semiconductor 3 may include a substrate 31, a molding compound 32, a device solder layer 33, and a device 34. The chip is fixed on the substrate, the molding compound is used to encapsulate the substrate, and the device 34 is fixed to the upper surface of the substrate 31 through the device solder layer 33.

[0044] In some embodiments, the substrate 31 may be a ceramic substrate, a metal substrate, or a composite material substrate, etc.

[0045] In some embodiments, the soldered device 34 may be a metal block, a metal plate, a printed circuit board (PCB), a copper-clad ceramic plate, a passive device, etc.

[0046] In some embodiments, a first packaging type can be used to package the power semiconductor. The power semiconductor packaged using the first packaging type can be referred to as a planar power semiconductor. This definition applies to all embodiments of this application and will not be further elaborated upon thereafter. Figure 1b As shown, a planar power semiconductor refers to a power semiconductor in which the upper surface of the substrate 31 is completely covered by the encapsulant 32. Optionally, the upper surface of the substrate 31 may or may not have signal pins.

[0047] In some embodiments, a second packaging type can be used to package the power semiconductor. The power semiconductor packaged using the second packaging type can be referred to as a bare-bottom power semiconductor. This definition applies to all embodiments of this application and will not be further elaborated upon thereafter. Figure 1c As shown, a bare-bottom power semiconductor refers to a power semiconductor on the upper surface of substrate 31 where a portion is not covered by the encapsulator 32. Optionally, the upper surface of substrate 31 may or may not have signal pins.

[0048] In some embodiments, a third packaging type can be used to package the power semiconductor. The power semiconductor packaged using the third packaging type can be referred to as a device-type power semiconductor. This definition applies to all embodiments of this application and will not be further elaborated upon thereafter. Figure 1d As shown, the device-type power semiconductor is a power semiconductor in which the solder layer 33 is completely covered by the molding compound 32, but the upper surface of the device 34 is not covered by the molding compound 34. Optionally, the upper surface of the substrate 31 may or may not have signal pins.

[0049] like Figure 1As shown, the solder thickness determination method of this disclosure embodiment may include, but is not limited to, the following steps: S101, Determine the target package type for the power semiconductor.

[0050] In some embodiments, the target package type of the power semiconductor module may include, but is not limited to, one of the following types: The first package type is the planar package type; The second package type is the bare bottom package type; The third packaging type is the device-type packaging type.

[0051] In some embodiments, the target package type of the power semiconductor can be input by the user.

[0052] In some embodiments, images of the power semiconductor module can be acquired to determine the target package type of the power semiconductor. Optionally, QR codes, barcodes, or text information on the surface of the power semiconductor module can be acquired to determine the target package type of the power semiconductor.

[0053] S102, based on the target package type, determine the thickness information of the constituent structure with a fixed height in the power semiconductor.

[0054] In some embodiments, once the target package type is determined, the mapping relationship between the package type and the constituent structure can be queried based on the target package type to determine the thickness information of the constituent structure with a fixed height in the power semiconductor under the target package type.

[0055] In some embodiments, the thickness information of the constituent structures with a fixed height in the power semiconductor can be obtained through sampling inspection before batch production. For example, before batch production, the substrate thickness is sampled multiple times, and the average of the substrate thicknesses obtained from multiple sampling inspections is taken as the substrate thickness for batch production. As another example, during the development phase, multiple batches of sampling, cutting, and observation can be performed to obtain the thickness of the molding compound and the device solder layer. The average of the observed molding compound thickness and device solder layer thicknesses is then calculated to obtain the thickness of the molding compound and device solder layer for batch production. Yet another example is that during the development phase, multiple batches of devices are sampled and measured to obtain multiple measured thicknesses of the device, and the average of these multiple measured thicknesses is taken as the fourth thickness of the device produced in any batch during mass production.

[0056] It should be noted that the thickness of the molding compound, the solder layer, and the device thickness only need to be measured during the development phase, and the thicknesses of these components should be used as constants during mass production. The substrate thickness, however, can be obtained by sampling the substrate raw materials before each batch of production and used as a constant for that batch.

[0057] In some embodiments, the target package type is a first package type, namely a planar package type, and the thickness information of the component structure with a fixed height in the power semiconductor may include the first thickness of the substrate and the second thickness of the molding compound.

[0058] In some embodiments, the target package type is a second package type, namely, a bare-bottom package type, and the thickness information of the constituent structure with a fixed height in the power semiconductor may include the first thickness of the substrate.

[0059] In some embodiments, the target package type is a third package type, namely a device package type. The thickness information of the constituent structure with a fixed height in the power semiconductor may include the first thickness of the substrate, the third thickness of the device solder layer, and the fourth thickness of the device.

[0060] S103, determine the target height of the power semiconductor, wherein the target height is the distance between a specified surface in the power semiconductor and the surface of the heat sink to be soldered.

[0061] In some embodiments, the specified surface corresponds to the target package type of the power semiconductor; that is, different target package types of power semiconductors correspond to different specified surfaces.

[0062] In some embodiments, the specified surface is the surface of the power semiconductor that is furthest from the heat sink in the target package type.

[0063] In some embodiments, such as Figure 1b As shown, the specified surface can be the top surface of the encapsulation 32 in the power semiconductor.

[0064] In some embodiments, the shortest distance from the top surface of the molding compound 32 to the soldered surface of the heat sink 1 is the target height of the power semiconductor module.

[0065] In some embodiments, such as Figure 1c As shown, the designated surface is the surface of the upper surface of the substrate 31 that is not covered by the encapsulant 32.

[0066] In some embodiments, the shortest distance from the surface not covered by the encapsulation 32 to the soldered surface of the heat sink 1 is the target height of the power semiconductor.

[0067] In some embodiments, such as Figure 1d As shown, the designated surface is the top surface of device 34.

[0068] In some embodiments, the shortest distance from the top surface of device 34 to the soldered surface of heat sink 1 is the target height of the power semiconductor.

[0069] S104, determine the solder thickness of the solder layer based on the target height and thickness information.

[0070] In some embodiments, the target height can reflect the overall height of the power semiconductor, which includes the height of each component in the power semiconductor. Based on the thickness information of the component structure with a fixed height, the solder thickness of the solder layer 2 can be determined according to the target height and the aforementioned thickness information.

[0071] Since the target height of a power semiconductor is determined by its internal structural components with fixed height and the thickness of the solder layer, this disclosure allows for the determination of the thickness information of the structural components with fixed height within the power semiconductor based on the target package type, and the measurement of the target height of the power semiconductor. Furthermore, based on the target height and the thickness information, the solder thickness of the solder layer is determined. This disclosure enables non-destructive testing of the solder layer thickness of power semiconductor modules, eliminating the need to cut the product to observe the solder layer thickness. This avoids the phenomenon of testing modules being scrapped due to testing issues, thereby reducing testing costs and improving testing efficiency. Moreover, because it is non-destructive testing, large-scale sampling or full-volume testing can be performed, ensuring overall production quality.

[0072] Furthermore, during online module production, fluctuations in raw materials, equipment, and process parameters may occur, leading to variations in solder thickness. This disclosure allows for online detection of solder thickness in the solder layer, effectively monitoring and providing feedback on solder thickness fluctuations during online module production. This prevents the scrapping of large batches of modules due to these fluctuations, reducing product scrap rates and saving resources and costs.

[0073] Figure 2 This is a flowchart illustrating another method for determining solder thickness according to an exemplary embodiment.

[0074] like Figure 2 As shown, the solder thickness determination method of this disclosure embodiment may include, but is not limited to, the following steps: S201, Determine the target package type for the power semiconductor.

[0075] In some embodiments, the target package type of the power semiconductor can be input by the user.

[0076] In some embodiments, the model information of the power semiconductor module can be determined, and the target package type of the power semiconductor can be determined based on the model information of the power semiconductor module.

[0077] In some embodiments, images of the power semiconductor module can be acquired to determine the target package type of the power semiconductor. Optionally, QR codes, barcodes, or text information on the surface of the power semiconductor module can be acquired to determine the target package type of the power semiconductor.

[0078] S202, in response to the target package type being a first package type, determine the first thickness of the substrate and the second thickness of the molding compound in the power semiconductor.

[0079] In some embodiments, such as Figure 2a As shown, in the first packaging type, namely the planar packaging type, the thickness information of the constituent structure with a fixed height in the power semiconductor can be obtained, including the first thickness h1 of the substrate and the second thickness h2 of the molding compound.

[0080] S203, determine the shortest distance from a specified surface in the power semiconductor to the surface of the heat sink to be soldered, as the target height of the power semiconductor.

[0081] In some embodiments, such as Figure 2a As shown, in the first package type, i.e., the planar package type, the designated surface of the power semiconductor is the top surface of the molding compound. The shortest distance from the top surface of the molding compound to the surface of the heat sink to be soldered can be determined as the target height H of the power semiconductor.

[0082] S204, obtain the first cumulative thickness corresponding to the first thickness and the second thickness, and obtain the first difference between the target height and the first cumulative thickness as the solder thickness of the solder layer. In some embodiments, such as Figure 2a As shown, H represents the relative height from the top surface of the molding compound (the specified surface) to the nearest point on the heat sink surface, h represents the solder thickness, h1 represents the thickness of the ceramic substrate, and h2 represents the thickness of the molding compound above the ceramic substrate. In other words, the target height H includes the first thickness h1 of the substrate, the second thickness h2 of the molding compound, and the solder thickness of the solder layer. For planar packaged power semiconductors, the first thickness h1 of the substrate, the second thickness h2 of the molding compound, and the solder thickness of the solder layer constitute the target height H of this type of power semiconductor.

[0083] In some embodiments, the first thickness h1 and the second thickness h2 are summed to obtain the corresponding first cumulative thickness. Further, the first difference between the target height H and the first cumulative thickness is obtained as the solder thickness h of the solder layer.

[0084] In other words, when the power semiconductor is packaged in the first type, i.e., a planar package, the solder thickness h of the solder layer can be determined using the following formula (1): h = H - h1 - h2 (1) This disclosure enables non-destructive testing of the solder layer thickness of power semiconductor modules, eliminating the need to cut the product open to observe the solder layer thickness. This avoids the phenomenon of testing modules being scrapped due to monitoring issues, thereby reducing testing costs and improving testing efficiency. Moreover, since it is non-destructive testing, it allows for large-scale sampling or full-scale testing, ensuring overall production quality.

[0085] Furthermore, during online module production, fluctuations in raw materials, equipment, and process parameters may occur, leading to variations in solder thickness. This disclosure allows for online detection of solder thickness in the solder layer, effectively monitoring and providing feedback on solder thickness fluctuations during online module production. This prevents the scrapping of large batches of modules due to these fluctuations, reducing product scrap rates and saving resources and costs.

[0086] Figure 3 This is a flowchart illustrating another method for determining solder thickness according to an exemplary embodiment.

[0087] like Figure 3 As shown, the solder thickness determination method of this disclosure embodiment may include, but is not limited to, the following steps: S301, Determine the target package type for the power semiconductor.

[0088] The specific implementation of step S301 can be any of the implementation methods in the various embodiments of this application, and will not be elaborated here.

[0089] S302, in response to the target package type being the second package type, determine the first thickness of the substrate in the power semiconductor.

[0090] In some embodiments, such as Figure 3a As shown, in the second packaging type, namely the bare bottom packaging type, the thickness information of the constituent structure with a fixed height in the power semiconductor can be obtained, including the first thickness h1 of the substrate.

[0091] S303 determines the shortest distance from a specified surface in the power semiconductor to the surface of the heat sink to be soldered, as the target height of the power semiconductor.

[0092] In some embodiments, such as Figure 3a As shown, in the second packaging type, namely the bare bottom packaging type, the designated surface in the power semiconductor is the area on the upper surface of the substrate that is not covered by the molding compound.

[0093] Furthermore, the shortest distance from the surface area not covered by the encapsulation to the surface of the radiator to be welded is determined as the target height H.

[0094] S304, obtain the second difference between the target height and the first thickness of the substrate, as the solder thickness of the solder layer. In some embodiments, such as Figure 3a As shown, H represents the relative height from the surface area not covered by the molding compound (the specified surface) to the nearest point on the heat sink surface, h represents the solder thickness, and h1 represents the thickness of the ceramic substrate. In other words, the target height H includes the first thickness h1 of the substrate and the solder thickness h of the solder layer. For power semiconductors in bare-bottom package type, the first thickness h1 and the solder thickness h of the solder layer constitute the target height H of this type of power semiconductor.

[0095] In some embodiments, a second difference between the target height H and the first thickness h1 of the substrate is obtained as the solder thickness h of the solder layer.

[0096] In other words, when the power semiconductor is packaged in the second package type, i.e., the bare bottom package type, the solder thickness h of the solder layer can be determined using the following formula (2): h = H - h1 (2) This disclosure enables non-destructive testing of the solder layer thickness of power semiconductor modules, eliminating the need to cut the product open to observe the solder layer thickness. This avoids the phenomenon of testing modules being scrapped due to monitoring issues, thereby reducing testing costs and improving testing efficiency. Moreover, since it is non-destructive testing, it allows for large-scale sampling or full-scale testing, ensuring overall production quality.

[0097] Furthermore, during online module production, fluctuations in raw materials, equipment, and process parameters may occur, leading to variations in solder thickness. This disclosure allows for online detection of solder thickness in the solder layer, effectively monitoring and providing feedback on solder thickness fluctuations during online module production. This prevents the scrapping of large batches of modules due to these fluctuations, reducing product scrap rates and saving resources and costs.

[0098] Figure 4 This is a flowchart illustrating another method for determining solder thickness according to an exemplary embodiment.

[0099] like Figure 4 As shown, the solder thickness determination method of this disclosure embodiment may include, but is not limited to, the following steps: S401, determine the target package type for the power semiconductor.

[0100] The specific implementation of step S401 can be any of the implementation methods in the various embodiments of this application, and will not be elaborated here.

[0101] S402, in response to the target package type being the third package type, determines the first thickness of the substrate in the power semiconductor, the third thickness of the device solder layer, and the fourth thickness of the device.

[0102] In some embodiments, such as Figure 4a As shown, under the third packaging type, namely the device type packaging type, the thickness information of the constituent structure with a fixed height in the power semiconductor can be obtained, including the first thickness h1 of the substrate, the third thickness h3 of the device solder layer, and the fourth thickness h4 of the device.

[0103] S403 determines the shortest distance from a specified surface in the power semiconductor to the surface of the heat sink to be soldered, as the target height of the power semiconductor.

[0104] In some embodiments, such as Figure 4a As shown, in the third packaging type, also known as the device-type packaging type, the designated surface in the power semiconductor is the top surface of the device. Furthermore, the shortest distance from the top surface of the device to the surface of the heat sink to which it is soldered is determined as the target height H.

[0105] S404, obtain the second cumulative thickness of the first thickness, the third thickness and the fourth thickness, and obtain the third difference between the target height and the second cumulative thickness as the solder thickness of the solder layer. In some embodiments, such as Figure 4a As shown, H represents the relative height from the top surface (specified surface) of the device to the nearest point on the heat sink surface, h represents the solder thickness, h1 represents the thickness of the ceramic substrate, h3 represents the solder layer of the device, and h4 represents the solder thickness of the solder layer. In other words, the target height H includes the first thickness h1 of the substrate, the third thickness h3 of the device solder layer, the fourth thickness h4 of the device, and the solder thickness h of the solder layer. For power semiconductors in device-type packages, the first thickness h1, the third thickness h3 of the device solder layer, the fourth thickness h4 of the device, and the solder thickness h of the solder layer constitute the target height H of this type of power semiconductor.

[0106] In some embodiments, the first thickness h1, the second thickness h3, and the third thickness h4 are summed to obtain the corresponding second cumulative thickness. Further, the first difference between the target height H and the second cumulative thickness is obtained as the solder thickness h of the solder layer.

[0107] In other words, when the power semiconductor is packaged in the third type, i.e., the device type, the solder thickness h of the solder layer can be determined using the following formula (3): h = H - h1 - h3 - h4 (3) This disclosure enables non-destructive testing of the solder layer thickness of power semiconductor modules, eliminating the need to cut the product open to observe the solder layer thickness. This avoids the phenomenon of testing modules being scrapped due to monitoring issues, thereby reducing testing costs and improving testing efficiency. Moreover, since it is non-destructive testing, it allows for large-scale sampling or full-scale testing, ensuring overall production quality.

[0108] Furthermore, during online module production, fluctuations in raw materials, equipment, and process parameters may occur, leading to variations in solder thickness. This disclosure allows for online detection of solder thickness in the solder layer, effectively monitoring and providing feedback on solder thickness fluctuations during online module production. This prevents the scrapping of large batches of modules due to these fluctuations, reducing product scrap rates and saving resources and costs.

[0109] Figure 5 This is a flowchart illustrating another method for determining solder thickness according to an exemplary embodiment.

[0110] like Figure 5 As shown, the solder thickness determination method of this disclosure embodiment may include, but is not limited to, the following steps: S501 determines the target package type for the power semiconductor.

[0111] The specific implementation of step S501 can be any of the implementation methods in the various embodiments of this application, and will not be elaborated here.

[0112] In some embodiments, steps S502 to S504 are executed in response to the target package type being a planar package type (first package type).

[0113] In some embodiments, in response to the target package type being a bare bottom package type (second package type), steps S505 to S507 are executed.

[0114] In some embodiments, in response to the target package type being a device type package type (third package type), steps S508 to S510 are executed.

[0115] S502, in response to the target package type being a planar package type, obtains the first thickness of the substrate and the second thickness of the molding compound.

[0116] In some embodiments, before batch production, the substrate thickness is sampled multiple times, and the average of the substrate thicknesses sampled multiple times is taken as the first thickness of the substrate for batch production.

[0117] In some embodiments, before batch production, multiple batches can be sampled, cut, and observed during the development phase to obtain the thickness of the encapsulated body. The thickness of the encapsulated body observed multiple times is averaged to obtain a second thickness of the encapsulated body suitable for each batch production.

[0118] S503, determine the shortest distance from the top surface of the encapsulation to the surface of the radiator to be welded as the target height.

[0119] S504, obtain the first cumulative thickness corresponding to the first thickness and the second thickness, and obtain the first difference between the target height and the first cumulative thickness as the solder thickness of the solder layer.

[0120] The specific implementation of steps S502 to S504 can be carried out using any of the implementation methods in the various embodiments of this application, and will not be elaborated here.

[0121] S505, in response to the target package type being a bare bottom package type, obtains the first thickness of the substrate.

[0122] S506, determine the shortest distance from the surface area not covered by the encapsulation to the surface of the radiator to be soldered as the target height.

[0123] S507, obtain the second difference between the target height and the first thickness of the substrate, as the solder thickness of the solder layer.

[0124] The specific implementation of steps S505 to S507 can be carried out using any of the implementation methods in the various embodiments of this application, and will not be described in detail here.

[0125] S508, in response to the target package type being a device package type, obtains the first thickness of the substrate, the third thickness of the device solder layer, and the fourth thickness of the device.

[0126] In some embodiments, during the development phase, multiple batches of sampling, sectioning, and observation can be performed to obtain the thickness of the device solder layer. The thickness of the device solder layer observed multiple times is averaged to obtain the thickness of the device solder layer suitable for each batch of production. For another example, during the development phase, multiple batches of devices can be sampled and measured to obtain multiple measured thicknesses of the device. The average of these multiple measured thicknesses is then used as the fourth thickness of the device in any batch during mass production.

[0127] It should be noted that the thickness of the molding compound, the solder layer, and the device thickness only need to be measured during the development phase, and the thicknesses of these components should be used as constants during mass production. The substrate thickness, however, can be obtained by sampling the substrate raw materials before each batch of production and used as a constant for that batch.

[0128] In this disclosure, sample analysis costs are only incurred during the data collection phase of the development and verification stage. The cost is extremely low and negligible during the stable mass production stage. Furthermore, no offline sample testing time is generated, and test results can be obtained as the samples are produced. This can solve the problems of high cost and long testing cycle of methods such as cross-sectional inspection and industrial CT inspection, and has high testing efficiency.

[0129] S509, determine the shortest distance from the top surface of the device to the surface of the heat sink to be soldered as the target height.

[0130] S510, obtain the second cumulative thickness of the first thickness, the third thickness and the fourth thickness, and obtain the third difference between the target height and the second cumulative thickness as the solder thickness of the solder layer.

[0131] The specific implementation of steps S507 to S510 can be carried out using any of the implementation methods in the various embodiments of this application, and will not be described in detail here.

[0132] In some embodiments, multiple measurement locations on a specified surface of the power semiconductor can be measured to obtain a target height corresponding to each measurement location. Further, based on the target height of each measurement location and the determined thickness information, the solder thickness corresponding to each measurement location is determined as the solder thickness of the solder layer in the power semiconductor. In this embodiment, by measuring at multiple locations, it can be determined whether the solder thickness of the solder layer is uniform.

[0133] In some embodiments, if the solder thickness at multiple measurement locations is not uniform, optimization information for the production and manufacturing of power semiconductor modules can be generated to ensure that the solder thickness in different areas is as uniform as possible, improve the heat dissipation uniformity of chips at different locations, and facilitate stronger chip capabilities.

[0134] In power semiconductor packaging, the solder thickness beneath the chip directly affects thermal resistance and is a key characteristic of the product. After obtaining the solder thickness at multiple measurement locations, data fitting can be performed on the solder thickness at these locations to determine the solder thickness beneath the chip, thus obtaining the final solder layer thickness. Optionally, in response to multiple chips, a target measurement location corresponding to each chip is determined from the multiple measurement locations. Further, a fusion analysis is performed on the solder thickness at the target measurement location corresponding to the chip to obtain the solder thickness beneath the chip. Optionally, linear fitting is performed on the solder thickness at the target measurement location corresponding to the chip to obtain the solder thickness beneath the chip. Optionally, a weighted average is applied to the solder thickness at the target measurement location corresponding to the chip to obtain the solder thickness beneath the chip. For example, the weight can be determined based on the distance between each target measurement location and the chip location.

[0135] In some embodiments, the target measurement position corresponding to the chip can be determined based on the distance between the measurement position and the chip position. At least one measurement position whose distance from the chip meets a set condition can be selected as the target measurement position of the chip. For example, the distances can be sorted from smallest to largest, and the top K measurement positions in the sort can be selected as the target measurement positions of the chip. Optionally, the target measurement position corresponding to the chip can be calibrated during the R&D stage. For example, based on the chip position, the region of chip performance can be predetermined, and the measurement positions within that region can be used as the target measurement positions of the chip.

[0136] Figure 5a This disclosure provides a structural layout diagram of a power semiconductor surface, wherein the shaded boxes indicate chip locations, including chip D1 and chip D2. Square and circular areas represent multiple measurement locations, including P1, P2, P3, P4, and P5. Each measurement location can obtain a corresponding solder thickness according to the above embodiments of this disclosure. To obtain the solder thickness beneath chips D1 and D2, target measurement locations corresponding to chips D1 and D2 can be determined from measurement locations P1, P2, P3, P4, and P5. For example, the target measurement locations corresponding to chip D1 include measurement locations P1, P2, and P3, while the measurement locations corresponding to chip D2 may include measurement locations P4 and P5.

[0137] Furthermore, for chip D1, the solder thickness at positions P1, P2, and P3 can be measured and data fitting performed to obtain the solder thickness below chip D1. For example, the solder thickness h below chip D1 can be determined using the following formula (4). D1 : h D1 =

[0138] Furthermore, for chip D2, the solder thickness at positions P4 and P5 can be measured and data fitting performed to obtain the solder thickness below chip D2. For example, the solder thickness h below chip D2 can be determined using the following formula (5). D2 : h D2 =

[0139] It should be noted that a, b, c, d, and e are constants. During the product development stage, by dissecting and observing several groups of samples, several sets of measured values ​​of D1, D2, P1, P2, P3, P4, and P5 are obtained. Furthermore, least squares fitting can be performed to obtain the optimal values ​​of a, b, c, d, and e, which are used as constants for mass production.

[0140] In some embodiments, after determining the solder thickness of the solder layer, the standard solder thickness range corresponding to the power semiconductor module can be determined based on the model information of the power semiconductor module. Further, in response to the determined solder thickness not being within the solder thickness range, the power semiconductor module is determined to be an abnormal power semiconductor module; in response to the determined solder thickness being within the solder thickness range, the power semiconductor module is determined to be a qualified power semiconductor module.

[0141] In some embodiments, abnormal power semiconductor modules can be flagged as faulty and scrapped.

[0142] In some implementations, the solder thickness of power semiconductor modules within the same batch can be determined individually. The number of qualified power semiconductor modules with solder thicknesses within the specified range can be counted, and / or the number of abnormal power semiconductor modules with solder thicknesses outside the specified range can be identified. Further, based on the number of qualified and / or abnormal power semiconductor modules, the module pass rate for that batch can be determined. If the pass rate of the batch is greater than a set threshold, it can be determined that the module's manufacturing parameters are reasonably designed, and production can continue. If the pass rate of the batch is not greater than the set threshold, it can be determined that the module's manufacturing parameters are unreasonable and need to be optimized to improve the module pass rate.

[0143] In some embodiments, the solder thickness determination method disclosed herein can be applied not only to power semiconductor modules in the motor controllers of new energy vehicles, but also extended to other product fields that use power semiconductor modules, such as photovoltaic inverters, industrial control inverters, and high-voltage frequency converters.

[0144] This disclosure enables non-destructive testing of the solder layer thickness of power semiconductor modules, eliminating the need to cut the product open to observe the solder layer thickness. This avoids the phenomenon of testing modules being scrapped due to monitoring issues, thereby reducing testing costs and improving testing efficiency. Moreover, since it is non-destructive testing, it allows for large-scale sampling or full-scale testing, ensuring overall production quality.

[0145] Furthermore, during online module production, fluctuations in raw materials, equipment, and process parameters may occur, leading to variations in solder thickness. This disclosure allows for online detection of the solder thickness in the solder layer, effectively monitoring and providing feedback on solder thickness fluctuations during online module production. This prevents the scrapping of large batches of modules due to these fluctuations, reducing product scrap rates and saving resources and costs.

[0146] Figure 6This is a schematic diagram illustrating the structure of a solder thickness determining device according to an exemplary embodiment. (Refer to...) Figure 6 The solder thickness determining device 600 of this disclosure includes a first determining module 601, a second determining module 602, a third determining module 603, and a fourth determining module 604. This solder thickness determining device 600 is applicable to power semiconductor modules, which include a heat sink, a solder layer, and a power semiconductor, wherein the solder layer is used to fix the power semiconductor to the heat sink.

[0147] The first determining module 601 is configured to determine the target package type of the power semiconductor module; The second determining module 602 is configured to determine the thickness information of the constituent structure with a fixed height in the power semiconductor according to the target package type. The third determining module 603 is configured to determine the target height of the power semiconductor module, wherein the target height is the distance between a specified surface in the power semiconductor module and the surface of the heat sink to be welded, and the specified surface is the surface of the power semiconductor module that is farthest from the surface to be welded under the target package type; The fourth determining module 604 is configured to determine the solder thickness of the solder layer based on the target height and the thickness information.

[0148] In some embodiments, the second determining module 602 is further configured to perform a determination of a first thickness of the substrate and a second thickness of the molding compound in response to the target packaging type being a first packaging type; wherein the molding compound is used to encapsulate the substrate, and the first packaging type is a type in which the substrate is completely covered by the molding compound.

[0149] In some embodiments, the designated surface is the top surface of the molding compound, and the shortest distance from the top surface of the molding compound to the surface to be welded is the target height.

[0150] In some embodiments, the fourth determining module 604 is further configured to perform the following actions: obtaining a first cumulative thickness corresponding to the first thickness and the second thickness; obtaining a first difference between the target height and the first cumulative thickness as the solder thickness of the solder layer. In some embodiments, the second determining module 602 is further configured to determine a first thickness of the substrate in the power semiconductor in response to the target packaging type being a second packaging type; wherein the power semiconductor further includes a molding compound for encapsulating the substrate, and the second packaging type is a type in which a portion of the upper surface of the substrate is not covered by the molding compound.

[0151] In some embodiments, the designated surface is the surface area on the upper surface of the substrate that is not covered by the molding compound, and the shortest distance from the surface area not covered by the molding compound to the surface to be soldered is the target height.

[0152] In some embodiments, the fourth determining module 604 is further configured to perform a second difference between the target height and the first thickness of the substrate, as the solder thickness of the solder layer. In some embodiments, the second determining module 602 is further configured to perform a process in response to the target package type being a third package type, determining a first thickness of the substrate, a third thickness of the device solder layer, and a fourth thickness of the device in the power semiconductor; wherein the power semiconductor includes a molding compound for encapsulating the substrate, the device is fixed to the upper surface of the substrate by the device solder layer, and the third package type is a package type in which the device solder layer is completely covered by the molding compound, but the upper surface of the device is not covered by the molding compound.

[0153] In some embodiments, the designated surface is the top surface of the device, and the shortest distance from the top surface of the device to the surface to be welded is the target height.

[0154] In some embodiments, the fourth determining module 604 is further configured to perform the following: obtaining a second cumulative thickness of the first thickness, the third thickness, and the fourth thickness; and obtaining a third difference between the target height and the second cumulative thickness as the solder thickness of the solder layer.

[0155] In some embodiments, the third determining module 603 is further configured to perform measurements on multiple measurement locations on the designated surface to obtain the target height corresponding to each measurement location.

[0156] In some embodiments, the fourth determining module 604 is further configured to determine the solder thickness corresponding to each measurement position based on the target height and the thickness information at each measurement position, as the solder thickness of the solder layer.

[0157] In some embodiments, multiple chips are deployed inside the power semiconductor, and the fourth determining module 604 is further configured to perform the following actions after determining the solder thickness corresponding to each measurement location: determining a target measurement location corresponding to the chip from the multiple measurement locations; and fusing the solder thickness corresponding to the target measurement location to determine the solder thickness under the chip.

[0158] In some embodiments, the first determining module 601 is further configured to determine the model information of the power semiconductor module and determine the target package type of the power semiconductor module based on the model information of the power semiconductor module.

[0159] In some embodiments, the fourth determining module 601 is further configured to, after determining the solder thickness of the solder layer, determine the standard solder thickness range corresponding to the power semiconductor module based on the model information of the power semiconductor module; determine the power semiconductor module as an abnormal power semiconductor module in response to the solder thickness not being within the solder thickness range; and / or provide an abnormal prompt for the abnormal power semiconductor module.

[0160] This disclosure enables non-destructive testing of the solder layer thickness of power semiconductor modules, eliminating the need to cut the product open to observe the solder layer thickness. This avoids the phenomenon of testing modules being scrapped due to monitoring issues, thereby reducing testing costs and improving testing efficiency. Moreover, since it is non-destructive testing, it allows for large-scale sampling or full-scale testing, ensuring overall production quality.

[0161] Furthermore, during online module production, fluctuations in raw materials, equipment, and process parameters may occur, leading to variations in solder thickness. This disclosure allows for online detection of solder thickness in the solder layer, effectively monitoring and providing feedback on solder thickness fluctuations during online module production. This prevents the scrapping of large batches of modules due to these fluctuations, reducing product scrap rates and saving resources and costs.

[0162] To implement the above embodiments, this disclosure also proposes an electronic device, such as... Figure 7 As shown, the electronic device 700 includes a processor 701 and a memory 702 for storing processor-executable instructions; wherein the processor 701 is configured to implement embodiments of the present disclosure. Figure 1-5 The steps of the solder thickness determination method shown are for determining the solder thickness of the solder layer inside the power semiconductor.

[0163] To implement the above embodiments, this disclosure also proposes a computer-readable storage medium storing computer program instructions thereon, which, when executed by a processor, implement the steps of the solder layer solder thickness determination method provided in this disclosure.

[0164] Alternatively, the computer-readable storage medium may be ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0165] To implement the above embodiments, this disclosure also proposes a chip including an interface circuit and a processing circuit coupled to each other, the interface circuit being used to input or output signals, and the processing circuit being configured to implement the steps of the solder thickness determination method provided in this disclosure.

[0166] Figure 8This is a schematic diagram illustrating the structure of a chip according to an exemplary embodiment. See also... Figure 8 The diagram shown is a schematic representation of the structure of chip 800, but is not limited to this.

[0167] Chip 800 includes processing circuitry 801, which is configured to perform any of the solder thickness determination methods described above.

[0168] In some embodiments, the chip 800 further includes one or more interface circuits 802. Optionally, the interface circuit 802 is connected to the memory 803, and the interface circuit 802 can be used to receive signals from the memory 360 or other devices, and the interface circuit 802 can be used to send signals to the memory 360 or other devices. For example, the interface circuit 802 can read instructions stored in the memory 803 and send the instructions to the processing circuit 801.

[0169] In some embodiments, the interface circuit 802 performs at least one of the communication steps such as sending and / or receiving in the above method, and the processing circuit 801 performs other steps.

[0170] In some embodiments, the terms interface circuit, interface, transceiver pin, transceiver, etc., can be used interchangeably.

[0171] In some embodiments, chip 800 further includes one or more memories 803 for storing instructions. Optionally, all or part of the memories 803 may be located outside of chip 800.

[0172] To implement the above embodiments, this disclosure also proposes a computer program product, including a computer program that, when executed by a processor, implements the steps of the solder thickness determination method provided in this disclosure.

[0173] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0174] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A method for determining solder thickness, characterized in that, Applicable to a power semiconductor module, the power semiconductor module comprising: a heat sink, a solder layer, and a power semiconductor, the solder layer being used to fix the power semiconductor to the heat sink, the method comprising: Determine the target package type for the power semiconductor; Based on the target package type, determine the thickness information of the constituent structure with a fixed height in the power semiconductor; Determine the target height of the power semiconductor, wherein the target height is the distance between a specified surface of the power semiconductor and the surface to be soldered to the heat sink, and the specified surface is the surface of the power semiconductor that is furthest from the surface to be soldered under the target package type; The solder thickness of the solder layer is determined based on the target height and the thickness information.

2. The method according to claim 1, characterized in that, The step of determining the thickness information of the constituent structure with a fixed height in the power semiconductor according to the target package type includes: In response to the target package type being a first package type, a first thickness of the substrate and a second thickness of the molding compound in the power semiconductor are determined; The molding compound is used to encapsulate the substrate, and the first encapsulation type is a type in which the substrate is completely covered by the molding compound.

3. The method according to claim 2, characterized in that, The designated surface is the top surface of the molding compound, and the shortest distance from the top surface of the molding compound to the surface to be welded is the target height.

4. The method according to claim 2 or 3, characterized in that, Determining the solder thickness of the solder layer based on the target height and the thickness information includes: Obtain the first cumulative thickness corresponding to the first thickness and the second thickness; The first difference between the target height and the first cumulative thickness is obtained as the solder thickness of the solder layer.

5. The method according to claim 1, characterized in that, The step of determining the thickness information of the constituent structure with a fixed height in the power semiconductor according to the target package type includes: In response to the target package type being a second package type, a first thickness of the substrate in the power semiconductor is determined; The power semiconductor further includes a molding compound for encapsulating the substrate, wherein the second encapsulation type is a type in which a portion of the upper surface of the substrate is not covered by the molding compound.

6. The method according to claim 5, characterized in that, The designated surface is the surface area on the upper surface of the substrate that is not covered by the molding compound, and the shortest distance from the surface area not covered by the molding compound to the surface to be soldered is the target height.

7. The method according to claim 5 or 6, characterized in that, Determining the solder thickness of the solder layer based on the target height and the thickness information includes: The second difference between the target height and the first thickness of the substrate is obtained as the solder thickness of the solder layer.

8. The method according to claim 1, characterized in that, The step of determining the thickness information of the constituent structure with a fixed height in the power semiconductor according to the target package type includes: In response to the target package type being a third package type, a first thickness of the substrate, a third thickness of the device solder layer, and a fourth thickness of the device in the power semiconductor are determined. The power semiconductor includes a molding compound for encapsulating the substrate. The device is fixed to the upper surface of the substrate by the device solder layer. The third packaging type is a packaging type in which the device solder layer is completely covered by the molding compound, but the upper surface of the device is not covered by the molding compound.

9. The method according to claim 8, characterized in that, The designated surface is the top surface of the device, and the shortest distance from the top surface of the device to the surface to be welded is the target height.

10. The method according to claim 8 or 9, characterized in that, Determining the solder thickness of the solder layer based on the target height and the thickness information includes: Obtain the second cumulative thickness of the first thickness, the third thickness, and the fourth thickness; The third difference between the target height and the second cumulative thickness is obtained as the solder thickness of the solder layer.

11. The method according to any one of claims 1-3, 5, 6, 7 or 8, characterized in that, The method further includes: Measure multiple measurement positions on the specified surface to obtain the target height corresponding to each measurement position; Based on the target height and thickness information at each measurement location, the solder thickness corresponding to each measurement location is determined and used as the solder thickness of the solder layer.

12. The method according to claim 11, characterized in that, The power semiconductor internally deploys multiple chips. After determining the solder thickness corresponding to each measurement position based on the target height and thickness information at each measurement position, the method further includes: The target measurement position corresponding to the chip is determined from the plurality of measurement positions; The solder thickness at the target measurement location is fused and analyzed to determine the solder thickness under the chip.

13. The method according to any one of claims 1-3, 5, 6, 7 or 8, characterized in that, Determining the target package type of the power semiconductor module includes: Determine the model information of the power semiconductor module; Based on the model information of the power semiconductor module, the target package type of the power semiconductor module is determined.

14. The method according to any one of claims 1-3, 5, 6, 7 or 8, characterized in that, After determining the solder thickness of the solder layer, the method further includes: Based on the model information of the power semiconductor module, determine the standard solder thickness range corresponding to the power semiconductor module; In response to the solder thickness not being within the solder thickness range, the power semiconductor module is determined to be an abnormal power semiconductor module; and / or, an abnormality prompt is given to the abnormal power semiconductor module.

15. A solder thickness determining device, characterized in that, Suitable for power semiconductor modules, the power semiconductor module comprising: a heat sink, a solder layer, and a power semiconductor, the solder layer being used to fix the power semiconductor to the heat sink, the device comprising: The first determining module is configured to determine the target package type of the power semiconductor module; The second determining module is configured to determine the thickness information of the constituent structure with a fixed height in the power semiconductor according to the target package type. The third determining module is configured to determine the target height of the power semiconductor module, wherein the target height is the distance between a specified surface in the power semiconductor module and the surface of the heat sink to be welded, and the specified surface is the surface of the power semiconductor module that is farthest from the surface to be welded under the target package type; The fourth determining module is configured to determine the solder thickness of the solder layer based on the target height and the thickness information.

16. The apparatus according to claim 15, characterized in that, The second determining module is further configured to perform, in response to the target package type being a first package type, determining a first thickness of the substrate and a second thickness of the molding compound within the power semiconductor module; The molding compound is used to encapsulate the substrate, and the first encapsulation type is a type in which the substrate is completely covered by the molding compound.

17. The apparatus according to claim 16, characterized in that, The designated surface is the top surface of the molding compound, and the shortest distance from the top surface of the molding compound to the surface to be welded is the target height.

18. The apparatus according to claim 16 or 17, characterized in that, The fourth determining module is further configured to obtain a first cumulative thickness corresponding to the first thickness and the second thickness, and obtain a first difference between the target height and the first cumulative thickness as the solder thickness of the solder layer.

19. The apparatus according to claim 15, characterized in that, The second determining module is further configured to perform a first thickness of the substrate within the power semiconductor module in response to the target package type being a second package type; The power semiconductor further includes a molding compound for encapsulating the substrate, wherein the second encapsulation type is a type in which a portion of the upper surface of the substrate is not covered by the molding compound.

20. The apparatus according to claim 19, characterized in that, The designated surface is the surface area on the upper surface of the substrate that is not covered by the molding compound, and the shortest distance from the surface area not covered by the molding compound to the surface to be soldered is the target height.

21. The apparatus according to claim 19 or 20, characterized in that, The fourth determining module is further configured to perform a second difference between the target height and the first thickness of the substrate, as the solder thickness of the solder layer.

22. The apparatus according to claim 15, characterized in that, The second determining module is further configured to perform, in response to the target package type being a third package type, to determine the first thickness of the substrate, the third thickness of the device solder layer, and the fourth thickness of the device within the power semiconductor module; The power semiconductor further includes a molding compound for encapsulating the substrate. The device is fixed to the upper surface of the substrate by the device solder layer. The third packaging type is a packaging type in which the device solder layer is completely covered by the molding compound, but the upper surface of the device is not covered by the molding compound.

23. The apparatus according to claim 22, characterized in that, The designated surface is the top surface of the device, and the shortest distance from the top surface of the device to the surface to be welded is the target height.

24. The apparatus according to claim 22 or 23, characterized in that, The second determining module is further configured to perform a second cumulative thickness of obtaining the first thickness, the third thickness, and the fourth thickness, and to obtain a third difference between the target height and the second cumulative thickness as the solder thickness of the solder layer.

25. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the steps of the method according to any one of claims 1-14.

26. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When executed by a processor, the program instructions implement the steps of the method described in any one of claims 1-14.

27. A chip, characterized in that, The chip includes an interface circuit and a processing circuit coupled to each other. The interface circuit is used to input or output signals, and the processing circuit is configured to implement the steps of the method according to any one of claims 1-14.

28. A computer program product, characterized in that, It includes a computer program, which, when executed by a processor, implements the steps of the method according to any one of claims 1-14.

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