Rapid scanning system and method based on YTO

Abstract

The invention discloses a rapid scanning system and method based on YTO, and belongs to the technical field of microwave signal source and frequency synthesis. In order to solve the problem that the scanning speed is limited due to the fact that lock losing is prone to occurring in the start-stop stage due to the hysteresis effect in an existing YTO simulation frequency sweeping scheme, the invention provides a method combining extended scanning and precise gating. According to the method, a wider extended scanning frequency band (F1 to F2) is calculated according to YTO hysteresis characteristics outside a target scanning frequency band (Fstart to Fstop) set by a user. The system controls the YTO to execute high-speed analog scanning in an extended frequency band, meanwhile, the FPGA accurately controls a pulse modulator in a radio frequency channel, signal output is started only when the scanning frequency is in a target frequency band (Fstart to Fstop), and output is closed in extended start-stop transition sections (F1 to Fstart and Fstop to F2). The influence of the hysteresis effect on the stability of the phase-locked loop is effectively avoided, the simulation scanning speed is increased from the traditional hundreds of MHz / ms magnitude to the GHz / ms magnitude, and the test efficiency is remarkably improved.

Description

Technical Field

[0001] This invention belongs to the field of microwave signal source and frequency synthesis technology, specifically relating to a fast scanning system and method based on YTO. Background Technology

[0002] Analog frequency sweeps have wide applications in many fields. In vector network analysis instruments, it is necessary to sweep the frequency in the frequency band to be measured to obtain the frequency characteristics of the device under test. In phase-locked loop tracking performance testing, an analog frequency sweep signal is also needed to simulate the Doppler effect of the actual signal.

[0003] Currently, high-end microwave instruments commonly employ YTO (YIG-Tuned Oscillator) phase-locked loop technology to achieve ultra-low phase noise performance. While YTO brings ultra-low noise, it also limits the scanning speed of analog scanning. Due to the hysteresis effect of YTO, traditional solutions use hysteresis compensation and perturbation to improve scanning speed, but the maximum scanning speed is only a few hundred megahertz per millisecond, which cannot meet the needs of high-end instruments.

[0004] The typical characteristic of hysteresis is that the YTO preset frequency rises slowly during the initial scan, making it easy for the loop to lose lock at the start of the scan. After the scan ends, due to the hysteresis effect, the YTO preset frequency is difficult to decrease quickly, also causing loop lock-up. Therefore, when the scan speed is increased, the initial and final scan frequency bands are prone to lock-up, making it difficult to increase the scan speed. This patent utilizes the characteristics of analog scanning, combining analog scanning with pulse modulation to shield the signals at the start and end of the scan, and synchronously and precisely control the signal switching, thereby achieving rapid scanning while meeting the required scanning accuracy. Ultimately, the scan speed can reach GHz / ms.

[0005] For traditional analog scanning schemes, such as Figure 1 As shown: The reference clock Fclock is divided into two paths: one is the phase detection reference signal, and the other is the FPGA clock signal. The YTO signal coupling output is phase-detected with the reference signal through a frequency divider. The phase detection output signal is integrated to control the YTO. The YTO output signal passes through the RF channel and then reaches the pulse modulator. The pulse modulation function in the whole machine is to realize pulse modulation. The signal is output after passing through the pulse modulator. Before scanning, the computer sends data according to the start frequency, end frequency, and scan time set by the user. When scanning starts: 1. User sets the starting frequency F start Termination frequency F stop and scan time T; 2. Control the starting frequency F via FPGA start Frequency division ratio (frequency division ratio N)start For F start / F clock ); 3. FPGA configuration of YTO presets: Provide compensation data based on the hysteresis effect of YTO; 4. Based on the scan time T, configure the scan time for this segment as T1; 5. Based on the clock frequency F of the frequency division. clock Calculate the division ratio step F of the frequency divider. step =(F stop -F start ) / (T1*F clock ); 6. Calculate the scan time step based on the total time T; 7. After scanning begins, timing control starts counting, and simultaneously, the frequency divider begins to operate according to the divided clock step F. step Accumulation begins. YTO synchronously sends preset data based on the calculated preset value. When time T1 is reached, the timer stops working, and the frequency divider simultaneously stops accumulating. At this time, the frequency division ratio of the frequency divider is N. stop At this point, scanning stops, and the scanning signal remains at the termination frequency; This method has a low scanning speed: due to the YTO hysteresis effect, the preset frequency changes slowly when the analog scan starts and cannot drop quickly when the scan ends, which will cause the loop to lose lock. Therefore, in order to lock the loop smoothly, the scanning speed can only be reduced, and the final scanning speed is only a few hundred MHz / ms.

[0006] With the increasing demands for testing efficiency, there is an urgent need for a technical solution that can overcome the limitations of YTO hysteresis effect and achieve higher-speed analog frequency sweep. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to overcome the defect of the existing YTO-based analog frequency sweep technology which is limited by the hysteresis effect in terms of scanning speed, and to provide a system and method that can significantly improve the analog frequency sweep speed without increasing hardware complexity or significantly sacrificing signal quality.

[0008] To achieve the above objectives, the present invention adopts the following technical solution: A YTO-based fast scanning system includes: YTO, or YIG tuned resonator, is used to generate radio frequency signals; A frequency divider is connected to the output of the YTO and is used to divide the radio frequency signal. A phase detector, whose first input is connected to a reference clock and whose second input is connected to the output of the frequency divider, is used to output a phase error signal; An integrator, whose input is connected to the output of the phase detector and whose output is connected to the tuning terminal of the YTO, together with the phase detector, YTO and frequency divider, forms a phase-locked loop; A radio frequency channel, the input of which is connected to the output of the YTO, is used to transmit the radio frequency signal. A pulse modulator, connected in series in the radio frequency channel, is used to turn the output of the radio frequency signal on or off according to a control signal. The control computer is used to receive scan parameters set by the user. The field-programmable gate array is connected to the control computer, the frequency divider, the preset terminal of the YTO, and the control terminal of the pulse modulator, respectively. The field-programmable gate array is configured to: The system receives scanning parameters from the control computer, including a start frequency Fstart, an end frequency Fstop, and a scanning time T. The extended scanning frequency range is calculated based on the hysteresis characteristics of the YTO. The actual starting frequency F1 of the extended scanning frequency range is lower than Fstart, and the actual ending frequency F2 is higher than Fstop. During the analog frequency scan from F1 to F2, a timing signal is generated to control the change of the division ratio of the frequency divider, and corresponding preset data is sent to the preset terminal of the YTO synchronously. A pulse control signal is generated, which is configured to: control the pulse modulator to turn off when the scan frequency is lower than Fstart and higher than Fstop; and control the pulse modulator to turn on when the scan frequency is within the range of Fstart to Fstop.

[0009] Preferably, the field-programmable gate array is also connected to the reference clock, using the reference clock as the reference clock source for its internal timing generation.

[0010] Furthermore, this invention also mentions a YTO-based fast scanning method, which employs a YTO-based fast scanning system as described above and includes the following steps: S1. Set scan parameters; Receives the scan start frequency Fstart, scan stop frequency Fstop, and scan time T set by the user; S2. Determine the extended scan range; Based on the hysteresis characteristics of the YTO, an extended scanning frequency range is calculated and determined, which has a lower actual start frequency F1 than Fstart and a higher actual stop frequency F2 than Fstop. S3. Perform extended scan and control signal output; The control phase-locked loop system performs an analog frequency scan from the actual start frequency F1 to the actual end frequency F2; During the scanning process, the FPGA controls the operating state of the pulse modulator, enabling: a. When the scanning frequency is in the range of [F1, Fstart), the pulse modulator is turned off, and there is no signal output; b. When the scanning frequency reaches Fstart, control the pulse modulator to turn on and start outputting the scanning signal; c. When the scanning frequency reaches Fstop, control the pulse modulator to turn off and stop outputting the scanning signal; d. Keep the pulse modulator off when the scan frequency is in the range of (Fstop, F2); S4. When the scanning frequency reaches F2, the scanning process is complete.

[0011] Preferably, in step S2, the method for determining the actual start frequency F1 and the actual stop frequency F2 is as follows: by obtaining the hysteresis response curves of the YTO in the start and stop stages through pre-testing or modeling, and by calculating the values ​​of F1 and F2 that can ensure the stable phase-locked loop of the scan signal in the Fstart to Fstop interval based on the response curves and the preset phase-locked loop stability margin.

[0012] Preferably, in step S3, the field-programmable gate array precisely controls the turn-on and turn-off times of the pulse modulator according to the synchronization timing generated by the reference clock, so as to achieve precise synchronization between the scanning frequency and the radio frequency output signal.

[0013] Preferably, in step S3, performing the analog frequency scan specifically includes: The field-programmable gate array (FPGA) calculates the division ratio change step of the frequency divider based on the extended scan range and total scan time. During the scan, the FPGA controls the division ratio of the frequency divider to accumulate according to the step and synchronously sends the corresponding preset voltage data to the YTO to achieve continuous frequency change.

[0014] The beneficial technical effects of this invention are as follows: 1. Significantly increased scan speed: By providing a pre-stabilization and slow-release "buffer" for the phase-locked loop, the direct impact of hysteresis on loop locking at the start and end points of the scan is fundamentally avoided, allowing the system to use higher scan rates without worrying about loss of lock. Scan speeds can be increased from the traditional hundreds of MHz / ms to 1-2 GHz / ms or even higher.

[0015] 2. Ensure output signal quality: The signal is only output within the target frequency band that has been stably locked by the phase-locked loop, ensuring that key indicators such as phase noise and frequency accuracy of the output scanning signal are not affected by the transient process of scanning start and end.

[0016] 3. Low implementation cost: This method does not require additional hardware circuits. It mainly relies on the logic control and algorithm optimization of FPGA. It can be implemented on existing hardware platforms through software upgrades, which has high cost performance and ease of implementation.

[0017] 4. Flexible application: The method is highly universal and applicable to various microwave signal generating devices that use the YTO phase-locked loop scheme, which can significantly improve the dynamic testing performance of such instruments. Attached Figure Description

[0018] Figure 1 This is a control block diagram for a traditional YTO-based analog frequency sweep system.

[0019] Figure 2 This is a control block diagram of a YTO-based fast scanning system provided in an embodiment of the present invention. Detailed Implementation

[0020] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: A preferred embodiment of the present invention combines Figure 2 This will be explained. The system hardware foundation of this embodiment and Figure 1 Similar to the conventional system shown, it includes: a reference clock, a phase detector, a loop filter (integrator), a YTO, a coupler, a frequency divider, an RF channel, a pulse modulator, and an FPGA and a host computer as the control core. The improvements of this invention are mainly reflected in the control logic and algorithms of the FPGA.

[0021] The innovation of this invention lies in the fact that the FPGA controls the pulse modulator to only turn on when the frequency is within the range of Fstart to Fstop, and turns it off in the extended ranges before and after (F1-Fstart, Fstop-F2). For the user, what is observed is a perfect scan signal from Fstart to Fstop with a duration of T.

[0022] The implementation steps of this method are as follows: Step S1: Parameter settings.

[0023] The user sets the desired start frequency Fstart, stop frequency Fstop, and scan time T through a computer software interface. The computer then sends these parameters to the FPGA.

[0024] Step S2: Calculate the extended scan parameters.

[0025] Based on the hysteresis characteristic of the YTO, an extended scanning frequency range is calculated and determined. The extended scanning frequency range has an actual starting frequency F1 lower than Fstart, an actual ending frequency F2 higher than Fstop, and an extended total scanning time T. Step S3: Perform extended scanning and control signal output.

[0026] The scanning control unit of the FPGA starts a timer and begins to update the frequency division ratio of the frequency divider with the calculated step value. At the same time, a corresponding tuned voltage data stream is synchronously sent to the preset port of the YTO. Meanwhile, the gating logic unit of the FPGA starts to work: In the initial stage of scanning, when the instantaneous frequency f < Fstart, the FPGA outputs a control signal to make the pulse modulator in the "off" state. The instrument has no RF signal output.

[0027] When the FPGA determines through an internal counter or frequency calculation logic that the instantaneous frequency f first reaches or exceeds Fstart, the gating logic unit immediately flips the control signal to turn on the pulse modulator. At this time, a stable RF signal starts to be output through the RF channel.

[0028] In the main stage of scanning, when f varies within the range [Fstart, Fstop], the pulse modulator remains on, and the instrument outputs a linearly varying scanning signal.

[0029] When it is determined that the instantaneous frequency f first reaches or exceeds Fstop, the gating logic unit immediately flips the control signal to turn off the pulse modulator. The output of the instrument is aborted.

[0030] In the ending stage of scanning, when f varies within the range (Fstop, F2], the pulse modulator remains off. The YTO and the phase-locked loop complete the remaining frequency change and relaxation process in this stage.

[0031] Step S4: Scanning is completed. When the scanning frequency reaches F2, the scanning process ends, and the system enters the standby state.

[0032] Key points and protected points of the present invention: This application innovatively proposes that in the actual scanning process, the starting frequency F1 is less than the starting frequency Fstart set for the whole machine, and the ending frequency F2 is higher than the ending frequency Fstop. That is, the actual scanning span includes the span to be scanned. The values of F1 and F2 are given by an algorithm formula according to the characteristics of different YTOs. This avoids the loop unlocking caused by the hysteresis effect of the YTO and ensures that the loop can be stably locked in the actually required scanning section.

[0033] The innovation of this application is to precisely control pulse modulation through FPGA. When F1 < Fstart and F2 > Fstop, the pulse is on and the output signal is off. When F1 = Fstart, the pulse is off and the output signal is on.

[0034] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by those skilled in the art within the scope of the essence of the present invention should also fall within the protection scope of the present invention.

Claims

1. A fast scanning system based on YTO, characterized in that, include: YTO, or YIG tuned resonator, is used to generate radio frequency signals; A frequency divider is connected to the output of the YTO and is used to divide the radio frequency signal. A phase detector, whose first input is connected to a reference clock and whose second input is connected to the output of the frequency divider, is used to output a phase error signal; An integrator, whose input is connected to the output of the phase detector and whose output is connected to the tuning terminal of the YTO, together with the phase detector, YTO and frequency divider, forms a phase-locked loop; The radio frequency channel has its input terminal connected to the output terminal of the YTO; Used to transmit the radio frequency signal; A pulse modulator, connected in series in the radio frequency channel, is used to turn the output of the radio frequency signal on or off according to a control signal. The control computer is used to receive scan parameters set by the user. The field-programmable gate array is connected to the control computer, the frequency divider, the preset terminal of the YTO, and the control terminal of the pulse modulator, respectively. The field-programmable gate array is configured to: The system receives scanning parameters from the control computer, including a start frequency Fstart, an end frequency Fstop, and a scanning time T. The extended scanning frequency range is calculated based on the hysteresis characteristics of the YTO. The actual starting frequency F1 of the extended scanning frequency range is lower than Fstart, and the actual ending frequency F2 is higher than Fstop. During the analog frequency scan from F1 to F2, a timing signal is generated to control the change of the division ratio of the frequency divider, and corresponding preset data is sent to the preset terminal of the YTO synchronously. A pulse control signal is generated, which is configured to: control the pulse modulator to turn off when the scan frequency is lower than Fstart and higher than Fstop; and control the pulse modulator to turn on when the scan frequency is within the range of Fstart to Fstop.

2. The YTO-based rapid scanning system according to claim 1, characterized in that, The field-programmable gate array is also connected to the reference clock, which serves as the reference clock source for its internal timing generation.

3. A fast scanning method based on YTO, characterized in that, The method of using a YTO-based fast scanning system as described in claim 1 includes the following steps: S1. Set scan parameters; Receives the scan start frequency Fstart, scan stop frequency Fstop, and scan time T set by the user; S2. Determine the extended scan range; Based on the hysteresis characteristics of the YTO, an extended scanning frequency range is calculated and determined, which has a lower actual start frequency F1 than Fstart and a higher actual stop frequency F2 than Fstop. S3. Perform extended scan and control signal output; The control phase-locked loop system performs an analog frequency scan from the actual start frequency F1 to the actual end frequency F2; During the scanning process, the FPGA controls the operating state of the pulse modulator, enabling: a. When the scanning frequency is in the range of [F1, Fstart), the pulse modulator is turned off, and there is no signal output; b. When the scanning frequency reaches Fstart, control the pulse modulator to turn on and start outputting the scanning signal; c. When the scanning frequency reaches Fstop, control the pulse modulator to turn off and stop outputting the scanning signal; d. Keep the pulse modulator off when the scan frequency is in the range of (Fstop, F2); S4. When the scanning frequency reaches F2, the scanning process is complete.

4. The fast scanning method based on YTO according to claim 3, characterized in that, In step S2, the method for determining the actual start frequency F1 and the actual stop frequency F2 is as follows: the hysteresis response curves of the YTO in the start and stop stages are obtained through pre-testing or modeling, and the values ​​of F1 and F2 that can ensure the stable phase-locked loop of the scanning signal in the Fstart to Fstop interval are calculated based on the response curves and the preset phase-locked loop stability margin.

5. The fast scanning method based on YTO according to claim 3, characterized in that, In step S3, the field-programmable gate array precisely controls the turn-on and turn-off times of the pulse modulator according to the synchronization timing generated by the reference clock, so as to achieve precise synchronization between the scanning frequency and the radio frequency output signal.

6. The fast scanning method based on YTO according to claim 3, characterized in that, In step S3, performing the analog frequency scan specifically includes: The field-programmable gate array (FPGA) calculates the division ratio change step of the frequency divider based on the extended scan range and total scan time. During the scan, the FPGA controls the division ratio of the frequency divider to accumulate according to the step and synchronously sends the corresponding preset voltage data to the YTO to achieve continuous frequency change.

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