Method for supporting data merging in multi-site test of upper computer

Abstract

The invention relates to the technical field of industrial automatic testing, and discloses a method for supporting data merging in multi-site testing of an upper computer, which comprises the following steps: the upper computer establishes a mapping relation between a test site sequence number and a physical position offset; updating a global index variable in response to a global index signal of the sorting machine; calculating a device unique identifier of each station according to the global index variable and the physical position offset; accessing the virtual shift register according to the unique identifier, querying a historical state to decide to issue an enabling or shielding instruction, and executing state inheritance; and associating and splicing the cleaned asynchronous test logs by taking the unique identifier of the device as a main key. According to the method, a logic operation system is constructed, mechanical motion is mapped into a unique identifier which does not change along with time, the test and motion time sequence is decoupled, the problem of data dislocation caused by communication delay, retest or physical empty materials in multi-site test is effectively solved, and the accuracy of production data is ensured.

Description

Technical Field

[0001] This invention relates to the field of industrial automation testing technology, specifically to a method for supporting data merging in multi-site testing on a host computer. Background Technology

[0002] In the back-end packaging and testing of semiconductor chips and electronic components, sorting machines typically need to drive the devices under test (DUTs) sequentially through multiple physical test stations to complete parallel or serial tests of different electrical parameters. The host computer system, as the control core of the entire production line, is responsible for coordinating mechanical actions, issuing test commands, and collecting and archiving test data.

[0003] Existing multi-site testing systems typically rely on the time sequence of test result uploads or a first-in-first-out (FIFO) queue logic to establish the correspondence between mechanical positions and test data. This approach requires strict synchronization between the mechanical action cycle of the sorting machine and the electrical test duration at each site. However, in actual production, the test durations at each testing site often differ and are susceptible to communication congestion or instrument response delays. If test data uploads from a particular site are delayed, relying solely on timestamps or sequential counting can easily lead to misalignment of all subsequent data records, making it impossible to correctly correlate the data in the test report with the actual physical device.

[0004] In terms of device status transmission and control, traditional technologies rely heavily on the level switching of hardware signal lines to trigger tests or transmit sorting results. While this hardware-coupled approach operates stably under ideal conditions, it lacks flexibility in handling abnormal operating conditions. For example, when the sorting machine nozzle fails to pick up the device, resulting in a physical empty material, or when a previous process determines that a device is unqualified and needs to skip subsequent tests, the hardware signal logic often struggles to handle the complex state inheritance requirements. This leads to a disconnect between the logic queue index of the host computer and the actual state at the physical workstation, making it difficult for the system to effectively identify and handle empty material or continuous failures, thus causing errors in the issuance of control commands.

[0005] In the final data aggregation stage, the lack of a logically unique identifier throughout the entire process poses challenges when processing redundant data generated from retesting at the same workstation or logs uploaded from multiple sites. Existing data processing methods often struggle to automatically remove invalid historical retest records and cannot accurately piece together scattered heterogeneous data in the absence of a unified logical primary key. This not only increases the workload of manual data verification but may also compromise the integrity and traceability of production reports due to incorrect data row alignment. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a method for supporting data merging in multi-site testing using a host computer. This method solves the problem of data misalignment caused by the asynchronous timing of mechanical actions and electrical tests in multi-site testing, as well as the difficulties in state transmission and data merging under physical empty materials or abnormal working conditions.

[0007] To achieve the above objectives, the present invention provides the following technical solution: The first aspect of this invention provides a method for supporting data merging in multi-site testing on a host computer, applicable to a testing system comprising a host computer, a sorting machine, and multiple test sites arranged in physical workstation order.

[0008] The method mainly includes: the host computer reads the configuration file and establishes a mapping relationship between the station number and the physical position offset of the test station to determine the number of workstation intervals of each test station relative to the first test station; the host computer receives the global index signal sent by the sorting machine and updates the internally maintained global index variable according to the change of the global index signal, using the global index variable as the spatiotemporal reference benchmark of the test system; after the global index variable is updated, the host computer calculates the device unique identifier of the device under test located at the test station at the current moment for each active test station based on the current global index variable and the physical position offset corresponding to the test station; the host computer accesses the virtual shift register configured in the running memory according to the device unique identifier, queries the historical test status of the device under test in the previous test cycle, and decides to issue a test enable command or test disable command to the current test station accordingly, and writes the test result back to the virtual shift register after the test is completed; the host computer uses the device unique identifier as the primary key to associate and concatenate the test logs of each test station belonging to the same device under test to generate a complete device test record.

[0009] In conjunction with the first aspect, in one possible implementation, the process of establishing the mapping relationship between the test site number and the physical location offset specifically includes: the host computer parses the configuration file to obtain the number of physical workstation intervals between two adjacent test sites; the physical location offset of the first test site is set to zero; for each subsequent test site, the host computer accumulates all the physical workstation intervals from the first test site to the current test site, and determines the accumulated value as the physical location offset of the current test site.

[0010] In conjunction with the first aspect, in one possible implementation, the process of updating the internally maintained global index variable based on changes in the global index signal specifically includes: when the global index signal is a pulse signal, the host computer monitors the level transition state of the pulse signal, and increments the global index variable when a valid level transition is detected; or, when the global index signal is a register count value, the host computer periodically reads the register count value, and increments the global index variable when the difference between the currently read value and the cached value is equal to a preset step increment.

[0011] In conjunction with the first aspect, in one possible implementation, the process of calculating the unique identifier of the device under test located at the test station at the current moment specifically includes: for each test station in an active state, the host computer directly calculates the unique identifier of the device by subtracting the physical location offset corresponding to the current test station from the current global index variable.

[0012] In conjunction with the first aspect, in one possible implementation, the virtual shift register adopts a key-value pair storage structure residing in the running memory. The virtual shift register includes: a unique device identifier as an index key; and a state vector as the stored value. The state vector contains multiple independent logical segments, each of which stores the test state of a test station. The test states include an initial state indicating that the device has not been reached, a qualified state indicating that the test has passed, a failed state indicating that the test has failed, and an empty state indicating that there is no physical device.

[0013] In conjunction with the first aspect, in one possible implementation, the process of querying the historical test status of the device under test in the previous test cycle and determining whether to issue a test enable command or a test disable command to the current test station specifically includes: when the test station is not the first test station, the host computer reads the logic segment value corresponding to the previous test station from the status vector; if the logic segment value of the previous test station is in a qualified state, the host computer determines that the test is allowed and generates a control message containing an enable opcode; if the logic segment value of the previous test station is in a failed state or an empty state, the host computer determines that the test is disabled and generates a control message containing a disable opcode.

[0014] In conjunction with the first aspect, in one possible implementation, when generating a control message containing a masking opcode, the method further includes performing a state inheritance operation: the host computer directly updates the value of the logic segment corresponding to the current test station in the virtual shift register to the same value as the value of the logic segment of the previous test station, so that the failure state or empty state is passed to the next logical position in the virtual shift register along with the device's unique identifier.

[0015] In conjunction with the first aspect, in one possible implementation, the test log includes a unique device identifier, a site number, and a generation timestamp. Before associating and concatenating the test logs, the method further includes a data cleaning step: the host computer temporarily stores the received test logs in a buffer pool and groups multiple test logs with the same unique device identifier and the same site number; the host computer retains the test log with the largest generation timestamp value in each group as a valid test record and removes the remaining test logs in the same group.

[0016] In conjunction with the first aspect, in one possible implementation, the process of associating and splicing test logs from various test sites belonging to the same device under test specifically includes: the host computer creating a target data table containing a unique device identifier column and multiple parameter columns; the host computer performing a full outer join operation on valid test records, filling the corresponding parameter columns of the target data table with valid test records belonging to the same unique device identifier; when the host computer does not find a valid test record corresponding to a specific test site, it fills the corresponding position in the target data table with a preset null value code or skip code.

[0017] In conjunction with the first aspect, in one possible implementation, the method further includes a step for handling physical empty materials: when the test station is the first test station and the inlet sensor outputs a low level, the host computer marks the logic segment value in the virtual shift register corresponding to the first test station as empty material; in the asynchronous data merging step, when the host computer recognizes that the test state corresponding to the device's unique identifier is empty material, it marks a skip flag in the generated device test record.

[0018] The present invention provides a method for supporting data merging in multi-site testing using a host computer. This method constructs a logical operation system based on global index variables and physical position offsets, mapping time-varying mechanical motion to unique device identifiers that do not change over time. A virtual shift register is then used to achieve logical transfer and inheritance of test states. This method decouples the test data generation time from the mechanical motion time, using the unique device identifier as the primary key for asynchronous data merging. This effectively solves the data misalignment problems caused by timing asynchrony, retesting, or empty components in multi-site testing, ensuring the integrity and accuracy of the final test record.

[0019] This invention provides a method for supporting data merging in multi-site testing on a host computer. It has the following beneficial effects: 1. This invention constructs a difference calculation model based on global index variables and physical location offsets, transforming the mechanical motion cycle of the sorting machine into a unique device identifier that does not change over time. Regardless of communication delays or retesting causing data upload delays at the test site, the host computer can accurately pinpoint data ownership based on this unique device identifier. This effectively solves the data misalignment problem caused by relying solely on timestamps or sequential counting in traditional methods, achieving logical decoupling between mechanical actions and electrical test timing.

[0020] 2. This invention utilizes a virtual shift register residing in memory to replace traditional hardware signal lines for state transmission. Through state inheritance logic, it ensures that failure states or empty states automatically follow the device's unique identifier. This hardware-software decoupling control method not only reduces the dependence on the synchronization of underlying hardware trigger signals but also prevents queue index confusion caused by physical empty components or skipped tests, thus improving the robustness of multi-site cascaded control.

[0021] 3. This invention employs an asynchronous data merging strategy using the unique identifier of the device as the primary key, coupled with a timestamp-based redundancy cleaning mechanism. This automatically removes invalid historical data generated by retesting at the same workstation and accurately stitches together the test logs from discretely distributed sites into a complete wide table record. This mechanism eliminates the risk of row misalignment caused by abnormal operating conditions, ensuring the integrity and traceability of the final output production data. Attached Figure Description

[0022] Figure 1 This is a flowchart of the method of the present invention. Detailed Implementation

[0023] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] Please see the appendix Figure 1This invention provides a method for supporting data merging in multi-site testing via a host computer. The system architecture includes a host computer, a sorting machine, and multiple test stations arranged in physical workstation order. The host computer establishes communication connections with the sorting machine and each test station. The host computer, as the control and data processing unit of the multi-site test data merging and control system, is equipped with a non-volatile storage medium and a central processing unit (CPU). The non-volatile storage medium stores computer programs and configuration files, and the CPU's memory allocates a key-value pair storage space for storing device status information; logically, this key-value pair storage space is constructed as a virtual shift register. The sorting machine carries the device under test (DUT) and drives it to move between the test stations. The sorting machine is equipped with a signal generation module, which generates a global index signal each time the sorting machine performs a mechanical action cycle. The test stations perform electrical parameter tests on the moved DUTs and feed the test results back to the host computer.

[0025] The communication connection between the host computer and the sorting machine is implemented using industrial Ethernet, a serial communication interface, or a digital I / O card. The host computer receives the global index signal sent by the sorting machine through the communication connection. The global index signal is configured as a pulse signal or a register count value. The communication connection between the host computer and each test station adopts a standard bus protocol. The host computer issues test commands and retrieves test logs through the communication connection. The mechanical drive structure of the sorting machine, the specific circuit implementation of the signal generation module, and the specific test instrument configuration of the test station can be implemented using existing general-purpose equipment by those skilled in the art, and are well-known technologies in this field, and will not be elaborated further here.

[0026] To address the data merging misalignment problem caused by asynchronous mechanical movement and electrical testing timing in multi-site testing, this embodiment provides a data processing method, mainly including steps S100 to S500.

[0027] S100, System Initialization and Physical Mapping Construction. The host computer reads a preset configuration file or receives configuration parameters input by the user. The configuration file records the physical position offsets of each test station on the test pipeline. The host computer establishes a mapping relationship between the station number and the physical position offset based on the physical position offsets to determine the number of workstation intervals for each test station relative to the first test station. The physical position offset is a fixed constant used to correct for differences in mechanical position, ensuring a consistent benchmark for subsequent calculations.

[0028] The S200 acquires the global index signal and monitors its periodic changes. The host computer monitors the global index signal input from the sorting machine in real time. When the sorting machine completes a mechanical action, it sends an updated global index signal via the communication interface. The host computer responds to changes in the global index signal by updating its internally maintained global index variables to confirm that the system has entered a new test cycle. The global index variables are a monotonically increasing integer sequence, serving as a spatiotemporal reference for merging multi-site test data and controlling the system.

[0029] The S300 performs parallel computation of the device's unique identifier (DID) at each test station. After the global index variable is updated, the host computer calculates the DID for each active test station, based on the current global index variable and the physical location offset of each test station. The DID is used to uniquely identify a specific DID throughout the entire process, ensuring that its value remains constant during the transfer of the DID.

[0030] S400 is a test access control system based on a virtual shift register. The host computer, using the unique device identifier calculated in step S300, accesses the virtual shift register in its running memory to query the historical test status of the device under test (DUT) in the previous test cycle, and determines whether to issue a test command to the current test station accordingly. If the historical test status shows "qualified," the host computer issues a test enable command; if the historical test status shows "failed" or "empty component," the host computer issues a test disable command and updates the status field of the current test station in the virtual shift register to the value of the status field of the previous test station. After the test is completed, the host computer writes the test result of the current test station back to the virtual shift register.

[0031] S500, Asynchronous Data Merging. During testing or after a test batch, the host computer merges test logs scattered across various time points and test sites based on the device's unique identifier. Using the device's unique identifier as the primary key, the host computer associates and concatenates test logs from different test sites belonging to the same device under test, generating a complete device test record. Step S500 eliminates row alignment errors caused by retesting, timeouts, or empty parts, achieving data merging based on the device's unique identifier.

[0032] To ensure that the software logical model corresponds to the hardware physical layout, the host computer performs system initialization and physical mapping construction as described in step S100 before starting the test process. Step S100 specifically includes sub-steps S110 to S130.

[0033] S110, Loading and parsing configuration files.

[0034] After the host computer powers on, it accesses the non-volatile storage medium and reads the pre-stored production line configuration file. The production line configuration file is written in a structured data format and contains the hardware topology information and site data definition information of the test pipeline. The hardware topology information includes the total number of active test sites. The system defines the test site data, including the physical workstation spacing between adjacent test sites and the required test result data type and bit width for each test site. The host computer calls the parser to traverse the production line configuration file, extract the test site number, physical workstation spacing, and data bit width configuration, and loads the extracted information into the configuration cache in the running memory.

[0035] S120, Calculation and mapping of physical location offset.

[0036] The host computer calculates the physical position offset of each test station relative to the first test station based on the number of physical workstation intervals in the configuration buffer. The host computer sets the physical location offset of the first test site. It is 0. For the subsequent... Test sites ( The host computer performs the cumulative calculation, and the calculation formula is: In the formula, Indicates the first The physical location offset of each test site; Indicates the first The test site and the first The number of physical workstation intervals between each test site. The host computer will calculate the physical position offset. With station number Establish key-value mapping relationships and generate a site configuration table. The site configuration table remains read-only during system operation.

[0037] S130, space pre-allocation for the virtual shift register.

[0038] The host computer parses the total number of test sites from the production line configuration file. The data bit width is configured, and a heap memory space is allocated in the running memory to construct the virtual shift register. The host computer defines the data structure of the state vector, which contains... Each status field is independent. The host computer initializes the head pointer of the hash map table or circular queue and resets all status bits in the heap memory space to their default values. Through space pre-allocation, the host computer reduces the dynamic memory allocation overhead during test runs, ensuring that the status record creation operation for new devices meets the system's real-time requirements.

[0039] The host computer executes step S200, which involves acquiring the global index signal and monitoring periodic changes. Step S200 specifically includes sub-steps S210 to S230.

[0040] S210, Signal Pattern Recognition and Validity Verification.

[0041] The host computer reads a preset hardware configuration file to determine the signal transmission protocol currently used by the sorting machine. If the transmission protocol is set to pulse trigger mode, the host computer starts an edge detection interrupt service routine to monitor the signal level transition. When the host computer detects a signal level transition from low to high, and the duration of the high level exceeds a preset software filtering threshold, the host computer determines that a valid mechanical step pulse has been received. If the transmission protocol is set to register value mode, the host computer periodically reads the sorting machine's internal position register via bus polling. The host computer calculates the difference between the currently read register value and the buffered value of the previous cycle. If the difference equals the preset step increment, the host computer determines that the mechanical action cycle is complete.

[0042] S220, cumulative update of global index variables.

[0043] When the host computer determines that the mechanical action cycle is complete in sub-step S210, the host computer checks the global index variable. Performs a numeric increment operation. Global index variable. Defined as an unsigned long integer, the value range of which covers the system's expected maximum number of operating cycles. When the host computer performs an auto-increment operation, it does not perform a clear or loop reset operation to ensure the global index variable... It maintains a monotonically increasing trend during a single system run. Global index variable. Each increase of 1 in the value represents the physical distance the sorting machine drives the device under test to move by one workstation.

[0044] S230, Abnormal Reset and Synchronization Calibration.

[0045] The host computer monitors the system's operating status flags in real time. When the host computer receives a system emergency stop recovery command or a power-down restart signal, it performs a synchronization calibration operation. The host computer reads the breakpoint count value stored in non-volatile memory and assigns the breakpoint count value to a global index variable. This restores the counting state before the power outage. If there is no valid record in the non-volatile memory, the host computer reads the status of the entry sensor at the first test station. If the entry sensor detects the device under test, the host computer will update the global index variable. Reset to the preset initial baseline value.

[0046] The host computer performs the parallel calculation of the unique device identifier of each test station as described in step S300. Step S300 specifically includes sub-steps S310 to S330.

[0047] S310, Loading of physical location offset.

[0048] The host computer reads the physical location offsets of all active test sites in the test pipeline from the configuration cache in the running memory. (Physical location offsets) Defined as the first The number of station intervals on the mechanical transmission path relative to the first test station. Physical position offset. It is a fixed constant calculated based on the system initialization phase in step S100.

[0049] S320 performs a difference operation on the device's unique identifier.

[0050] Whenever global index variable During the update, the host computer performs updates for each test site. Perform a subtraction operation to generate the current location at the test site. The unique device identifier of the device under test at the location The operational logic follows the formula for calculating the unique identifier of the device: In the formula, Indicates the first The unique identifier of the device under test corresponding to each test station at the current moment; This indicates the current value of the global index variable; Indicates the first The physical location offset of each test site relative to the first test site.

[0051] S330, Identifier Consistency Verification.

[0052] When the sorting machine drives the device under test from the first The test site moved to the [number]th [location]. When testing a single site, the global index variable Increase by 1, and at the same time the first The test site is relative to the first Physical location offset of each test site It also increases by 1 accordingly. This is due to the global index variable. The increment is equal to the increment of the physical location offset, global index variable The difference between the physical location offset and the actual location offset remains constant. The host computer uses this constant difference as a unique identifier for the device. And uniquely identified by the device Using the primary key, the device under test is tracked throughout the entire process. Regardless of the... The host computer determines when each test site uploads test data based on the unique identifier of the device corresponding to the moment the test data is generated. Archive the test results.

[0053] The host computer executes the test permission control based on the virtual shift register as described in step S400. Step S400 specifically includes sub-steps S410 to S440.

[0054] S410, Memory Construction and Status Encoding of Virtual Shift Registers.

[0055] The host computer allocates a dynamic storage area in the CPU's RAM and constructs a key-value pair storage structure to instantiate the virtual shift register. The host computer defines a unique identifier for the device. As the index key of the key-value pair storage structure, a state vector is defined as the storage value corresponding to the index key. The state vector is configured to contain... A multi-byte structure of independent logical segments, in which This equals the total number of test sites that are active in the production line configuration file. The first logical segment is specifically used to store the first... The test status of each test station is recorded. The host computer establishes a binary status encoding table, mapping the test status to logical values: binary "00" is defined as the initial state, indicating that the device under test has not yet arrived at the test station; binary "01" is defined as the qualified state, indicating that the device under test has passed the test at the test station; binary "10" is defined as the failure state, indicating that the device under test has failed the test at the test station; binary "11" is defined as the empty state, indicating that there is no physical device at the logical location corresponding to the test station.

[0056] S420, the logic for querying and determining test permissions.

[0057] When the sorting machine drives the device under test to reach the first... After each test site, the host computer uses the unique device identifier calculated in step S320. Address the virtual shift register. If the virtual shift register does not contain a unique device identifier... The corresponding status record, and the current station sequence number The host computer creates a new state record and initializes all logical segments of the state vector to their initial state. If the state record exists, the host computer performs a cascaded judgment: For the first test site ( The host computer reads the voltage level of the physical sensor at the entrance of the first test station. If the physical sensor outputs a high level, the host computer determines that the current state is valid and under test; if the physical sensor outputs a low level, the host computer determines that the current state is empty.

[0058] For subsequent test sites ( The host computer reads the state vector from the first... The value of the logical segment. If the first... The value of the first logic segment equals the binary code corresponding to the qualified state, and the host computer determines that the current test is allowed; if the value of the first logic segment is equal to the binary code corresponding to the qualified state, the host computer determines that the current test is allowed; The value of each logic segment is equal to the binary code corresponding to the failure state or empty material state, and the host computer determines that the current test is blocked.

[0059] S430, control command generation and state inheritance.

[0060] The host computer sends the decision result of sub-step S420 to the first... The test station sends a control message. If the determination result is test allowed, the host computer sends a control message containing an enable opcode, triggering the first test station to send a control message. Each test site performs electrical parameter tests. If the result indicates shielding, the host computer sends a control message containing the shielding operation code. Each test site remains in standby mode.

[0061] When the host computer sends a control message containing a masked opcode, it performs a state inheritance operation: the host computer moves the first bit in the virtual shift register... The value of the first logical segment is updated to match the value of the second logical segment. The same value for each logical segment. State inheritance ensures that the failure state or empty state is propagated forward in the virtual shift register along with the index position of the device's unique identifier, making the first logical segment... The test site can be used for subsequent queries based on the first... The value of each logical segment continues to trigger the masking logic.

[0062] S440, test result write-back and memory maintenance.

[0063] When the When each test site completes the test and uploads the test result data, the host computer uses the unique identifier of the device. The virtual shift register is addressed again to map the test result data into the corresponding binary code and write it into the state vector. Each logical segment completes one state update.

[0064] Meanwhile, to prevent memory overflow, the host computer executes a sliding window-based cleanup logic. The host computer calculates the current global index variable in real time. Unique identifier of the device in the storage record The difference. If the difference satisfies the following clearing formula: In the formula, This is a preset maximum retention capacity threshold, which represents the maximum number of online devices allowed by the system. When the clearing formula is true, the host computer determines the unique identifier of the device. The corresponding device under test has left the testing line and released its unique device identifier. The corresponding memory space.

[0065] To address the issues of discrete data recordings and redundant retest data in asynchronous testing environments, the host computer executes the asynchronous data merging described in step S500. Step S500 specifically includes sub-steps S510 to S530.

[0066] S510 is a standardized cache for distributed logs.

[0067] After receiving test result data from various test sites, the host computer temporarily stores the test result data in a buffer pool in the running memory. The host computer then encapsulates each raw test result data into a standardized test log record. The test log record contains four fields: a unique device identifier... Station Number Test parameter set and generate timestamps Among them, the device's unique identifier The host computer, based on the logic in steps S320 and S420 above, associates the value with the current test site at the start of the test. Site Number Corresponding to the physical location number of the test site. Generate timestamp. The system time for uploading test result data to the host computer was recorded. The host computer, through a packaging operation, converted test result data uploaded using different communication protocols into a unified data format.

[0068] S520, redundancy cleaning based on time priority.

[0069] In cases where the sorting machine pauses its mechanical operation and the test station performs multiple repeated tests on the same device under test, the buffer pool will contain multiple entries with the same unique device identifier. Same station number But generating timestamps Different redundant records. The host computer performs data cleaning steps, traversing the data records in the buffer pool and classifying them according to the device's unique identifier. and station number The data records are grouped. Within each group, the host computer compares the generation timestamps of all data records. The host computer retains the generated timestamp. The data record with the largest value is selected as the valid test record, and the remaining data records in the same group are marked as invalid historical data or deleted from the buffer pool. The data cleaning step ensures that in the subsequent merging operation, only one valid test record is retained for each logical workstation of each test site.

[0070] S530, horizontal splicing based on unique identifiers.

[0071] The host computer triggers the merging operation based on a preset batch size or time interval. The host computer creates a target data table, which includes a unique identifier column for each device and a corresponding column for all devices. The parameter list for each test site. The host computer uses the device as a unique identifier. As the index key, a full external join operation is performed. The host computer will uniquely identify devices from different test sites that have the same component. Valid test records are spliced ​​together in the horizontal direction.

[0072] The concatenation logic follows the following data merging formula: In the formula, Indicates unique identification of the device The final merged record row with the primary key; This indicates the total number of test sites; This indicates a field concatenation operation; The site number is And the device is uniquely identified as The set of test parameters in the valid test records.

[0073] During the concatenation operation, if the host computer does not find the first concatenation node in the buffer pool... The valid test records corresponding to each test site are recorded in the target data table by the host computer. Each parameter column is filled with a preset null code or skip code. Using a data merging formula, the host computer reassembles the discrete test log records into continuous wide table data and outputs it to the production execution system.

[0074] To ensure the integrity of data logic under abnormal conditions such as physical material shortage, communication delay, and unexpected power failure, the host computer further executes exception handling logic including sub-steps S240, S450, and S540 during the execution of the aforementioned main process.

[0075] S240, breakpoint recovery after abnormal power failure.

[0076] In response to unexpected power outages or emergency shutdowns during production, the host computer executes a breakpoint recovery procedure. The host computer allocates power-off recovery storage addresses in non-volatile storage media. This is done using the global index variable described in step S220. During the update process, the host computer synchronously updates the global index variable. Write to non-volatile storage medium. When the system powers on again, the host computer reads the value from the non-volatile storage medium and loads it into the running memory as a global index variable after recovery. Subsequently, the host computer prompts the operator to confirm the physical status of the current workstation within the sorting machine. If the operator confirms that there is no error or the sensor verification passes, the host computer restores the memory mapping of the virtual shift register and continues executing the test process before the interruption. Sub-step S240 avoids errors in calculating the unique identifier of the device caused by the global index variable returning to zero due to a system restart.

[0077] S450, logic retention for physical empty data.

[0078] In response to scenarios where the sorting machine experiences material failures or drops during operation, resulting in empty material, the host computer executes empty material handling steps. When the sorting machine drives an empty station without any physical components to the [missing information - likely a specific location or stage], [the following steps are taken]. When testing at a single station, the host computer calculates the unique identifier of the device corresponding to the empty station based on the aforementioned formula. The host computer queries the virtual shift register and identifies the device's unique identifier. The corresponding status field is "empty material state". At this time, the host computer does not send any data to the first... Instead of sending test commands individually, the test stations send control messages containing masked opcodes. Simultaneously, the host computer retains a unique device identifier in the virtual shift register. The corresponding empty material state record will not be deleted. In the subsequent data merging stage, the host computer will use the unique identifier of the device. The final report generates a record marked "SKIP". Sub-step S450 maintains the numerical continuity of the device unique identifier sequence, preventing data of subsequent devices under test from being misaligned in the queue due to physical gaps.

[0079] S540, Asynchronous Waiting and Data Archiving.

[0080] Regarding the first In the scenario where the test site's testing time exceeds the mechanical action cycle of the sorting machine, the host computer executes an asynchronous waiting step. When the first... When a test site is busy, the sorting machine suspends mechanical transmission and does not send a new global index signal to the host computer. The host computer detects that the global index signal has not changed and maintains the current global index variable. The value remains unchanged. During the sorting machine's pause, the host computer continuously polls the status of each test station. Once the... Each test site completes the test and uploads the test results data. The host computer then uses the currently unchanged global index variable... Passing the exam Physical location offset of each test site Recalculate the unique identifier of the device. The test results data will be linked to the device's unique identifier. Perform associated archiving. Sub-step S540 ensures that the associated key value of the data depends only on the physical location index, and not on the absolute timestamp at the end of the test.

[0081] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for supporting data merging in multi-site testing using a host computer, applied to a testing system comprising a host computer, a sorting machine, and multiple test stations arranged in physical workstation order, characterized in that... The method includes the following steps: S100, System Initialization and Physical Mapping Construction: The host computer reads the configuration file and establishes the mapping relationship between the station number and the physical location offset of the test station to determine the number of workstation intervals of each test station relative to the first test station. S200. Acquire global index signal and monitor periodic changes: The host computer receives the global index signal sent by the sorting machine and updates the internally maintained global index variable in response to the change of the global index signal. The global index variable serves as the spatiotemporal reference benchmark of the test system. S300. Parallel calculation of the device unique identifier of each test station: After the global index variable is updated, the host computer calculates the device unique identifier of the device under test located at the test station at the current moment for each test station that is in an active state, based on the current global index variable and the physical location offset corresponding to the test station. S400, Test permission control based on virtual shift register: The host computer accesses the virtual shift register residing in the running memory according to the unique identifier of the device, queries the historical test status of the device under test in the previous test cycle, and decides to issue a test enable command or test disable command to the current test station accordingly, and writes the test result back to the virtual shift register after the test is completed. S500, Asynchronous Data Merging: The host computer uses the unique identifier of the device as the primary key to associate and merge the test logs of each test station belonging to the same device under test, generating a complete device test record.

2. The method for supporting data merging in multi-site testing on a host computer according to claim 1, characterized in that, The mapping relationship between the site number and physical location offset of the test site is established in step S100, specifically including: The host computer parses the configuration file to obtain the number of physical workstation intervals between two adjacent test sites; The host computer sets the physical location offset of the first test site to zero; For each subsequent test station, the host computer performs an accumulation calculation on all the physical workstation intervals between the first test station and the current test station, and determines the accumulated value as the physical position offset of the current test station.

3. The method for supporting data merging in multi-site testing on a host computer according to claim 1, characterized in that, The S200 process, which updates the internally maintained global index variable in response to changes in the global index signal, specifically includes: When the global index signal is a pulse signal, the host computer monitors the level transition state of the pulse signal, and performs a value increment operation on the global index variable when a valid level transition is detected. When the global index signal is a register count value, the host computer periodically reads the register count value, and when the difference between the currently read value and the cached value is equal to the preset step increment, it performs a value increment operation on the global index variable.

4. The method for supporting data merging in multi-site testing on a host computer according to claim 1, characterized in that, In step S300, based on the current global index variable and the physical location offset corresponding to the test station, the unique identifier of the device under test located at the test station at the current moment is calculated. Specifically, the host computer performs a subtraction operation for each test station that is in an active state. The subtraction operation is as follows: subtract the physical location offset corresponding to the current test site from the current global index variable to obtain the unique identifier of the device.

5. The method for supporting data merging in multi-site testing on a host computer according to claim 1, characterized in that, The virtual shift register in S400 is configured as a key-value pair storage structure residing in the running memory. The virtual shift register includes: a unique identifier of the device as an index key; and a state vector as a stored value, the state vector containing multiple independent logic segments, each of which stores the test state of a test station. The test states include the initial state where the device has not arrived, the qualified state where the test has passed, the failed state where the test has failed, and the empty state where there is no physical device.

6. The method for supporting data merging in multi-site testing on a host computer according to claim 5, characterized in that, In step S400, the historical test status of the device under test (DUT) in the previous test cycle is queried, and based on this, a test enable command or test disable command is issued to the current test station, specifically including: When the test station is not the first test station, the host computer reads the logical segment value corresponding to the previous test station from the state vector; When the logic segment value of the previous test station is in the qualified state, the host computer determines that the test is allowed and generates a control message containing the enable opcode; When the logic segment value of the previous test station is in the failure state or the empty material state, the host computer determines that the test is blocked and generates a control message containing the blocking operation code.

7. A method for supporting data merging in multi-site testing on a host computer according to claim 6, characterized in that, When generating a control message containing a masked opcode, the method further includes performing a state inheritance operation: The host computer directly updates the value of the logic segment corresponding to the current test station in the virtual shift register to the same value as the value of the logic segment of the previous test station, so that the failure state or the empty material state is passed forward in the virtual shift register along with the device's unique identifier.

8. A method for supporting data merging in multi-site testing on a host computer according to claim 1, characterized in that, The test log in S500 includes the device's unique identifier, site number, and generation timestamp. Before associating and splicing the test logs, the method further includes a data cleaning step: the host computer temporarily stores the received test logs in a buffer pool and groups multiple test logs with the same unique device identifier and the same site number. The host computer retains the test log with the largest generated timestamp value in each group as a valid test record and removes the rest of the test logs in the same group.

9. A method for supporting data merging in multi-site testing on a host computer according to claim 8, characterized in that, In step S500, the test logs of each test station belonging to the same device under test are associated and spliced, specifically including: The host computer creates a target data table containing a unique identifier column for the device and multiple parameter columns; The host computer performs a full external connection operation on the valid test records, filling the parameter column corresponding to the target data table with the valid test records belonging to the same unique identifier of the device; When the host computer fails to retrieve the valid test record corresponding to the specific test site, it fills the corresponding position in the target data table with a preset null value code or skip code.

10. A method for supporting data merging in multi-site testing on a host computer according to claim 5, characterized in that, The method also includes a processing step for physical empty material: when the test station is the first test station and the inlet sensor outputs a low level, the host computer marks the logic segment value in the virtual shift register corresponding to the first test station as the empty material state; In the asynchronous data merging step of S500, when the host computer recognizes that the test state corresponding to the unique identifier of the device is the empty material state, it marks a skip flag in the generated device test record.

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