Chip with current mirror type voltage source

Abstract

The invention discloses a chip with a current mirror type voltage source, and the current mirror type voltage source comprises a first n-channel metal oxide semiconductor field effect transistor (NMOS) and a second NMOS, the drains of which are coupled to a first voltage source; the output end of the operational amplifier is coupled to the grid electrodes of the first NMOS and the second NMOS, the negative input end of the operational amplifier is coupled to the source electrode of the first NMOS to form a negative feedback loop, and the positive input end of the operational amplifier is coupled to the source electrode of the second NMOS to form a positive feedback loop; wherein the operational amplifier is powered by a second voltage source larger than the first voltage source, so that the first NMOS and the second NMOS work in a saturation region, and the current mirror type voltage source outputs a load current mirrored with a first current. By adopting the mode, the grid electrodes of the first NMOS and the second NMOS are controlled by the output end of the operational amplifier, and the working voltage margin of the pair of NMOS, namely the first NMOS and the second NMOS, is wider.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to chips with current mirror voltage sources. Background Technology

[0002] Figure 1 illustrates a conventional chip power supply design. As shown, a low-dropout regulator (LDO) 102 and a current mirror 104 power the load RL. The LDO 102 uses an n-channel metal-oxide-semiconductor field-effect transistor (NMOS) Mn as the power MOSFET to improve the power supply rejection ratio (PSRR). The regulated voltage (e.g., 0.85V) generated by the LDO 102 powers the current mirror 104, which generates a load current IL to drive the load RL. The current mirror 104 uses a p-channel metal-oxide-semiconductor field-effect transistor (PMOS) Mp to supply the load current IL to the load RL. Cascaded NMOS Mn and PMOS Mp need to share a limited dynamic margin (e.g., 1V to 0.6V). PMOSMp may introduce power supply jitter (PSJ) from the 1V voltage source to the load RL, typically 3% to 5% UI (UI is an abbreviation for Unit Interval in high-speed SerDes applications). Summary of the Invention

[0003] In view of this, the present invention provides a novel chip with a novel power supply design that includes a voltage source structure that operates as a current source with an improved power supply rejection ratio (PSRR). This voltage source structure is also known as a current-mirror-like voltage source.

[0004] In one exemplary embodiment, a chip with a current mirror voltage source is shown. The current mirror voltage source includes a first n-channel metal-oxide-semiconductor field-effect transistor (NMOS), a second NMOS, and an operational amplifier. The drains of the first and second NMOS are coupled to the first voltage source. The output of the operational amplifier is coupled to the gates of the first and second NMOS, with its negative input coupled to the source of the first NMOS to form a negative feedback loop and its positive input coupled to the source of the second NMOS to form a positive feedback loop. The operational amplifier is powered by a second voltage source greater than the first voltage source, causing the first and second NMOS to operate in the saturation region, thereby causing the current mirror voltage source to output a load current mirrored to the first current.

[0005] In one exemplary embodiment, the chip also has a low-resistance load. This low-resistance load is driven by the load current and its resistance is below a threshold, thereby ensuring that the current mirror voltage source operates in its stable region.

[0006] In one exemplary embodiment, the chip also includes a charge pump and a low-pass filter. The charge pump pumps current from a first voltage source to a second voltage source. The low-pass filter is coupled to the output of the charge pump to filter the second voltage source and then couples the filtered second voltage source to an operational amplifier. This significantly suppresses power supply jitter (PSJ) introduced into the load.

[0007] In one exemplary embodiment, the drains of the first and second NMOS are directly coupled to a first voltage source without passing through any transistors.

[0008] In one exemplary embodiment, the source of the second NMOS is directly coupled to a low-resistance load without passing through any transistor. This provides a stable current to the load RL.

[0009] Furthermore, it also includes: a low-resistance load driven by the load current, wherein the resistance of the low-resistance load is below a threshold value that ensures the current mirror voltage source operates in a stable region.

[0010] Furthermore, the threshold depends on the first resistor and the size ratio of the second NMOS to the first NMOS; the first resistor is determined by V1 / I1, where I1 is the first current and V1 is the voltage at the first connection node between the negative input terminal of the operational amplifier and the source of the first NMOS; and the low-impedance load is coupled to the second connection node between the positive input terminal of the operational amplifier and the source of the second NMOS.

[0011] Furthermore, the threshold is R1 / M, where R1 is the first resistance and M is the size ratio of the second NMOS to the first NMOS.

[0012] Furthermore, it also includes a ring oscillator driven by the load current, thereby driving the ring oscillator to operate stably.

[0013] Furthermore, it also includes: a charge pump that pumps the first voltage source to the second voltage source; and a low-pass filter located at the output of the charge pump, used to filter the second voltage source and couple the filtered second voltage source to the operational amplifier. This results in a stable and clean second voltage source output, ensuring stable operation of the operational amplifier and providing a wider operating voltage margin for the first and second NMOS transistors, thus suppressing PSJ.

[0014] Furthermore, the first voltage source and the second voltage source are external voltage sources coupled to the chip, thereby providing a stable voltage source for the chip to operate.

[0015] Furthermore, the first connection node between the negative input terminal of the operational amplifier and the source of the first NMOS is at a first voltage V1; the second connection node between the positive input terminal of the operational amplifier and the source of the second NMOS is at a second voltage V2; the operational amplifier outputs a third voltage V3; V3 is greater than V1 plus Vth1, where Vth1 is the threshold voltage of the first NMOS; and V3 is greater than V2 plus Vth2, where Vth2 is the threshold voltage of the second NMOS.

[0016] Furthermore, V3 is less than Vdd1 plus Vth1 and also less than Vdd1 plus Vth2, where Vdd1 is the first voltage source.

[0017] Furthermore, the drains of the first NMOS and the second NMOS are directly coupled to the first voltage source without passing through any transistors.

[0018] Furthermore, the source of the second NMOS is directly coupled to the low-resistance load driven by the load current, without passing through any transistor. This provides a stable current to the load RL.

[0019] Furthermore, it also includes a current mirror, which is coupled to a first connection node between the negative input terminal of the operational amplifier and the source of the first NMOS, for determining the first current. Thus, a stable first current is provided using the current mirror.

[0020] Furthermore, it also includes a third NMOS, whose drain is coupled to the second connection node to provide an additional current path to regulate the load current driving the low-resistance load.

[0021] One advantage of this invention is that the chip with a current mirror voltage source includes: a first n-channel metal-oxide-semiconductor field-effect transistor (NMOS) and a second NMOS, whose drains are coupled to a first voltage source; and an operational amplifier, whose output is coupled to the gates of the first and second NMOS, whose negative input is coupled to the source of the first NMOS to form a negative feedback loop, and whose positive input is coupled to the source of the second NMOS to form a positive feedback loop. The operational amplifier is powered by a second voltage source with a voltage greater than that of the first voltage source, so that the first and second NMOS operate in the saturation region, thereby causing the current mirror voltage source to output a load current mirrored to the first current. In this way, the gates of the first and second NMOS are controlled by the output of the operational amplifier, providing a wider operating voltage margin for this pair of NMOS transistors. Furthermore, the clean second voltage source improves the power supply rejection ratio (PSRR), and the load operation is no longer affected by the noisy first voltage source, but relies more on the clean second voltage source. Therefore, PSRR can be suppressed to 1% or lower, thereby improving chip performance. Attached Figure Description

[0022] Figure 1 illustrates a conventional power supply design on the chip; Figure 2 illustrates a power supply design according to an exemplary embodiment of the present invention; Figure 3 shows the DC analysis of the circuit shown in Figure 2; Figure 4 illustrates a power supply design according to another exemplary embodiment of the present invention; and Figure 5 shows the DC analysis of the circuit shown in Figure 4. Detailed Implementation

[0023] The following description is for illustrative purposes only and should not be construed as limiting. The scope of the invention is best determined by reference to the appended claims. In embodiments of the invention, when a component or layer is referred to as being "located in," "connected to," or "coupled to" another component or layer, it may be directly located in, connected to, or coupled to that other component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as being "directly located in," "directly connected to," or "directly coupled to" another component or layer, there are no intermediate components or layers. The same numbers always refer to the same component. Certain terms are used in the following description and claims, which refer to specific components. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to a particular component. This document is not intended to distinguish between components with different names but the same function. In the following description and claims, the terms "comprising" and "including" are used in an open-ended manner and should therefore be understood as "including but not limited to...".

[0024] Figure 2 illustrates a power supply design according to an exemplary embodiment of the present invention. The load RL is driven by a stable load current IL provided by the current mirror voltage source 202 introduced in this invention. In addition to the load RL, Figure 2 The circuit shown in Figure 2 can be called a power supply circuit. It can be part of the chip and integrated within it. The load RL can be located either inside or outside the chip.

[0025] The current mirror voltage source 202 includes a first n-channel metal-oxide-semiconductor field-effect transistor (NMOS) Mn1, a second NMOS Mn2, and an operational amplifier OPAMP. The drains of both the first NMOS Mn1 and the second NMOS Mn2 are coupled to a first voltage source Vdd1 (e.g., 1V or another voltage value). The gates of both the first NMOS Mn1 and the second NMOS Mn2 are controlled by the operational amplifier OPAMP. The positive input terminal of the operational amplifier OPAMP is coupled to the source of the second NMOS Mn2, forming a positive feedback loop. The negative input terminal of the operational amplifier OPAMP is coupled to the source of the first NMOS Mn1, forming a negative feedback loop. Specifically, the operational amplifier OPAMP is powered by a second voltage source Vdd2 (e.g., 1.8V), which is greater than the first voltage source Vdd1 (e.g., 1V). Therefore, the operational amplifier OPAMP can turn on the first and second NMOS Mn1 and Mn2, thereby forming both positive and negative feedback loops. Based on the concept of a negative impedance converter, an NMOS source follower controlled by an operational amplifier (OPAMP) forms a current mirror voltage source 202.

[0026] In this invention, the operational amplifier OPAMP, powered by the second voltage source Vdd2 (greater than the first voltage source Vdd1), causes the first NMOS Mn1 and the second NMOS Mn2 to operate in the saturation region, thereby causing the current mirror voltage source 202 to output the load current IL obtained by mirroring the first current I1.

[0027] Specifically, the load RL driven by the load current IL is a low-resistance load with a resistance below a threshold, thereby ensuring that the current mirror voltage source 202 operates in its stable region. This low-resistance load (RL) can be a ring oscillator or any current-driven device.

[0028] In the example shown in Figure 2, the size of the second NMOS Mn2 is M times that of the first NMOS Mn1. A first connection node n1 between the source of the first NMOS Mn1 and the negative input of the operational amplifier OPAMP is connected to a current mirror 204, which determines a first current I1. A second connection node between the source of the second NMOS Mn2 and the positive input of the operational amplifier OPAMP is connected to the load RL to provide a load current IL (IL = M × I1, mirrored from the first current I1) to drive the load RL.

[0029] As shown in Figure 2, the drains of the first and second NMOS transistors Mn1 and Mn2 are directly coupled to the first voltage source Vdd1 without passing through any transistors; the source of the second NMOS transistor Mn2 is directly coupled to the load RL without passing through any transistors. Unlike the cascaded NMOS pair of LDO 102 and PMOS pair of current mirror 104 in Figure 1 to share a limited voltage margin, the NMOS pair (Mn1 and Mn2) of the current-mirror-like voltage source 202 proposed in this embodiment has a much wider operating voltage margin.

[0030] Figure 2 also illustrates the charge pump 206 and the low-pass filter 208. The charge pump 206 pumps a first voltage source Vdd1 (1V) to a second voltage source Vdd2 (1.8V). The second voltage source Vdd2 (1.8V) is filtered by the low-pass filter 208 before being coupled to the operational amplifier OPAMP. Because the operational amplifier OPAMP is designed for low power consumption, the low-pass filter 208 can be very small. The clean second voltage source Vdd2 (1.8V) improves the power supply rejection ratio (PSRR). As shown in Figure 1, the operation of the load RL is no longer affected by the noisy 1V power supply, but relies more on the clean 1.8V voltage source, thus the PSRR can be suppressed to 1% or lower.

[0031] In another exemplary embodiment, both the first voltage source Vdd1 (1V) and the second voltage source Vdd2 (1.8V) are external voltage sources. In this case, the charge pump 206 and the low-pass filter 208 are not required.

[0032] In another exemplary embodiment, the bias voltage V3 is generated by directly pumping the first voltage source using only Vdd1 as the voltage source. In this design, the charge pump 206 and the low-pass filter 208 are not necessary. Alternatively, the charge pump 206 and the low-pass filter 208 can be incorporated into this pumping technique.

[0033] The operating conditions of the current mirror voltage source 202 will be discussed in the following paragraphs. First, the first NMOS Mn1 and the second NMOS Mn2 need to operate in the saturation region. Furthermore, the current mirror voltage source 202 needs to operate in the stable region.

[0034] To ensure that the first NMOS Mn1 and the second NMOS Mn2 are in saturation, the bias voltage V3 generated by the operational amplifier (OPAMP) needs to be greater than (V1 + Vth1). V3 is less than Vdd1 + Vth1 and also less than Vdd1 + Vth2, where Vdd1 is the first voltage source and V2 is the second voltage source. The threshold voltage of the first NMOS Mn1 is Vth1, and the threshold voltage of the second NMOS Mn2 is Vth2. More specifically, V3 is less than Vdd1 + Vth1 and also less than Vdd1 + Vth2, where Vdd1 is the first voltage source.

[0035] Regarding stability, the negative feedback loop needs to be stronger than the positive feedback loop. The resistance from the source of the first NMOS Mn1 to the current mirror 204 is the first resistance R1 (=V1 / I1). The low-resistance load threshold used to implement the load RL may depend on the first resistance R1 (=V1 / I1) and the size ratio M of the second NMOS Mn2 to the first NMOS Mn1. For example, the threshold could be R1 / M. Low-resistance loads with resistance less than R1 / M are suitable for the current mirror voltage source 202.

[0036] In another exemplary embodiment, the size (xM) of the second NMOS Mn2 depends on the ratio of R1 / RL. For example, when R1 / RL is 40, M should be less than 40 (e.g., M=32), thereby making the negative feedback loop stronger than the positive feedback loop, and the current mirror voltage source 202 operates stably.

[0037] Figure 3 shows the DC analysis of the circuit in Figure 2, where the first NMOS Mn1 is represented by its transconductance Gm1, and the second NMOS Mn2 is represented by its transconductance Gm2 (Gm2 = M × Gm1). In this structure, V1 = V2, and I DS2 = M×I DS1 (=M×I1). The working principle of the circuit can be derived mathematically as follows: Formula 1; Formula 2; The figure shows behavior similar to that of an electric current.

[0038] Regarding stability analysis, the stability of the dual-loop structure is achieved by ensuring that the negative feedback gain is greater than the positive feedback gain; therefore: Gm1 × R1 > Gm2 × RL; I DS1 × R1>I DS2 × RL; I DS1 × R1>I DS1 × M × RL; R1>M × RL; The low-impedance load RL using the current mirror voltage source 202 satisfies the following relationship: R1 > M × RL. In this embodiment, the maximum voltage supplied to the load RL can also be increased, thus making it suitable for more scenarios.

[0039] Figure 4 illustrates a power supply design according to another exemplary embodiment of the present invention. Compared to Figure 2, the power supply design of Figure 4 further utilizes a third NMOS Mn3 to establish an additional current path to regulate the load current IL driving the load RL. Figure 4 It also has another NMOS, which can be a counterpart to the third NMOS Mn3. Figure 4 Apart from the load RL, the rest of the circuit can be called the power supply circuit, which can be located inside or on the chip. The load RL can be located inside or outside the chip.

[0040] Figure 5 shows the DC analysis of the circuit in Figure 4, where the first NMOS Mn1 is represented by its transconductance Gm1, the second NMOS Mn2 by its transconductance Gm2 (Gm2=Gm1×K / 2), and the third NMOS Mn3 by its transconductance Gm3 (Gm3=Gm×K / 32). In this structure, V1 = V2, I DS2 = K / 2 × I DS1 (=K / 2 × I1), I2 = K / 32 ×I DS1 (=K / 32 × I1). The operating principle of this power supply design can be derived mathematically as follows: Formula 3; Formula 4; Figure 4 The structure shown also exhibits current characteristics. Both the first and second NMOS transistors, Mn1 and Mn2, operate in the saturation region, where: V1 + Vth1 <V3<Vdd1 + Vth1; V2 + Vth2 <V3<Vdd1 + Vth2; In addition, to ensure the stability of the power circuit design, the load resistance RL should be low enough (determined by the resistance value calculated based on V1 / I1 and the size ratio (K / 2) of the first NMOS Mn1 to the second NMOS Mn2) to satisfy the relationship that the strength of the negative feedback loop is greater than that of the positive feedback loop.

[0041] In summary, any power circuit design that uses a pair of NMOS transistors (Mn1 and Mn2) and an operational amplifier (OPAMP) to form a dual-loop source follower as a current mirror voltage source 202 should be within the scope of this invention.

[0042] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and similar arrangements (as will be apparent to those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A chip with a current mirror voltage source, characterized in that, The current mirror voltage source includes: A first n-channel metal-oxide-semiconductor field-effect transistor (NMOS) and a second NMOS, their drains coupled to a first voltage source; and An operational amplifier, the output of which is coupled to the gate of the first NMOS and the second NMOS, the negative input of which is coupled to the source of the first NMOS to form a negative feedback loop, and the positive input of which is coupled to the source of the second NMOS to form a positive feedback loop. The operational amplifier is powered by a second voltage source that is greater than the first voltage source, so that the first NMOS and the second NMOS operate in the saturation region, thereby causing the current mirror voltage source to output a load current that mirrors the first current.

2. The chip as described in claim 1, characterized in that, Also includes: A low-resistance load, driven by the load current, has a resistance below a threshold that ensures the current mirror voltage source operates in a stable region.

3. The chip as described in claim 2, characterized in that, The threshold depends on the first resistor and the size ratio of the second NMOS to the first NMOS; The first resistor is determined by V1 / I1, where I1 is the first current and V1 is the voltage at the first connection node between the negative input terminal of the operational amplifier and the source of the first NMOS transistor; and The low-impedance load is coupled to a second connection node between the positive input terminal of the operational amplifier and the source of the second NMOS.

4. The chip as described in claim 3, characterized in that, The threshold is R1 / M. Where R1 is the first resistor, and M is the size ratio of the second NMOS to the first NMOS.

5. The chip as described in claim 1, characterized in that, Also includes: A charge pump that pumps the first voltage source to the second voltage source; as well as A low-pass filter located at the output of the charge pump is used to filter the second voltage source and couple the filtered second voltage source to the operational amplifier.

6. The chip as described in claim 1, characterized in that, The first voltage source and the second voltage source are external voltage sources coupled to the chip.

7. The chip as described in claim 1, characterized in that, The first connection node between the negative input terminal of the operational amplifier and the first NMOS source is at a first voltage V1; The second connection node between the positive input terminal of the operational amplifier and the source of the second NMOS is at the second voltage V2; The operational amplifier outputs a third voltage V3; V3 is greater than V1 plus Vth1, where Vth1 is the threshold voltage of the first NMOS; and V3 is greater than V2 plus Vth2, where Vth2 is the threshold voltage of the second NMOS.

8. The chip as described in claim 7, characterized in that, V3 is less than Vdd1 plus Vth1, and also less than Vdd1 plus Vth2, where Vdd1 is the first voltage source.

9. The chip as described in claim 1, characterized in that, The drains of the first NMOS and the second NMOS are directly coupled to the first voltage source without passing through any transistor; or / and the source of the second NMOS is directly coupled to a low-resistance load driven by the load current without passing through any transistor.

10. The chip as described in claim 1, characterized in that, Also includes: A current mirror, coupled to a first connection node between the negative input terminal of the operational amplifier and the source of the first NMOS, is used to determine the first current.

11. The chip as described in claim 3, characterized in that, Also includes: A third NMOS, whose drain is coupled to the second connection node, provides an additional current path to regulate the load current driving the low-resistance load.

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