Test pattern generation device, resource board card and test machine

Abstract

The invention relates to a test pattern generation device, a resource board card and a test machine, and the test pattern generation device comprises a sequence controller which is used for issuing corresponding data signals and control signals; the address generation module is used for performing multi-channel address selection operation on the received data signal according to the received control signal and outputting an address after multi-channel operation to the delay module; the data generation module is used for performing multi-path data selection operation on the received data signal according to the received control signal and outputting multi-path operated data to the delay module; the delay module is used for delaying the addresses and the data after multi-path operation and then sending the delayed addresses and the delayed data to the signal mapping module; and the signal mapping module is used for selecting multiple paths of specified physical mapped addresses and data output from the multiple paths of operated addresses and the multiple paths of operated data according to the received control signal, so that the data volume generated by the test pattern is conveniently increased, and the test efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and in particular to a test pattern generation device, a resource board, and a testing machine. Background Technology

[0002] Semiconductor automated testing refers to the use of Automatic Test Equipment (ATE) to inspect various parameters of the Device Under Test (DUT), eliminating defective products and controlling the quality of semiconductor devices before they leave the factory. The resource boards of the test equipment are responsible for generating corresponding test signals based on the test pattern information and sending them to the DUT. However, due to the increasingly higher demands on test speeds, the current data generation rate of the resource boards is insufficient to meet these requirements. Therefore, improving test efficiency is a pressing issue that needs to be addressed. Summary of the Invention

[0003] Therefore, it is necessary to provide a test pattern generation device, resource board, and test machine that can improve testing efficiency to address the above problems.

[0004] The first aspect of this application provides a test pattern generation apparatus, comprising:

[0005] The sequence controller connects the address generation module, the data generation module, and the signal mapping module, and is used to send out the corresponding data signals and control signals respectively.

[0006] The address generation module is connected to the delay module and is used to perform multi-address selection operation on the received data signal according to the received control signal, and output the multi-address after multi-address selection to the delay module.

[0007] The data generation module is connected to the delay module and is used to perform multi-channel data selection operation on the received data signal according to the received control signal, and output the multi-channel processed data to the delay module.

[0008] The delay module is connected to the signal mapping module and is used to delay the multi-processed address and multi-processed data before sending them to the signal mapping module.

[0009] The signal mapping module is used to select multiple specified physical mapped addresses and data from the multi-processed addresses and multi-processed data according to the received control signals and output them.

[0010] The address generation module, the data generation module, and the delay module all simultaneously receive the output data from the previous module and the control signal issued by the sequence controller, and process the output data of the previous module accordingly based on the received control signal.

[0011] In one embodiment, the address generation module receives N address data from the sequence controller. Each address data includes X sets of address data, Y sets of address data, and Z sets of register data. Each address data is combined with an immediate value for logical operation to obtain N first intermediate data. The address generation module also combines the N first intermediate data and the second register data from the sequence controller as data sources for M logical operations. Each operation outputs two sets of addresses, where when N equals 1, M is greater than N; when N is greater than 1, M is greater than or equal to N.

[0012] In one embodiment, the address generation module receives N channels of first register data from the sequence controller. Each channel of first register data includes X groups of maximum address limits, Y groups of maximum address limits, and third register data. These data are used to perform logical operations by combining the X groups of address data, the Y groups of address data, and the immediate values ​​within the corresponding channel of address data to generate the first intermediate data for the corresponding channel.

[0013] In one embodiment, each path of the first register number is combined with the X group of address data, the Y group of address data, and the immediate value within the corresponding path of address data to perform logical operations, including:

[0014] The selected data from the third register is logically operated on with the X group address data / the Y group address data. The output data after the logical operation is then compared with the maximum limit of the X group address / the maximum limit of the Y group address.

[0015] If the data after the logical operation is greater than the maximum limit of the X group address / the maximum limit of the Y group address, the data after the logical operation is subtracted from the maximum limit of the X group address / the maximum limit of the Y group address, and the remainder is used as the first intermediate number of the X group address / the first intermediate number of the Y group address, and the carry data is output to participate in the logical operation of the Y group address data / Z group register data;

[0016] If the data after the logical operation is less than the maximum limit of the X group address / the maximum limit of the Y group address, the data after the logical operation is output as the first intermediate number of the X group address / the first intermediate number of the Y group address.

[0017] In one embodiment, the address generation module combines the second register data, the N sets of first intermediate data, and the second intermediate data for every two logical operations as data sources to perform logical operations on each path, and outputs two sets of addresses after the operations on each path.

[0018] In one embodiment, when the total number of logic operations M is even, the address generation module sequentially combines the second intermediate data of every two logic operations, the second register data, and the N sets of first intermediate data as data sources to perform logic operations on each path; when the total number of logic operations M is odd, the address generation module sequentially combines the second intermediate data of every two logic operations, the second register data, and the N sets of first intermediate data as data sources to perform logic operations on path M-1, and combines the second register data and the N sets of first intermediate data as data sources to perform logic operations on path M.

[0019] In one embodiment, when N equals 1, the address generation module performs two logical operations in one logical operation, using the first intermediate data RXA-RXH, the first intermediate data RYA-RYH, and the first intermediate data RZA-RZE as data sources, to obtain the second intermediate data XS1 and the second intermediate data YS1. Combining the second intermediate data XS1, the second intermediate data YS1, the first intermediate data RZA-RZE, and the second intermediate data XS2 and the second intermediate data YS2 of another logical operation as data sources, it performs two logical operations to obtain the third intermediate data XT and the third intermediate data YT. Combining the third intermediate data XT, the third intermediate data YT, and the corresponding second register data, it performs two logical operations to output the post-operation address X1 and the post-operation address Y1.

[0020] The first intermediate data RXA-RXH is intermediate data obtained by performing logical operations on the immediate value and the X group of address data, and the first intermediate data RYA-RYH is intermediate data obtained by performing logical operations on the immediate value and the Y group of address data.

[0021] In one embodiment, the address generation module combines the second intermediate data XS1, the second intermediate data YS1, the first intermediate data RZA-RZE, the second intermediate data XS2 and the second intermediate data YS2 of another logical operation, and the configured specified address data as data sources to perform two logical operations respectively to obtain the third intermediate data XT and the third intermediate data YT.

[0022] In one embodiment, the data generation module performs logical operations on the 2M sets of fourth register data issued by the sequence controller in combination with immediate values ​​to obtain 2M sets of fourth intermediate data. The data generation module also performs M-way logical operations on the 2M sets of fourth intermediate data and the fifth register data issued by the sequence controller as data sources, and outputs two sets of processed data on each way.

[0023] In one embodiment, each pair of fourth register data is combined with immediate values ​​to perform logical operations, generating two pairs of fourth intermediate data to form one path of fourth intermediate data; the data generation module also combines the fourth intermediate data of each pair of paths and the corresponding fifth register data as data sources to perform M-path logical operations, and outputs two sets of processed data for each path.

[0024] In one embodiment, when the total number of logic operations M is even, the data generation module sequentially combines the fourth intermediate data of every two logic operations and the corresponding fifth register data as data sources to perform logic operations on each path; when the total number of logic operations M is odd, the data generation module sequentially combines the fourth intermediate data of every two logic operations and the corresponding fifth register data as data sources to perform logic operations on M-1 paths, and then combines the fourth intermediate data of the Mth path and the corresponding fifth register data as data sources to perform logic operations on the Mth path.

[0025] In one embodiment, the fifth register data includes toggled data and DBI comparison data. Based on the fourth intermediate data, a first leading edge intermediate data and a first trailing edge intermediate data are selected. After the first leading edge intermediate data and the first trailing edge intermediate data are logically operated with the toggled data, the operation results are respectively subjected to data bus toggled operation with the DBI comparison data, and the operation results are output as the operation results of the leading edge data LDATA1 and the operation results of the trailing edge data TDATA1.

[0026] In one embodiment, the data generation module compares the DBI comparison data with the received calculation result. If the number of addresses with 1 in the calculation result is greater than the data bit width / 2, the received calculation result is completely flipped, and the leading edge data LDATA1 and the trailing edge data TDATA1 after the calculation are output.

[0027] In one embodiment, the test pattern generation apparatus further includes:

[0028] The first verification module, connected to the address generation module and the delay module, is used to verify the received processed address according to the received control signal and output the multi-processed address information to the delay module.

[0029] The second verification module is connected to the data generation module and the delay module. It is used to verify the received processed data according to the received control signal and output the multi-processed data information to the delay module.

[0030] Both the first verification module and the second verification module simultaneously receive the output data from the previous module and the control signal issued by the sequence controller, and process the output data of the previous module accordingly based on the received control signal;

[0031] The delay module delays the processed address information and processed data information before sending them to the signal mapping module. The signal mapping module selects and outputs multiple specified physically mapped addresses and data from the processed address information and processed data information according to the received control signal.

[0032] In one embodiment, the test pattern generating apparatus includes a first test pattern generating module and a second test pattern generating module;

[0033] The first test pattern generation module includes the sequence controller, the address generation module, the data generation module, the delay module, the signal mapping module, the comparison enable parameter delay module, and the output enable parameter delay module. The comparison enable parameter delay module and the output enable parameter delay module are both connected to the sequence controller.

[0034] The second test pattern generation module includes an output enable data module, a comparison enable data module, and a multiplexer. The output enable data module is connected to the output enable parameter delay module, the comparison enable data module is connected to the comparison enable parameter delay module, and the multiplexer is connected to the signal mapping module, the output enable data module, the comparison enable data module, and the timing module. The timing module is connected to the device under test through a PE chip.

[0035] The output enable parameter delay module is used to delay the output enable parameters of the corresponding path issued by the sequence controller before sending them to the output enable data module; the comparison enable parameter delay module is used to delay the comparison enable parameters of the corresponding path issued by the sequence controller before sending them to the comparison enable data module; the output enable data module enables or disables the output based on the received output enable parameters; the comparison enable data module performs a comparison or does not perform a comparison based on the received comparison enable parameters.

[0036] The multiplexer is used to select and output each enabled or disabled output, each comparison output or non-comparison output, and each physically mapped address and data output by the signal mapping module to the timing module.

[0037] In one embodiment, the first test pattern generation module further includes a specified data parameter delay module, and the second test pattern generation module further includes a specified data module and a graphic data storage module. The specified data parameter delay module is connected to the sequence controller and the specified data module, and the multiplexer is connected to the specified data module and the graphic data storage module.

[0038] The specified data parameter delay module is used to delay the specified data parameters of the corresponding channel issued by the sequence controller before sending them to the specified data module; the specified data module selects the specified data of the corresponding channel from the preset data according to the received specified data parameters and sends it to the multiplexer; the multiplexer selects and outputs the enabled or disabled output of each channel, the comparison output of each channel, the physical mapped address and data of each channel, the specified data of each channel, and the preset graphics data in the graphics data storage modules of each channel to the timing module.

[0039] The second aspect of this application provides a resource board, including a timing module, a PE chip, and the aforementioned test pattern generation device. The timing module performs waveform conversion and outputs the waveform change edge to the PE chip after delaying the received data. It also samples and compares the signal returned by the PE chip at the comparison time according to the comparison expectation value, obtains the comparison result, and stores it in the storage module.

[0040] A third aspect of this application provides a test machine, including the aforementioned resource board.

[0041] The aforementioned test pattern generation device, resource board, and test machine, along with the sequence controller, respectively send out corresponding data and control signals. The address generation module, based on the received control signal, performs a multi-channel address selection operation on the received data signal and outputs the multi-channel processed addresses to the delay module. The data generation module, based on the received control signal, performs a multi-channel data selection operation on the received data signal and outputs the multi-channel processed data to the delay module. The delay module delays both the multi-channel processed addresses and data before sending them to the signal mapping module. The signal mapping module, based on the received control signal, selects multiple specified physically mapped addresses and data from the multi-channel processed addresses and data for output. By performing multi-channel address selection and multi-channel data selection operations, and finally selecting multiple specified physically mapped addresses and data for output, the amount of data generated for test patterns can be increased, improving test efficiency. Attached Figure Description

[0042] Figure 1 This is a structural block diagram of a test pattern generation device in one embodiment;

[0043] Figure 2 This is a schematic diagram of the structure of a test pattern generation device in one embodiment;

[0044] Figure 3 This is a schematic diagram of the test pattern generation device in another embodiment;

[0045] Figure 4Here is a logic block diagram of the address generation module (1WAY) in one embodiment;

[0046] Figure 5 Here is a logic block diagram of the address generation module (2WAY) in one embodiment;

[0047] Figure 6 Here is a logic block diagram of the data generation module (1WAY) in one embodiment;

[0048] Figure 7 This is a logic block diagram of a data generation module (2WAY) in one embodiment. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. It is understood that the term "connection" in the following embodiments, if the connected circuits, modules, units, etc., transmit electrical signals or data to each other, should be understood as "electrical connection," "communication connection," etc.

[0051] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, operations, components, parts, or combinations thereof.

[0052] In one embodiment, such as Figure 1As shown, a test pattern generation device is provided, including a sequence controller 110, an address generation module 120, a data generation module 130, a delay module 160, and a signal mapping (PDM) module 170. The sequence controller 110 is connected to the address generation module 120, the data generation module 130, and the signal mapping module 170, and is used to send corresponding data signals and control signals respectively. The address generation module 120 is connected to the delay module 160, and is used to perform multi-channel address selection operation on the received data signal according to the received control signal, and output the multi-channel processed address to the delay module. Module 160; Data generation module 130 is connected to delay module 160 and is used to perform multi-channel data selection operation on the received data signal according to the received control signal, and output the multi-channel processed data to delay module 160; Delay module 160 is connected to signal mapping module 170 and is used to delay the multi-channel processed address and multi-channel processed data, and then send them to signal mapping module 170; Signal mapping module 170 is used to select multiple specified physical mapped addresses and data from the multi-channel processed address and multi-channel processed data according to the received control signal and output them.

[0053] The sequence controller 110 can be connected to a test pattern memory and sends corresponding data and control signals based on the test pattern information stored in the memory. The address generation module 120, data generation module 130, and delay module 160 all simultaneously receive the output data from the previous module and the control signals from the sequence controller 110, and process the output data of the previous module accordingly based on the received control signals. Specifically, the address generation module 120 selects a specified bit from the data signal sent by the sequence controller 110 as the original address according to the control signal sent by the sequence controller 110, and then performs operations on the original address and data signal, such as addition, subtraction, multiplication, division, AND, OR, XOR, and flipping operations, as well as selection operations, to obtain the processed address. The data generation module 130 selects a specified bit from the data signal sent by the sequence controller 110 as the original data according to the control signal sent by the sequence controller 110, and then performs operations on the original data and data signal, such as addition, subtraction, multiplication, division, AND, OR, XOR, and flipping operations, as well as selection operations, to obtain the processed data. The delay module 160 delays the received processed address and processed data to ensure that the processed address and processed data transmitted to the signal mapping module 170 at the same time are aligned with the control signals and data signals issued by the sequence controller 110.

[0054] Furthermore, such as Figure 2As shown, the test pattern generation device also includes a first verification module 140 and a second verification module 150. The first verification module 140 is connected to the address generation module 120 and the delay module 160, and is used to verify the received processed address according to the received control signal, and output the multi-processed address information to the delay module 160. The second verification module 150 is connected to the data generation module 130 and the delay module 160, and is used to verify the received processed data according to the received control signal, and output the multi-processed data information to the delay module 160. Both the first verification module 140 and the second verification module 150 simultaneously receive the output data of the previous module and the control signal issued by the sequence controller 110, and perform corresponding processing on the output data of the previous module based on the received control signal. Correspondingly, the delay module 160 delays the multi-processed address information and multi-processed data information before sending them to the signal mapping module 170; the signal mapping module 170 selects multiple specified physically mapped addresses and data from the multi-processed address information and multi-processed data information according to the received control signal and outputs them.

[0055] The specific types of the first verification module 140 and the second verification module 150 are not unique. In this embodiment, the first verification module 140 is an even parity check module. Based on the control signal sent by the sequence controller 110, it selects an even parity check rule to verify the processed address. The output processed address information includes the even parity check result and the processed address. The second verification module 150 is a CRC check module. Based on the control signal sent by the sequence controller 110, it selects a CRC check rule (including not performing CRC operation), performs a CRC operation on the processed data according to the selected CRC check rule, and the output processed data information includes the check result, and, according to the check rule, also includes or partially includes the reversed data.

[0056] It is understandable that the functions performed by the above modules are different, so the control signals sent by the sequence controller 110 to each module are also different. Each module performs its corresponding function based on the control signals it receives. The physically mapped address and data output by the signal mapping module 170 are data of fixed bit length. The signal mapping module 170 controls each bit to select the processed address information and processed data information according to the received control signals, thereby forming the fixed-bit physically mapped address and data. The sequence controller 110 also sets the time interval for sending different control signals according to the processing time of the address generation module 120, data generation module 130, first verification module 140, second verification module 150, delay module 160, and signal mapping module 170. This ensures that the address generation module 120, data generation module 130, first verification module 140, second verification module 150, delay module 160, and signal mapping module 170 all simultaneously receive the output data of the previous module and the control signals sent by the sequence controller 110, and process the output data of the previous module accordingly based on the received control signals. It is understandable that the sequence controller 110 can also output control signals from each module simultaneously. Each control signal is delayed through a corresponding transmission path to ensure that the control signals received by each functional module and the output data of the previous module arrive at the same time.

[0057] In other embodiments, when the sequence controller 110 simultaneously sends control signals to each module, the control signal of each module can be sent to the corresponding module after a corresponding path delay, or the control signal of each module can be sent down serially with a delay within the address generation module 120 and the first verification module 140 (or the data generation module 130 and the second verification module 150). The control signals and data signals required by the subsequent modules are delayed by the processing time required by the current module before being sent to the subsequent modules, so that different modules can simultaneously receive the output data and corresponding control signals of the previous module.

[0058] Test pattern generation devices can be built based on FPGAs (Field-Programmable Gate Arrays) or other types of processing devices. Taking FPGA as an example, the test pattern generation device can use the same FPGA to build internal modules, or it can use multiple FPGAs to build a separate architecture.

[0059] In one embodiment, such as Figure 2As shown, the test pattern generation device includes a first test pattern generation module ALPG1 and a second test pattern generation module ALPG2. The first test pattern generation module ALPG1 includes a sequence controller 110, an address generation module 120, a data generation module 130, a first verification module 140, a second verification module 150, a delay module 160, a signal mapping module 170, an output enable (DRE) parameter delay module 180, and a comparison enable (CPE) parameter delay module 190. Both the comparison enable parameter delay module 190 and the output enable parameter delay module 180 are connected to the sequence controller 110. The second test pattern generation module ALPG2 includes an output enable data module 210, a comparison enable data module 220, and a multiplexer MUX. The output enable data module 210 is connected to the output enable parameter delay module 180, the comparison enable data module 220 is connected to the comparison enable parameter delay module 190, and the multiplexer MUX is connected to the signal mapping module 170, the output enable data module 210, the comparison enable data module 220, and the timing module 250. The timing module 250 is connected to the device under test (DUT) through the PE (pin circuit) chip 300.

[0060] The first test pattern generation module ALPG1 can be distributed on one or more FPGAs on the motherboard of the resource board, and the second test pattern generation module ALPG2 can be distributed on one or more FPGAs on the daughterboard of the resource board. The output enable parameter delay module 180 is used to delay the output enable parameters of the corresponding channel issued by the sequence controller 110 and then send them to the output enable data module 210; the comparison enable parameter delay module 190 is used to delay the comparison enable parameters of the corresponding channel issued by the sequence controller 110 and then send them to the comparison enable data module 220; the output enable data module 210 enables or disables the output according to the received output enable parameters; the comparison enable data module 220 compares or does not compare according to the received comparison enable parameters; the multiplexer MUX is used to select and output each enabled or disabled output, each comparison output or non-comparison output, and each physically mapped address and data output by the signal mapping module 170 to the timing module 250. Specifically, the output enable data module 210 enables or disables the output based on the received output enable parameters (including enable and disable). Enabling output pulls the pin state of the device under test (DUT) high or low, while disabling output sets the pin state of the DUT to a high-impedance state. The comparison enable data module 220 performs comparison output and does not compare output based on the received comparison enable parameters (including comparison and non-comparison). This output indicates whether the current pattern and the waveform fed back by the DUT are compared; for example, 1 indicates comparison, and 0 indicates no comparison.

[0061] The output enable parameter delay module 180 and the comparison enable parameter delay module 190 delay the DRE parameters and CPE parameters of the corresponding path sent by the sequence controller 110, respectively. The first test pattern generation module ALPG1 frames and packages the physically mapped address and data output by the signal mapping module 170, the DRE parameters output by the output enable parameter delay module 180, and the CPE parameters output by the comparison enable parameter delay module 190 at the same time, and transmits them to the second test pattern generation module ALPG2. Based on the time interval of the control signals sent by the sequence controller 110 to each module and the time required for the signal mapping module 170 to perform physical mapping, the time when the signal mapping module 170 outputs the physically mapped address and data can be determined. Based on this, the output enable parameter delay module 180 and the comparison enable parameter delay module 190 are configured to perform a pause (output stop) upon receiving the DRE / CPE parameters, until the signal mapping module 170 completes the physical mapping before outputting the DRE / CPE parameters. This ensures that the physically mapped address and data, the delayed DRE parameters, and the delayed CPE parameters of the corresponding path are synchronously transmitted to the second test pattern generation module ALPG2. The multiplexer MUX selects whether the corresponding path's output is enabled or disabled, compared or not compared, and the physically mapped address and data, outputting the calculated graphic data to the timing module 250.

[0062] Furthermore, the first test pattern generation module ALPG1 also includes a specified data parameter delay module 200, and the second test pattern generation module ALPG2 also includes a specified data module 230 and a graphic data storage module 240. The specified data parameter delay module 200 is connected to the sequence controller 110 and the specified data module 230, and the multiplexer MUX is connected to the specified data module 230 and the graphic data storage module 240. The specified data parameter delay module 200 is used to delay the specified data parameters of the corresponding channel issued by the sequence controller 110 and then send them to the specified data module 230. The specified data module 230 selects the specified data of the corresponding channel from the preset data according to the received specified data parameters and sends it to the multiplexer MUX. The multiplexer MUX outputs the enabled or disabled outputs, the comparison outputs or non-comparison outputs, the physical mapped addresses and data of each channel, the specified data of each channel, and the preset graphic data in each graphic data storage module 240 to the timing module 250.

[0063] Similarly, the specified data parameter delay module 200 can pause output after receiving the specified data parameters, so that the physical mapping address and data of the corresponding channel, the delayed DRE parameters, the delayed CPE parameters, and the delayed specified data parameters are synchronously sent to the second test pattern generation module ALPG2. The multiplexer MUX selects the enabled or disabled output, the comparison output or the non-comparison output, and the physical mapping address and data of the corresponding channel as the calculated graphic data output to the timing module 250, or selects the enabled or disabled output, the comparison output or the non-comparison output, and the specified data of the corresponding channel as the calculated graphic data output to the timing module 250, or outputs the preset graphic data in the graphic data storage module 240 of the corresponding channel to the timing module 250. The timing module 250 performs waveform conversion and outputs the waveform change edge after delay according to the received data to the PE chip 300, and samples and compares the signal returned by the PE chip 300 according to the comparison expectation value at the comparison time when the comparison is enabled, obtains the comparison result, and stores it.

[0064] It can be understood that the address generation module 120 performs multi-way (nWAY, n≥2) address selection operations. This can be done within the same address generation module 120, or by using n address generation modules 120 to perform each operation separately. Adjacent address generation modules 120 are connected to share intermediate data for logical operations. Similarly, the data generation module 130 performs multi-way (nWAY, n≥2) data selection operations. This can be done within the same data generation module 130, or by using n data generation modules 130 to perform each operation separately. Adjacent data generation modules 130 are connected to share intermediate data for logical operations. Correspondingly, the number of the first verification module 140 (specifically an even verification module), the second verification module 150 (specifically a CRC verification module), the output enable parameter delay module 180, the comparison enable parameter delay module 190, the specified data parameter delay module 200, the output enable data module 210, the comparison enable data module 220, the specified data module 230, and the graphics data storage module 240 can also be one or n.

[0065] In one embodiment, such as Figure 3As shown, there are n address generation modules 120 and n data generation modules 130. Each address generation module 120 and data generation module 130 performs one address selection operation and one data selection operation, respectively. The processed address output by each address generation module 120 is verified by an even parity check module, and the processed address information is output to the delay module 160. The processed data output by the n data generation modules 130 is verified by the same CRC check module, and the processed data information is output to the delay module 160. The delay module 160 delays the processed address information and processed data information of the n channels before sending them to the signal mapping module 170. The signal mapping module 170 selects and outputs a fixed-bit physically mapped address and data. A copy mechanism is added to the signal mapping module 170, that is, signal mapping module 2, signal mapping module 3, ..., signal mapping module n copy the output data of signal mapping module 1, so that the output of each signal mapping module is the same as the output of signal mapping module 1.

[0066] The number of output enable parameter delay module 180, comparison enable parameter delay module 190, specified data parameter delay module 200, output enable data module 210, comparison enable data module 220, specified data module 230, and graphics data storage module 240 are all n. After physical mapping, the address and data, DRE parameters, and CPE parameters of the same path are framed and packaged and transmitted to the second test pattern generation module ALPG2. The multiplexer MUX selects the same path's output enable data, comparison enable data, and physically mapped address and data, or selects the same path's enabled output or disabled output, comparison output or non-comparison output, and specified data, as the calculated graphics data output to the timing module 250, or selects a preset graphics data in the graphics data storage module 240 and outputs it to the timing module 250.

[0067] The timing module 250 performs waveform conversion and waveform edge delay on the data, address, DRE (drive enable), and CPE (compare enable) output by the test pattern generator ALPG and outputs them to the PE chip 300. The PE chip 300 converts the level of the signal output by the timing module 250 to the level required by the pin of the device under test (DUT) and then outputs it to the DUT. The PE chip 300 also performs a logic high comparison to obtain the CA signal and a logic low comparison to obtain the CB signal from the feedback signal of the DUT, and transmits the CA and CB signals to the timing module 250. The timing module 250 also samples the CA and CB signals returned by the PE chip 300 according to the set time, compares the sampled values ​​with the expected CPE value (determined based on the comparison enable data), and stores the comparison result in the storage module (not shown in the figure).

[0068] For ease of understanding, the following explanations will use the same address generation module 120 and the same data generation module 130 as examples of multi-channel operations. Each channel of the address generation module 120 outputs two sets of processed addresses (X address data and Y address data), and each channel of the data generation module 130 outputs two sets of processed data (leading edge data and trailing edge data).

[0069] The specific methods by which the address generation module 120 and the data generation module 130 perform calculations are not unique. In one embodiment, the address generation module 120 receives N address data from the sequence controller 110. Each (WAY) address data includes X sets of address data, Y sets of address data, and Z sets of register data. Each address data is combined with an immediate value to perform logical operations to obtain N first intermediate data. The address generation module 120 also combines the N first intermediate data and the second register data from the sequence controller 110 as data sources to perform M logical operations. Each output has two sets of addresses after the operation. When N equals 1, M is greater than N; when N is greater than 1, M is greater than or equal to N.

[0070] In this system, M is the same as the number of address paths (nWAY) required after the operation, and N can be set according to actual needs; that is, N can be less than or equal to M. The address generation module 120 receives data signals and control signals from the sequence controller 110. The data signals include address data, register data, immediate values, and specified address data. The address data, register data, immediate values, and specified address data for each path (WAY) can be the same or different. The address data includes X groups of address data, Y groups of address data, and Z groups of register data. The register data is divided into first register data, second register data, third register data, or more types of register data, which are used for corresponding logical operations.

[0071] In this embodiment, when N equals 1, the address generation module 120 performs logical operations on the X groups of address data, Y groups of address data, and Z groups of register data issued by the sequence controller 110, respectively, in conjunction with immediate values, to obtain the corresponding first intermediate data. The address generation module 120 also performs multi-path logical operations on each of the first intermediate data, in conjunction with the register data issued by the sequence controller, outputting two sets of processed addresses from each path. Specifically, the address generation module 120 performs logical operations on the address data, in conjunction with immediate values, to obtain first intermediate data RXA-RXH, first intermediate data RYA-RYH, and first intermediate data RZA-RZE. The address generation module 120 combines the first intermediate data and the second register data issued by the sequence controller 110 as data sources to perform M-path logical operations, with each path outputting two sets of processed addresses X1 and Y1. The use of X groups of address data, Y groups of address data, Z groups of register data, and immediate values ​​in the logical operations increases the diversity of the first intermediate data. Simultaneously, the multi-path logical operations on all the first intermediate data increase the diversity of the output addresses X1 and Y1.

[0072] In other embodiments, when N is greater than 1, the address generation module 120 performs logical operations on the X groups of address data, Y groups of address data, and Z groups of register data for each channel issued by the sequence controller 110, combining them with immediate values ​​to obtain the first intermediate data for multiple channels. The address generation module 120 also combines the first intermediate data for each channel with the register data issued by the sequence controller 110 as data sources to perform logical operations on the corresponding channel, outputting two sets of processed addresses for each channel. Specifically, each pair of channels may share a single logic for generating the first intermediate data. Figure 5 The purple dashed boxes in the diagram represent the data output by each path. For example, 1WAY and 2WAY share the same purple dashed box (first intermediate data RXA-RXH, first intermediate data RYA-RYH, and first intermediate data RZA-RZE). 3WAY and 4WAY share another purple dashed box, and so on. nWAY corresponds to n / 2 purple dashed boxes. The logic within the yellow dashed boxes for each path is consistent with the above and will not be repeated. It can be understood that generating the first intermediate data (…) Figure 5 The number of paths (the purple dashed boxes in the diagram) is not unique. For example, nWAY can also correspond to n purple dashed boxes, with each path having a purple dashed box that generates the first intermediate data, which is then sent into the yellow dashed box for logical operations.

[0073] In one embodiment, the address generation module 120 receives N channels of first register data from the sequence controller 110. Each channel of first register data includes X groups of maximum address limits, Y groups of maximum address limits, and third register data R0-15. This data is used to perform logical operations with the X groups of address data, Y groups of address data, and immediate values ​​within the corresponding address data to generate the first intermediate data for that channel. Logical operations include AND, OR, addition, subtraction, multiplication, division, XOR, and flipping operations, as well as selection operations. Taking the logical operation of X groups of address data, immediate values, X groups of maximum address limits XTH, and third register data R0-15 as an example, the logical operation generates the first intermediate number for the X groups of addresses. This intermediate number can be any one of the X groups of address data, immediate values, or third register data R0-15, or it can be the result of operating on the selected first register data and the X groups of address data. Similarly, the logical operation principle for the Y groups of maximum address limits YTH, third register data R0-15, Y groups of address data, and immediate values ​​is the same and will not be elaborated here. The third register data R0-15 are combined with the X group address data, Y group address data, and immediate values ​​to perform logical operations, increasing the diversity of the first intermediate data.

[0074] In one embodiment, the first intermediate data includes the output of the first intermediate number of the X group address and the first intermediate number of the Y group address. Each first register number is combined with the X group address data, Y group address data, and immediate value within the corresponding address data for logical operations, including:

[0075] The data selected from the third register is logically operated on with the address data from group X / group Y. The output of the logically operated data is compared with the maximum limit of address data from group X / group Y. If the logically operated data is greater than the maximum limit of address data from group X / group Y, the logically operated data is subtracted from the maximum limit of address data from group X / group Y, and the remainder is used as the first intermediate number of address data from group X / group Y. The carry data is then output to participate in the logical operation of address data from group Y / group Z register data. If the logically operated data is less than the maximum limit of address data from group X / group Y, the logically operated data is output as the first intermediate number of address data from group X / group Y.

[0076] Specifically, logical operations include AND, OR, addition, subtraction, multiplication, division, XOR, and flipping operations, as well as selection operations. The data selected from the third register is logically operated on with the data from the X group address / Y group address data. The output of the logically operated data includes the data from the third register, selective output of either the X group address data / Y group address data, and operations involving the selected data from the third register and the X group address data / Y group address data. When the logically operated data exceeds the maximum limit of the X group address / Y group address, carry / borrow data is added to participate in the logical operation of the Y group address data / Z group register data, increasing the diversity of logical operations on the Y group address data / Z group register data, and increasing the diversity of output of the first intermediate number of the Y group address and the first intermediate number of the Z group address.

[0077] In one embodiment, the address generation module 120 combines the second register data, N sets of first intermediate data, and the second intermediate data of every two logical operations as data sources to perform logical operations on each path, outputting two sets of addresses after each operation. Specifically, the address generation module 120 can sequentially use the second intermediate data of two logical operations as data sources for each path's logical operations; for example, the second intermediate data of the first way and the second way are both used as data sources for the first way and the second way, the second intermediate data of the third way and the fourth way are both used as data sources for the third way and the fourth way, and so on. Alternatively, the address generation module 120 can use the second intermediate data of every two adjacent logical operations as data sources for each path's logical operations; for example, the second intermediate data of the first way and the second way are both used as data sources for the first way and the second way, the second intermediate data of the second way and the third way are both used as data sources for the second way and the third way, the second intermediate data of the third way and the fourth way are both used as data sources for the third way and the fourth way, and so on.

[0078] In this embodiment, when the total number of logic operations M is even, the address generation module 120 sequentially combines the second intermediate data of every two logic operations, the second register data, and N sets of first intermediate data as data sources for each logic operation. When the total number of logic operations M is odd, the address generation module 120 sequentially combines the second intermediate data of every two logic operations, the register data, and the first intermediate data as data sources for M-1 logic operations, and then combines the second register data and N sets of first intermediate data as data sources for the Mth logic operation. In other embodiments, when the total number of logic operations M is odd, the address generation module 120 may also use the intermediate data of the (M-1)th logic operation as the data source for the Mth logic operation.

[0079] For example, when N equals 1, the address generation module receives one channel of address data. The X group of address data, Y group of address data, and Z group of register data in this one channel are combined with immediate values ​​for logical operations to obtain one channel of first intermediate data, namely, first intermediate data RXA-RXH, first intermediate data RYA-RYH, and first intermediate data RZA-RZE. In any one-way logical operation, the address generation module 120 uses the first intermediate data RXA-RXH, first intermediate data RYA-RYH, and first intermediate data RZA-RZE as the data source for each operation. Two logical operations are performed to obtain the second intermediate data XS1 and the second intermediate data YS1. Combining the second intermediate data XS1, the second intermediate data YS1, the first intermediate data RZA-RZE, and the second intermediate data XS2 and YS2 from another logical operation (adjacent to 1WAY), two logical operations are performed respectively to obtain the third intermediate data XT and the third intermediate data YT. Combining the third intermediate data XT, the third intermediate data YT, and the corresponding second register data, two logical operations are performed respectively to output the processed addresses X1 and Y1. The first intermediate data RXA-RXH are intermediate data obtained by logical operations combining immediate values ​​and X sets of address data, and the first intermediate data RYA-RYH are intermediate data obtained by logical operations combining immediate values ​​and Y sets of address data.

[0080] Furthermore, the address generation module 120 also combines the second intermediate data XS1, the second intermediate data YS1, the first intermediate data RZA-RZE, the second intermediate data XS2 and the second intermediate data YS2 of another logical operation, and the configured specified address data as data sources to perform two logical operations respectively to obtain the third intermediate data XT and the third intermediate data YT.

[0081] In one embodiment, the 1WAY logic block diagram of the address generation module 120 is as follows: Figure 4As shown. Group X address data includes XA-XH, group Y address data includes YA-YH, group Z register data includes ZA-ZE, R0-15 is the third register data issued by the sequence controller 110, XTH and YTH are the maximum limits of group X and group Y addresses issued by the sequence controller 110, XT0-15, XOS, YOS, and YT0-15 are the second register data issued by the sequence controller 110, CB0-1 is the carry / borrow flag, ACT is the specified address data, and ALU represents the arithmetic logic unit, performing AND, OR, addition, subtraction, multiplication, division, XOR, and flip operations, as well as selection operations. RXA-RXH, RYA-RYH, and RZA-RZE are the first intermediate data generated during data logic operations; the second intermediate data XS1 and YS1, and the third intermediate data XT and YT are the intermediate data generated by further logic operations. X1 and Y1 correspond to the addresses generated by the 1WAY address after the operations.

[0082] Specifically, continue to refer to Figure 4 During logical operations on the address data within the purple dashed box (X group), the address data XA-XH of group X are used as the left-hand data. This can be an assignment value or the return value of the previous pattern operation. The data in the third register, R0-15, are used as the right-hand data and participate in the ALU operation along with the left-hand data. The ALU can either select data from the left and right-hand data for logical operations and then output it, or it can directly pass through data selected from the left, right, and immediate values. When selecting data from the left and right-hand data for logical operations, XTH is the maximum limit of the address group X. The data after the ALU logical operation (the data after the logical operation) is compared with the maximum limit of the address group XTH. If the data after the logical operation is less than the maximum limit of the address group XTH, it is output directly. If the data after the logical operation is greater than the maximum limit of the address group XTH, the ALU subtracts the data after the logical operation from the maximum limit of the address group XTH and outputs the remainder as the first intermediate number of the address group X. The carry data CB0-1 is then carried over to the ALU of the address data group Y for logical operations.

[0083] When performing logical operations on the address data in the Y group within the purple dashed box, the ALU can either select data from the third register data R0-15 and the Y group address data YA-YH for logical operations and then output the result, or it can select data from the third register data R0-15, the Y group address data YA-YH, and the immediate value and transmit it directly. When performing logical operations on data selected from the third register data R0-15 and the third register data YA-YH, YTH is the maximum limit of the Y group address. The ALU selects data from the third register data R0-15 and the third register data YA-YH for logical operations. The ALU compares the logically operated data with the maximum limit of the Y group address YTH. If the logically operated data is less than the maximum limit of the Y group address YTH, the logically operated data is directly output. If the logically operated data is greater than the maximum limit of the Y group address YTH, the ALU subtracts the logically operated data from the maximum limit of the Y group address YTH and outputs the remainder as the first intermediate number of the Y group address. The carry data CB0-1 is carried over to the Z group register data. The ALU participating in the logical operation participates in the operation.

[0084] Similarly, when performing logical operations on the data in register group Z within the purple dashed box, the ALU can either select data for logical operations or pass it directly through. When selecting data for logical operations, the ALU will also combine the selected data with the carry data output after logical operations on the address data in group Y, and output the first intermediate data RZA-RZE, which will not be elaborated further here.

[0085] Figure 4 Within the yellow dashed box, XT0-15 / YT0-15 are directly specified data that can be directly output, and XOS / YOS are address shifts. The corresponding ALU can select specified data from XT0-15 / YT0-15 as the output address X1 / Y1 after the operation, or it can perform an operation between the third intermediate data XT / YT and XOS / YOS, and then shift the address of the third intermediate data XT / YT accordingly to obtain the output address X1 / Y1 after the operation.

[0086] When N equals 1, the difference between the addresses generated by 2WAY and 1WAY is that 2WAY is generated by copying the logic block diagram of 1WAY. Figure 4The logic within the yellow dashed box shares immediate values, X-group address data (XA-XH), Y-group address data (YA-YH), Z-group register data (ZA-ZE), R0-15, XTH, YTH, XT0-15, XOS, YOS, YT0-15, ACT, and other register data, as well as the logic within the purple dashed box. Simultaneously, 2WAY shares the four sets of second intermediate data (XS1, YS1, XS2, YS2), and incorporates the second intermediate data generated by another path into one logic operation, increasing the diversity of obtaining the third intermediate data (XT and YT), thereby enriching the data sources for the leading and trailing edge address data. In this embodiment, the leading edge address data is X1, and the trailing edge address data is Y1. Figure 5 As shown. 3-way address generation involves the first two logical operations generating X1, X2, Y1, and Y2 address signals (i.e., the processed addresses) according to the logic of 2-way. The third path generates X3 and Y3 address signals according to the logic of 1-way, or by sharing the intermediate data between the third and second paths, and so on. 4-way address generation replicates the address generation logic of 2-way. That is, the first two paths generate X1, X2, Y1, and Y2 address signals according to the 2-way address generation method, and the last two paths generate X3, X4, Y3, and Y4 address signals according to the 2-way address generation method; and so on, thus achieving n-way address generation.

[0087] like Figure 5As shown, taking the generation of a 2-way address as an example, each 1-way within the yellow dashed box uses the first intermediate data RXA-RXH, the first intermediate data RYA-RYH, and the first intermediate data RZA-RZE as data sources to perform two logical operations. This can be done by selecting the first intermediate data RXA-RXH / RYA-RYH / RZA-RZE as input for logical operations, or by combining at least two of the first intermediate data RXA-RXH, RYA-RYH, and RZA-RZE to select partial data (e.g., partial data from RXA-RXH and RYA-RYH) as input for logical operations, thereby generating address signals XS1, XS2, YS1, and YS2 (second intermediate data). In each wave, address signals XS1, XS2, YS1, and YS2 are shared. These signals, combined with the first intermediate data RZA-RZE and the configured specified address data ACT, serve as the data source for the next two logical operations. The outputs of these two logical operations are the third intermediate data XT and YT, respectively. In the final two logical operations, the third intermediate data XT, register data XT0-15, and XOS are used as the data source for one logical operation to obtain the processed address X1 (X2). The third intermediate data YT, register data YT0-15, and YOS are used as the data source for one logical operation to obtain the processed address Y1 (Y2).

[0088] Of course, for M WAY, the address generation module 120 receives N address data sent by the sequence controller 110. When N is greater than 1, it copies the logic block diagram of 1 WAY ( Figure 4 The logic within the purple dashed box in the diagram () consists of N different address data, immediate values, and first register values ​​within the purple dashed boxes. The address data includes X groups of address data, Y groups of address data, and Z groups of register data, resulting in N channels of first intermediate data. Copy the 1WAY logic block diagram ( Figure 4 The logic within the yellow dashed box () replicates M and N paths of first intermediate data as data sources for the M-path logic operations, with each path outputting two sets of addresses after computation. The N paths of first intermediate data participate in each path's logic operation, increasing the diversity of input sources.

[0089] In one embodiment, the data generation module 130 performs logical operations on the 2M sets of fourth register data sent by the sequence controller 110, combining them with immediate values, to obtain 2M sets of fourth intermediate data. The data generation module 130 also performs M-channel logical operations using the 2M sets of fourth intermediate data and the fifth register data sent by the sequence controller 110 as data sources, outputting two sets of processed data from each channel. Specifically, the data generation module 130 receives control signals and data signals from the sequence controller 110, including fourth register data, fifth register data, and immediate values. The data generation module 130 generates the fourth intermediate data by performing logical operations on the fourth register data, fifth register data, and immediate values ​​according to the control signals. Simultaneously, the data generation module 130 also performs logical flips on specified positions (specified bits / regions / buses) of the intermediate data according to the control signals sent by the sequence controller 110, outputting LDATA1 and TDATA1 data signals, i.e., the processed data. Specifically, the specified bit specifies which bits are flipped, the specified address region specifies which address domain is flipped, and the specified bus specifies the entire bus is flipped. When the specified address region is flipped, the data generation module 130 is also connected to the address generation module 120. Combined with the processed address output by the address generation module 120, the corresponding address region of the intermediate data is flipped.

[0090] In this process, every two sets of fourth register data are combined with immediate values ​​for logical operations to generate two sets of fourth intermediate data, forming one path of fourth intermediate data. The data generation module 130 also combines the fourth intermediate data from each pair of paths with the corresponding fifth register data as data sources to perform M-path logical operations, outputting two sets of processed data for each path. M-path logical operations can be performed by combining any two sets of fourth intermediate data from any pair of paths with the corresponding fifth register data, thus expanding data diversity. For example, the data generation module 130 may sequentially use the fourth intermediate data of two logical operations as the data source for each logical operation. For instance, the fourth intermediate data of the first and second channels may both be used as the data source for the first and second channels, and the fourth intermediate data of the third and fourth channels may both be used as the data source for the third and fourth channels, and so on. Alternatively, the data generation module 130 may use the fourth intermediate data of every two adjacent logical operations as the data source for each logical operation. For instance, the fourth intermediate data of the first and second channels may both be used as the data source for the first and second channels, and the fourth intermediate data of the second and third channels may both be used as the data source for the second and third channels, and the fourth intermediate data of the third and fourth channels may both be used as the data source for the third and fourth channels, and so on. In addition, the data generation module 130 can also select the fourth intermediate data of two non-adjacent logic operations as the data source for each logic operation. For example, the fourth intermediate data of the first WAY and the third WAY can both be used as the data source of the first WAY and the third WAY, the fourth intermediate data of the second WAY and the fourth WAY can both be used as the data source of the second WAY and the fourth WAY, and so on.

[0091] In this embodiment, when the total number of logic operations M is even, the data generation module 130 sequentially combines the fourth intermediate data of every two logic operations with the corresponding fifth register data as the data source for each logic operation. When the total number of logic operations M is odd, the data generation module 130 sequentially combines the fourth intermediate data of every two logic operations with the corresponding fifth register data as the data source for M-1 logic operations, and then combines the fourth intermediate data of the Mth logic operation with the corresponding fifth register data as the data source for the Mth logic operation. In other embodiments, when the total number of logic operations is odd, the data generation module 130 can also use the fourth intermediate data of the (M-1)th logic operation as the data source for the Mth logic operation. In this case, the fourth intermediate data for each logic operation is obtained by performing logical operations on two sets of fourth register data combined with immediate values.

[0092] Specifically, the fifth register data includes toggled data and DBI comparison data. Based on the fourth intermediate data, the first leading edge intermediate data and the first trailing edge intermediate data are selected. After the first leading edge intermediate data and the first trailing edge intermediate data are logically operated with the toggled data, the operation results are respectively compared with the DBI comparison data to perform data bus toggled operation, and the operation results are output as the operation results of the leading edge data LDATA1 and the trailing edge data TDATA1.

[0093] The 1-way logic block diagram of data generation module 130 is as follows: Figure 6 As shown. Data DAR0-3, DAH0-3, and DPA_INI are the fourth register data issued by the sequence controller 110. DPA and DPB are the fourth intermediate data generated in the data logic operation. SWAP indicates replacement. DINV is the toggle data issued by the sequence controller 110. BUS_INV indicates bus toggle. DBI_CP is the DBI comparison data issued by the sequence controller 110, used to implement the data bus inversion mechanism.

[0094] Specifically, the DPA within the blue dashed box can be an assigned value or the DPA value calculated from the previous pattern operation. The ALU can either select a subset of data from DPA, DAR0-3, DAH0-3, DPA_INI, and immediate values, perform logical operations, and then output the fourth intermediate data DPA and DPB, or it can directly pass the selected data through to output the fourth intermediate data DPA and DPB. For example, the ALU can select data from DPA and DAR0-3, perform logical operations, and then output, or it can select from DAH0-3, DPA_INI, and immediate values. The corresponding values ​​of the fourth intermediate data DPA and DPB differ for 1-way operations, and the corresponding values ​​of the fourth intermediate data DPC and DPD also differ for 2-way operations, which can increase data diversity. The fourth intermediate data DPA, DPB, DPC, and DPD are passed into the yellow dashed box and used as the data source for the two ALUs in the first stage. 0 is a direct zeroing operation. The two ALUs in the first stage can directly zero out or select data from the intermediate data DPA, DPB, DPC, and DPD to output to the two ALUs in the second stage. The two ALUs in the second stage perform logical operations with the toggling data DINV and output the operation result to perform bus toggling in the next stage.

[0095] BUS_INV receives the calculation result and determines whether the DBI condition is met. If it is, the address data is toggled. Specifically, DBI-CP represents the toggle condition. BUS_INV enables or disables the toggle operation based on the received control signal (toggle enable signal). When the toggle operation is enabled, the DBI comparison data is compared with the received calculation result. If the number of addresses with 1 in the received calculation result is greater than the data bit width / 2, the entire received calculation result is toggled, and the leading edge data LDATA1 and the trailing edge data TDATA1 are output.

[0096] The difference between 2-way and 1-way data generation: 2-way replicates the logic of 1-way. Each logic operation includes two sets of fourth register data and immediate values. Each set of fourth register data contains DAR0-3, DAH0-3, and DPA_INI register data, and each set of fourth register data and the immediate values ​​involved in the logic operation are different. Therefore, each path of fourth intermediate data is different. 2-way will generate two paths of fourth intermediate data: DPA, DPB, DPC, and DPD. 2-way shares these four sets of fourth intermediate data (DPA, DPB, DPC, and DPD), enriching the data sources for both leading and trailing edges. Figure 7 As shown. 3-way data generation involves the first two channels generating LDATA1, TDATA1, LDATA2, and TDATA2 data signals (i.e., processed data) according to the 2-way logic. The third channel generates LDATA1 and TDATA3 data signals according to the 1-way logic, or shares the intermediate data from the third and second channels to generate LDATA1 and TDATA3 data signals, and so on. 4-way data generation replicates the 2-way data generation logic; that is, the first two channels generate LDATA1, TDATA1, LDATA2, and TDATA2 data signals according to the 2-way data generation method, and the last two channels generate LDATA3, TDATA3, LDATA4, and TDATA4 data signals according to the 2-way data generation method; and so on, thus achieving n-way data generation.

[0097] like Figure 7As shown, taking 2-way data generation as an example, each channel combines immediate values, DAR0-3, DAH0-3, and DPA_INI register data for logical processing to generate fourth intermediate data DPA and DPB (intermediate data DPC and DPD). Within the yellow dashed box, the two channels share the fourth intermediate data DPA, DPB, DPC, and DPD for two logic operations at the first level. The results are output by directly setting the data to zero or selecting data for logical operations. The results of the two operations are then fed into two logic operations at the second level, combined with the toggled data DINV for the second-level logic operations. The results of the two second-level logic operations are then combined with the DBI comparison data DBI_CP for bus toggling, resulting in the processed data LDATA1 and TDATA1 (LDATA2 and TDATA2).

[0098] The test pattern generation device provided in this application realizes n-way waveform generation based on the ALPG split architecture. Compared with 1-way waveform generation, it increases the amount of waveform data generated while keeping the hardware architecture unchanged, thereby improving the test speed and efficiency.

[0099] In one embodiment, a resource board is also provided, including a timing module, a PE chip, and the aforementioned test pattern generation device. The timing module performs waveform conversion and outputs the waveform change edge to the PE chip after delaying the received data. Furthermore, it samples and compares the signal returned by the PE chip at the comparison time according to the expected comparison value, obtains the comparison result, and stores it in the storage module.

[0100] In one embodiment, a test machine is also provided, including the resource board described above.

[0101] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A test pattern generation device, characterized in that, include: The sequence controller connects the address generation module, the data generation module, and the signal mapping module, and is used to send out the corresponding data signals and control signals respectively. The address generation module is connected to the delay module and is used to perform multi-address selection operation on the received data signal according to the received control signal, and output the multi-address after multi-address selection to the delay module. The data generation module is connected to the delay module and is used to perform multi-channel data selection operation on the received data signal according to the received control signal, and output the multi-channel processed data to the delay module. The delay module is connected to the signal mapping module and is used to delay the multi-processed address and multi-processed data before sending them to the signal mapping module. The signal mapping module is used to select multiple specified physical mapped addresses and data from the multi-processed addresses and multi-processed data according to the received control signals and output them. The address generation module, the data generation module, and the delay module all simultaneously receive the output data from the previous module and the control signal issued by the sequence controller, and process the output data of the previous module accordingly based on the received control signal.

2. The test pattern generating device according to claim 1, characterized in that, The address generation module receives N address data from the sequence controller. Each address data includes X sets of address data, Y sets of address data, and Z sets of register data. Each address data is combined with an immediate value for logical operation to obtain N sets of first intermediate data. The address generation module also combines the N sets of first intermediate data and the second register data from the sequence controller as data sources for M sets of logical operations. Each set outputs two sets of addresses after the operation, where when N equals 1, M is greater than N; when N is greater than 1, M is greater than or equal to N.

3. The test pattern generating device according to claim 2, characterized in that, The address generation module receives N channels of first register data from the sequence controller. Each channel of first register data includes X groups of maximum address limits, Y groups of maximum address limits, and third register data. These data are used to perform logical operations by combining the X groups of address data, the Y groups of address data, and the immediate values ​​within the corresponding channel's address data to generate the first intermediate data for that channel.

4. The test pattern generating device according to claim 3, characterized in that, The first register number for each path is combined with the X group of address data, the Y group of address data, and the immediate value within the corresponding path's address data to perform logical operations, including: The data selected from the third register is logically operated on with the X group address data / the Y group address data, and the output data after the logical operation is compared with the maximum limit of the X group address / the maximum limit of the Y group address; If the data after the logical operation is greater than the maximum limit of the X group address / the maximum limit of the Y group address, the data after the logical operation is subtracted from the maximum limit of the X group address / the maximum limit of the Y group address, and the remainder is used as the first intermediate number of the X group address / the first intermediate number of the Y group address, and the carry data is output to participate in the logical operation of the Y group address data / Z group register data; If the data after the logical operation is less than the maximum limit of the X group address / the maximum limit of the Y group address, the data after the logical operation is output as the first intermediate number of the X group address / the first intermediate number of the Y group address.

5. The test pattern generating apparatus according to any one of claims 2 to 4, characterized in that, The address generation module combines the second register data, the N sets of first intermediate data, and the second intermediate data of each pair of logical operations as data sources to perform logical operations on each path, and outputs two sets of addresses after the operations on each path.

6. The test pattern generating apparatus according to claim 5, characterized in that, When the total number of logic operations M is even, the address generation module sequentially combines the second intermediate data of every two logic operations, the second register data, and the N sets of first intermediate data as data sources to perform logic operations on each path; when the total number of logic operations M is odd, the address generation module sequentially combines the second intermediate data of every two logic operations, the second register data, and the N sets of first intermediate data as data sources to perform logic operations on path M-1, and combines the second register data and the N sets of first intermediate data as data sources to perform logic operations on path M.

7. The test pattern generating apparatus according to any one of claims 2 to 4, characterized in that, When N equals 1, the address generation module performs two logical operations in one logical operation, using the first intermediate data RXA-RXH, the first intermediate data RYA-RYH, and the first intermediate data RZA-RZE as data sources, to obtain the second intermediate data XS1 and the second intermediate data YS1. Combining the second intermediate data XS1, the second intermediate data YS1, the first intermediate data RZA-RZE, and the second intermediate data XS2 and the second intermediate data YS2 of another logical operation as data sources, it performs two logical operations to obtain the third intermediate data XT and the third intermediate data YT. Combining the third intermediate data XT, the third intermediate data YT, and the corresponding second register data, it performs two logical operations to output the post-operation address X1 and the post-operation address Y1. The first intermediate data RXA-RXH is intermediate data obtained by performing logical operations on the immediate value and the X group of address data, and the first intermediate data RYA-RYH is intermediate data obtained by performing logical operations on the immediate value and the Y group of address data.

8. The test pattern generating apparatus according to claim 7, characterized in that, The address generation module combines the second intermediate data XS1, the second intermediate data YS1, the first intermediate data RZA-RZE, the second intermediate data XS2 and the second intermediate data YS2 of another logical operation, and the configured specified address data as data sources to perform two logical operations to obtain the third intermediate data XT and the third intermediate data YT.

9. The test pattern generating apparatus according to claim 1, characterized in that, The data generation module performs logical operations on the 2M sets of fourth register data sent by the sequence controller in combination with immediate values ​​to obtain 2M sets of fourth intermediate data. The data generation module also performs M-way logical operations on the 2M sets of fourth intermediate data and the fifth register data sent by the sequence controller as data sources, and outputs two sets of processed data on each way.

10. The test pattern generating apparatus according to claim 9, characterized in that, Each pair of fourth register data is combined with immediate values ​​to perform logical operations, generating two pairs of fourth intermediate data to form one channel of fourth intermediate data; the data generation module also combines the fourth intermediate data of each pair of channels and the corresponding fifth register data as data sources to perform M-channel logical operations, outputting two sets of processed data for each channel.

11. The test pattern generating apparatus according to claim 10, characterized in that, When the total number of logic operations M is even, the data generation module sequentially combines the fourth intermediate data of every two logic operations with the corresponding fifth register data as the data source to perform logic operations on each path; when the total number of logic operations M is odd, the data generation module sequentially combines the fourth intermediate data of every two logic operations with the corresponding fifth register data as the data source to perform logic operations on M-1 paths, and then combines the fourth intermediate data of the Mth path with the corresponding fifth register data as the data source to perform logic operations on the Mth path.

12. The test pattern generating apparatus according to claim 9, characterized in that, The fifth register data includes toggled data and DBI comparison data. Based on the fourth intermediate data, the first leading edge intermediate data and the first trailing edge intermediate data are selected. The first leading edge intermediate data and the first trailing edge intermediate data are logically operated with the toggled data respectively. The operation results are then subjected to data bus toggled operation with the DBI comparison data respectively, and the operation results are output as the operation results of the leading edge data LDATA1 and the operation results of the trailing edge data TDATA1.

13. The test pattern generating apparatus according to claim 12, characterized in that, The data generation module compares the DBI comparison data with the received calculation result. If the number of addresses with 1 in the calculation result is greater than the data bit width / 2, the received calculation result is completely flipped, and the leading edge data LDATA1 and the trailing edge data TDATA1 after the calculation are output.

14. The test pattern generating apparatus according to claim 1, characterized in that, Also includes: The first verification module, connected to the address generation module and the delay module, is used to verify the received processed address according to the received control signal and output the multi-processed address information to the delay module. The second verification module is connected to the data generation module and the delay module. It is used to verify the received processed data according to the received control signal and output the multi-processed data information to the delay module. Both the first verification module and the second verification module simultaneously receive the output data from the previous module and the control signal issued by the sequence controller, and process the output data of the previous module accordingly based on the received control signal; The delay module delays the processed address information and processed data information before sending them to the signal mapping module. The signal mapping module selects and outputs multiple specified physically mapped addresses and data from the multi-processed address information and multi-processed data information based on the received control signals.

15. The test pattern generating apparatus according to claim 1, characterized in that, It includes a first test pattern generation module and a second test pattern generation module; The first test pattern generation module includes the sequence controller, the address generation module, the data generation module, the delay module, the signal mapping module, the comparison enable parameter delay module, and the output enable parameter delay module. The comparison enable parameter delay module and the output enable parameter delay module are both connected to the sequence controller. The second test pattern generation module includes an output enable data module, a comparison enable data module, and a multiplexer. The output enable data module is connected to the output enable parameter delay module, the comparison enable data module is connected to the comparison enable parameter delay module, and the multiplexer is connected to the signal mapping module, the output enable data module, the comparison enable data module, and the timing module. The timing module is connected to the device under test through a PE chip. The output enable parameter delay module is used to delay the output enable parameters of the corresponding path issued by the sequence controller before sending them to the output enable data module; the comparison enable parameter delay module is used to delay the comparison enable parameters of the corresponding path issued by the sequence controller before sending them to the comparison enable data module; the output enable data module enables or disables the output based on the received output enable parameters; the comparison enable data module performs a comparison or does not perform a comparison based on the received comparison enable parameters. The multiplexer is used to select and output each enabled or disabled output, each comparison output or non-comparison output, and each physically mapped address and data output by the signal mapping module to the timing module.

16. The test pattern generating apparatus according to claim 15, characterized in that, The first test pattern generation module further includes a specified data parameter delay module, and the second test pattern generation module further includes a specified data module and a graphic data storage module. The specified data parameter delay module is connected to the sequence controller and the specified data module, and the multiplexer is connected to the specified data module and the graphic data storage module. The specified data parameter delay module is used to delay the specified data parameters of the corresponding channel issued by the sequence controller before sending them to the specified data module; the specified data module selects the specified data of the corresponding channel from the preset data according to the received specified data parameters and sends it to the multiplexer; the multiplexer selects and outputs the enabled or disabled output of each channel, the comparison output of each channel, the physical mapped address and data of each channel, the specified data of each channel, and the preset graphics data in the graphics data storage modules of each channel to the timing module.

17. A resource board, characterized in that, The device includes a timing module, a PE chip, and a test pattern generation apparatus as described in any one of claims 1 to 16. The timing module performs waveform conversion and waveform change delay on the received data and outputs it to the PE chip. It also samples and compares the signal returned by the PE chip at the comparison time according to the comparison expectation value, obtains the comparison result, and stores it in the storage module.

18. A testing machine, characterized in that, Includes the resource board as described in claim 17.

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