Test method, device and system for nonvolatile memory and nonvolatile memory
By introducing test control logic units into the non-volatile memory and reusing some external communication ports for testing, the problems of low efficiency and high cost in testing SPI interface non-volatile memory are solved, and an efficient and low-cost testing solution is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-14
- Publication Date
- 2026-05-12
AI Technical Summary
When using the SPI interface, existing non-volatile memory has low testing efficiency and high cost, mainly because multiple signal ports need to be brought out for testing, resulting in low testing efficiency and high testing cost.
By adding a test control logic unit to the non-volatile memory and performing tests by reusing some external communication ports, the testing of the non-volatile memory array can be realized, reducing the usage frequency of the SPI control logic unit.
It improves testing efficiency, reduces testing costs, saves on external communication port connection costs, increases the number of parallel tests, and reduces wear and tear on test pin cards.
Smart Images
Figure CN122024804A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data storage technology, and for example to a test method, apparatus and system for non-volatile memory, and non-volatile memory. Background Technology
[0002] Non-volatile memory (NVRAM) is a type of memory chip that retains stored data even after power loss. It communicates with external devices through an interface, and different interfaces determine its communication speed, complexity, cost, and applicable scenarios. There are many types of NVRAM interfaces, each corresponding to different communication protocols and often requiring a different number of signal ports. Among them, the SPI interface is widely used due to its advantages such as lightweight design, high compatibility, high stability, easy expansion, and low cost. The SPI interface is a general-purpose serial input / output interface, physically typically including at least four ports: chip select signal CS#, input signal SI#, output signal SO#, and clock signal SCLK#. In scenarios requiring higher transmission rates, more signal ports are used; for example, a four-wire scenario typically includes IO0 (SI#), IO1 (SO#), IO2, and IO3, while even higher speed requirements may require IO4, IO5, IO6, and IO7.
[0003] Non-volatile memory (NVMemory) testing typically consists of two parts: testing the NNVMemory array itself and testing the control logic and input / output ports. The NNVMemory array testing primarily examines each individual memory cell. In this scenario, if the NNVMemory uses an SPI interface, all multiple signal ports of the interface need to be brought out individually for testing, leading to low testing efficiency and high testing costs.
[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0005] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.
[0006] This disclosure provides a testing method, apparatus, and system for non-volatile memory, and a non-volatile memory. By adding a test control logic unit to a non-volatile memory equipped with an SPI communication logic unit, testing of the non-volatile memory array can be performed using only a portion of the external communication ports, thereby improving testing efficiency and reducing testing costs.
[0007] In some embodiments, the non-volatile memory includes a non-volatile memory array, a logic selection unit, a test control logic unit, an SPI control logic unit, and an external communication port, wherein the external communication port controlled by the test control logic unit multiplexes a portion of the external communication ports controlled by the SPI control logic unit; the testing method for the non-volatile memory includes: The first control information is loaded from the non-volatile memory array using the logic selection unit, so as to turn on the test control logic unit and turn off the SPI control logic unit based on the first control information; Test control information is obtained from external test equipment through the multiplexed external communication port controlled by the test control logic unit, and the test control information is used to control the non-volatile memory to enter engineering mode. After the non-volatile memory enters engineering mode, it obtains a first test signal from an external test device via a multiplexed external communication port, sends the first test signal to the non-volatile memory array using the test control logic unit to obtain a first test result, and sends the first test result to the external test device via the multiplexed external communication port.
[0008] In some embodiments, the testing apparatus for non-volatile memory includes a processor and a memory storing program instructions, wherein the processor is configured to execute the above-described testing method for non-volatile memory when the program instructions are executed.
[0009] In some embodiments, the non-volatile memory includes a non-volatile memory array, a logic selection unit, a test control logic unit, an SPI control logic unit, and an external communication port, wherein the external communication port controlled by the test control logic unit multiplexes a portion of the external communication ports controlled by the SPI control logic unit; wherein: The non-volatile memory array stores the first control information; The logic selection unit is connected to the non-volatile memory array, the test control logic unit, and the SPI control logic unit, and is configured to load first control information from the non-volatile memory array to turn on the test control logic unit and turn off the SPI control logic unit based on the first control information. The test control logic unit, connected to the non-volatile memory array and the multiplexed external communication interface, is configured to obtain test control information from the external test equipment via the multiplexed external communication port, so as to control the non-volatile memory to enter the engineering mode using the test control information; after the non-volatile memory enters the engineering mode, it obtains a first test signal from the external test equipment via the multiplexed external communication port, sends the first test signal to the non-volatile memory array to obtain a first test result, and sends the first test result to the external test equipment via the multiplexed external communication port.
[0010] In some embodiments, a test system for non-volatile memory includes: At least one of the above-mentioned non-volatile memories; External testing equipment is connected to the non-volatile memory via a test pin card.
[0011] The testing method, apparatus, and system for non-volatile memory, as well as the non-volatile memory provided in this disclosure, can achieve the following technical effects: In this embodiment of the disclosure, when testing a non-volatile memory array, the test control logic unit is turned on and the SPI control logic unit is turned off. Since the external communication port controlled by the test control logic unit reuses a portion of the external communication port controlled by the SPI control logic unit, the test efficiency is improved and the connection cost of the external communication port is saved when obtaining the first test signal and sending the first test result from the external test device through the reused external communication port controlled by the test control logic unit.
[0012] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description
[0013] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of the structure of a conventional SPI interface non-volatile memory; Figure 2 This is a schematic diagram of the structure of a non-volatile memory provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of the communication control module structure of a non-volatile memory provided in an embodiment of this disclosure; Figure 4 This is a schematic flowchart of a testing method for non-volatile memory provided in an embodiment of this disclosure; Figure 5 This is a schematic flowchart of a testing method for non-volatile memory provided in an embodiment of this disclosure; Figure 6 This is a schematic flowchart of a testing method for non-volatile memory provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of the structure of a test system for non-volatile memory provided in an embodiment of this disclosure; Figure 8 This is a schematic diagram of the structure of a test system for non-volatile memory provided in an embodiment of this disclosure; Figure 9This is a schematic diagram of a test apparatus for non-volatile memory provided in an embodiment of this disclosure. Detailed Implementation
[0014] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.
[0015] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.
[0016] Unless otherwise stated, the term "multiple" means two or more.
[0017] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.
[0018] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.
[0019] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.
[0020] Currently, conventional SPI interface non-volatile memory such as Figure 1 As shown, if external communication typically involves at least four external communication ports—SPI input port (SI), SPI output port (SO), SPI chip select signal port (CS), and SPI clock signal port (SCLK)—then, when testing a non-volatile memory array, all the signal ports of the SPI interface need to be brought out one by one for testing. This limits the number of non-volatile memories that can be connected to the same test pin card, meaning that a smaller number of non-volatile memories can be tested simultaneously in the same test process, resulting in low testing efficiency. Furthermore, since test pin cards are consumables, over time, testing the same number of non-volatile memories will consume more test pin cards, increasing testing costs.
[0021] Combination Figure 2 and Figure 3 As shown, this disclosure provides a non-volatile memory, including a non-volatile memory array, a communication control module, and an external communication port module. The external communication port module includes multiple external communication ports, and the communication control module includes a logic selection unit, a test control logic unit, and an SPI control logic unit. Wherein: The non-volatile memory array stores first control information. In its initial state, this first control information is configured to control the test control logic unit to be turned on and the SPI control logic unit to be turned off. Thus, when the non-volatile memory enters the testing process after production, the logic selection unit can load the first control information from the non-volatile memory array upon power-up. Based on this first control information, the test control logic unit is turned on and the SPI control logic unit is turned off. Then, by utilizing the external communication port multiplexed through the test control logic unit, test control information is obtained from external test equipment, and the first test result is sent to the external test equipment. This initial configuration method meets the common testing process for non-volatile memory before shipment: after production, the test control logic unit is turned on first, and the non-volatile memory array is tested using fewer external communication ports, followed by SPI control logic testing and port testing.
[0022] The SPI control logic unit controls the connection of all external communication ports for communication with external devices based on the SPI interface protocol; the external communication ports controlled by the test control logic unit reuse a portion of the external communication ports controlled by the SPI control logic unit for communication with external devices based on the test interface protocol.
[0023] The logic selection unit is connected to the non-volatile memory array, the test control logic unit, and the SPI control logic unit, and is configured to load first control information from the non-volatile memory array to turn on the test control logic unit and turn off the SPI control logic unit based on the first control information.
[0024] The test control logic unit is connected to the non-volatile memory array and the multiplexed external communication interface. It is configured to obtain test control information from the external test equipment via the multiplexed external communication port, so as to control the non-volatile memory to enter the engineering mode using the test control information. After the non-volatile memory enters the engineering mode, the test control logic unit obtains a first test signal from the external test equipment via the multiplexed external communication port, sends the first test signal to the non-volatile memory array to obtain a first test result, and sends the first test result to the external test equipment via the multiplexed external communication port.
[0025] The non-volatile memory provided in this embodiment has a built-in logic control unit corresponding to two communication protocols. In the scenario of testing non-volatile memory arrays, it can control the connection of the test logic control unit and communicate with external test equipment through part of the external communication. This saves the connection cost of the external communication port. The external test equipment can use a single test pin card to connect and test more non-volatile memories at the same time, increasing the number of parallel tests, improving test efficiency, reducing the wear and tear of the test pin card, and reducing test costs.
[0026] In some practical applications, such as Figure 2 As shown, the external communication ports controlled by the SPI control logic unit include the SPI input port, SPI output port, SPI chip select signal port, and SPI clock signal port. The multiplexed external communication ports controlled by the test control logic unit include multiplexed data ports and multiplexed clock signal ports. The multiplexed data ports multiplex the SPI input ports, and the multiplexed clock signal ports multiplex the SPI clock signal ports.
[0027] The non-volatile memory disclosed in this embodiment reduces the waste of external communication ports and lowers production costs by reusing external communication ports. The following example illustrates this using the I2C interface protocol for the test control logic unit. The test control logic unit connects to two external communication ports: a test data port (SDA) and a test clock signal port (SCL). The SPI control logic unit connects to multiple external communication ports, including an SPI input port (SI), an SPI output port (SO), an SPI chip select signal port (CS), and an SPI clock signal port (SCLK). The test data port (SDA) reuses the SPI input port (SI), and the test clock signal port (SCL) reuses the SPI clock signal port (SCLK). On the one hand, the reused interfaces originally transmit the same type of information, so they do not affect normal information transmission, reducing the probability of errors in the non-volatile memory and lowering the implementation difficulty. On the other hand, port reuse reduces the waste of communication ports and lowers production costs.
[0028] It should be noted that other communication protocols supporting two-port communication can be used instead of the I2C communication protocol in this solution, such as UART or other custom communication protocols. This embodiment uses the I2C communication protocol only for illustrative purposes and does not impose any specific limitations. In addition, I2C and SPI are standard communication protocols and are basic knowledge in the industry, so they will not be elaborated upon.
[0029] Combination Figure 4 As shown, this disclosure provides a testing method for non-volatile memory, including: 401. Load first control information from the non-volatile memory array using the logic selection unit, so as to turn on the test control logic unit and turn off the SPI control logic unit based on the first control information.
[0030] 402. The test control information is obtained from the external test equipment through the multiplexed external communication port controlled by the test control logic unit, and the test control information is used to control the non-volatile memory to enter the engineering mode.
[0031] 403. After the non-volatile memory enters the engineering mode, it obtains the first test signal from the external test equipment through the multiplexed external communication port, sends the first test signal to the non-volatile memory array through the test control logic unit to obtain the first test result, and sends the first test result to the external test equipment through the multiplexed external communication port.
[0032] When testing a non-volatile memory array, the test control logic unit is turned on and the SPI control logic unit is turned off. Since the external communication port controlled by the test control logic unit reuses part of the external communication port controlled by the SPI control logic unit, the connection cost of the external communication port is saved when obtaining the first test signal and sending the first test result from the external test equipment through the reused external communication port controlled by the test control logic unit. The external test equipment can use a single test probe card to connect and test more non-volatile memories simultaneously, increasing the number of parallel tests, improving test efficiency, reducing the wear and tear of the test probe card, and lowering the test cost.
[0033] In some practical applications, sending a first test signal to a non-volatile memory array to obtain a first test result includes: obtaining a first test result read signal from an external test device via a multiplexed external communication port; and sending the first test result read signal to the non-volatile memory array to obtain the first test result from the non-volatile memory array after executing the first test signal.
[0034] In some practical applications, the first test signal includes an analog calibration command, which typically includes multiple analog input values. Correspondingly, the first test result includes the calibration result returned by the non-volatile memory array after completing the analog calibration, which typically includes multiple analog output values. Further, the external testing equipment calculates the calibration result based on the first test signal and the first test result, according to a preset fitting function. In the testing of the memory array, performing analog calibration first can effectively reduce the impact of material differences on the acquisition accuracy in subsequent tests, improve data processing efficiency, and reduce memory usage.
[0035] In some practical applications, sending a first test signal to a non-volatile memory array to obtain a first test result includes: obtaining a first test status read signal from an external test device via a multiplexed external communication port; sending the first test status read signal to the non-volatile memory array to obtain a first execution status of executing the first test signal from the non-volatile memory array; after sending the first execution status to the external test device, obtaining a first test result read signal from the external test device via a multiplexed external communication port; and sending the first test result read signal to the non-volatile memory array to obtain a first test result of executing the first test signal from the non-volatile memory array.
[0036] In some practical applications, the first test signal includes one or more of a write command and an erase command.
[0037] Taking a write command as an example, the first test signal includes a write address and write data. Correspondingly, the first test status read signal obtained from the external test device via the multiplexed external communication port is the read write status command. The read write status command is used to check whether the non-volatile memory array has completed the write command. The read write status command is sent to the non-volatile memory array to obtain the execution status of the write command. This execution status is the non-volatile memory array's execution status for the write command; for example, 0 represents that the write command is not completed, and 1 represents that the write command is completed. When the non-volatile memory completes the write command, the external device sends a first test result read signal, i.e., a read write result command, which includes a read address. Then, the write result of the write command is obtained from the non-volatile memory array. The write result may include the address and its corresponding data.
[0038] When the first test signal is an erase command, the execution process is similar to that of a write command, and will not be elaborated here. Through write and erase commands, the performance and stability of the non-volatile memory array under continuous data writing and erasing conditions can be evaluated. The following example uses the I2C interface protocol for the test control logic unit, combined with... Figure 5 As shown, the specific execution process is described below: 501. After the logic selection unit is powered on, it automatically reads the first control information of the initial state from the non-volatile memory array and controls the connection of the test control logic unit. At this time, the SPI logic control unit is turned off. The non-volatile memory under test 1 communicates with the outside world through the test data port (SDA) and the test clock signal port (SCL) using the I2C protocol.
[0039] 502. After the test control logic unit is turned on, it obtains test control information from the external test equipment and controls the non-volatile memory to enter the engineering mode based on the test control information.
[0040] 503, obtains analog calibration commands for the non-volatile memory array from external test equipment via the test data port (SDA).
[0041] 504. After the non-volatile memory array completes analog calibration, it returns the calibration result through the test data port (SDA).
[0042] 505, receive an erase command for the non-volatile memory array 12 from the external test device 3 via the test data port (SDA).
[0043] 506. After receiving an erase command from an external test device, the non-volatile memory 1 turns on its internal clock and performs an erase operation on the internal non-volatile memory array.
[0044] 507 receives read / erase status commands for the non-volatile memory array from an external test device via the test data port (SDA).
[0045] 508 returns the execution status of the non-volatile memory array for the erase command via the Test Data Port (SDA).
[0046] 509 receives read / erase commands for the non-volatile memory array from an external test device via the test data port (SDA).
[0047] 510, returns the erase results of the non-volatile memory array via the test data port (SDA).
[0048] The write test and erase test for the storage array are performed similarly, and will not be described in detail here.
[0049] In engineering mode, during testing, instructions and addresses can be sent and received through the test data port. After the instruction is received, the test data port is switched to output mode. Those skilled in the art should understand that, generally, the first test signal and its corresponding execution result include a clock signal, providing a timing reference for data transmission to ensure accuracy and reliability. In this case, only the test data port and the test clock signal port are needed to complete the testing of the non-volatile memory array, saving test resources and increasing the number of parallel tests. In certain special cases, such as asynchronous data transmission, data sending and receiving do not depend on a common clock signal. Instead, data transmission uses start and stop bits to mark the beginning and end of the data frame. This type of transmission is typically used for low-speed data communication, such as when the test control logic unit uses a serial communication interface (e.g., RS-232). The non-volatile memory and external test equipment synchronize their internal clocks by detecting the start bit when receiving data and reset their clocks upon receiving the stop bit. The clock signal is not necessary; in this case, only the test data port is needed to complete the testing of the non-volatile memory array, further increasing the number of parallel tests.
[0050] In some possible implementations, to ensure comprehensive testing, after completing the testing for the non-volatile memory array, the control logic and input / output of the logic control unit must also be tested. In this case, such as Figure 6 As shown, the test method also includes: 601. Obtain second control information from an external test device via a multiplexed external communication port, so that the logic selection unit shuts down the test control logic unit and turns on the SPI control logic unit based on the second control information.
[0051] 602. All external communication ports controlled by the SPI control logic unit obtain the second test signal from the external test equipment, and perform SPI control logic test based on the second test signal to obtain the second test result.
[0052] 603. Send the second test result to the external test equipment via all external communication ports.
[0053] Specifically, the process involves obtaining a second test signal from an external test device, performing SPI control logic testing based on the second test signal to obtain a second test result, and sending the second test result to the external test device. This includes: obtaining a second test signal from an external test device and performing SPI control logic testing based on the second test signal; obtaining a second read signal from an external test device and sending the result of the control logic test to the external test device.
[0054] During the SPI control logic test, the input / output capabilities of each communication port were also tested.
[0055] In some practical applications, information in the logic selection unit is lost upon power failure, and the logic selection unit needs to reload the first control information each time it is powered on. Therefore, upon receiving the second control information, the logic selection unit not only shuts down the test control logic unit and connects the SPI control logic unit based on the second control information, but also stores the second control information in the non-volatile memory array, overwriting the original first control information to generate new first control information. Thus, after the test process ends and the non-volatile memory is powered on again, the logic selection unit can load the new first control information from the non-volatile memory array, and connect the SPI control logic unit and shut down the test control logic unit based on the new first control information. This achieves the updated storage of configuration information, ensuring uninterrupted normal communication and facilitating user operation.
[0056] Those skilled in the art will understand that, based on the non-volatile memory in the embodiments of this disclosure, new second control information can be sent to the logic selection unit via an external communication port through an external device outside the non-volatile memory, based on usage requirements, to activate the test control logic unit or the SPI control logic unit. For example, in the initial state, the first control information is configured to activate the first logic selection unit. After the logic selection unit reads the first control information from the non-volatile memory array, it activates the test control logic unit to efficiently and with low power consumption complete the test of the non-volatile memory array. After this test is completed, the control logic and ports of the SPI logic control unit also need to be tested. At this time, other devices need to send second control information to the logic selection unit via the external communication port and the test control logic unit. This second control information is used to control the logic selection unit to deactivate the test control logic unit and activate the SPI control logic unit, thus enabling testing of the control logic and ports of the SPI logic control unit. When the non-volatile memory array needs to be tested again, new second control information can be sent, which is configured to control the logic selection unit to activate the test control logic unit and deactivate the SPI control logic unit. In this way, testers or ordinary users can freely switch between the test control logic unit and the SPI control logic unit, making it more flexible and convenient. It is worth noting that, to ensure communication stability, only one of the test control logic unit and the SPI control logic unit can be activated at any given time.
[0057] Combination Figure 7 As shown, this disclosure provides a test system for non-volatile memory, including: at least one non-volatile memory and an external test device, wherein the external communication device is connected to the non-volatile memory via a test pin card.
[0058] During testing of non-volatile memory arrays, external test equipment simultaneously connects to multiplexed external communication ports controlled by the test control logic unit in each non-volatile memory via a first test probe card. This allows for testing of non-volatile memory arrays using a test control logic unit with a more streamlined communication protocol and fewer external communication ports. Furthermore, a single test probe card can be used to test a larger number of non-volatile memory arrays, improving testing efficiency and reducing testing costs.
[0059] Optionally, combined Figure 8 As shown, the test system also includes a second test pin card. When the non-volatile memory disables the test control logic unit and enables the SPI control logic unit, the external test equipment connects simultaneously to all external communication ports controlled by the SPI control logic units in each non-volatile memory via the second test pin card. This allows for testing of the control logic of the SPI control logic unit and all external communication ports. In actual testing, the above tests for all external communication ports and control logic can be completed through a complete interface after the non-volatile memory is packaged, ensuring comprehensive and complete testing.
[0060] Combination Figure 9 As shown, this disclosure provides a testing apparatus for non-volatile memory, including a processor and a memory storing program instructions. The processor is configured to execute the aforementioned testing method for non-volatile memory when running the program instructions. Optionally, the apparatus may further include a communication interface 902 and a bus 903. The processor 900, communication interface 902, and memory 901 can communicate with each other via the bus 903. The communication interface 902 can be used for information transmission. The processor 900 can invoke logical instructions in the memory 901 to execute the testing method for non-volatile memory described in the above embodiment.
[0061] Furthermore, the logic instructions in the aforementioned memory 901 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.
[0062] The memory 901, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 900 executes functional applications and data processing by running the program instructions / modules stored in the memory 901, thereby implementing the testing method for non-volatile memory described in the above embodiments.
[0063] The memory 901 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 901 may include high-speed random access memory and may also include non-volatile memory.
[0064] Compared with existing technologies, the testing apparatus for non-volatile memory provided in this disclosure can perform non-volatile memory array testing using only a portion of the communication ports, greatly increasing the number of parallel tests for non-volatile memory, improving testing efficiency, reducing test pin wear, and lowering testing costs, while not affecting the integrity of the testing process. Other technical features of this testing apparatus are the same as those disclosed in the testing method, and will not be repeated here.
[0065] This disclosure provides an electronic device, including a device body and the aforementioned test apparatus for non-volatile memory. The test apparatus for non-volatile memory is mounted on the device body. The mounting relationship described herein is not limited to placement within the product, but also includes mounting connections with other components of the product, including but not limited to physical connections, electrical connections, or signal transmission connections. Those skilled in the art will understand that the test apparatus for non-volatile memory can be adapted to feasible product bodies to achieve other feasible embodiments.
[0066] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.
[0067] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
Claims
1. A testing method for non-volatile memory, characterized in that, The non-volatile memory includes a non-volatile memory array, a logic selection unit, a test control logic unit, an SPI control logic unit, and an external communication port. The external communication port controlled by the test control logic unit reuses a portion of the external communication ports controlled by the SPI control logic unit. The test methods include: The first control information is loaded from the non-volatile memory array using the logic selection unit, so as to turn on the test control logic unit and turn off the SPI control logic unit based on the first control information; Test control information is obtained from external test equipment through the multiplexed external communication port controlled by the test control logic unit, and the test control information is used to control the non-volatile memory to enter engineering mode. After the non-volatile memory enters engineering mode, it obtains a first test signal from an external test device via a multiplexed external communication port, sends the first test signal to the non-volatile memory array using the test control logic unit to obtain a first test result, and sends the first test result to the external test device via the multiplexed external communication port.
2. The test method according to claim 1, characterized in that, Sending the first test signal to the non-volatile memory array to obtain the first test result includes: The first test result read signal is obtained from the external test equipment via a multiplexed external communication port; The first test result read signal is sent to the non-volatile memory array to obtain the first test result of executing the first test signal from the non-volatile memory array; or, The first test status read signal is obtained from the external test equipment via a multiplexed external communication port; Send the first test state read signal to the non-volatile memory array to obtain the first execution state of executing the first test signal from the non-volatile memory array; After sending the first execution status to the external test equipment, the first test result read signal is obtained from the external test equipment via the multiplexed external communication port; The first test result read signal is sent to the non-volatile memory array to obtain the first test result of executing the first test signal from the non-volatile memory array.
3. The test method according to claim 1 or 2, characterized in that, The first test signal includes one or more of the following: analog calibration command, write command, and erase command.
4. The test method according to claim 1, characterized in that, The testing methods also include: The second control information is obtained from the external test equipment via the multiplexed external communication port, so that the logic selection unit shuts down the test control logic unit and turns on the SPI control logic unit based on the second control information. All external communication ports connected via the SPI control logic unit acquire the second test signal from the external test equipment, and perform SPI control logic testing based on the second test signal to obtain the second test result; The second test result is sent to the external test equipment via all external communication ports.
5. The test method according to claim 4, characterized in that, The second control information is stored in a non-volatile memory array to overwrite the original first control information, thereby generating new first control information.
6. The test method according to claim 1, characterized in that, The test interface protocol for the test control logic unit adopts the I2C interface protocol.
7. A testing apparatus for non-volatile memory, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to perform the test method for non-volatile memory as described in any one of claims 1 to 6 when executing the program instructions.
8. A non-volatile memory, characterized in that, It includes a non-volatile memory array, a logic selection unit, a test control logic unit, an SPI control logic unit, and an external communication port. The external communication port controlled by the test control logic unit reuses a portion of the external communication ports controlled by the SPI control logic unit. The non-volatile memory array stores the first control information; The logic selection unit is connected to the non-volatile memory array, the test control logic unit, and the SPI control logic unit, and is configured to load first control information from the non-volatile memory array to turn on the test control logic unit and turn off the SPI control logic unit based on the first control information. The test control logic unit, connected to the non-volatile memory array and the multiplexed external communication interface, is configured to obtain test control information from the external test equipment via the multiplexed external communication port, so as to control the non-volatile memory to enter the engineering mode using the test control information; after the non-volatile memory enters the engineering mode, it obtains a first test signal from the external test equipment via the multiplexed external communication port, sends the first test signal to the non-volatile memory array to obtain a first test result, and sends the first test result to the external test equipment via the multiplexed external communication port.
9. The non-volatile memory according to claim 8, characterized in that, The external communication ports controlled by the SPI control logic unit include the SPI input port, SPI output port, SPI chip select signal port, and SPI clock signal port. The multiplexed external communication ports controlled by the test control logic unit include multiplexed data ports and multiplexed clock signal ports. The multiplexed data ports multiplex the SPI input ports, and the multiplexed clock signal ports multiplex the SPI clock signal ports.
10. A test system for non-volatile memory, characterized in that, include: At least one non-volatile memory as described in claim 9; External testing equipment is connected to the non-volatile memory via a test pin card.