Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a substrate including a first region and a second region; a gate structure positioned over the substrate and extending from the first region to the second region; a laminate positioned in the second region over the substrate; first supports extending through the gate structure in the first region and successively arranged in the first direction; and a second support extending between the gate structure and the stack in a second direction intersecting the first direction in the second region, at least one of the first supports may include a first protrusion protruding toward the second region, and the second support may include a second protrusion protruding toward the first region.

Description

Technical Field

[0001] This disclosure relates to electronic devices and methods of manufacturing electronic devices, and more specifically, to semiconductor devices and methods of manufacturing semiconductor devices. Background Technology

[0002] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as the integration density of semiconductor devices where memory cells are formed as a single layer on a substrate has reached its limit, three-dimensional semiconductor devices where memory cells are stacked on a substrate are being proposed. Furthermore, various structures and manufacturing methods are being developed to improve the operational reliability of semiconductor devices. Summary of the Invention

[0003] According to embodiments of the present disclosure, a semiconductor device may include: a substrate including a first region and a second region; a gate structure positioned above the substrate and extending from the first region to the second region; a laminate positioned above the substrate in the second region; a first support extending through the gate structure in the first region and disposed sequentially in a first direction; and a second support extending between the gate structure and the laminate in the second region along a second direction intersecting the first direction, wherein at least one of the first supports may include a first protrusion projecting toward the second region, and the second support may include a second protrusion projecting toward the first region.

[0004] According to embodiments of the present disclosure, a semiconductor device may include: a gate structure including a first portion and a second portion positioned on the first portion; a stack positioned at a level corresponding to the gate structure; a first support extending through the gate structure and disposed sequentially in a first direction; and a second support extending between the gate structure and the stack along a second direction intersecting the first direction, wherein at least one of the first supports may include a first protrusion projecting toward the second support, the second support may include a second protrusion projecting toward the first support, and at least one of the first protrusion or the second protrusion may be positioned at a level corresponding to the first portion.

[0005] According to embodiments of the present disclosure, a method of manufacturing a semiconductor device may include the following steps: forming a first sub-layer; forming a first support hole extending through the first sub-layer; forming a support sacrificial layer in the first support hole; forming a second sub-layer on the first sub-layer; forming a second support hole extending through the second sub-layer and the first sub-layer and exposing the sidewalls of the support sacrificial layer; removing the support sacrificial layer through the second support hole; and forming a support member in the first support hole and the second support hole.

[0006] According to embodiments of the present disclosure, a method of manufacturing a semiconductor device may include the following steps: forming a first sub-layer stack; forming a first channel via extending through the first sub-layer stack; forming a first support via extending through the first sub-layer stack; forming a channel sacrificial layer in the first channel via; forming a support sacrificial layer in the first support via; forming a second sub-layer stack on the first sub-layer stack; forming a second support via extending through the second sub-layer stack and the first sub-layer stack and exposing the sidewalls of the support sacrificial layer; removing the support sacrificial layer through the second support via; and forming a support member including a protrusion in the first support via and the second support via. Attached Figure Description

[0007] Figure 1A , Figure 1B , Figure 1C and Figure 1D This is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2A , Figure 2B , Figure 2C and Figure 2D This is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 4A , Figure 4B , Figure 4C and Figure 4D , Figure 5A , Figure 5B , Figure 5C and Figure 5D , Figure 6A , Figure 6B , Figure 6C and Figure 6D , Figure 7A , Figure 7B , Figure 7C and Figure 7D as well as Figure 8A , Figure 8B , Figure 8C and Figure 8D This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0011] Embodiments of this disclosure provide a semiconductor device with a stable structure and improved properties, and a method for manufacturing the semiconductor device.

[0012] According to embodiments of this technology, a semiconductor device with a stable structure and improved reliability can be provided.

[0013] In the following description, embodiments based on the technical spirit of this disclosure are described with reference to the accompanying drawings.

[0014] Terms such as “first” and “second” are used to distinguish between various elements and do not imply the size, order, priority, quantity, or importance of the elements. For example, in one example, a first element may be named a second element, and in another example, a second element may be named a first element. Terms such as “top,” “above,” “upper,” “side,” “upper part,” “lower part,” “row,” “column,” “inner,” and “outer,” and other terms that imply relative spatial relationships or orientations, are used only for the purpose of description or reference to the accompanying drawings and are not intended to limit in any other way. Crosshairs running through the drawings illustrate corresponding or similar areas between the drawings and do not indicate material associated with those areas. It will be understood that when an element or layer is referred to as being “on”, “connected to,” or “attached to” another element or layer, it may be directly on, directly connected to, or attached to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element or layer is referred to as being “directly on”, “directly connected to,” or “directly attached to” another element or layer, there are no intermediate elements or layers.

[0015] Figures 1A to 1D This is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 1A It's a floor plan. Figure 1B It is along Figure 1A A cross-sectional view taken from line A-A'. Figure 1C It is along Figure 1A The cross-sectional view taken by line B-B', and Figure 1D It is along Figure 1A The cross-sectional view taken from line C-C'.

[0016] Reference Figures 1A to 1D The semiconductor device may include a substrate 100, peripheral circuitry PC, laminate 110S, gate structure 110G, channel structure 120, first support 130, and second support 140. The semiconductor device may also include a third support 150, a fourth support 160, contact vias 170, contact plugs 180, slit structures 190, interlayer insulating layers 110L, interconnect structures 110C, component isolation layers 110S, source structures 110S, first insulating spacers 111 and second insulating spacers 112.

[0017] The substrate 100 may include a first region R1 and a second region R2. The first region R1 and the second region R2 may be adjacent to each other in a first direction I. The first region R1 may be a region in which a memory cell is located. The second region R2 may be a region in which a contact plug 180 electrically connected to a peripheral circuit PC is located. Contact vias 170 connected to the conductive layer 110C of the gate structure 110G may be located in the first region R1 and the second region R2.

[0018] The peripheral circuit PC can be positioned on the substrate 100. For example, the peripheral circuit PC can be positioned in the second region R2. However, this disclosure is not limited thereto, and the peripheral circuit PC can be positioned in the first region R1 and the second region R2. The peripheral circuit PC may include a transistor 1, a capacitor, etc. The transistor 1 may include junctions 1A and 1B, a gate electrode 1D, and a gate insulating layer 1C. Here, the gate insulating layer 1C can be positioned between the gate electrode 1D and the substrate 100. A component isolation layer ISO can be positioned in the substrate 100, the active region can be defined by the component isolation layer ISO, and the transistor 1 can be positioned in the active region.

[0019] The interconnect structure IC can be positioned on the peripheral circuit PC. The interconnect structure IC can also be positioned within the interlayer insulating layer IL. Here, the interlayer insulating layer IL can be positioned on the substrate 100. The interconnect structure IC may include vias ICA and lines ICB.

[0020] The interconnect structure IC can be connected to an external circuit PC. For example, at least one of the through-hole ICAs can be connected to transistor 1. At least one of the through-hole ICAs can interconnect with a line ICB. The line ICB can interconnect with the through-hole ICAs. The interconnect structure IC can include a conductive material such as tungsten. The interlayer insulating layer IL can include an insulating material such as oxide.

[0021] The source structure SS can be located on the interlayer insulating layer IL. The source structure SS can be single-layer or multi-layer. The source structure SS can include conductive materials such as polysilicon.

[0022] A gate structure 110G may be positioned above a substrate 100. The gate structure 110G may extend from a first region R1 to a second region R2. The gate structure 110G may include alternating layers of a first insulating layer 110A and a conductive layer 110C. The gate structure 110G may include a first portion 110G1 and a second portion 110G2 positioned on the first portion 110G1. For example, the gate structure 110G may include a first portion 110G1 having a first height H1 (i.e., 110G1(H1)) and a second portion 110G2 having a second height H2 (i.e., 110G2(H2)). Here, the first height H1 and the second height H2 may be substantially equal to or different from each other. For example, the second height H2 may be smaller than the first height H1.

[0023] The conductive layer 110C can be a gate line such as a source select line, word line, or drain select line. Source select transistors, memory cells, or drain select transistors can be located in the region where the channel structure 120 and the conductive layer 110C intersect. For example, at least one source select transistor, multiple memory cells, and at least one drain select transistor stacked along the channel structure 120 can be configured as a memory string. The conductive layer 110C can comprise a conductive material such as tungsten, molybdenum, or polysilicon.

[0024] The stack 110S can be positioned above the substrate 100. The stack 110S can be positioned within the second region R2. The stack 110S may include alternately stacked first insulating layer 110A and second insulating layer 110B. In the process of manufacturing a semiconductor device, the second insulating layer 110B may be retained without being replaced by the conductive layer 110C. The first insulating layer 110A and the second insulating layer 110B may include different materials. For example, the first insulating layer 110A may include an insulating material such as an oxide, and the second insulating layer 110B may include a sacrificial material such as a nitride.

[0025] The channel structure 120 may be located in the first region R1 and may extend through the gate structure 110G. For example, the channel structure 120 may extend through the gate structure 110G into the source structure SS. Each of the channel structures 120 may include a first sub-channel structure 120S1 and a second sub-channel structure 120S2. For example, the channel structure 120 may include a first sub-channel structure 120S1 extending through the first portion 110G1, and may include a second sub-channel structure 120S2 extending through the second portion 110G2 and connected to the first sub-channel structure 120S1. The first sub-channel structure 120S1 may include a first sub-channel layer 120A1, a first sub-memory layer 120B1 surrounding the first sub-channel layer 120A1, and a first sub-insulating core 120C1 in the first sub-channel layer 120A1. The second sub-channel structure 120S2 may include a second sub-channel layer 120A2, a second sub-memory layer 120B2, and a second sub-insulating core 120C2 in the second sub-channel layer 120A2.

[0026] The first support member 130 can be positioned in the first region R1 and can extend through the gate structure 110G. The first support members 130 can be arranged consecutively in the first direction I. For example, the first support members 130 arranged consecutively in the first direction I can be configured as a first group 130G1. Furthermore, the first support members 130 arranged in a second direction II intersecting the first direction I, spaced apart from the first group 130G1 and arranged consecutively in the first direction I, can be configured as a second group 130G2.

[0027] The first support member 130 may include a first body portion 130A and / or a first protrusion 130B. For example, at least one of the first support members 130 may include a first body portion 130A and a first protrusion 130B. Here, the first body portion 130A may extend through the gate structure 110G, and the first protrusion 130B may protrude from the first body portion 130A within the gate structure 110G. For example, the first protrusion 130B may protrude from the first body portion 130A and remain within the gate structure 110G. For example, the first protrusion 130B may protrude from the first body portion 130A and protrude into the gate structure 110G. The first protrusion 130B may protrude toward the second support member 140. For example, the first protrusion 130B may protrude toward the second region R2. The first protrusion 130B may be positioned at a level corresponding to the first portion 110G1. For example, the first protrusion 130B may be positioned at a level corresponding to the first sub-channel structure 120S1. In an implementation, the first protrusion 130B or the second protrusion 140B may be positioned at a level that at least partially overlaps with the first portion 110G1 along the first direction I, such as... Figure 1C and Figure 1DAs shown. In an embodiment, the stack 110S can be positioned at a level that at least partially overlaps with the gate structure 110G along the first direction I, such as... Figure 1B As shown. In the implementation method, as Figure 1B , Figure 1C and Figure 1D As shown, the first protrusion 130B or the second protrusion 140B may be positioned at a level that at least partially overlaps with the first sub-channel structure 120S1 along the first direction I. The second support 140 may include an insulating material such as an oxide.

[0028] The second support member 140 can be positioned in the second region R2 and can extend between the gate structure 110G and the stack 110S. The second support member 140 can extend in the second direction II. The second support member 140 may include a second body portion 140A and a second protrusion 140B. Here, the number of second protrusions 140B can be multiple.

[0029] The second body portion 140A may extend between the gate structure 110G and the stack 110S. For example, the second body portion 140A may include a first extension extending in a first direction I and a second extension extending in a second direction II, and the first extension may be interconnected through the second extension. In other words, the second body portion 140A may have a C-shape. However, this disclosure is not limited thereto, and the second body portion 140A may also be configured with a closed region by the first extension and a plurality of second extensions. The second protrusion 140B may protrude from the second body portion 140A within the gate structure 110G. For example, the second protrusion 140B may protrude from the second body portion 140A and remain in the gate structure 110G. For example, the second protrusion 140B may protrude from the second body portion 140A and protrude into the gate structure 110G. The second protrusion 140B may protrude toward the first support 130. For example, the second protrusion 140B may protrude toward the first region R1. The second protrusion 140B may be positioned at a level corresponding to the first portion 110G1. For example, the second protrusion 140B can be positioned at a level corresponding to the first sub-channel structure 120S1. The first support 130 may include an insulating material such as an oxide.

[0030] The third support member 150 may be positioned within the first region R1 and may extend through the gate structure 110G. The third support member 150 may extend in a first direction I. For example, the third support member 150 may be positioned between a first group 130G1 and a second group 130G2 of the first support members 130, and may extend in the first direction I. At least one of the third support members 150 may include a third body portion 150A and / or a third protrusion 150B. Here, the third body portion 150A may extend through the gate structure 110G, and the third protrusion 150B may protrude within the gate structure 110G toward the second region R2. For example, the third protrusion 150B may protrude from the third body portion 150A and remain within the gate structure 110G. For example, the third protrusion 150B may protrude from the third body portion 150A and protrude into the gate structure 110G. The third protrusion 150B may be positioned at a level corresponding to the first sub-channel structure 120S1. The third support 150 may include an insulating material such as an oxide.

[0031] The fourth support member 160 can be positioned in the second region R2 and can extend through the gate structure 110G. The fourth support members 160 can be arranged consecutively in the first direction I. For example, the fourth support members 160 arranged consecutively in the first direction I can be configured as a first group 160G1. In addition, the fourth support members 160 spaced apart from the first group 160G1 in the second direction II and arranged consecutively in the first direction I can be configured as a second group 160G2. Here, the second support member 140 can be positioned between the first group 160G1 and the second group 160G2.

[0032] At least one of the fourth support members 160 may include a fourth body portion 160A and / or a fourth protrusion 160B. Here, the fourth body portion 160A may extend through the gate structure 110G, and the fourth protrusion 160B may protrude within the gate structure 110G toward the first region R1. For example, the fourth protrusion 160B may protrude from the fourth body portion 160A and remain within the gate structure 110G. For example, the fourth protrusion 160B may protrude from the fourth body portion 160A and protrude into the gate structure 110G. The fourth protrusion 160B may be positioned at a level corresponding to the first sub-channel structure 120S1. The fourth support member 160 may include an insulating material such as an oxide.

[0033] The contact via 170 may extend through the gate structure 110G and may be connected to the conductive layer 110C. Here, a first insulating spacer SP1 may surround the sidewall of the contact via 170. The contact via 170 may be located in a first region R1 and a second region R2. For example, the contact via 170 may be located between the first support 130 and the third support 150, between the third supports 150, and / or between the first support 130 / the third support 150 and the second support 140. The first insulating spacer SP1 may comprise an insulating material such as an oxide, and the contact via 170 may comprise a conductive material such as tungsten.

[0034] For reference, although not shown in this figure, the gate structure 110G may include a stepped structure configured through the conductive layer 110C, and an interlayer insulating layer may be positioned on the stepped structure. Here, the upper surface of the conductive layer 110C and the interlayer insulating layer may be in contact with each other. Furthermore, the contact via 170 may extend through the interlayer insulating layer and may be connected to the upper surface of the conductive layer 110C. In this case, the first insulating spacer SP1 may be omitted.

[0035] Contact plug 180 may be positioned within the second region R2 and may extend through the laminate 110S. For example, contact plug 180 may extend through the laminate 110S and through the source structure SS and may be electrically connected to the peripheral circuit PC. Contact plug 180 may be electrically connected to the peripheral circuit PC via an interconnect structure IC. Here, a second insulating spacer SP2 may surround the sidewall of contact plug 180 within the source structure SS. The second insulating spacer SP2 may comprise an insulating material such as an oxide, and contact plug 180 may comprise a conductive material such as tungsten.

[0036] The region where the contact via 170 is located and the region where the contact plug 180 is located can be different from each other. For example, the contact via 170 can be located in the first region R1 and the second region R2 and can extend through the gate structure 110G. On the other hand, the contact plug 180 can be located in the second region R2 and can extend through the laminate 110S.

[0037] The first support 130, the third support 150, and the fourth support 160 can be positioned between the contact vias 170, and the second support 140 can be positioned around the stack 110S to define an area where the stack 110S is retained in the process of manufacturing the semiconductor device. In this case, the shape and arrangement of the first support 130, the second support 140, the third support 150, and the fourth support 160 positioned in the first region R1 and the second region R2 can be different. For example, the first support 130 and the third support 150 can be regularly arranged in the first region R1, and the second support 140 and the fourth support 160 can be regularly arranged in the second region R2. In other words, the regularity of the supports can be changed at the boundary between the first region R1 and the second region R2. Therefore, bending of the gate structure 110G and / or the stack 110S may occur at the boundary between the first region R1 and the second region R2, and this problem may become more severe as the height of the gate structure 110G and / or the stack 110S increases.

[0038] Furthermore, in this embodiment, to form the contact via 170 at the portion where the regularity of the support changes, it is necessary to ensure a margin between the first support 130 / third support 150 and the second support 140 / fourth support 160. In this embodiment, when the distance between the first support 130 / third support 150 and the second support 140 / fourth support 160 is increased to ensure this margin, the first support 130, second support 140, third support 150, and fourth support 160 may not be able to adequately support the gate structure 110G and / or the stack 110S. In other words, in this embodiment, the supporting force of the first support 130, second support 140, third support 150, and fourth support 160 may weaken near the boundary surface between the first region R1 and the second region R2.

[0039] According to embodiments of this disclosure, a first protrusion 130B and a third protrusion 150B may be included, projecting from a first region R1 toward a second region R2, and a second protrusion 140B and a fourth protrusion 160B may be included, projecting from the second region R2 toward the first region R1. In this case, compared to the case where the first protrusion 130B, the second protrusion 140B, the third protrusion 150B, and the fourth protrusion 160B are absent, the thickness of the first support member 130, the second support member 140, the third support member 150, and the fourth support member 160 can be increased, and the distance between the first support member 130 / the third support member 150 and the second support member 140 / the fourth support member 160 can become relatively shorter, thereby increasing the supporting force of the first support member 130, the second support member 140, the third support member 150, and the fourth support member 160.

[0040] For example, refer to Figure 1C Compared to the case where only the second main body portion 140A and the third main body portion 150A exist, the thickness of the second support member 140 and the third support member 150 can be increased. Furthermore, the distance between the second support member 140 and the third support member 150 can be a first distance L1 based on the second main body portion 140A and the third main body portion 150A, and can be a second distance L2 based on the second protrusion 140B and the third protrusion 150B, which is smaller than the first distance L1. Additionally, referring to… Figure 1D Compared to the case where only the first main body portion 130A and the fourth main body portion 160A exist, the thickness of the first support member 130 and the fourth support member 160 can be increased. Furthermore, the distance between the first support member 130 and the fourth support member 160 can be a third distance L3 based on the first main body portion 130A and the fourth main body portion 160A, and can be a fourth distance L4 based on the first protrusion 130B and the fourth protrusion 160B, which is smaller than the third distance L3. Therefore, in this embodiment, the supporting force of the first support member 130, the second support member 140, the third support member 150, and the fourth support member 160 can be increased at the boundary between the first region R1 and the second region R2, and bending of the gate structure 110G and the stack 110S can be prevented or reduced.

[0041] The slit structure 190 may extend through the gate structure 110G. At least one of the slit structures 190 may extend from the first region R1 to the second region R2. The slit structure 190 may include an insulating material, a conductive material, and / or a semiconductor material.

[0042] According to an embodiment of the above structure, the semiconductor device may include a first support 130 / third support 150 positioned in a first region R1, and may include a first protrusion 130B / third protrusion 150B projecting toward a second region R2. A second support 140 / fourth support 160 positioned in the second region R2 may include a second protrusion 140B / fourth protrusion 160B projecting toward the first region R1. In this case, in the embodiment, the support force of the first support 130, second support 140, third support 150, and fourth support 160 may be increased near the boundary surface between the first region R1 and the second region R2, where the support force of the first support 130, second support 140, third support 150, and fourth support 160 may weaken.

[0043] Figures 2A to 2D This is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 2A It's a floor plan. Figure 2B It is along Figure 2A A cross-sectional view taken from line D-D'. Figure 2C It is along Figure 2A The cross-sectional view taken by line E-E', and Figure 2D It is along Figure 2A The cross-sectional view taken by line F-F'. In the following text, content overlapping with the above is omitted.

[0044] Reference Figures 2A to 2D The semiconductor device may include a substrate 200, peripheral circuit PC, laminate 210S, gate structure 210G, channel structure 220, first support member 230, second support member 240, third support member 250, fourth support member 260, contact via 270, contact plug 280, slit structure 290, first interlayer insulating layer IL1, second interlayer insulating layer IL2, first interconnect structure IC1, second interconnect structure IC2, element isolation layer ISO, source structure SS, insulating spacer SP, and bonding structure BS.

[0045] The substrate 200 may include a first region R1 and a second region R2. The first region R1 and the second region R2 may be adjacent to each other in a first direction I. The first region R1 may be a region where memory cells are located, and may also be a region where contact vias 270 are located, respectively connected to the conductive layer 210C of the gate structure 210G. The second region R2 may be a region where contact plugs 280 electrically connected to the peripheral circuit PC are located, and may also be a region where contact vias 270 are located.

[0046] The peripheral circuit PC can be positioned on the substrate 200. For example, the peripheral circuit PC can be positioned in the second region R2. However, this disclosure is not limited thereto, and the peripheral circuit PC can be positioned in the first region R1 and the second region R2. The transistor 1 may include junctions 1A and 1B, a gate electrode 1D, and a gate insulating layer 1C.

[0047] The first interconnect structure IC1 can be positioned on the peripheral circuit PC. The first interconnect structure IC1 can be positioned within the first interlayer insulating layer IL1. Here, the first interlayer insulating layer IL1 can be positioned on the substrate 200. The first interconnect structure IC1 may include a first via ICA and a first line ICB.

[0048] The bonding structure BS can be positioned on the first interconnect structure IC1. The bonding structure BS can be positioned within a first region R1 and a second region R2. The bonding structure BS may include a first bonding pad BP1 and a second bonding pad BP2. The first bonding pad BP1 can be positioned within a first interlayer insulating layer IL1. The second bonding pad BP2 can be positioned within a second interlayer insulating layer IL2. Here, the second interlayer insulating layer IL2 can be positioned on the first interlayer insulating layer IL1.

[0049] A gate structure 210G may be positioned above a substrate 200. The gate structure 210G may extend from a first region R1 to a second region R2. The gate structure 210G may include alternating layers of a first insulating layer 210A and a conductive layer 210C. The gate structure 210G may include a first portion 210G1 and a second portion 210G2 positioned on the first portion 210G1. For example, the gate structure 210G may include a first portion 210G1 having a first height H1 and a second portion 210G2 having a second height H2. Here, the first height H1 and the second height H2 may be substantially equal to or different from each other. For example, the second height H2 may be less than the first height H1. The conductive layer 210C may include a conductive material such as tungsten, molybdenum, or polysilicon.

[0050] The laminate 210S can be positioned above the substrate 200. The laminate 210S can be positioned in the second region R2. The laminate 210S may include an alternately stacked first insulating layer 210A and a second insulating layer 210B. The first insulating layer 210A may include an insulating material such as an oxide, and the second insulating layer 210B may include a sacrificial material such as a nitride.

[0051] The channel structure 220 may be located in the first region R1 and may extend through the gate structure 210G. For example, the channel structure 220 may extend through the gate structure 210G into the source structure SS. Here, the source structure SS may be located on the channel structure 220. Each of the channel structures 220 may include a first sub-channel structure 220S1 and a second sub-channel structure 220S2. For example, the channel structure 220 may include a first sub-channel structure 220S1 extending through the first portion 210G1, and may include a second sub-channel structure 220S2 extending through the second portion 210G2 and connected to the first sub-channel structure 220S1. The first sub-channel structure 220S1 may include a first sub-channel layer 220A1, a first sub-memory layer 220B1 surrounding the first sub-channel layer 220A1, and a first sub-insulating core 220C1 in the first sub-channel layer 220A1. Here, the first sub-channel layer 220A1 of the first sub-channel structure 220S1 can be connected to the source structure SS. The second sub-channel structure 220S2 may include the second sub-channel layer 220A2, the second sub-memory layer 220B2, and the second sub-insulating core 220C2 in the second sub-channel layer 220A2.

[0052] The second interconnect structure IC2 can be positioned on the bonding structure BS. The second interconnect structure IC2 can also be positioned within the second interlayer insulating layer IL2. The second interconnect structure IC2 may include a second via ICC and a second line ICD. The contact plug 280 can be electrically connected to the peripheral circuit PC via the second interconnect structure IC2, the bonding structure BS, and the first interconnect structure IC1. For reference, although not shown in this figure, the channel structure 220 and / or the contact via 270 can be electrically connected to the peripheral circuit PC via the second interconnect structure IC2, the bonding structure BS, and the first interconnect structure IC1.

[0053] The first support member 230 may be positioned in the first region R1 and may extend through the gate structure 210G. The first support members 230 may be arranged sequentially in a first direction I. At least one of the first support members 230 may include a first body portion 230A and a first protrusion 230B. Here, the first body portion 230A may extend through the gate structure 210G, and the first protrusion 230B may protrude from the first body portion 230A in the gate structure 210G. The first protrusion 230B may protrude toward the second support member 240. For example, the first protrusion 230B may protrude toward the second region R2. The first protrusion 230B may be positioned at a level corresponding to the first portion 210G1. For example, the first protrusion 230B may be positioned at a level corresponding to the first sub-channel structure 220S1. The first support member 230 may include an insulating material such as an oxide.

[0054] The second support member 240 may be positioned in the second region R2 and may extend between the gate structure 210G and the stack 210S. The second support member 240 may extend in the second direction II. The second support member 240 may include a second body portion 240A and a second protrusion 240B. Here, the number of second protrusions 240B may be multiple. The second body portion 240A may extend between the gate structure 210G and the stack 210S. The second protrusion 240B may protrude from the second body portion 240A in the gate structure 210G. The second protrusion 240B may protrude toward the first support member 230. For example, the second protrusion 240B may protrude toward the first region R1. The second protrusion 240B may be positioned at a level corresponding to the first portion 210G1. For example, the second protrusion 240B may be positioned at a level corresponding to the first sub-channel structure 220S1. The second support member 240 may include an insulating material such as an oxide.

[0055] The third support member 250 may be positioned in the first region R1 and may extend through the gate structure 210G. The third support member 250 may extend in a first direction I. At least one of the third support members 250 may include a third body portion 250A and / or a third protrusion 250B. Here, the third body portion 250A may extend through the gate structure 210G, and the third protrusion 250B may protrude in the gate structure 210G toward the second region R2. The third protrusion 250B may be positioned at a level corresponding to the first sub-channel structure 220S1. The third support member 250 may include an insulating material such as an oxide.

[0056] A fourth support member 260 may be positioned in the second region R2 and may extend through the gate structure 210G. The fourth support members 260 may be arranged sequentially in the first direction I. At least one of the fourth support members 260 may include a fourth body portion 260A and / or a fourth protrusion 260B. Here, the fourth body portion 260A may extend through the gate structure 210G, and the fourth protrusion 260B may protrude in the gate structure 210G toward the first region R1. The fourth protrusion 260B may be positioned at a level corresponding to the first sub-channel structure 220S1. The fourth support member 260 may include an insulating material such as an oxide.

[0057] The contact via 270 can extend through the gate structure 210G and can be connected to the conductive layer 210C. Here, the insulating spacer SP can surround the sidewall of the contact via 270. The contact via 270 can be located in the first region R1 and the second region R2. For example, the contact via 270 can be located between the first support 230 and the third support 250, between the third supports 250, and / or between the first support 230 / the third support 250 and the second support 240. The insulating spacer SP can include an insulating material such as oxide, and the contact via 270 can include a conductive material such as tungsten.

[0058] Contact plug 280 may be positioned in the second region R2 and may extend through the laminate 210S. For example, contact plug 280 may extend through the laminate 210S and may be electrically connected to an external circuit PC. Contact plug 280 may comprise a conductive material such as tungsten.

[0059] According to embodiments of this disclosure, a first protrusion 230B and a third protrusion 250B may be included, projecting from a first region R1 toward a second region R2, and a second protrusion 240B and a fourth protrusion 260B may be included, projecting from the second region R2 toward the first region R1. In this case, compared to the absence of the first protrusion 230B, the second protrusion 240B, the third protrusion 250B, and the fourth protrusion 260, the thickness of the first support member 230, the second support member 240, the third support member 250, and the fourth support member 260 can be increased, the distance between the first support member 230 / the third support member 250 and the second support member 240 / the fourth support member 260 can become relatively shorter, and therefore, in the embodiment, the supporting force of the first support member 230, the second support member 240, the third support member 250, and the fourth support member 260 can be improved.

[0060] The slit structure 290 may extend through the gate structure 210G. At least one of the slit structures 290 may extend from the first region R1 to the second region R2. The slit structure 290 may include an insulating material, a conductive material, and / or a semiconductor material.

[0061] According to the above structure, the semiconductor device may include a bonding structure BS. The bonding structure BS may be positioned on and electrically connected to the peripheral circuit PC. Therefore, the channel structure 220, the contact via 270, and / or the contact plug 280 can be electrically connected to the peripheral circuit PC through the bonding structure BS.

[0062] Figures 3A to 3E This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. In the following text, content overlapping with the above description is omitted.

[0063] Reference Figure 3A A first sub-laminated composite 310S1 can be formed. For example, a first material layer 310A and a second material layer 310B can be alternately laminated to form the first sub-laminated composite 310S1. Here, the first sub-laminated composite 310S1 may have a first height H1. The first material layer 310A and the second material layer 310B may include different materials. For example, the first material layer 310A may include an insulating material such as an oxide, and the second material layer 310B may include a sacrificial material such as a nitride.

[0064] Subsequently, a first support hole SH1 extending through the first sub-layer 310S1 can be formed. Here, the first support hole SH1 can be formed using a plasma process. For example, the first support hole SH1 can be formed by plasma etching of the first sub-layer 310S1. However, this disclosure is not limited to this, and the first support hole SH1 can be formed by various methods. Subsequently, a support sacrificial layer 320S can be formed in the first support hole SH1. Here, the support sacrificial layer 320S can include a sacrificial material such as a metallic material. For example, the support sacrificial layer 320S can include titanium nitride, tungsten, etc.

[0065] Reference Figure 3B A second sub-laminated layer 310S2 can be formed on the first sub-laminated layer 310S1. For example, a first material layer 310A and a second material layer 310B can be alternately laminated on the first sub-laminated layer 310S1 to form the second sub-laminated layer 310S2. Here, the second sub-laminated layer 310S2 can have a second height H2. The second height H2 can be substantially equal to or different from the first height H1. For example, the second height H2 can be less than the first height H1.

[0066] Subsequently, a second support hole SH2 extending through the second sub-laminate 310S2 can be formed. For example, a second support hole SH2 can be formed through the second sub-laminate 310S2 to expose the support sacrificial layer 320S. Here, the second support hole SH2 can be formed such that the center of the first support hole SH1 and the center of the second support hole SH2 are misaligned. In this case, the second support hole SH2 can expose a portion of the upper surface of the support sacrificial layer 320S.

[0067] According to embodiments of this disclosure, the second height H2 of the second sub-laminate 310S2 can be smaller than the first height H1 of the first sub-laminate 310S1. In other words, the second sub-laminate 310S2 can be formed with a relatively small height. In this case, in the embodiment, when the second support hole SH2 is formed such that the center of the first support hole SH1 and the center of the second support hole SH2 are not aligned, the second support hole SH2 can be formed more accurately at the desired position.

[0068] Reference Figure 3C The second support hole SH2 can extend. For example, a second support hole SH2 can be formed that extends through the first sub-layer 310S1 and exposes the sidewall of the support sacrificial layer 320S. Here, the second support hole SH2 can extend along the contour of the support sacrificial layer 320S.

[0069] The second support hole SH2 can be formed using a plasma process. For example, the second support hole SH2 can be formed by plasma etching of the second sub-layer 310S2 and the first sub-layer 310S1. Because the support sacrificial layer 320S can include a metallic material, ions in the plasma can be attracted to the metallic material during the process of forming the second support hole SH2, and the second support hole SH2 can be formed along the contour of the support sacrificial layer 320S. Therefore, the second support hole SH2 can extend along the sidewall of the support sacrificial layer 320S.

[0070] For reference, when the second support hole SH2 is formed without forming the support sacrificial layer 320S, the second support hole SH2 can be formed as a tapered shape with its width regularly decreasing from top to bottom. However, when the support sacrificial layer 320S is formed and the second support hole SH2 is formed, the second support hole SH2 can be formed along the sidewall of the support sacrificial layer 320S. In other words, the second support hole SH2 can be formed in a direction parallel to the sidewall of the support sacrificial layer 320S. Therefore, the shape of the second support hole SH2 when the support sacrificial layer 320S is not formed and the shape of the second support hole SH2 when the support sacrificial layer 320S is formed can be different from each other.

[0071] Reference Figure 3D The support sacrificial layer 320S can be removed through the second support hole SH2. Subsequently, a support member 320 can be formed in the second support hole SH2 and the first support hole SH1. In this case, each of the support members 320 may include a main body portion 320A and a protrusion 320B projecting from the main body portion 320A. Here, the protrusions 320B may project toward different support members 320 respectively. The support member 320 may include an insulating material such as an oxide.

[0072] Subsequently, the second material layer 310B can be removed to form the opening OP. For example, the second material layer 310B of the first sub-laminate 310S1 and the second sub-laminate 310S2 can be removed to form the opening OP. Here, in the embodiment, when the supporting force of the support member 320 is weak, the first sub-laminate 310S1 and the second sub-laminate 310S2 may bend. In the embodiment, this problem may be exacerbated as the height of the first sub-laminate 310S1 and the second sub-laminate 310S2 increases.

[0073] According to embodiments of this disclosure, compared to the case where only the main body portion 320A is formed, the support member 320 can form a protrusion 320B. Therefore, the thickness of the lower portion including the protrusion 320B can be greater than the thickness of the upper portion excluding the protrusion 320B. Thus, in this embodiment, the supporting force of the support member 320 can be increased.

[0074] Furthermore, the distance between the support members 320 can be a first distance L1 based on the main body portion 320A, and a second distance L2, smaller than the first distance L1, based on the protrusion 320B. In this embodiment, reducing the distance between the support members 320 can increase the supporting force of the support members 320. Therefore, in this embodiment, by forming the protrusion 320B, bending of the first sub-laminate 310S1 and the second sub-laminate 310S2 can be prevented or reduced.

[0075] Reference Figure 3E A third material layer 310C can be formed in the opening OP. Therefore, a gate structure 310G in which a first material layer 310A and a third material layer 310C are alternately stacked can be formed. Here, the third material layer 310C may include a conductive material such as tungsten.

[0076] For reference, although not shown in this figure, an additional support sacrificial layer may be formed in the second sub-laminate 310S2 before the second support hole SH2 is formed. The additional support sacrificial layer in the second sub-laminate 310S2 may be formed to connect to the support sacrificial layer 320S in the first sub-laminate 310S1. Subsequently, the second support hole SH2 may be formed along the additional support sacrificial layer and the support sacrificial layer 320S. In this case, the support member may include additional protrusions not only in the first sub-laminate but also in the second sub-laminate. Therefore, in the embodiment, since both the lower and upper thicknesses of the support member can be increased, the supporting force of the support member can be improved.

[0077] According to the manufacturing method described above, a plasma process can be used in the process of forming the second support hole SH2. In this case, the second support hole SH2 can be formed along the contour of the support sacrificial layer 320S, which includes a metallic material. Subsequently, the support sacrificial layer 320S can be removed through the second support hole SH2 to form the support member 320. Here, in the embodiment, the area where the support sacrificial layer 320S is formed can be configured with protrusions 320B of the support member 320, and the supporting force of the support member 320 can be improved.

[0078] Figures 4A to 4D , Figures 5A to 5D , Figures 6A to 6D , Figures 7A to 7D as well as Figures 8A to 8D This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. In the following text, content overlapping with the above description is omitted.

[0079] Reference Figures 4A to 4DA peripheral circuit PC can be formed on a substrate 400 including a first region R1 and a second region R2. Here, the first region R1 and the second region R2 can be adjacent to each other in a first direction I. The first region R1 can be a region where memory cells are formed. The second region R2 can be a region where contact plugs electrically connected to the peripheral circuit PC are formed. Contact vias connected to conductive layers of the gate structure can be formed in the first region R1 and the second region R2, respectively.

[0080] The peripheral circuit PC can be formed in the second region R2. However, this disclosure is not limited thereto, and the peripheral circuit PC can be formed in the first region R1 and the second region R2. The peripheral circuit PC may include a transistor 1, a capacitor, etc. The transistor 1 may include junctions 1A and 1B, a gate electrode 1D, and a gate insulating layer 1C. Here, the gate insulating layer 1C may be formed between the gate electrode 1D and the substrate 400. A component isolation layer ISO may be formed in the substrate 400, the active region may be defined by the component isolation layer ISO, and the transistor 1 may be positioned in the active region.

[0081] Subsequently, interconnect structure ICs can be formed on the peripheral circuit PC. The interconnect structure ICs can be formed in the interlayer insulating layer IL. Here, the interlayer insulating layer IL can be formed on the substrate 400. The interconnect structure ICs may include vias ICA and lines ICB.

[0082] The interconnect structure IC can be connected to an external circuit PC. For example, at least one of the through-hole ICAs can be connected to transistor 1. At least one of the through-hole ICAs can interconnect with a line ICB. The line ICB can interconnect with the through-hole ICAs. The interconnect structure IC can include a conductive material such as tungsten. The interlayer insulating layer IL can include an insulating material such as oxide.

[0083] Subsequently, a source structure SS can be formed on the interconnect structure IC. The source structure SS can be formed as a single layer or multiple layers. The source structure SS can include conductive materials such as polysilicon and insulating materials such as oxides.

[0084] Subsequently, a preliminary second insulating spacer SP2A can be formed in the source structure SS. The preliminary second insulating spacer SP2A can be formed in the region where the contact plug is to be formed. For example, the preliminary second insulating spacer SP2A can be formed in the second region R2. The preliminary second insulating spacer SP2A can include an insulating material such as an oxide.

[0085] Subsequently, a first sub-layer 410S1 can be formed on the source structure SS. For example, a first material layer 410A and a second material layer 410B can be alternately stacked to form the first sub-layer 410S1. Here, the first sub-layer 410S1 can be formed with a first height H1. The first material layer 410A may include an insulating material such as an oxide. The second material layer 410B may include a sacrificial material such as a nitride.

[0086] Subsequently, a first channel hole CH1 extending through the first sub-layer 410S1 can be formed. For example, a first channel hole CH1 extending through the first sub-layer 410S1 into the source structure SS can be formed. The first channel hole CH1 can be formed in the first region R1.

[0087] A first support hole SH1 extending through the first sub-laminated structure 410S1 can be formed. For example, a first support hole SH1 extending through the first sub-laminated structure 410S1 into the source structure SS can be formed. The first support hole SH1 can be formed in the first region R1 and the second region R2. For example, the first support hole SH1 can be formed near the boundary between the first region R1 and the second region R2. The first support hole SH1 can be formed when the first channel hole CH1 is formed. However, this disclosure is not limited thereto, and the first channel hole CH1 and the first support hole SH1 can be formed at different times.

[0088] Subsequently, a channel sacrificial layer 420S can be formed in the first channel hole CH1. A support sacrificial layer SHS can be formed in the first support hole SH1. The support sacrificial layer SHS can be formed while the channel sacrificial layer 420S is being formed. However, this disclosure is not limited thereto, and the channel sacrificial layer 420S and the support sacrificial layer SHS can be formed in separate processes. At least one of the channel sacrificial layer 420S or the support sacrificial layer SHS can comprise a metallic material. For example, at least one of the channel sacrificial layer 420S or the support sacrificial layer SHS can comprise at least one of titanium nitride or tungsten.

[0089] Reference Figures 5A to 5D A second sub-layer 410S2 can be formed on the first sub-layer 410S1. For example, the first material layer 410A and the second material layer 410B can be alternately laminated on the first sub-layer 410S1 to form the second sub-layer 410S2. Here, the second sub-layer 410S2 can be formed to have a second height H2 that is smaller than the first height H1.

[0090] Subsequently, a second channel hole CH2 extending through the second sub-layer 410S2 can be formed. For example, a second channel hole CH2 can be formed through the second sub-layer 410S2 to expose the channel sacrificial layer 420S.

[0091] Subsequently, the channel sacrificial layer 420S can be removed through the second channel hole CH2. Then, a channel structure 420 can be formed in the first channel hole CH1 and the second channel hole CH2. For example, a channel structure 420 including a first sub-channel structure 420S1 and a second sub-channel structure 420S2 can be formed. The first sub-channel structure 420S1 includes a first sub-channel layer 420A1, a first sub-memory layer 420B1, and a first sub-insulating core 420C1 formed in the first channel hole CH1, and the second sub-channel structure 420S2 includes a second sub-channel layer 420A2, a second sub-memory layer 420B2, and a second sub-insulating core 420C2 formed in the second channel hole CH2.

[0092] Reference Figures 6A to 6D The first support member 430 and the third support member 450 can be formed in the first region R1, and the second support member 440 and the fourth support member 460 can be formed in the second region R2.

[0093] The first support member 430 may be configured to be arranged sequentially in a first direction I. The first support member 430 may include a first main body portion 430A and / or a first protrusion 430B. For example, at least one of the first support members 430 may include the first main body portion 430A and the first protrusion 430B. Here, the first main body portion 430A may extend through the first sub-laminate 410S1 and the second sub-laminate 410S2, and the first protrusion 430B may protrude from the first main body portion 430A in the first sub-laminate 410S1. The first protrusion 430B may protrude toward the second region R2.

[0094] The second support member 440 may extend in a second direction II intersecting the first direction I. The second support member 440 may include a second main body portion 440A and a second protrusion 440B. Here, the number of second protrusions 440B may be multiple. The second main body portion 440A may extend through the first sub-laminate 410S1 and the second sub-laminate 410S2. The second main body portion 440A may include a first extension extending in the first direction I and a second extension extending in the second direction II, and the first extensions may be interconnected through the second extensions. The second protrusion 440B may protrude from the second main body portion 440A in the first sub-laminate 410S1. The second protrusion 440B may protrude toward the first region R1.

[0095] The third support member 450 may extend in the first direction I. At least one of the third support members 450 may include a third body portion 450A and / or a third protrusion 450B. Here, the third body portion 450A may extend through the first sub-laminate 410S1 and the second sub-laminate 410S2, and the third protrusion 450B may protrude in the first sub-laminate 410S1 toward the second region R2.

[0096] The fourth support member 460 may be arranged sequentially in the first direction I. At least one of the fourth support members 460 may include a fourth body portion 460A and / or a fourth protrusion 460B. Here, the fourth body portion 460A may extend through the first sub-laminate 410S1 and the second sub-laminate 410S2, and the fourth protrusion 460B may protrude in the first sub-laminate 410S1 toward the first region R1. The first support member 430, the second support member 440, the third support member 450, and the fourth support member 460 may include an insulating material such as an oxide.

[0097] Here, the first support member 430, the second support member 440, the third support member 450, and the fourth support member 460, including the protrusions 430B, 440B, 450B, and 460B, can be aligned with... Figures 3A to 3E The method is the same / similar. First, a second support hole can be formed to expose the sidewalls of the support sacrificial layer SHS formed in the first region R1 and the second region R2. Subsequently, the support sacrificial layer SHS can be removed through the second support hole. Subsequently, the first support member 430, the second support member 440, the third support member 450, and the fourth support member 460, including protrusions 430B, 440B, 450B, and 460B, can be formed in the first support hole SH1 and the second support hole SH2.

[0098] Reference Figures 7A to 7D A slit SL extending in the first direction I can be formed. A slit SL extending through the first sub-layer 410S1 and the second sub-layer 410S2 can be formed.

[0099] For reference, although not shown in the figure, a portion of the source structure SS can be removed to form a source opening, exposing the first sub-channel structure 420S1 through the slit SL. Subsequently, a portion of the first sub-memory layer 420B1 can be removed through the source opening, exposing the first sub-channel layer 420A1. Semiconductor material, etc., can then be formed in the source opening. Therefore, the first sub-channel layer 420A1 of the channel structure 420 can be connected to the source structure SS.

[0100] Subsequently, the second material layer 410B of the first sub-laminated stack 410S1 and the second material layer 410B of the second sub-laminated stack 410S2 can be removed through the slit SL to form the opening OP.

[0101] Subsequently, a third material layer 410C can be formed in the opening OP to form a gate structure 410G. Therefore, a gate structure 410G comprising alternating layers of a first material layer 410A and a third material layer 410C can be formed. However, this disclosure is not limited thereto, and when the second material layer 410B of the first sub-layer 410S1 and the second sub-layer 410S2 comprises a conductive material, the process of replacing the second material layer 410B with the third material layer 410C can be omitted. In this case, the first sub-layer 410S1 and the second sub-layer 410S2 can be used as the gate structure 410G. Here, the third material layer 410C can be a gate line serving as a conductive layer, such as a source select line, a word line, and a drain select line.

[0102] A portion of the first sub-layer 410S1 and the second sub-layer 410S2 may be retained without being replaced by the gate structure 410G. For example, the first sub-layer 410S1 and the second sub-layer 410S2 surrounded by the second support 440 may be retained without being replaced by the gate structure 410G.

[0103] Subsequently, a slit structure 470 can be formed in the slit SL. The slit structure 470 may include an insulating material, a conductive material, and / or a semiconductor material.

[0104] Reference Figures 8A to 8D A contact through-hole 480 and a contact plug 490 can be formed. For example, the contact through-hole can be formed in a first region R1 and a second region R2, and the contact plug 490 can be formed in the second region R2. The contact through-hole 480 can be formed between the first support member 430 and the third support member 450, between the third support members 450, and / or between the first support member 430 / the third support member 450 and the second support member 440. The contact plug 490 can be formed in the region surrounded by the second support member 440.

[0105] The contact via 480 can extend through the gate structure 410G and can be connected to the third material layer 410C. Here, the side surface of the contact via 480 can be surrounded by a first insulating spacer SP1. The first insulating spacer SP1 can include an insulating material such as oxide, and the contact via 480 can include a conductive material such as tungsten.

[0106] Contact plug 490 may extend through the first sub-laminate 410S1 and the second sub-laminate 410S2 and may be electrically connected to the peripheral circuit PC. For example, contact plug 490 may extend through the first sub-laminate 410S1 and the second sub-laminate 410S2 through the source structure SS and may be electrically connected to the peripheral circuit PC via the interconnect structure IC. In this case, the initial second insulating spacer SP2A may be separated into a second insulating spacer SP2. Contact plug 490 may comprise a conductive material such as tungsten.

[0107] According to the above manufacturing method, a first support member 430 and a third support member 450 can be formed, including a first protrusion 430B and a third protrusion 450B protruding from the first region R1 toward the second region R2, and a second support member 440 and a fourth support member 460 can be formed, including a second protrusion 440B and a fourth protrusion 460B protruding from the second region R2 toward the first region R1.

[0108] In this embodiment, compared to the case where the first protrusion 430B, the second protrusion 440B, the third protrusion 450B, and the fourth protrusion 460B are not formed, the thickness of the lower part of the first support member 430, the second support member 440, the third support member 450, and the fourth support member 460 can be increased, and the distance between the first support member 430 / the third support member 450 and the second support member 440 / the fourth support member 460 can become relatively shorter, thereby improving the supporting force of the first support member 430, the second support member 440, the third support member 450, and the fourth support member 460.

[0109] Although embodiments according to the technical spirit of this disclosure have been described with reference to the accompanying drawings, this is only for describing embodiments based on the concept of this disclosure, and this disclosure is not limited to the described embodiments. Within the scope of the technical spirit of this disclosure as described in the claims, those skilled in the art will be able to make various substitutions, modifications, and changes to the embodiments, and these also fall within the scope of this disclosure.

[0110] Cross-references to related applications

[0111] This application claims priority to Korean Patent Application No. 10-2024-0154631, filed on November 4, 2024, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A substrate, the substrate comprising a first region and a second region; A gate structure, wherein the gate structure is positioned above the substrate and extends from the first region to the second region; A laminate positioned above the substrate in the second region; A first support member extends through the gate structure in the first region and is arranged sequentially in a first direction; as well as A second support member extends in the second region between the gate structure and the stack along a second direction intersecting the first direction. Wherein, at least one of the first support members includes a first protrusion projecting toward the second region, and The second support member includes a second protrusion that extends toward the first region.

2. The semiconductor device according to claim 1, wherein, The at least one first support member in the first support member includes: A first main body portion, the first main body portion extending through the gate structure; and The first protrusion protrudes from the first body portion within the gate structure.

3. The semiconductor device according to claim 1, wherein, The second support member includes: A second main body portion extends between the gate structure and the stack; and The second protrusion protrudes from the second body portion within the gate structure.

4. The semiconductor device according to claim 1, further comprising: A third support member extends through the gate structure in the first region and extends in the first direction; as well as A fourth support member extends through the gate structure in the second region and is arranged sequentially in the first direction.

5. The semiconductor device according to claim 4, in, At least one of the third supports includes a third body portion extending through the gate structure and a third protrusion protruding from the third body portion toward the second region within the gate structure, and At least one of the fourth supports includes a fourth body portion extending through the gate structure and a fourth protrusion protruding from the fourth body portion toward the first region within the gate structure.

6. The semiconductor device according to claim 1, wherein, The gate structure includes: The first part, the first part having a first height; and The second part is positioned on the first part and has a second height that is less than the first height.

7. The semiconductor device according to claim 6, further comprising: The channel structures each include a first sub-channel structure extending through the first portion and a second sub-channel structure extending through the second portion and connected to the first sub-channel structure.

8. The semiconductor device according to claim 7, wherein, At least one of the first protrusion or the second protrusion is located at a level corresponding to the first subchannel structure.

9. The semiconductor device according to claim 1, in, The gate structure includes alternately stacked insulating and conductive layers, and The semiconductor device further includes contact vias extending through the gate structure to be connected to the conductive layer, and each contact via is located in the first region or the second region.

10. The semiconductor device of claim 1, further comprising: Peripheral circuitry, wherein the peripheral circuitry is positioned above the substrate; as well as A contact plug extends through the stack to be electrically connected to the peripheral circuitry and is positioned in the second region.

11. A semiconductor device, the semiconductor device comprising: A gate structure, the gate structure comprising a first portion and a second portion positioned on the first portion; A stack, the stack being positioned at a level corresponding to the gate structure; A first support member extends through the gate structure and is arranged sequentially in a first direction; as well as A second support member extends between the gate structure and the stack along a second direction intersecting the first direction. Wherein, at least one of the first support members includes a first protrusion projecting toward the second support member, and the second support member includes a second protrusion projecting toward the first support member, and Wherein, at least one of the first protrusion or the second protrusion is located at a level corresponding to the first portion.

12. The semiconductor device of claim 11, further comprising: The substrate includes a first region and a second region. The gate structure is positioned above the substrate and extends from the first region to the second region. The laminate is positioned above the substrate within the second region.

13. The semiconductor device according to claim 12, in, The first protrusion protrudes toward the second region, and The second protrusion protrudes toward the first region.

14. The semiconductor device according to claim 12, in, The gate structure includes alternately stacked insulating and conductive layers, and The semiconductor device further includes contact vias extending through the gate structure to be connected to the conductive layer, and each contact via is located in the first region or the second region.

15. The semiconductor device of claim 12, further comprising: Peripheral circuitry, wherein the peripheral circuitry is positioned above the substrate; as well as A contact plug extends through the stack to be electrically connected to the peripheral circuitry and is positioned in the second region.

16. The semiconductor device according to claim 11, wherein, The at least one first support member in the first support member includes: A first main body portion, the first main body portion extending through the gate structure; and The first protrusion protrudes from the first body portion within the gate structure.

17. The semiconductor device according to claim 11, wherein, The second support member includes: A second main body portion extends between the gate structure and the stack; and The second protrusion protrudes from the second body portion within the gate structure.

18. The semiconductor device of claim 12, further comprising: A third support member extends through the gate structure in the first region and extends in the first direction; as well as A fourth support member extends through the gate structure in the second region and is arranged sequentially in the first direction.

19. The semiconductor device according to claim 18, in, At least one of the third supports includes a third body portion extending through the gate structure and a third protrusion protruding from the third body portion toward the fourth support within the gate structure, and At least one of the fourth supports includes a fourth body portion extending through the gate structure and a fourth protrusion protruding from the fourth body portion toward the third support within the gate structure.

20. The semiconductor device according to claim 11, in, The first part has a first height, and The second part has a second height that is less than the first height.

21. The semiconductor device of claim 11, further comprising: The channel structures each include a first sub-channel structure extending through the first portion and a second sub-channel structure extending through the second portion to connect to the first sub-channel structure.

22. The semiconductor device according to claim 21, wherein, At least one of the first protrusion or the second protrusion is located at a level corresponding to the first subchannel structure.

23. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming the first sub-layer; Forming a first support hole extending through the first sub-layer; A sacrificial support layer is formed within the first support hole; A second sub-layer is formed on the first sub-layer; A second support hole is formed that extends through the second sub-layer and the first sub-layer and exposes the sidewall of the support sacrificial layer; The support sacrificial layer is removed through the second support hole; as well as A support member is formed in the first support hole and the second support hole.

24. The method according to claim 23, further comprising the following step: Forming a first channel hole extending through the first sub-layer; A channel sacrificial layer is formed in the first channel hole; Forming a second channel hole through the second sub-layer to expose the channel sacrificial layer; Remove the channel sacrificial layer through the second channel aperture; and A channel structure is formed in the first channel hole and the second channel hole.

25. The method according to claim 24, in, The first support hole is formed during a first time interval, and the first channel hole is formed during a second time interval. The first time interval and the second time interval at least partially overlap each other.

26. The method according to claim 24, in, The support sacrificial layer is formed during a first time interval, and the channel sacrificial layer is formed during a second time interval. The first time interval and the second time interval at least partially overlap each other.

27. The method according to claim 23, wherein, The supporting sacrificial layer comprises metal.

28. The method according to claim 27, wherein, The supporting sacrificial layer includes at least one of titanium nitride or tungsten.

29. The method according to claim 23, wherein, The support component comprises oxide.

30. The method according to claim 23, in, The first sub-layer has a first height, and The second sub-layer has a second height that is less than the first height.

31. The method according to claim 23, wherein, The step of forming the second support hole uses a plasma process.

32. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming the first sub-layer; Forming a first channel hole extending through the first sub-layer; Forming a first support hole extending through the first sub-layer; A channel sacrificial layer is formed in the first channel hole; A support sacrificial layer is formed in the first support hole; A second sub-layer is formed on the first sub-layer; A second support hole is formed that extends through the second sub-layer and the first sub-layer and exposes the sidewall of the support sacrificial layer; The support sacrificial layer is removed through the second support hole; as well as A support member including a protrusion is formed in the first support hole and the second support hole.

33. The method according to claim 32, wherein, The first support hole is formed during a first time interval, and the first channel hole is formed during a second time interval. The first time interval and the second time interval at least partially overlap each other.

34. The method according to claim 32, wherein, The support sacrificial layer is formed during a first time interval, and the channel sacrificial layer is formed during a second time interval. The first time interval and the second time interval at least partially overlap each other.

35. The method according to claim 32, further comprising the following steps: Forming a second channel hole through the second sub-layer to expose the channel sacrificial layer; The channel sacrificial layer is removed through the second channel hole; as well as A channel structure is formed in the first channel hole and the second channel hole.

36. The method according to claim 32, wherein, At least one of the channel sacrificial layer or the support sacrificial layer comprises metal.

37. The method of claim 36, wherein, At least one of the channel sacrificial layer or the support sacrificial layer includes at least one of titanium nitride or tungsten.

38. The method according to claim 32, wherein, The support component comprises oxide.

39. The method according to claim 32, in, The first sub-layer has a first height, and The second sub-layer has a second height that is less than the first height.

40. The method according to claim 32, wherein, The step of forming the second support hole uses a plasma process.

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