Memory device and method of manufacturing the same

Abstract

The invention discloses a memory device and a method of manufacturing the same. The memory device includes a stack in which conductive layers and interlayer insulating layers are alternately stacked in a stacking direction. The memory device further includes a chip protector surrounding a chip region of the stack, the chip protector penetrating the stack in a stacking direction. The memory device also includes a test electrode electrically coupled to the chip protector. The test electrodes are spaced apart from each other, and at least a portion of the chip region is disposed between the test electrodes.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to memory devices and methods of manufacturing such memory devices, and more specifically, to memory devices comprising memory blocks having a three-dimensional (3D) structure and methods of manufacturing such memory devices. Background Technology

[0002] Semiconductor integration processes allow multiple chip regions to be formed on a semiconductor substrate. These chip regions can be distinguished from each other using scribe lines as boundaries. The chip regions are then separated by a dicing process, thus enabling the fabrication of multiple semiconductor chips.

[0003] Each semiconductor chip may include a non-volatile memory device that retains stored data even when the power supply is interrupted. Based on the structure in which the memory cells are arranged, non-volatile memory devices can be classified as two-dimensional (2D) or three-dimensional (3D) structures. The memory cells of a 2D non-volatile memory device can be arranged in a single layer on a substrate, while the memory cells of a 3D non-volatile memory device can be vertically stacked on the substrate. Because the integration density of 3D non-volatile memory devices is higher than that of 2D non-volatile memory devices, the number of electronic devices using 3D non-volatile memory devices has recently increased. Summary of the Invention

[0004] According to embodiments of this disclosure, a memory device may include: a laminate, wherein conductive layers and interlayer insulating layers are alternately laminated in a lamination direction; a chip protector surrounding a chip region of the laminate, the chip protector penetrating the laminate in the lamination direction; and test electrodes electrically connected to the chip protector. The test electrodes are spaced apart from each other, and at least a portion of the chip region is disposed between the test electrodes.

[0005] According to embodiments of the present disclosure, a method of manufacturing a memory device may include the following steps: forming a laminate in which sacrificial layers and interlayer insulating layers are alternately stacked; forming a first set of openings and a second set of openings through the laminate; forming cell plugs filling the first set of openings; forming a vertical structure filling the second set of openings; replacing the sacrificial layers with conductive layers; forming a chip protector, wherein the chip protector includes the vertical structure; and forming test electrodes electrically connected to the chip protector and a test circuit, wherein the test circuit is configured to determine whether a defect has occurred in the laminate using an electrical signal input to the chip protector through the test electrodes. Attached Figure Description

[0006] Figure 1 A diagram illustrating the structure of a memory device according to an embodiment of the present disclosure is shown.

[0007] Figure 2A and Figure 2B A diagram is shown to illustrate a memory device including a chip protector according to the present disclosure.

[0008] Figure 3A , Figure 3B and Figure 3C A diagram illustrating the arrangement of test electrodes and the planar shape of the chip protector according to various embodiments of the present disclosure is shown.

[0009] Figure 4A and Figure 4B A diagram is shown illustrating a memory device including a chip protector and a detection circuit according to the present disclosure.

[0010] Figure 5A and Figure 5B A diagram is shown to illustrate a memory device including a chip protector and an array of memory cells according to the present disclosure.

[0011] Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E A diagram is shown illustrating a method for manufacturing a memory device including a chip protector according to the present disclosure.

[0012] Figure 7 This is a diagram illustrating a memory card system using a memory device according to the present disclosure.

[0013] Figure 8 This is a diagram illustrating a solid-state drive (SSD) system that utilizes a memory device according to the present disclosure. Detailed Implementation

[0014] The specific structural or functional descriptions of the embodiments of this disclosure provided in this specification or application are offered as examples of embodiments describing the concept of this disclosure. Embodiments of the concept of this disclosure may be practiced in various forms and should not be construed as limited to those described in this specification or application.

[0015] Various embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, which illustrate embodiments of the present disclosure so that those skilled in the art to which this disclosure pertain can practice the technical spirit of the present disclosure.

[0016] Some embodiments of this disclosure relate to a memory device and a method of manufacturing the memory device, which can enhance the ability to identify whether a defect has occurred in a region adjacent to a chip protector.

[0017] Figure 1A diagram illustrating the structure of a memory device according to an embodiment of the present disclosure is shown.

[0018] Memory devices may include a structure STR. For example, the structure STR may include a substrate (e.g., a silicon wafer, a SiGe wafer, or an SOI wafer) and a material pattern formed on the substrate.

[0019] Reference Figure 1 The structure STR can include a chip region CHA, a protection region GDA, and a scribing region SLA. For example, the structure STR can include a chip region CHA, a protection region GDA that surrounds the chip region CHA, and a scribing region SLA that surrounds the protection region GDA.

[0020] A chip region CHA can be a region in which a semiconductor chip is formed. Chip regions CHA can be arranged along the X and Y directions. Semiconductor chips can be formed separately through semiconductor integration processes performed on the chip regions CHA. For example, when each semiconductor chip formed in a chip region CHA includes a memory cell array, the corresponding semiconductor chip can be a memory device. Semiconductor chips formed in multiple chip regions CHA within a structure STR can be substantially identical. After the semiconductor integration process is completed on the substrate, the structure STR is separated into corresponding chip regions CHA, and therefore the chip regions CHA can be separated into the form of semiconductor chips.

[0021] Each protective region (GDA) can be adjacent to a chip region (CHA). Each protective region (GDA) can surround a chip region (CHA). For example, a protective region (GDA) can be formed at a certain distance from the boundary surface of the corresponding chip region (CHA). When the plane of each chip region (CHA) has a rectangular shape, the plane of the corresponding protective region (GDA) can also have a rectangular shape, with a hollow center to surround the periphery of the chip region (CHA). The side surfaces of the chip region (CHA) and the inner surfaces of the corresponding protective region (GDA) can be in contact with each other.

[0022] Within the protected area GDA, a chip protector can be formed. The chip protector prevents moisture or oxygen from penetrating from the outside of the chip area CHA into the corresponding chip area CHA. Furthermore, the chip protector can reduce inter-die interference during the packaging process performed after the chip area CHA has been separated into the corresponding semiconductor chips. See below. Figure 2A and Figures 3A to 3C Describe in detail the shape of the chip protector formed in the GDA protection area.

[0023] The scribing trace area (SLA) can be located outside the chip region (CHA) and the protective region (GDA). For example, the scribing trace area (SLA) can be positioned between the chip regions (CHA). Furthermore, the scribing trace area (SLA) can surround the protective region (GDA). After the semiconductor integration process is completed, the scribing trace area (SLA) can be cut during the dicing process to separate the semiconductor chips. The structure STR is cut along the scribing trace area (SLA), thereby allowing the chip region (CHA) to be separated individually. Each separated semiconductor chip can include the chip region (CHA) and a corresponding protective region (GDA) surrounding the chip region (CHA). The process for cutting the structure STR can employ methods such as sawing using blades, laser processing using lasers, or stealth scribing. In this embodiment, electrical test patterns, process monitoring patterns, and alignment keys can be arranged within the scribing trace area (SLA).

[0024] Although for the sake of ease of description Figure 1 Six chip regions CHA are illustrated, but the scope of this disclosure is not limited to this structure. For example, the structure STR may include various numbers (e.g., seven or more) of chip regions CHA. Furthermore, although the chip regions CHA, guard regions GDA, and scribing regions SLA are described separately in this disclosure, this is for ease of description, and the chip regions CHA, guard regions GDA, and scribing regions SLA may be continuously connected to each other without being physically separated. For example, the respective boundary surfaces of the chip regions CHA, guard regions GDA, and scribing regions SLA may not be clearly visible. Moreover, the positions of the chip regions CHA, guard regions GDA, and scribing regions SLA can be arbitrarily determined within the structure STR. In this disclosure, the chip regions CHA, guard regions GDA, and scribing regions SLA may refer to a finite space within the horizontal direction of the structure STR, rather than referring to regions in the substrate.

[0025] Figure 2A and Figure 2B A diagram is shown to illustrate a memory device including a chip protector according to the present disclosure. Figure 2A A plan view is shown to describe the layout of the memory device. Figure 2B It shows along Figure 2A A cross-sectional view taken from line A-A'.

[0026] Reference Figure 2A The chip region CHA can be surrounded by a scribing area SLA and a guard area GDA. Although not illustrated in the figure, the chip region CHA may include a central region containing the center of the chip region CHA. The memory cell array can be arranged in the central region of the chip region CHA. See below. Figure 5A and Figure 5B Describe the memory cell array in detail.

[0027] Within the protection region GDA, a chip protector GD can be formed. The chip protector GD can surround the chip region CHA. The chip protector GD can extend along the boundary of the chip region CHA. For example, the chip region CHA can represent a rectangular plane, and the chip protector GD can have a shape extending along the four side surfaces of the chip region CHA. The chip protector GD can directly contact the interface of the chip region CHA or can be spaced apart from the surface of the chip region CHA. The scribing area SLA can be outside the chip protector GD. Figure 2A The planar shapes of each of the chip region CHA and chip protector GD shown are merely examples and do not limit the scope of this disclosure. See below for further details. Figure 3C Examples describing the planar shape of each of the chip region CHA and the chip protection component GD.

[0028] Test electrodes TE can be coupled to the chip protector GD. The test electrodes TE can be spaced apart from each other, and at least a portion of the chip region CHA can be disposed between the test electrodes TE. The test electrodes TE can be formed to be spaced apart from each other, and a central region including the center of the chip region CHA can be disposed between the test electrodes TE. For example, the test electrodes TE can be arranged symmetrically with respect to the central region of the chip region CHA. For example, one test electrode TE can be formed to contact the chip protector GD from the chip region CHA in the positive X direction, and the other test electrode TE can be formed to contact the chip protector GD from the chip region CHA in the negative X direction. Further details will be provided later. Figure 3A and Figure 3B Describe in detail the various arrangements of the test electrode TE.

[0029] The test electrode TE can extend from the chip protector GD into the chip region CHA. The test electrode TE can also extend from the protector region GDA into the chip region CHA. A portion of the test electrode TE can be in the chip region CHA, and the remaining portion can be in the protector region GDA.

[0030] Reference Figure 2B The memory device may include a stack STK. The stack STK may include alternating layers of conductive layers CD and interlayer insulating layers IL. The conductive layers CD and interlayer insulating layers IL may be alternately stacked in the Z direction. The conductive layers CD may serve as select lines or word lines for the memory device. Each conductive layer CD may contain at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), or polysilicon (Poly-Si). The interlayer insulating layers IL may insulate the conductive layers CD from each other. For example, each interlayer insulating layer IL may include an oxide layer (e.g., a silicon oxide layer).

[0031] The stack-up STK can extend from the chip region CHA to the guard region GDA. For example, the chip region CHA may include a portion of the stack-up STK. Furthermore, the guard region GDA may include another portion of the stack-up STK. Although not illustrated in the figure, the stack-up STK can further extend from the chip region CHA and the guard region GDA to the scribing region SLA.

[0032] The substrate SUB can be disposed beneath the stack-up STK. The substrate SUB can extend from the chip region CHA to the guard region GDA. The substrate SUB can extend in both the X and Y directions. For example, the substrate SUB can be a silicon wafer, a SiGe wafer, or an SOI wafer.

[0033] The substrate SUB may include an active region PA. The active region PA may be a region in which impurities are implanted into the substrate SUB. Impurities may include elements from Group 13 or Group 15 of the periodic table. For example, impurities may be boron (B) or indium (In) from Group 13, or phosphorus (P) from Group 15.

[0034] The lower insulating layer (LIL) may be located between the laminate (STK) and the substrate (SUB). The lower insulating layer (LIL) may also be located on the substrate (SUB). The lower insulating layer (LIL) may be formed as a single layer or a multilayer structure. The lower insulating layer (LIL) may contain an insulating material (e.g., oxide).

[0035] A semiconductor layer SL and an insulating pattern IP can be disposed between the stack STK and the lower insulating layer LIL. The insulating pattern IP can penetrate the semiconductor layer SL. The semiconductor layer SL and the insulating pattern IP can be at the same height. The semiconductor layer SL can be in at least a portion of the chip region CHA. The insulating pattern IP can be in the guard region GDA. Although not illustrated, the insulating pattern IP can also be formed in the chip region CHA. The semiconductor layer SL can contain undoped silicon or doped silicon. The insulating pattern IP can contain oxide material.

[0036] The upper insulating layer UIL can be disposed on the laminate STK. The upper insulating layer UIL can be formed as a single layer or a multilayer structure. The upper insulating layer UIL can contain an insulating material (e.g., oxide).

[0037] The chip protector GD can be located within the protected region GDA. The chip protector GD can extend in the Z direction. The chip protector GD can penetrate the laminate STK. The chip protector GD can extend in the Z direction within the laminate STK. The chip protector GD can have a shape extending in the Z direction to prevent moisture or oxygen from penetrating from the outside of the chip region CHA into the chip region CHA.

[0038] The chip protector GD can extend in the horizontal direction. For example, the portion of the chip protector GD located in the X direction of the chip region CHA can extend in the Y direction. Furthermore, the portion of the chip protector GD located in the Y direction of the chip region CHA can extend in the X direction. The chip protector GD can extend along the direction in which the chip region CHA extends.

[0039] The chip protection component GD may include a vertical structure VS that penetrates the laminate STK. The vertical structure VS may penetrate the laminate STK. The vertical structure VS may extend along the Z-direction within the laminate STK. The vertical structure VS may extend into the insulating pattern IP. For example, the vertical structure VS may penetrate the insulating pattern IP. The vertical structure VS may be formed of a multilayer structure. For example, the vertical structure VS may include conductive pillars containing conductive material and insulating spacers surrounding the conductive pillars.

[0040] In this implementation, the vertical structure VS may include multiple pillar structures. For example, the vertical structure VS may include multiple pillar structures arranged in the X or Y direction. The pillar structures may be arranged to surround the periphery of the chip region CHA. The pillar structures may be arranged parallel to the boundary of the chip region CHA. Each pillar structure may extend in the Z direction.

[0041] In implementations, the vertical structure VS can have a shape extending in the horizontal direction. For example, the vertical structure VS can extend along the X or Y direction. The vertical structure VS can have the shape of a slit or plate extending along the interface of the chip region CHA. In addition, the vertical structure VS included in the chip protector GD can be formed in various shapes that penetrate the laminate STK.

[0042] The chip protector GD may include at least one top line and at least one top plug located on the laminate STK. For example, the chip protector GD may include a first top plug UP1, a first top line UL1, a second top plug UP2, and a second top line UL2 located on the laminate STK. The first top plug UP1, the first top line UL1, the second top plug UP2, and the second top line UL2 may be surrounded by an upper insulating layer UIL. The first top plug UP1 may contact the upper surface of the vertical structure VS. Each of the first top plug UP1, the first top line UL1, the second top plug UP2, and the second top line UL2 may contain a conductive material.

[0043] Furthermore, the chip protector GD may include at least one lower line and at least one lower plug located below the stack STK. For example, the chip protector GD may include a first lower plug LP1, a first lower line LL1, a second lower plug LP2, a second lower line LL2, a third lower plug LP3, a third lower line LL3, and a fourth lower plug LP4 located below the stack STK. The first lower plug LP1, the first lower line LL1, the second lower plug LP2, the second lower line LL2, the third lower plug LP3, the third lower line LL3, and the fourth lower plug LP4 may be surrounded by a lower insulating layer LIL. The fourth lower plug LP4 may contact the lower surface of the vertical structure VS. Each of the first lower plug LP1, the first lower line LL1, the second lower plug LP2, the second lower line LL2, the third lower plug LP3, the third lower line LL3, and the fourth lower plug LP4 may include a conductive material.

[0044] The chip protection component GD may include an active region PA in the substrate SUB. The first lower plug LP1 can be directly connected to the active region PA.

[0045] The chip protector GD may have a shape extending from the substrate SUB through the laminate STK into the upper insulating layer UIL. In an embodiment, the chip protector GD can reduce the penetration of moisture and / or oxygen from the outside of the chip protector GD into the chip region CHA.

[0046] Figure 2B The number, arrangement, and connection relationships of the upper line, upper plug, lower line, and lower plug shown can vary in different embodiments. In the example, the chip protector GD may include components with a higher density than... Figure 2B The lower lines show fewer or more layers. In the example, the first lower plug LP1 to the fourth lower plug LP4 can be as follows: Figure 2B The alignment shown is in the Z direction, or may be different. Figure 2B The ones shown do not overlap in the Z direction. In the example, when along... Figure 2A When comparing the cross section taken by line A-A' with other cross sections, the number of layers, arrangement positions, and connection relationships of the upper line, upper plug, lower line, and lower plug can be different from each other.

[0047] Test electrodes TE can be electrically connected to the chip protector GD. Each of the test electrodes TE can be connected to the chip protector GD via a third upper plug UP3. Test electrodes TE can have a shape extending in the X direction. Test electrodes TE can be located at a height higher than the chip protector GD. Test electrodes TE can not overlap with the chip protector GD in the Z direction. Each third upper plug UP3 can connect the test electrode TE to the corresponding second upper line UL2.

[0048] and Figure 2B Unlike the examples shown, the test electrode TE can be formed at the same height as a portion of the chip protector GD. For example, the test electrode TE can be formed to directly contact the second upper line UL2. Alternatively, the test electrode TE can be above the chip protector GD in the Z direction. The test electrode TE can be formed to overlap with the chip protector GD in the Z direction. As long as the test electrode TE is connected to the chip protector GD, the positional relationship between the test electrode TE and the chip protector GD does not limit the scope of this disclosure.

[0049] The test electrode TE can extend from the chip protector GD into the chip region CHA. A portion of the corresponding test electrode TE can be in the protector GD, and the remaining portion can be in the chip region CHA. However, compared to... Figure 2B Unlike the example in the example, the test electrode TE can be in the protection region GDA without extending into the chip region CHA.

[0050] During the manufacturing or testing of a semiconductor chip according to the present disclosure, a test electrode TE can be used to identify whether a defect has occurred in the stack-up STK. In embodiments, the memory device according to the present disclosure may further include a test circuit connected to the test electrode TE. The test circuit can input an electrical signal to a chip protector GD via the test electrode TE. Furthermore, the test circuit can measure the resistance of the chip protector GD via the test electrode TE. For example, the test circuit can obtain resistance gradient information via the test electrode TE. The test circuit can use the resistance gradient information to identify whether a defect has occurred in the stack-up STK. For example, when a defect such as a crack occurs in a portion of the stack-up STK or in a portion of the chip protector GD penetrating the stack-up STK, or when a not-open defect occurs where a structure such as the chip protector GD cannot completely penetrate the stack-up STK, the trend of the resistance gradient information differs from the trend in cases where no defect has occurred in the stack-up STK. Therefore, when the resistance gradient information exceeds a specified range, the test circuit can detect the occurrence of a defect in the stack-up STK.

[0051] In some embodiments, a separate test apparatus can be connected to test the memory device according to the present disclosure. The test apparatus can be electrically connected to a test electrode TE. The test apparatus can use the test electrode TE as a resistance measurement node. The test apparatus can measure the resistance of the chip protector GD through the test electrode TE. For example, the test apparatus can obtain resistance gradient information through the test electrode TE. The test apparatus can use the resistance gradient information to identify whether a defect has occurred in the stack-up STK. Therefore, when the resistance gradient information falls outside a specified range, the test apparatus can detect the occurrence of a defect in the stack-up STK.

[0052] The test electrodes TE can be spaced apart from each other, and the chip region CHA can be positioned between the test electrodes TE. For example, the test electrodes TE can be positioned on the left and right sides of the chip region CHA, respectively. The test electrodes TE can be spaced apart as far as possible to allow measurement of the resistance of the chip protection device GD over a wider range. See below. Figure 3A and Figure 3B Additional implementation methods related to the arrangement of the test electrode TE are described.

[0053] Figures 3A to 3C A diagram illustrating the arrangement of test electrodes and the planar shape of the chip protector according to various embodiments of the present disclosure is shown.

[0054] Reference Figure 3A and Figure 3B The test electrodes TE can be spaced apart from each other, and at least a portion of the chip region CHA can be located between the test electrodes TE. For example, the test electrodes TE can be arranged symmetrically with respect to the central region of the chip region CHA. The central region of the chip region CHA can refer to any region including the central point of the chip region CHA.

[0055] Reference Figure 3A One test electrode TE can be located in the region of the chip protection device GD's slave chip region CHA in the Y direction, and another test electrode TE can be located in the region of the chip protection device GD's slave chip region CHA in the negative Y direction. The test electrode TE can have a shape that extends in the Y direction.

[0056] Reference Figure 3BOne test electrode TE can be positioned close to a first vertex of the chip protector GD, and another test electrode TE can be positioned close to a second vertex of the chip protector GD located in the opposite direction to the first vertex. The first vertex can be one of the four vertices of the chip protector GD located in the X and Y directions, and the second vertex can be one of the four vertices of the chip protector GD located in the negative X and negative Y directions. Furthermore, the fact that the first and second vertices are opposite to each other can mean that the vertices are located in opposite directions relative to the central region of the chip region CHA. Although in Figure 3B In this example, the test electrode TE is illustrated as being arranged near the vertex of the chip protector GD, but the test electrode TE can also be arranged to contact the vertices individually. Furthermore, although in Figure 3B Each test electrode TE is illustrated as having a shape extending in the Y direction, but the test electrode TE can extend in various directions (such as by extending toward the central region of the chip region CHA).

[0057] Figure 2A , Figure 3A and Figure 3B The arrangement of the test electrodes TE shown may correspond to some examples. Additionally, the test electrodes TE may be arranged in different directions relative to at least a portion of the chip region CHA. In this disclosure, different directions may include directions opposite to each other or directions intersecting each other.

[0058] exist Figure 2A , Figure 3A and Figure 3B Although the illustration assumes that the plane of the chip region CHA has a rectangular shape, the planar shape of the chip region CHA is not limited to rectangles. For example, as shown... Figure 3C As shown, the plane of the chip region CHA can have an octagonal shape. When the chip region CHA has an octagonal plane, the chip protector GD extends along the side surface of the chip region CHA, and therefore the chip protector GD can have an octagonal plane with a hollow center. Even if the plane of each of the chip region CHA and the chip protector GD changes from a rectangular shape to an octagonal shape, the test electrode TE can be arranged in a different direction relative to at least a portion of the chip region CHA. For example, as Figure 3C As shown, the test electrode TE can be formed to contact two opposite corners of the eight corners of the chip protector GD.

[0059] Figure 4A and Figure 4B A diagram is shown illustrating a memory device including a chip protector and a detection circuit according to the present disclosure. Figure 4A A plan view is shown to describe the layout of the memory device. Figure 4BIt shows along Figure 4A The cross-sectional view taken by line A-A'. Figure 4A and Figure 4B Among the components shown, details about... are omitted or briefly described. Figure 2A and Figure 2B as well as Figures 3A to 3C The description of the component.

[0060] Reference Figure 4A A chip protector GD and a detection circuit DC can be formed in a protection region GDA. The detection circuit DC can be disposed between the chip region CHA and the chip protector GD. At least a portion of the detection circuit DC can surround the chip region CHA. At least a portion of the detection circuit DC can extend along the side surface of the chip region CHA. The detection circuit DC can extend into the chip region CHA. A portion of the detection circuit DC can be in the protection region GDA, and another portion of the detection circuit DC can be in the chip region CHA.

[0061] Reference Figure 4B The detection circuit DC may include at least one upper detection line and at least one upper detection plug located above the laminate STK. For example, the detection circuit DC may include a first upper detection line DUL1, an upper detection plug DUP, and a second upper detection line DUL2 located above the laminate STK. The first upper detection line DUL1, the upper detection plug DUP, and the second upper detection line DUL2 may be surrounded by an upper insulating layer UIL. The first upper detection line DUL1 may be at the same height as the first upper line UL1. The upper detection plug DUP may be at the same height as the second upper plug UP2. The second upper detection line DUL2 may be at the same height as the second upper line UL2. Each of the first upper detection line DUL1, the upper detection plug DUP, and the second upper detection line DUL2 may contain a conductive material.

[0062] Furthermore, the detection circuit DC may include at least one lower detection line and at least one lower detection plug located below the stacked structure STK. For example, the detection circuit DC may include a first lower detection line DLL1, a first lower detection plug DLP1, a second lower detection line DLL2, a second lower detection plug DLP2, and a third lower detection line DLL3 located below the stacked structure STK. The first lower detection line DLL1, the first lower detection plug DLP1, the second lower detection line DLL2, the second lower detection plug DLP2, and the third lower detection line DLL3 may be surrounded by a lower insulating layer LIL. The first lower detection line DLL1 may be at the same height as the first lower line LL1. The first lower detection plug DLP1 may be at the same height as the second lower plug LP2. The second lower detection line DLL2 may be at the same height as the second lower line LL2. The second lower detection plug DLP2 may be at the same height as the third lower plug LP3. The third lower detection line DLL3 may be at the same height as the third lower line LL3. Each of the first lower detection line DLL1, the first lower detection plug DLP1, the second lower detection line DLL2, the second lower detection plug DLP2, and the third lower detection line DLL3 may contain conductive material.

[0063] However, Figure 4B The number, arrangement, and connection relationships of the upper detection line, upper detection plug, lower detection line, and lower detection plug shown indicate one embodiment and do not limit the scope of this disclosure. In the example, the detection circuit DC may include a higher... Figure 4B The diagram shows a lower detection line with fewer or more layers. In the example, the first lower detection plug DLP1 and the second lower detection plug DLP2 can be as follows: Figure 4B As shown, align along the Z direction, or it can be with Figure 4B The examples in the example do not overlap each other along the Z direction. In the example, when along... Figure 4A When comparing the cross section taken by line A-A' with other cross sections, the number of layers, arrangement positions and connection relationships of the upper detection line, upper detection plug, lower detection line and lower detection plug can be different from each other.

[0064] The detection circuit DC can be used to detect whether a defect has occurred in the chip protector GD. The detection circuit DC can be configured to be adjacent to the chip protector GD. When a defect such as a crack occurs in the chip protector GD, it can be detected by the detection circuit DC.

[0065] The detection circuit DC may not penetrate the stack-up STK. The detection circuit DC can be located on or below the stack-up STK without extending into it. For example, the first upper detection line DUL1, the upper detection plug DUP, and the second upper detection line DUL2 (hereinafter referred to as the "upper detection circuit") can be electrically connected to each other to surround the periphery of the chip region CHA. Furthermore, the first lower detection line DLL1, the first lower detection plug DLP1, the second lower detection line DLL2, the second lower detection plug DLP2, and the third lower detection line DLL3 (hereinafter referred to as the "lower detection circuit") can be electrically connected to each other to surround the periphery of the chip region CHA. However, the upper detection circuit and the lower detection circuit can be electrically insulated from each other.

[0066] When the detection circuit DC does not penetrate the stacked structure STK, it is difficult to identify whether a defect has occurred in the chip protector GD at the height corresponding to the stacked structure STK. Therefore, when a defect occurs in a portion of the chip protector GD at the height corresponding to the stacked structure STK, the defect may not be detected by the detection circuit DC. However, according to this disclosure, in addition to the detection circuit DC, a test electrode TE is formed connected to the chip protector GD. As a result, even if a defect such as a crack or a non-open defect occurs at the height corresponding to the stacked structure STK, the defect such as a crack or a non-open defect can be detected.

[0067] Figure 5A and Figure 5B A diagram is shown to illustrate a memory device including a chip protector and an array of memory cells according to the present disclosure. Figure 5A A plan view is shown to describe the layout of the memory device. Figure 5B It shows along Figure 5A The cross-sectional view taken by line A-A'. Figure 5A and Figure 5B Among the components shown, details about... are omitted or briefly described. Figure 2A and Figure 2B as well as Figures 3A to 3C The description of the component.

[0068] Reference Figure 5A A memory cell array can be formed within a chip region CHA. For example, the memory cell array can be formed in the central region of the chip region CHA, which includes the center of the chip region CHA. The memory cell array can include cell plugs CPL and contacts CT. Test electrodes TE can be located in different directions relative to the memory cell array. For example, the test electrodes TE can be arranged in opposite directions (e.g., on the left and right sides) relative to at least one cell plug CPL.

[0069] Reference Figure 5BCell plugs (CPLs) can penetrate the stack-up structure (STK) in the chip region CHA. Each cell plug (CPL) may include a memory layer (ML), a channel layer (CH), and a die pillar (CO). In an embodiment, the memory layer (ML) may have a cylindrical shape. The plane or XY cross-section of the memory layer (ML) may have a circular shape. The memory layer (ML) may surround the periphery of the channel layer (CH). Although not shown in the figures, the memory layer (ML) may include a barrier layer, a charge trapping layer, and a tunneling layer. In an embodiment, the plane of the memory layer (ML) may have an elliptical shape or a clover shape. However, for ease of description, it is assumed that the planar shape of the cell plug (CPL) is circular.

[0070] The blocking and tunneling layers included in the memory layer ML can be formed of oxide layers (e.g., silicon oxide layers) or oxide oxynitride layers (e.g., silicon oxynitride layers) or combinations thereof. The charge trapping layer included in the memory layer ML can include nitride layers or variable resistance materials.

[0071] The channel layer CH can be formed along the inner wall of the memory layer ML. The die CO can fill the channel layer CH. The die CO can have a cylindrical shape surrounded by the channel layer CH. The channel layer CH can be formed from an undoped silicon layer or a doped silicon layer. The die CO can be formed from an insulating layer (e.g., an oxide layer) or a conductive layer.

[0072] Cell plugs (CPLs) can extend into the semiconductor layer (SL). Cell plugs (CPLs) can contact the semiconductor layer (SL). For example, the channel layer (CH) can directly contact the semiconductor layer (SL).

[0073] Contacts CT can be connected to conductive layers CD in the chip region CHA. The conductive layer CD may have a stepped structure, and the contacts CT can contact the ends included in the stepped structure. The contacts CT may contain a conductive material. In an embodiment, with... Figure 5B Unlike the examples shown, the conductive layer CD may not include a stepped structure. In a laminate STK without a stepped structure, openings can be formed to expose the corresponding conductive layer CD, and contacts CT can be formed in the openings respectively.

[0074] The vertical structure VS of the chip protector GD can have a width corresponding to the cell plug CPL. For example, an opening filled with the vertical structure VS and an opening filled with the cell plug CPL can be formed by a single etching process. That is, an opening through the stack STK can be formed by an etching process that etches a portion of the stack STK, the vertical structure VS can be formed in some of these openings, and the cell plug CPL can be formed in the other openings. Therefore, the width of the vertical structure VS in the X direction can be equal to the width of the cell plug CPL in the X direction.

[0075] Figures 6A to 6E A diagram is shown illustrating a method for manufacturing a memory device including a chip protector according to the present disclosure. Figures 6A to 6E and Figure 5A The cross-sectional view of line A-A' corresponds to that.

[0076] Reference Figure 6A Active regions PA can be formed in the substrate SUB. Active regions PA can be formed in the guard region GDA. Active regions PA can be formed as sub-regions extending from or separated from each other. Active regions PA can be formed by implanting impurities (e.g., elements from Group 13 or 15 of the periodic table) into the substrate SUB.

[0077] Subsequently, a first lower plug LP1, a first lower line LL1, a second lower plug LP2, a second lower line LL2, a third lower plug LP3, a third lower line LL3, and a fourth lower plug LP4 can be formed on the substrate SUB. These components can be formed within the protection region GDA. The lower insulating layer LIL can surround these components. Although not shown in the figure, lower lines and lower plugs electrically connected to the memory cell array can be additionally formed even within the chip region CHA.

[0078] For example, after forming a first insulating layer of thickness, a portion of the first insulating layer can be etched, and a first lower plug LP1 can be formed in the etched area. After forming a second insulating layer covering the first lower plug LP1, a portion of the second insulating layer can be etched, and a first lower line LL1 can be formed in the etched area. In this way, the lower line and the lower plug can be formed sequentially in the Z direction.

[0079] Reference Figure 6B A semiconductor layer SL and an insulating pattern IP can be formed on the lower insulating layer LIL. For example, a semiconductor layer SL covering the lower insulating layer LIL can be formed, a portion of the semiconductor layer SL can be etched, and an insulating pattern IP can be formed to fill the etched portion of the semiconductor layer SL.

[0080] Subsequently, a preliminary stack pSTK comprising alternating layers of interlayer insulating layer IL and sacrificial layer SF can be formed. The interlayer insulating layer IL and the sacrificial layer SF can be stacked on top of each other in the Z direction. The interlayer insulating layer IL can be formed of an insulating material. For example, the interlayer insulating layer IL can be formed of an oxide layer (e.g., a silicon oxide layer). The sacrificial layer SF can be formed of a material that can be selectively removed in subsequent processes. The sacrificial layer SF can be formed of a material having an etch selectivity different from that of the interlayer insulating layer IL. For example, the sacrificial layer SF can be a nitride layer.

[0081] Reference Figure 6C An opening can be formed through the initial stack pSTK. A portion of the opening can be formed in the chip region CHA, and other portions of the opening can be formed in the guard region GDA. For example, each of the openings formed in the chip region CHA and the guard region GDA can have a circular or elliptical cross-sectional shape in the XY plane. In the example, the opening formed in the chip region CHA can have a circular or elliptical shape, and the opening formed in the guard region GDA can have a slit shape.

[0082] Next, cell plugs (CPLs) and dummy cell plugs (DCPLs) with filled openings can be formed. Each cell plug (CPL) may include a memory layer (ML), a channel layer (CH), and a die (CO). Each dummy cell plug (DCPL) may include a dummy memory layer (DML), a dummy channel layer (DCH), and a dummy die (DCO). The dummy memory layer (DML) may contain the same material as the memory layer (ML). The dummy channel layer (DCH) may contain the same material as the channel layer (CH). The dummy die (DCO) may contain the same material as the die (CO).

[0083] Reference Figure 6D A stepped structure can be formed by etching a portion of the initial stack pSTK. The lengths of the corresponding sacrificial layers SF in the X direction can be formed to be different from each other. For example, a stepped structure can be formed by sequentially etching the sacrificial layers SF to different lengths.

[0084] Furthermore, the dummy cell plug DCPL can be removed. The vertical structure VS can be formed in the space from which the dummy cell plug DCPL has been removed. For example, as the dummy cell plug DCPL is removed, Figure 6C Some of the openings described herein can be reopened. Through these reopened openings, the side surfaces of the initial laminate pSTK can be exposed. Insulating spacers can be formed along the exposed side surfaces of the initial laminate pSTK. Furthermore, conductive posts surrounded by insulating spacers can be formed. The vertical structure VS can be formed to connect to the fourth lower plug LP4. For example, the conductive post can contact the fourth lower plug LP4.

[0085] Reference Figure 6E The sacrificial layer SF can be replaced with a conductive layer CD, thereby forming a laminate STK. For example, the sacrificial layer SF can be selectively removed, and the space where the sacrificial layer SF has been removed can be filled with a conductive material to form the conductive layer CD.

[0086] Then, a first upper plug UP1, a first upper line UL1, a second upper plug UP2, a second upper line UL2, and a third upper plug UP3 can be formed on the stacked body STK. The first upper plug UP1, the first upper line UL1, the second upper plug UP2, and the second upper line UL2 can be formed in the protection region GDA. The first upper plug UP1, the first upper line UL1, the second upper plug UP2, the second upper line UL2, and the third upper plug UP3 can be surrounded by the upper insulating layer UIL. Furthermore, upper lines and upper plugs connected to the contact CT can be formed in the chip region CHA. Although not illustrated in the figures, upper lines and upper plugs connected to the cell plug CPL can also be additionally formed.

[0087] For example, after forming a first insulating layer of thickness, a portion of the first insulating layer can be etched, and a first upper plug UP1 can be formed in the etched area. After forming a second insulating layer covering the first upper plug UP1, a portion of the second insulating layer can be etched, and a first upper line UL1 can be formed in the etched area. In this way, the upper line and the upper plug can be formed sequentially in the Z direction.

[0088] Subsequently, test electrodes TE can be formed to connect to the chip protection component GD. The test electrodes TE can be electrically connected to the vertical structure VS via upper lines (e.g., UL1 and UL2) and upper plugs (e.g., UP1, UP2, and UP3). The test electrodes TE can be formed to be spaced apart from each other, with unit plugs CPL disposed between the test electrodes TE. For example, the test electrodes TE can be arranged on either side of the unit plug CPL and the contact CT.

[0089] Subsequently, the presence of defects at the height corresponding to the stack-up STK can be detected using the test electrode TE. For example, a test circuit or separate test apparatus can measure the resistance of the chip protector GD using the test electrode TE. The test circuit or test apparatus can use the test electrode TE to monitor whether defects related to the chip protector GD have occurred at the height corresponding to the stack-up STK.

[0090] The above reference Figures 6A to 6EThe manufacturing methods described are for illustrative purposes only and do not limit the scope of this disclosure. For example, the order of some processes may be changed, some processes may be skipped, or some processes may be replaced with similar processes.

[0091] Figure 7 This is a diagram illustrating a memory card system using a memory device according to the present disclosure.

[0092] Reference Figure 7 The memory card system 3000 includes a controller 3100, a memory device 3200, and a connector 3300.

[0093] Controller 3100 can be connected to memory device 3200. Controller 3100 can access memory device 3200. For example, controller 3100 can control programming operations, reading operations, or erasing operations of memory device 3200, or control background operations of memory device 3200. Controller 3100 can provide an interface between memory device 3200 and a host. Controller 3100 can run firmware for controlling memory device 3200. In embodiments, controller 3100 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and error correction circuitry.

[0094] Controller 3100 can communicate with external devices via connector 3300. Controller 3100 can communicate with external devices (e.g., a host) based on specific communication standards. For example, controller 3100 can communicate with external devices via at least one of various communication standards such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), WiFi, Bluetooth, and High-Speed ​​Non-Volatile Memory (NVMe). For example, connector 3300 can be defined by at least one of the various communication standards described above.

[0095] Memory device 3200 may include multiple memory cells. Controller 3100 and memory device 3200 may be integrated into a single semiconductor device to form a memory card. For example, controller 3100 and memory device 3200 may be integrated into a single semiconductor device and may then form a memory card such as a PC card (PCMCIA), compact flash memory card (CF), smart media card (SM or SMC), memory stick, multimedia card (MMC, RS-MMC, micro MMC or eMMC), SD card (SD, mini SD, micro SD or SDHC), or universal flash memory (UFS).

[0096] Figure 8 This is a diagram illustrating a solid-state drive (SSD) system that utilizes a memory device according to the present disclosure.

[0097] Reference Figure 8 The SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 can exchange signals with the host 4100 through a signal connector 4001 and can receive power through a power connector 4002. The SSD 4200 may include a controller 4210, multiple memory devices 4221 to 422n, an auxiliary power supply 4230, and a cache memory 4240.

[0098] The controller 4210 can control multiple memory devices 4221 to 422n in response to signals received from the host 4100. For example, the signals can be indicated based on the interface between the host 4100 and the SSD 4200. For example, the signals can be signals defined by at least one interface such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), WiFi, Bluetooth, and High-Speed ​​Non-Volatile Memory (NVMe).

[0099] Each of the plurality of memory devices 4221 to 422n may include a plurality of memory cells for storing data. The plurality of memory devices 4221 to 422n may communicate with the controller 4210 via channels CH1 to CHn.

[0100] Auxiliary power supply 4230 can be connected to host 4100 via power connector 4002. Auxiliary power supply 4230 can be supplied with power voltage from host 4100 and can be charged. When power supply from host 4100 is unavailable or exceeds voltage tolerance, auxiliary power supply 4230 can provide power voltage to SSD 4200. For example, auxiliary power supply 4230 can be located inside or outside SSD 4200. For example, auxiliary power supply 4230 can be located on the motherboard, and it can also provide auxiliary power to SSD 4200.

[0101] Buffer memory 4240 can be used as a buffer memory for SSD 4200. For example, buffer memory 4240 can store data received from host 4100 or data received from multiple memory devices 4221 to 422n, or it can store metadata (e.g., a mapping table) of memory devices 4221 to 422n. Buffer memory 4240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0102] Some embodiments of this disclosure can improve the quality of memory devices by enhancing the ability to identify defects occurring in regions outside the chip region.

[0103] Cross-reference to related applications

[0104] This application claims priority to Korean Patent Application No. 10-2024-0157182, filed on November 7, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: The laminate, the conductive layer and the interlayer insulating layer are alternately stacked in the laminate in the stacking direction; A chip protector that surrounds the chip region of the laminate and penetrates the laminate in the lamination direction; as well as Test electrodes, which are electrically connected to the chip protection device, The test electrodes are spaced apart from each other, and at least a portion of the chip region is disposed between the test electrodes.

2. The memory device according to claim 1, wherein, The chip protection component includes: A vertical structure that penetrates the laminate; At least one upper line and at least one upper plug, said at least one upper line and said at least one upper plug being located above the laminate; and At least one lower line and at least one lower plug, the at least one lower line and the at least one lower plug being located below the laminate.

3. The memory device according to claim 2, wherein, At least one of the test electrodes is connected to the at least one upper line.

4. The memory device according to claim 2, wherein, The vertical structure includes: Multiple column structures, which extend in the stacking direction and are arranged along a first direction intersecting the stacking direction.

5. The memory device according to claim 2, wherein, The vertical structure includes a plate extending along a first direction that intersects the stacking direction.

6. The memory device according to claim 1, wherein, The test electrodes are arranged symmetrically with respect to the center of the chip region surrounded by the chip protector.

7. The memory device according to claim 1, wherein, The first test electrode in the test electrode is connected to the chip protection component, and The second test electrode of the test electrode is connected from the first test electrode across the chip region to the chip protection.

8. The memory device according to claim 1, wherein, The test electrode extends from the chip protector into the chip region.

9. The memory device of claim 1, further comprising: The test circuit is connected to the test electrode. The test circuit uses electrical signals input to the chip protection device to determine whether a defect has occurred in the stack.

10. The memory device according to claim 9, wherein, The test circuit uses the resistance gradient information obtained through the test electrodes to determine whether a defect has occurred in the laminate.

11. The memory device of claim 1, further comprising: A detection circuit is disposed between the chip area and the chip protection element.

12. The memory device according to claim 11, wherein, The detection circuit includes: At least one upper detection line and at least one upper detection plug, wherein the at least one upper detection line and the at least one upper detection plug are located above the laminate; and At least one lower detection line and at least one lower detection plug are located below the laminate.

13. The memory device according to claim 11, wherein, The detection circuit does not penetrate the laminate.

14. The memory device of claim 1, further comprising: A unit plug that penetrates the stack in the chip region; as well as Contacts, which are respectively connected to the conductive layer in the chip region.

15. The memory device of claim 14, further comprising: A semiconductor layer is located beneath the laminate. The unit plug contacts the semiconductor layer.

16. A method of manufacturing a memory device, the method comprising the steps of: This forms a laminate with alternating layers of sacrificial layers and interlayer insulation layers; Forming a first set of openings and a second set of openings through the laminate; Forming a unit plug that fills the first set of openings; This forms a vertical structure that fills the second set of openings; Replace the sacrificial layer with a conductive layer; A chip protection component is formed, wherein the chip protection component includes the vertical structure; Test electrodes are formed that are electrically connected to the chip protection device and the test circuit. The test circuit uses electrical signals input to the chip protection device through the test electrodes to determine whether a defect has occurred in the laminate.

17. The method of claim 16, further comprising the step of: Before the formation of the laminated body Forming the lower insulating layer; and Form at least one lower wire and at least one lower plug surrounded by the lower insulation layer.

18. The method according to claim 17, wherein, The steps for forming the vertical structure include the following: The vertical structure is formed to connect to the at least one lower line and the at least one lower plug.

19. The method of claim 16, further comprising the step of: Before the test electrode is formed An upper insulating layer is formed on the laminate; as well as Form at least one upper wire and at least one upper plug surrounded by the upper insulating layer.

20. The method of claim 16, wherein, The steps for forming the test electrode include the following: The test electrodes are formed to be spaced apart from each other, wherein the unit plugs are disposed between the test electrodes.

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