Memory architecture with bipolar semiconductor channel

Abstract

The invention relates to a memory architecture with a bipolar semiconductor channel. A memory device may include: a plurality of conductors each associated with a respective active line of a memory array; and a strut extending through the conductor. The pillar may include a semiconductor material extending along a length of the pillar and associated with a bipolar channel along the length of the pillar. The memory device may also include a plurality of memory portions each including one or more memory materials (e.g., for storing charge, dipole polarization, or a combination thereof). Each memory portion may be associated with a respective memory cell of the memory array and may be positioned along the length of the pillar between a respective one of the conductors and a respective portion of the semiconductor material.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 19 / 373,387, filed October 29, 2025, entitled "Memory Architectures with AmbIPOLAR SEMICONDUCTOR CHANNELS," filed by Fantini et al., and U.S. Patent Application No. 63 / 719,503, filed November 12, 2024, entitled "Memory Architectures with AmbIPOLAR SEMICONDUCTOR CHANNELS," each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to one or more systems for memory, including memory architectures with bipolar semiconductor channels. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read (e.g., sense, detect, retrieve, identify, determine, evaluate) the state of one or more memory cells within the memory device. To store information, a component can write (e.g., program, set, assign) one or more memory cells within the memory device to the corresponding state.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR and NAND memory devices, and others. Memory devices can be described in terms of volatile or non-volatile configurations. Volatile memory cells (e.g., DRAM) lose their programmed state over time unless periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND) can maintain their programmed state for extended periods, even without external power. Summary of the Invention

[0006] A memory device is described. The memory device may include: a plurality of conductors distributed along a direction from a substrate of the memory device, each of the plurality of conductors being associated with a corresponding one of a plurality of active lines of a memory array; a pillar extending from the substrate along the direction through the plurality of conductors, the pillar including a semiconductor material extending along the length of the pillar and associated with a bipolar channel along the length of the pillar; and a plurality of memory portions, each of the plurality of memory portions being associated with a corresponding memory cell of the memory array and including one or more memory materials positioned along the length of the pillar between a corresponding one of the plurality of conductors and a corresponding portion of the semiconductor material.

[0007] A method for operating a memory device is described. The method for operating the memory device may include: writing logic state to memory cells of a memory array, wherein the writing includes: biasing a pillar with a first voltage, the pillar being associated with a bipolar semiconductor channel of a plurality of activation lines extending along the length of the pillar through the memory array; biasing a first activation line of the plurality of activation lines with a second voltage less than the first voltage, the first activation line being coupled to the memory cell; biasing one or more second activation lines of the plurality of activation lines other than the first activation line with a third voltage different from the first voltage and the second voltage; and storing an electric field in one or more memory materials, the one or more memory materials being positioned between the first activation line and the bipolar semiconductor channel, at least in part based on biasing the pillar with the first voltage, biasing the first activation line with the second voltage, and biasing the one or more second activation lines with the third voltage.

[0008] Describe a memory device. The memory device may include: one or more memory arrays; and a circuit system coupled to and configured such that the memory device: writes logic states into memory cells of the memory arrays in the one or more memory arrays, wherein the writing includes: biasing a pillar with a first voltage, the pillar being associated with a bipolar semiconductor channel of a plurality of activation lines extending along the length of the pillar through the memory array; biasing a first activation line of the plurality of activation lines with a second voltage less than the first voltage, the first activation line being coupled to the memory cell; biasing one or more second activation lines of the plurality of activation lines other than the first activation line with a third voltage different from the first voltage and the second voltage; and storing an electric field in one or more memory materials at least in part based on biasing the pillar with the first voltage, biasing the first activation line with the second voltage, and biasing the one or more second activation lines with the third voltage, the one or more memory materials being positioned between the first activation line and the bipolar semiconductor channel. Attached Figure Description

[0009] Figure 1 Examples of memory systems supporting memory architectures with bipolar semiconductor channels, based on the examples disclosed herein, are shown.

[0010] Figure 2 Examples of memory architectures supporting memory architectures with bipolar semiconductor channels are shown, based on the examples disclosed herein.

[0011] Figure 3 Examples of architectures supporting memory architectures with bipolar semiconductor channels are shown, based on the examples disclosed herein.

[0012] Figure 4A and 4B Examples of operations performed on an architecture supporting a memory architecture with a bipolar semiconductor channel, based on the examples disclosed herein.

[0013] Figure 5 A block diagram illustrating a memory device supporting a memory architecture with a bipolar semiconductor channel, based on examples disclosed herein.

[0014] Figure 6 The flowchart illustrates one or more methods for supporting memory architectures with bipolar semiconductor channels, based on the examples disclosed herein. Detailed Implementation

[0015] Some memory systems are expected to support data-intensive applications, such as artificial intelligence (AI) applications and other processes associated with relatively large numbers of access operations. These applications are associated with relatively high-speed data access and can utilize a substantial portion of the memory device. However, some memory devices (such as dynamic random-access memory (DRAM) and central processing unit (CPU) memory) may be constrained by relatively limited storage capacity and bandwidth capabilities, which may be insufficient to handle large amounts of data. Furthermore, other memory devices (such as solid-state drive (SSD) and hard disk drive (HDD) storage devices) can support relatively higher storage capacities but may be associated with relatively high latency, which may hinder the performance of applications associated with increasing data processing speed. In some cases, capacity enhancements through reducing component size or spacing (e.g., along one or more dimensions of the memory array) may be limited by the practical and physical limitations of such technologies (e.g., may become infeasible or otherwise ineffective).

[0016] According to one or more techniques described herein, memory systems (e.g., NAND memory systems, ferroelectric NAND (FeNAND) systems) can support architectures comprising bipolar channels (e.g., bipolar semiconductor channels, pillar channels) containing semiconductor materials (e.g., transition metal dichalcogenide (TMD)). The bipolar characteristic of this channel can refer to the material's ability to generate (e.g., mobilize, conduct) both electrons (e.g., negative charge, charge reduction, electron increase) and holes (e.g., positive charge, charge increase, electron reduction) at the same or relatively similar rates (e.g., the material's ability to behave as both an n-type and p-type semiconductor). In some instances, the use of such semiconductor materials enables relatively efficient generation of electrons and holes, which can support faster or lower power read operations or faster or lower power write operations (e.g., faster switching between electron and hole generation, faster charge mobility, faster switching to the storage electric field) or both using corresponding portions of the memory material in memory cells associated with (e.g., formed along the length of the bipolar channel). For example, such memory materials can store electric fields corresponding to the logical states of memory cells, and such memory materials can include charge-trapping materials operable to store electric fields by moving charges (e.g., electrons) into or out of charge-trapping materials, or polarizing materials (e.g., ferroelectric materials, dipole materials), or combinations thereof, operable to store electric fields by applying coercive electric fields through transpolarization materials to store polarizations (e.g., dipole polarization, dipole orientation, electric field polarization, electric field orientation). In some instances, the memory material can include a ferroelectric layer (e.g., in contact with a semiconductor material) that complements the bipolar capabilities of the semiconductor material in the context of memory operation (e.g., faster switching between electron and hole generation, support for positive and negative electric field orientations). Such techniques enable memory systems to support next-generation applications, such as AI applications and other data-intensive processes. For example, by implementing bipolar strut channels, memory systems can support more efficient access operations (e.g., in-situ write algorithms), which can reduce processing overhead by reducing memory management operations (e.g., discarded item collection) and reduce write amplification effects. Therefore, memory systems can be configured to support higher capacity, reduced latency, increased lifespan, lower power consumption, and other benefits.

[0017] Beyond the memory systems described herein, techniques for memory architectures with bipolar semiconductor channels can typically be implemented to improve the performance of various electronic devices and systems, including AI applications, augmented reality (AR) applications, virtual reality (VR) applications, and games. Some electronic device applications, including high-performance applications such as AI, AR, VR, and games, are associated with relatively high processing requirements to meet user expectations. Therefore, improving the processing power of electronic devices by reducing response time, improving power consumption, reducing complexity, increasing data throughput or access speed, reducing communication time, or increasing memory capacity or density, as well as other performance metrics, can improve user experience or appeal. Implementing the techniques described herein can improve the performance of electronic devices by improving memory access speed (e.g., by supporting in-situ write access operations) and supporting increased capacity, which can reduce processing or latency, improve response time, and otherwise improve user experience and other benefits.

[0018] Features of this disclosure are described and illustrated in the context of systems, apparatus, and circuits. Features of this disclosure are further described and illustrated in the context of memory architectures and flowcharts.

[0019] Figure 1 Examples of a memory system 100 (e.g., a memory device) supporting a memory architecture with a bipolar semiconductor channel, based on the examples disclosed herein, are shown. Figure 1 This is an illustrative representation of the various components and features of the memory system 100. Therefore, the components and features of the memory system 100 are shown to illustrate functional interrelationships and do not necessarily indicate physical locations within the memory system 100. Furthermore, although included in... Figure 1 Some elements are labeled with numerical indicators, but some other corresponding elements are not labeled, even if they are the same or should be understood as similar, in order to improve the visibility and clarity of the depicted features.

[0020] The memory system 100 may include one or more memory cells 105, such as memory cells 105-a and memory cells 105-b. In some instances, the memory cells 105 may be NAND memory cells, as shown in an enlarged view of memory cell 105-a. Each memory cell 105 may be programmed to store a logical value representing one or more information bits. In some instances, a single memory cell 105 (e.g., a memory cell 105 configured as a single-level cell (SLC)) is programmable to one of two supported states and therefore can store one information bit (e.g., logic 0 or logic 1) at a time. In some other instances, a single memory cell 105 (e.g., a memory cell 105 configured as a multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), or other type of multi-level memory cell 105) is programmable to more than one of two supported states and therefore can store more than one information bit at a time. In some cases, multilevel memory cells 105 (e.g., MLC memory cells, TLC memory cells, QLC memory cells) may be physically different from SLC cells. For example, multilevel memory cells 105 may use different cell geometries or may be manufactured using different materials. In some instances, multilevel memory cells 105 may be physically the same as or similar to SLC cells, and other circuitry within the memory block (e.g., controllers, sense amplifiers, drivers) may be configured to operate (e.g., read and program) the memory cells as SLC cells, MLC cells, or TLC cells, etc.

[0021] In some NAND memory arrays, each memory cell 105 may be described as a transistor comprising a material portion (e.g., a floating gate, a replacement gate, a dielectric material, a charge-trapping material, or a ferroelectric material) configured to store an electric field representing a logic value. For example, Figure 1The enlarged view illustrates a NAND memory cell 105-a containing a transistor 110 (e.g., a metal-oxide-semiconductor (MOS) transistor) for storing logic values. The transistor 110 may include a control gate 115 and a storage portion 120. In some instances, the storage portion 120 may be located between a dielectric material 125 (e.g., a gate dielectric) and a semiconductor channel (e.g., in contact with the semiconductor channel), or between two portions of the dielectric material 125 (e.g., as illustrated), and other embodiments. The storage portion 120 may include a charge-trapping storage portion 120-a (e.g., a charge-trapping material) or a ferroelectric storage portion 120-b (e.g., a ferroelectric material including a ferroelectric dipole 121) or a combination of charge-trapping storage portions 120-a and ferroelectric storage portions 120-b, and other embodiments configured to store an electric field (e.g., between the control gate 115 and the semiconductor channel). Transistor 110 may also include a first node 130 (e.g., source or drain) and a second node 135 (e.g., drain or source), and a semiconductor channel (e.g., of memory cell 105, serial or of memory cell 105) may be coupled between the first node 130 and the second node 135.

[0022] Logic values ​​can be stored in memory cell 105 (e.g., in transistor 110) by storing (e.g., writing, sensing) an electric field into storage portion 120 of memory cell 105. For example, memory cell 105 can be written with cell states 195 (e.g., electric field state, charge state, polarization state, write state, corresponding to logic states), such as cell state 195-a (e.g., "erase" state) or cell state 195-b (e.g., "program" state). While the examples of cell states 195-a and 195-b illustrate instances where two logic states can be supported (e.g., for an SLC implementation), the described techniques can be implemented to support more than two cell states 195 (e.g., more than two logic states, for a multi-level cell implementation), which can be further based on different storage electric field strengths (e.g., combinations with electric field polarization (e.g., positive or negative electric fields)) and other implementations.

[0023] An electric field stored at storage portion 120 can affect the threshold voltage of transistor 110, thereby affecting the amount of current flowing through transistor 110 (e.g., through channel portion 131 corresponding to the semiconductor channel between first node 130 and second node 135) when transistor 110 is activated (e.g., when a voltage is applied to control gate 115, when memory cell 105-a is read). For example, cell state 195-a may be associated with activating channel portion 131 with a relatively low voltage at gate 115 (e.g., for a given voltage at gate 115, through a relatively low activation voltage, relatively low VT, and relatively high conductivity of channel portion 131), while cell state 195-b may be associated with activating channel portion 131 with a relatively high voltage at gate 115 (e.g., for a given voltage at gate 115, through a relatively high activation voltage, relatively high VT, and relatively low conductivity of channel portion 131).

[0024] In some instances, writing an electric field to memory cell 105 may involve moving charges (e.g., electrons) into or out of storage portion 120 (e.g., charge trapping storage portion 120-a), and different stored charges may correspond to different logic states. For example, the electric field associated with cell state 195-a may contain a net positive charge (e.g., stored in charge trapping storage portion 120-a as a result of transferring electrons from storage portion 120, as a result of hole injection), and the electric field associated with cell state 195-b may contain a net negative charge (e.g., stored in charge trapping storage portion 120-a as a result of transferring electrons into storage portion 120, as a result of electron injection).

[0025] In some instances, writing an electric field to memory cell 105 may involve storing polarizations (e.g., dipole polarization, polarization orientation, dipole orientation, local electric field orientation) in memory portion 120 (e.g., ferroelectric memory portion 120-b), and different polarizations may correspond to different logic states. For example, the electric field associated with cell state 195-a may correspond to a first polarization of ferroelectric memory portion 120-b (e.g., a first orientation of dipole 121, corresponding to a positive local electric field from gate 115 to channel portion 131), and the electric field associated with cell state 195-b may correspond to a second polarization of ferroelectric memory portion 120-b (e.g., a second orientation of dipole 121, corresponding to a negative local electric field from gate 115 to channel portion 131). Various embodiments of the described techniques may involve writing an electric field based on moving charges into or out of memory portion 120 or storing polarizations in memory portion 120, or combinations thereof.

[0026] The logic value stored in transistor 110 can be sensed (e.g., as part of a read operation) by applying a voltage to control gate 115 (e.g., via word line 165 to control node 140) to activate transistor 110 and measuring (e.g., detecting, sensing) the amount of current flowing through first node 130 or second node 135 (e.g., via bit line 155 through channel portion 131). For example, sensing component 170 can determine whether SLC memory cell 105 stores logic 0 or logic 1 in binary (e.g., based on the presence or absence of current through memory cell 105 when read voltage is applied to control gate 115, based on whether the current is above or below a threshold current). For a three-level memory cell 105, sensing component 170 can determine the logic value stored in memory cell 105 based on various intermediate threshold current levels when read voltage is applied to control gate 115 or by applying different read voltages to control gate and evaluating different resulting current levels through transistor 110, or various combinations thereof. In one example of a multi-level architecture, the sensing component 170 can determine the logic value of the TLC memory cell 105 based on eight different current levels or current ranges that define eight potential logic values ​​that can be stored by the TLC memory cell 105.

[0027] SLC memory cell 105 can be written by applying one of two voltages (e.g., a voltage above a threshold or a voltage below a threshold) to memory cell 105 to store an electric field on storage portion 120, thereby causing memory cell 105 to store one of two possible logic values. For example, when a first voltage (e.g., via word line 165 for writing a “programmed” state) (e.g., a voltage across storage portion 120) is applied to control node 140 relative to block node 145 (e.g., body node) or channel portion 131 of transistor 110, electrons can tunnel into storage portion 120 (e.g., charge-trapping storage portion 120-a), or (e.g., dipole 121 of ferroelectric storage portion 120-b) can be oriented with a negative field along the direction from control gate 115 to channel portion 131, or both. Such an operation can be referred to as programming memory cell 105 and can occur as part of a write operation. In some cases, a programmed memory cell can be considered as storing logic 0. When a second voltage (e.g., for writing an "erase" state) is applied to the control node 140 relative to the bulk node 145 or channel portion 131 of transistor 110, electrons may (e.g., from charge-trapping storage portion 120-a) leave storage portion 120, or dipole 121 (e.g., from ferroelectric storage portion 120-b) may be positively oriented from control gate 115 to channel portion 131, or both. Such an operation may be referred to as erasing memory cell 105 and may occur as part of an erase operation. In some cases, the erased memory cell may be considered as storing logic 1.

[0028] Writing to a multi-level (e.g., MLC, TLC, or QLC) memory cell 105, compared to writing to an SLC memory cell 105, may involve applying different electric fields to the memory cell 105 (e.g., its control node 140 or block node 145) at a finer granular level to more precisely control the amount of electric field stored at the memory portion 120, thereby enabling the representation of a larger set of logic values. Therefore, the multi-level memory cell 105 can provide a higher density of storage compared to the SLC memory cell 105, but in some cases, it may involve supporting narrower read or write margins or greater complexity in the circuitry.

[0029] In some instances, each page memory cell 105 may be connected to a corresponding word line 165, and each column memory cell 105 may be connected to a corresponding bit line 155 (e.g., a number line). Therefore, a memory cell 105 may be located at the intersection of the word line 165 and the bit line 155. This intersection may be referred to as the address of the memory cell 105. In some cases, the word line 165 and the bit line 155 may be substantially perpendicular to each other and may be collectively referred to as access lines or select lines.

[0030] In some cases, the memory system 100 may include a three-dimensional (3D) memory array, wherein multiple two-dimensional (2D) memory arrays may be formed one on top of the other. In some instances, this arrangement can increase the number of memory cells 105 that can be fabricated on a single die or substrate compared to a 1D array, which in turn can reduce manufacturing costs or improve the performance of the memory array, or both. Figure 1 In some instances, the memory system 100 comprises memory cells 105 in multiple hierarchical (e.g., layer, plane, level) layers. In some instances, the layers may be separated by an electrically insulating material. Each layer may be aligned or positioned such that the memory cells 105 can be aligned with each other across each layer (e.g., precise alignment, overlap, or approximate alignment), thereby forming a memory cell stack 175. In some cases, the memory cells aligned along the memory cell stack 175 may be referred to as a string of memory cells 105 (e.g., as shown in the reference). Figure 2 describe).

[0031] Access to memory cell 105 can be controlled by row decoder 160 and column decoder 150. For example, row decoder 160 can receive a row address from memory controller 180 and activate the appropriate word line 165 based on the received row address. Similarly, column decoder 150 can receive a column address from memory controller 180 and activate the appropriate bit line 155. Thus, a memory cell 105 can be accessed by activating a word line 165 and a bit line 155. As part of this access, sensing component 170 can read (e.g., sense) memory cell 105. For example, sensing component 170 can be configured to determine the stored logic value of memory cell 105 based on a signal generated by accessing memory cell 105. The signal may include current, voltage, or both current and voltage on bit line 155 of memory cell 105 and may depend on the logic value stored by memory cell 105. Sensing component 170 may include various circuit systems (e.g., transistors, amplifiers) configured to detect and amplify the signal (e.g., current or voltage) on bit line 155. The logic value of the memory cell 105 detected by the sensing component 170 can be output via the input / output component 190. In some cases, the sensing component 170 may be part of the column decoder 150 or the row decoder 160, or the sensing component 170 may be otherwise connected to or in electronic communication with the column decoder 150 or the row decoder 160.

[0032] Memory cell 105 can be programmed or written to enable logical values ​​(e.g., representing one or more information bits) to be stored in memory cell 105 by activating associated word lines 165 and bit lines 155. Column decoder 150 or row decoder 160 can (e.g., from input / output component 190) accept data to be written to memory cell 105. In the case of NAND memory, memory cell 105 can be written to by storing electrons in charge-trapping structures or insulating layers.

[0033] The memory controller 180 can control the operation (e.g., read, write, rewrite, refresh) of the memory cell 105 through various components (e.g., row decoder 160, column decoder 150, and sensing component 170). In some cases, one or more of the row decoder 160, column decoder 150, and sensing component 170 may be co-located with the memory controller 180. The memory controller 180 can generate row and column address signals to activate the desired word line 165 and bit line 155. In some instances, the memory controller 180 can generate and control various voltages or currents used during the operation of the memory device 100.

[0034] Some memory systems are expected to support data-intensive applications, such as artificial intelligence (AI) applications and other processes associated with relatively large numbers of access operations. However, in some cases, memory systems may be constrained by relatively limited storage capacity and bandwidth capabilities, which may be insufficient to handle large amounts of data. In other instances, memory systems may support relatively higher storage capacities, but this may be associated with relatively high latency, thus hindering data processing speed. In some cases, capacity enhancements through reducing component size or spacing may be limited by the practical and physical constraints of such technologies.

[0035] According to one or more techniques described herein, memory system 100 may support an architecture comprising a bipolar channel (e.g., a bipolar semiconductor channel, pillar channel, or bipolar channel portion 131 between corresponding nodes 130 and 135) containing a semiconductor material (e.g., TMD). In some instances, the use of such a semiconductor material in channel portion 131 enables relatively efficient generation of electrons and holes, which can support faster or lower power read operations or faster or lower power write operations (e.g., faster switching between electron and hole generation, faster charge mobility, faster transition to the storage electric field) or both using corresponding storage portions 120 of memory cells 105 associated with (e.g., formed along the length of the bipolar channel) of the bipolar channel. Such techniques enable memory systems to support next-generation applications, such as AI applications and other data-intensive processes. For example, by implementing a bipolar pillar channel, memory systems can support more efficient access operations (e.g., in-situ write algorithms), which can mitigate processing overhead by reducing memory management operations (e.g., obsolete item collection) and reduce write amplification effects. Therefore, the memory system 100 can be configured to support higher capacity, reduced latency, increased lifespan, reduced power consumption, and other benefits.

[0036] Figure 2 Examples of memory architecture 200 supporting a memory architecture with a bipolar semiconductor channel, based on the examples disclosed herein, are shown. Memory architecture 200 may be an example of a memory system (e.g., memory system 100). Although Figure 2 It contains some elements from a set of elements (e.g., an array of elements), but some elements may be omitted for the sake of visibility and clarity of the depicted elements. Furthermore, although... Figure 2 Some of the components are labeled with reference numerals, but some other corresponding components are not labeled, although they may be understood by one of ordinary skill in the art to be the same as or similar to the labeled components. Aspects of the memory architecture 200 may be described with reference to the x, y, and z directions of the illustrated coordinate system.

[0037] Memory architecture 200 includes a three-dimensional array of memory cells 205, which may be used as a reference. Figure 1Examples of memory cells 105 described herein include (e.g., transistor 110, NAND memory cells). In some instances, memory cells 205 may be connected in a 3D NAND configuration. For example, memory cells 205 may be contained in a block 210, which may be arranged as a 3D array of m memory cells along the x-direction, n memory cells along the y-direction, and o memory cells along the z-direction. Each memory cell 205 may be located (e.g., addressed) according to an index i along the x-direction, an index j along the y-direction, and an index k along the z-direction (e.g., for locating memory cell 205-a-ijk). According to the examples disclosed herein, memory system 100 may contain any number of one or more blocks 210, and different blocks 210 may be adjacent along the x-direction, along the y-direction, or along the z-direction, or any combination thereof.

[0038] In an example of memory architecture 200, block 210 may be divided into a set of pages 215 (e.g., o pages 215) along the z-direction, containing pages 215-a-1 associated with memory cells 205-a-111 to 205-a-mn1. In some instances, each page 215 may be associated with the same word line 265 (e.g., reference 265). Figure 1 The word line 265 described is associated with each other and may be coupled to the control gate 115 of each of the memory cells 205 in page 215. For example, page 215-a-1 may be associated with word line 265-a-1, and other pages 215-ai may be associated with different corresponding word lines 265-ai (not shown). In some instances, word line 265 according to memory architecture 200 may be implemented as a planar conductor (e.g., in the xy plane) coupled to each of the memory cells 205 in page 215.

[0039] In an example of memory architecture 200, block 210 may also be divided into a set of strings 220 (e.g., (m×n) strings 220) in the xy plane, containing strings 215-a-mn associated with memory cells 205-a-mn1 to 205-a-mno. In some instances, each string 220 may contain a set of memory cells 205 connected in series (e.g., along the z-direction, where the drain of one memory cell 205 in string 220 may be coupled to the source of another memory cell 205 in string 220). In some instances, the memory cells 205 of string 220 may be implemented along a common channel, such as a pillar channel (e.g., a pillar channel, doped semiconductor pillar) along the z-direction. Each memory cell 205 in string 220 may be associated with a different word line 265, such that the number of word lines 265 in memory architecture 200 may be equal to the number of memory cells 205 in string 220. Therefore, string 220 may include memory cells 205 from multiple pages 215, and page 215 may include memory cells 205 from multiple strings 220.

[0040] In some instances, memory cell 205 can be programmed (e.g., set to logic 0) and read at a granular level, such as at the granularity of page 215 or a portion thereof, but may not be erased at a granularity of, for example, page 215 or a portion thereof (e.g., reset to logic 1). For instance, NAND memory can be erased at a different (e.g., higher) granularity level, such as at the granularity of block 210. In some cases, memory cell 205 needs to be erased before it can be reprogrammed. Different memory devices may have different read, write, or erase characteristics.

[0041] In some instances, each string 220 of block 210 may be coupled to a corresponding transistor 230 (e.g., string select transistor, drain select transistor) at one end of string 220 (e.g., along the z-direction) and a corresponding transistor 240 (e.g., source select transistor, ground select transistor) at the other end of string 220. In some instances, the drain of each transistor 230 may be coupled to a bit line 250 of a set of bit lines 250 associated with block 210, wherein bit line 250 may be a reference. Figure 1 An example of bit line 155 is described. The gate of each transistor 230 may be coupled to select line 235 (e.g., string select line, drain select line). Thus, transistor 230 can be used to couple string 220 to bit line 250 based on applying a voltage to select line 235 and therefore to the gate of transistor 230. Although illustrated as a separate line along the x-direction, in some instances, select line 235 may be shared by all transistors 230 associated with block 210 (e.g., common bias string select node). For example, like word line 265 of block 210, in some instances, select line 235 associated with block 210 may be implemented as a planar conductor (e.g., in the xy plane) coupled to each of the transistors 230 associated with block 210.

[0042] In some instances, the source of each transistor 240 associated with block 210 may be coupled to a source line 260 of a set of source lines 260 associated with block 210. In some instances, the set of source lines 260 may be associated with a common source node (e.g., a ground node) corresponding to block 210. The gate of each transistor 240 may be coupled to a select line 245 (e.g., a source select line, a ground select line). Thus, transistor 240 can be used to couple string 220 to source line 260 based on applying a voltage to select line 245 and thus to the gate of transistor 240. Although illustrated as a separate line along the x-direction, in some instances, select line 245 may also be shared by all transistors 240 associated with block 210 (e.g., a common bias ground select node). For example, like word line 265 of block 210, in some instances, select line 245 associated with block 210 may be implemented as a planar conductor (e.g. in the xy plane) coupled to each of the transistors 240 associated with block 210.

[0043] To operate memory architecture 200 (e.g., to perform programming, reading, or erasing operations on one or more memory cells 205 of block 210), various voltages may be applied to one or more select lines 235 (e.g., gates of transistors 230), one or more bit lines 250 (e.g., drains of transistors 230), one or more word lines 265, one or more select lines 245 (e.g., gates of transistors 240), one or more source lines 260 (e.g., sources of transistors 240), or the block body of memory cells 205 (not shown) of block 210. In some cases, each memory cell 205 of block 210 may have a common block body, the voltage of which may be controlled independently of the block bodies of other blocks 210.

[0044] In some cases, as part of a read operation on memory cell 205, a positive voltage may be applied to the corresponding bit line 250, while the corresponding source line 260 may be grounded or otherwise biased at a voltage lower than that applied to bit line 250. In some instances, for memory cell 205, voltages higher than the threshold voltages of transistors 230 and 240 may be applied concurrently to select lines 235 and 245, thereby activating transistors 230 and 240, such that a channel (e.g., a pillar channel) associated with the string 220 containing memory cell 205 can be electrically connected to the corresponding bit line 250 and source line 260 (e.g., electrically connected between the corresponding bit line 250 and source line 260). The channel may be an electrical path through the memory cell 205 in the string 220, which can conduct current under certain operating conditions (e.g., through the source and drain of the transistors in the memory cell 205 of the string 220).

[0045] In some instances, multiple word lines 265 of block 210 (e.g., in some cases, all word lines 265) (except for the word lines 265 associated with page 215 of the memory cell 205 to be read) may be concurrently set to a voltage higher than the threshold voltage (VT) of the memory cell 205 (e.g., VREAD). VREAD may cause all memory cells 205 in the unselected page 215 to be activated such that each unselected memory cell 205 in the string 220 can maintain high conductivity within the channel. In some instances, the word line 265 associated with the memory cell 205 to be read may be set to a voltage VTarget. When the memory cell 205 operates as an SLC memory cell, VTarget may be a voltage between (i) the VT of the memory cell 205 in an erase state (e.g., cell state 195-a) and (ii) the VT of the memory cell 205 in a programmed state (e.g., cell state 195-b).

[0046] When the memory cell 205 to be read exhibits an erase VT (e.g., VTarget > VT of memory cell 205 associated with cell state 195-a), memory cell 205 can be "turned on" in response to VTarget applied to word line 265 of selected page 215, which allows current to flow in the channel of string 220 and thus from bit line 250 to source line 260. When the memory cell 205 to be read exhibits a programming VT (e.g., VTarget < VT of selected memory cell associated with cell state 195-b), memory cell 205 can remain "turned off" although VTarget is applied to word line 265 of selected page 215, thus preventing current from flowing in the channel of string 220 and thus preventing current from flowing from bit line 250 to source line 260.

[0047] Signals on bit line 250 of memory cell 205 (e.g., current amounts below or above a threshold) can be sensed (e.g., via a reference). Figure 1 The described sensing component 170 can indicate whether the memory cell 205 becomes conductive or remains non-conductive in response to a word line 265 applied to the selected page 215 by VTarget. The sensed signal can therefore indicate whether the memory cell 205 is in an erase state (e.g., storing logic 1) or a programming state (e.g., storing logic 0). Although aspects of the above example read operation have been explained in the context of SLC memory cell 205 for clarity, such techniques can be extended or modified and applied in the context of multi-level memory cells 205 (e.g., by using multiple VTarget values ​​corresponding to different amounts of charge that can be stored in a multi-level memory cell 205).

[0048] In some cases, as part of the programming operation of memory cell 205, an electric field may be stored in a portion of memory cell 205 (e.g., one or more memory sections 120) such that when memory cell 205 is read later, the flow of current through memory cell 205 and thus through the corresponding string 220 can be suppressed. For example, depending on cell state 195-b, charge (e.g., electrons) may be injected into charge-trapping storage section 120-a, or polarization may be written to ferroelectric storage section 120-b, or both. In some cases, a corresponding voltage may be applied to the word line 265 of the page 215 to be programmed and the block of memory cell 205 (e.g., across memory sections 120), such that the control gate 115 of memory cell 205 is at a relatively high voltage (e.g., a positive voltage may be applied to word line 265). Voltages higher than the threshold voltages of transistors 230 and 240 can be concurrently applied to select line 235, select line 245, or both, thereby activating transistors 230 and / or 240, and the bit line 250 of the memory cell 205 to be programmed can be set to a relatively high voltage. In some instances, this can result in an electric field that draws electrons into the storage portion 120 of the memory cell 205 (e.g., through dielectric material 125) and thereby injects them into the storage portion 120 through a process that in some cases may be referred to as tunneling injection or altering the polarization of the storage portion 120, or both.

[0049] In some cases, a single programming operation can program some or all of the memory cells 205 in page 215 because the memory cells 205 of page 215 can all share a common word line 265 and a common block. For memory cells 205 of page 215 that are not intended to be written to with logic 0 (e.g., not intended to be programmed), the corresponding bit line 250 can be set to a relatively low voltage (e.g., ground), which can suppress the writing of electric fields to memory portion 120. Although aspects of the programming operation in the examples above have been explained in the context of SLC memory cells 205 for clarity, such techniques are scalable and applicable to the context of multi-level memory cells 205 (e.g., by using multiple programming voltages applied to word line 265 or multiple passes or pulses of programming voltage applied to word line 265, corresponding to different electric field amounts that can be stored in a multi-level memory cell 205).

[0050] In some cases, as part of an erase operation on memory cell 205, an electric field may be stored in a portion of memory cell 205 (e.g., one or more memory sections 120) such that when memory cell 205 is read later, current flowing through memory cell 205 and thus through the corresponding string 220 is not suppressed (e.g., is allowed, at least to a greater extent). For example, depending on cell state 195-b, charge (e.g., electrons) may be removed from charge-trapping storage section 120-a, or polarization may be written to ferroelectric storage section 120-b, or both. In some cases, a corresponding voltage may be applied to the word line 265 of the page 215 to be erased and the block of memory cell 205 such that the control gate 115 of memory cell 205 is at a relatively low voltage (e.g., a negative voltage may be applied to word line 265), which may cause electrons to be pulled out from storage section 120 and into the block of memory cell 205 or change the polarization of storage section 120 or both of the electric field.

[0051] According to one or more techniques described herein, memory architecture 200 may include a bipolar channel (e.g., a bipolar semiconductor channel, pillar channel, along string 220) of semiconductor material (e.g., TMD). In some instances, the use of such semiconductor materials enables relatively efficient generation of electrons and holes, which can support faster or lower power read operations or faster or lower power write operations (e.g., faster switching between electron and hole generation, faster charge mobility, faster switching to the storage electric field) or both, using corresponding portions of the storage material of memory cells 205 associated with the bipolar channel (e.g., formed along the length of the bipolar channel). For example, such memory materials can store electric fields corresponding to logic states, and such memory materials can include charge-trapping materials operable to store electric fields by moving charges (e.g., electrons) into or out of charge-trapping materials, or polarizing materials (e.g., ferroelectric materials, dipole materials) or combinations thereof operable to store electric fields by applying coercive electric fields through transpolarizing materials to store polarizations (e.g., dipole polarization, dipole orientation, electric field polarization, electric field orientation). In some instances, the memory material can include a ferroelectric layer (e.g., in contact with a semiconductor material) that can complement the bipolar capabilities of the semiconductor material in the context of memory operation (e.g., faster switching between electron and hole generation, support for positive and negative electric field orientations).

[0052] The described techniques enable memory architecture 200 to support next-generation applications, such as AI applications and other data-intensive processes. For example, by implementing a bipolar strut channel (e.g., along string 220), the memory system can support more efficient access operations (e.g., in-situ write algorithms), which can mitigate processing overhead by reducing memory management operations (e.g., discarded item collection) and reduce write amplification effects. For example, compared to other techniques for erasing memory cells 205 (e.g., by biasing the block body of memory cells 205 in block 210, by concurrently erasing block 210), memory cells 205 implementing a bipolar channel architecture can additionally or alternatively erase or write in-situ (e.g., individually, in different logic states) by changing (e.g., inverting, reducing) the charge or polarization of the corresponding memory portion 120 when different write biases are applied across memory portion 120 (e.g., applied between the corresponding word line 265 and the corresponding bit line 250). Therefore, the memory system can be configured to support higher capacity, reduced latency, increased lifetime, reduced power consumption, and other benefits.

[0053] Figure 3 Examples of architecture 300 supporting a memory architecture with bipolar semiconductor channels are shown below, based on the examples disclosed herein. Architecture 300 may be an example of memory system 100 and memory architecture 200, or an aspect comprising memory system 100 and memory architecture 200. For example, architecture 300 may include one or more pillars 305 extending along the z-direction in the xy-plane, each having a cross-sectional shape (e.g., circular, toroidal, elliptical, prismatic) (e.g., pillar channels corresponding to strings 220 implemented along a common channel, or columnar channels that may be implemented as an array of pillars 305 arranged along the x-direction, along the y-direction, or both). Architecture 300 may also include one or more conductors 365 (e.g., word lines 265, word lines 165) distributed along the z-direction (e.g., above a substrate) and each extending along the x-direction, y-direction, or both (e.g., for supporting planar word lines 265). Along pillar 305 (e.g., arranged as part of pillar 305), architecture 300 may include storage material 320 comprising various portions 322 (e.g., corresponding to storage portion 120, which may include charge trapping storage portion 120-a, ferroelectric storage portion 120-b, or both) and may include material 330 (e.g., dielectric material) between conductors 365 and corresponding to reference Figure 1 and 2 Other components of the described aspect. Aspects of architecture 300 can be described with reference to the x, y, and z directions of the illustrated coordinate system.

[0054] In some instances, pillar 305 may refer to a structure within a memory device that provides conductive channels to connect various layers or components, such as semiconductor materials, charge-trapping materials, dielectric materials, and other materials that facilitate data storage and retrieval operations. For example, pillar 305 may include dielectric material 315 (e.g., a core dielectric), a channel 310 formed of a semiconductor material (e.g., molybdenum disulfide (MoS2) material or other semiconductor materials exhibiting bipolar properties) (e.g., a bipolar channel around dielectric material 315), storage material 320 (e.g., a ferroelectric material (which may be based on hafnium dioxide or include hafnium oxide material around channel 310) or a charge-trapping material or both), dielectric material 325 (e.g., a gate sandwich around storage material 320, a gate dielectric, dielectric material 125, which in some instances may be used as a charge-trapping material), or any combination thereof.

[0055] In some instances, architecture 300 may implement (e.g., utilize, fully leverage) a channel 310 associated with bipolar characteristics (e.g., exhibiting bipolar characteristics) and may be referred to as bipolar channel 310. For example, the semiconductor material of channel 310 may become conductive based on two or more different activation voltage ranges (e.g., a negative voltage range and a positive voltage range). For example, channel 310 may be activated based on a voltage below a first threshold voltage (e.g., V1) or above a second threshold voltage (e.g., V2) (e.g., one or more gate voltages, one or more activation voltages, one or more conductor voltages 365). In some instances, one or more TMD materials may be used for channel 310 based on bipolar conductivity (e.g., NAND memory channels, which offer advantages in terms of spacing extension and performance enhancement in memory systems). Among such materials, MoS2 may be a non-limiting example of a material exhibiting a set of characteristics suitable for bipolar channel 310. In some instances, MoS2 deposition can be integrated into a memory architecture (e.g., architecture 300) based on one or more techniques such as atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PVCVD).

[0056] In some instances, TMD materials (e.g., containing MoS2) can support high-speed bipolar operation based on their bipolar conductivity. For example, using TMD materials as semiconductors enables rapid generation of both electrons and holes along channel 310. In contrast, other architectures (e.g., other 3D NAND architectures) may use polysilicon materials along the channel, which can be associated with relatively slow hole generation (e.g., due to gate-induced drain leakage (GIDL) processes), resulting in relatively slow erase operations (e.g., this facilitates data erasure at the block level rather than the page or cell level). However, channel 310 (e.g., a hollow channel, a hollow bipolar MoS2 channel) can overcome or mitigate such limitations by facilitating relatively faster programming and erasing operations on memory cells (e.g., thus enhancing FeNAND devices). Furthermore, TMD materials (e.g., MoS2) can provide higher string currents than other materials (e.g., polysilicon), enabling relatively faster read operations. In some instances, using TMD material as part of architecture 300 (e.g., when the memory array is organized in a cladding configuration) can mitigate the resistive-capacitive characteristics of word line 265 (e.g., conductor 365).

[0057] For example, graph 335 illustrates an example of curve 340 showing the bipolar conduction of a TMD material (e.g., MoS2). The horizontal axis of graph 335 may represent voltage values ​​(e.g., in volts (V)), and the vertical axis of graph 335 may represent conduction or current values ​​(e.g., in amperes (A), expressed on a logarithmic scale). In some instances, the TMD material may be activated in response to an applied activation voltage when the conductivity (e.g., I) is higher than a threshold conductivity I1. For example, the TMD material may be activated in response to an activation voltage lower than or equal to a first threshold voltage V1 (e.g., having conductivity or current higher than I1). The TMD material may also be activated in response to an activation voltage higher than or equal to a second threshold voltage V2 (e.g., having conductivity or current higher than I1). The TMD material may be deactivated in response to an activation voltage between the first threshold voltage V1 and the second threshold voltage V2 (e.g., having conductivity or current lower than I1). In some instances, V1 can be a negative voltage (e.g., less than the ground voltage, a negative threshold voltage) and V2 can be a positive voltage (e.g., greater than the ground voltage, a positive threshold voltage).

[0058] In some instances, storage material 320 may comprise various portions 322, each of which may be associated with a corresponding conductor 365 (e.g., associated with word line 265, associated with memory cell 205) and may be a location for storing one or more logical states (e.g., data bits). For example, portion 322-a-1 of storage material 320 (e.g., wound around post 305, outside channel 310) may be associated with conductor 365-a-1 and may store logical states (e.g., electric fields) based on the operation of conductor 365-a-1 and channel 310.

[0059] In some instances, storage material 320 may comprise ferroelectric material (e.g., ferroelectric storage portion 120-b). In such instances, polarization (e.g., dipole polarization, dipole orientation, charge distribution) can be induced in the ferroelectric material of storage material 320 by an electric field (e.g., in the corresponding portion 322). Alternatively, storage material 320 may comprise charge-trapping material (e.g., charge-trapping storage portion 120-a). In such instances, charge (e.g., positive or negative charge) can be injected into the channel sandwich portion by an electric field (e.g., through electron injection or removal). Thus, the memory cell associated with storage material 320 is operable to store a corresponding logic state (e.g., as a storage electric field between conductor 365 and channel 310) based on the charge stored in the corresponding portion of the charge-trapping material of storage material 320, the dipole orientation stored in the corresponding portion of the ferroelectric material of storage material 320, or both.

[0060] In some instances, a polarization voltage (e.g., a saturation voltage associated with polarizing at least one of the storage materials 320) may be applied to the storage material 320, the magnitude of which is greater than the gate activation voltage applied to the conductor 365 (e.g., less than the voltage of V1 in the first charge state and greater than the voltage of V2 in the second charge state). In some instances, the activation voltage (e.g., V1, V2) of the channel 310 may have a magnitude less than the voltage that interferes with the cell state 195 (e.g., the storage electric field) of the storage material 320, such that a portion of the channel 310 may be activated without interfering with the logic states stored in the storage material 320 along the pillar 305. In some instances, the channel 310 may be in direct contact with the storage material 320 (e.g., there may be no material between the ferroelectric material and the TMD channel). The storage material 320 may also be in contact with one or more dielectric materials 325 (e.g., gate sandwich layers). The dielectric material 325 may comprise a combination of multiple dielectric layers or may comprise a single dielectric material.

[0061] In some instances, architecture 300 may further include one or more select lines (e.g., select line 245), source lines (e.g., source line 260), and other components that facilitate the operation of architecture 300. Such features enable architecture 300 to implement a slab-block array architecture that integrates multiple pillars 305 (e.g., each containing multiple memory cells) to improve access speed performance and reduce power consumption. In some instances, architecture 300 may support more efficient memory access operations, such as in-situ write array operations. Such operations can reduce (e.g., eliminate) the relatively slow operations associated with GIDL at memory cell blocks (e.g., hole generation operations).

[0062] As an illustrative example, a memory device may include a plurality of conductors 365 distributed from a substrate (not shown) of the memory device along a direction (e.g., the z-direction). In some embodiments, each of the conductors 365 may be associated with a corresponding one of a plurality of active lines (e.g., word lines 265) of a memory array. In some embodiments, the memory device may include a pillar 305 extending from the substrate along a direction through the group of conductors 365. The pillar 305 may include a semiconductor material extending along the length of the pillar 305 and associated with a bipolar channel 310 along the length of the pillar 305.

[0063] In some instances, in response to an activation voltage below a first threshold voltage (e.g., below V1), the conductivity of the bipolar channel 310 may be higher than a threshold conductivity (e.g., higher than I1, can be activated, and can facilitate hole transfer). In some instances, in response to an activation voltage above a second threshold voltage (e.g., higher than V2), the conductivity of the bipolar channel 310 may be higher than a threshold conductivity (e.g., higher than I1, can be activated, and can facilitate electron transfer). In some instances, in response to an activation voltage between the first and second threshold voltages, the conductivity of the bipolar channel 310 may be lower than a threshold conductivity (e.g., lower than I1, and can be deactivated). In some instances, the semiconductor material of the channel 310 may comprise a TMD material (e.g., MoS2). Alternatively or additionally, the semiconductor material may be a layer of semiconductor material surrounding the dielectric core (e.g., dielectric material 315) of the pillar 305.

[0064] In some instances, architecture 300 may include a plurality of portions 322 of storage material 320. Each portion 322 of storage material 320 may be associated with a corresponding memory cell of a memory array and may be positioned along the length of pillar 305 (e.g., in the z-direction) between a corresponding conductor 365 and a corresponding portion of semiconductor material (e.g., of channel 310). In some instances, storage material 320 may comprise a ferroelectric material. In some instances, portions 322 of storage material 320 may be included in a continuous composition of storage material 320 surrounding semiconductor material. Alternatively or additionally, portions 322 of storage material 320 may be discontinuous compositions of storage material 320 surrounding semiconductor material (e.g., formed between material layers 330, having corresponding discontinuous portions of dielectric material 325).

[0065] In some instances, each portion 322 of the storage material 320 may be in contact with a corresponding portion of a semiconductor material (e.g., channel 310). In some instances, each of the memory cells (e.g., associated with portion 322, SLC, MLC, TLC, QLC, or combinations thereof) is operable to store a corresponding logic state based on an electric field (e.g., polarization, charge, or a combination thereof) stored in the corresponding portion 322 of the storage material 320. In some instances, architecture 300 may include one or more dielectric materials 325 positioned between conductor 365 and portion 322 of the storage material 320. In some instances, architecture 300 may include a first select line (e.g., select line 245) operable to couple a first end of pillar 305 to a first access line (e.g., source line 260) of the memory array, and may include a second select line (e.g., select line 235) operable to couple a second end of pillar 305 to a second access line (e.g., bit line 250) of the memory array.

[0066] Therefore, by utilizing architecture 300, the memory system can support the implementation of relatively advanced and data-intensive applications. For example, by including bipolar channel 310, the memory system can support relatively fast access operations, thereby achieving more efficient data processing, reduced latency, and lower power consumption. Furthermore, the bipolar characteristics of channel 310 and storage material 320 (e.g., ferroelectric materials, charge-trapping materials, or combinations thereof) can lead to reduced processing overhead based on the ability to support more efficient memory access algorithms (e.g., in-situ write algorithms). Thus, the memory system can be configured to operate with higher capacity, reduced latency, increased lifetime, lower power consumption, and other benefits.

[0067] Figure 4A and 4B Examples of operation of an architecture 400 supporting a memory architecture with a bipolar semiconductor channel, based on the examples disclosed herein, are shown. For example, Figure 4A It can display the first set of operations performed on architecture 400, and Figure 4B This can demonstrate a second set of operations performed on architecture 400. In some instances, one or more operations performed on architecture 400 may be referred to as an in-situ write procedure, an in-situ write algorithm, or an in-situ write operation.

[0068] Architecture 400 (e.g., memory device) can be implemented reference Figures 1 to 3 Aspects of the described memory system 100, memory architecture 200, and architecture 300, or those implemented therein, are described. For example, architecture 400 may include (e.g., string 220) one or more pillars 405 and one or more activation lines 465 (e.g., word lines 265), which may be instances of pillars 305 and conductors 365, respectively. Architecture 400 may also include one or more select lines 435 (e.g., select line 235), one or more access lines 450 (e.g., bit lines 250), one or more select lines 445 (e.g., select line 245), one or more access lines 460 (e.g., source lines 260), or any combination thereof. For example, a memory device may include select lines 435-a-1 and 435-a-2 operable to couple or isolate (e.g., via corresponding transistor 230) respective first ends of one or more pillars 405 from access lines 450-a-1, and may include select lines 445-a-1 and 445-a-2 operable to couple or isolate (e.g., via corresponding transistor 240) respective second ends of one or more pillars 405 from access lines 460-a-1, and may include select lines 445-a-1 and 445-a-2 operable to couple or isolate (e.g., via corresponding transistor 240) respective second ends of one or more pillars 405 from access lines 460-a-1.

[0069] In some instances, one or more operations (such as memory access operations, programming operations, and erase operations) can be performed on architecture 400. These operations can be performed by memory controller 180 or another circuitry within the memory system. For example, an access operation may involve using one or more voltages (e.g., V). PASS V ERS V PRG This biases one or more activation lines 465 (e.g., word lines). As described herein, "bias" can refer to the process of applying a voltage to a device or component (e.g., activation line 465) to establish a reference level for its operation.

[0070] The first group of operations can be performed, such as Figure 4AThe examples illustrate this. The first set of operations may be associated with erasing logical states (e.g., clear, reset, write cell state 195-a, write "erase" state) from memory cell 410 (e.g., memory cell 205) along pillar 405-a-2. Pillar 405-a-2 may be associated with a bipolar semiconductor channel (e.g., channel 310) extending along the length of pillar 405-a-2 through activation line 465 (e.g., and select lines 435-a-2 and 445-a-2). In some instances, the first operation (e.g., erase operation) may be performed in response to (e.g., based on) a write command (e.g., received from a host system or another device), and in some instances, it may be performed before performing one or more other write operations (e.g., the erase operation may be the first step in a cell programming procedure).

[0071] In some instances, erasing the logic state may involve biasing pillar 405-a-2 with a first voltage (e.g., 0 V). In some instances, biasing pillar 405-a-2 with the first voltage may be based on (e.g., in response to) coupling pillar 405-a-2 to access line 450-a-1 (e.g., based on applying an activation voltage to select line 435-a-2). In some instances, access line 450-a-1 may be coupled to a first end of pillar 405-a-2, and the first operation may involve isolating a second end of pillar 405-a-2 (e.g., opposite to the first end) from access line 460-a-1 while the pillar is coupled to access line 450-a-1 (e.g., based on applying a deactivation voltage to select line 445-a-2). In some instances, the first operation may further include (e.g., during an erase operation) isolating a first end of pillar 405-a-1 from access line 450-a-1 (e.g., based on applying a deactivation voltage to select line 435-a-1) and isolating a second end of pillar 405-a-1 from access line 460-a-1 (e.g., based on applying a deactivation voltage to select line 445-a-1).

[0072] In some instances, the first operation may include using a second voltage (e.g., V) greater than the first voltage. ERS A second voltage (+Vg, where +Vg can be equal to +3 V) is used to bias the activation line 465-a-2. This second voltage can be based on the thickness of the storage material 320 of the pillar 405 (e.g., a ferroelectric layer, a charge trapping layer) or generated based on the electric field of the memory cell 410 (e.g., for removing electrons, for changing polarization), or both. In some instances, biasing the activation line 465-a-2 with the second voltage (e.g., where the difference between the second voltage and the first voltage is greater than a threshold voltage V2) can be configured to activate a first portion of the bipolar semiconductor channel (e.g., portion 322 associated with the memory cell 410) of the pillar 405-a-2.

[0073] In some instances, the first operation may include using a third voltage (e.g., V) that may be different from the first and second voltages. PASS +V PASS This biases one or more activation lines 465 (e.g., activation lines 465-a-1, 465-a-3, and 465-a-4) other than activation line 465-a-2. In some instances, the third voltage may also be greater than the first voltage (e.g., it may be a positive voltage), but may have a lower value than the second voltage (e.g., 2 V, which may be between the first and second voltages). In some other instances, the third voltage may be less than the first voltage (e.g., it may be a negative voltage). In some instances, biasing one or more activation lines 465 (e.g., where the difference between the third voltage and the first voltage is also greater than a threshold voltage V2, and where the difference between the third voltage and the first voltage is less than a threshold voltage V1) with the third voltage can be configured to activate one or more second portions of the bipolar semiconductor channel. In some instances, the second voltage (e.g., V...) ERS The absolute difference between the voltage and the first voltage (e.g., 0 V) ​​can be greater than the third voltage (e.g., V). PASS The absolute difference between the voltage and the first voltage (e.g., used to support changes in the storage electric field at memory cell 410, while also activating other portions of the channel along pillar 405-a-2, for example, having a lower voltage value).

[0074] In some instances, the first operation may include storing charge (e.g., positive charge, representing a logic state, representing an erase state, representing an initialization state) in one or more memory materials 320 between the bipolar semiconductor channel of activation line 465-a-2 and pillar 405-a-2. In some instances, storage may be based on biasing pillar 405-a-2 with a first voltage, biasing activation line 465-a-2 with a second voltage, and biasing other activation lines 465 with a third voltage. In some instances, erasing a logic state from memory cell 410 may be based on transferring electrons from charge-trapping storage portion 120-a. That is, the first operation may facilitate the transfer of electrons (e.g., removal of electrons) from the charge-trapping material of memory cell 410 (e.g., during a threshold duration).

[0075] Alternatively, the first operation may include storing a first polarization (e.g., a dipole polarization) in one or more storage materials 320 between the bipolar semiconductor channel of the activation line 465-a-2 and the pillar 405-a-2 (e.g., oriented the dipole 121 of the ferroelectric storage portion 120-b to support a positive electric field orientation from the activation line 465-a-2 to the pillar 405-a-2). In such an example, the first polarization may create a first dipole, wherein a negative charge concentration may be stored at a first side of the ferroelectric material and a positive charge concentration may be stored at a second side of the ferroelectric material opposite the first side. In such an example, the first side of the ferroelectric material may be oriented toward the activation line 465-a-2 (e.g., in contact with or toward the dielectric material 325), and the second side of the ferroelectric material may be oriented toward the pillar 405-a-2 (e.g., in contact with or toward the channel 310 (a portion of the bipolar channel)).

[0076] The second set of operations can be performed, such as Figure 4B The examples illustrate this. The second set of operations can be associated with writing a logical state to memory cell 410 (e.g., programming, writing cell state 195-b, writing the "programmed" state). In some instances, the second operation can be performed in response to a write command (e.g., received from a host system or another device). The second set of operations can be performed in response to (e.g.) Figure 4A The first set of operations (e.g., after, based on, or in conjunction with the first set of operations) may be executed, or may be executed independently of other operations.

[0077] In some instances, writing a logic state may involve biasing pillar 405-a-2 with a first voltage (e.g., 0 V). In some instances, biasing pillar 405-a-2 with the first voltage may be based on (e.g., in response to) coupling pillar 405-a-2 to access line 450-a-1 (e.g., based on applying an activation voltage to select line 435-a-2). In some instances, access line 450-a-1 may be coupled to a first end of pillar 405-a-2, and a second operation may involve isolating a second end of pillar 405-a-2 (e.g., opposite the first end) from access line 460-a-1 while the pillar is coupled to access line 450-a-1 (e.g., based on applying a deactivation voltage to select line 445-a-2). In some instances, the second operation may further include (e.g., during a write operation) isolating the first end of pillar 405-a-1 from access line 450-a-1 (e.g., based on applying a deactivation voltage to select line 435-a-1) and isolating the second end of pillar 405-a-1 from access line 460-a-1 (e.g., based on applying a deactivation voltage to select line 445-a-1).

[0078] In some instances, the second operation may involve using a fourth voltage (e.g., V) that is less than the first voltage.PGR A negative gate voltage (-Vg, which may be equal to -3 V) biases the activation line 465-a-2. The fourth voltage may be generated based on the thickness of the storage material 320 of the pillar 405 or based on the electric field of the memory cell 410, or both. In some instances, the activation line 465-a-2 may be coupled to the memory cell 410. In some instances, biasing the activation line 465-a-2 with the fourth voltage (e.g., where the difference between the fourth voltage and the first voltage is less than a threshold voltage V1) may be configured to activate a first portion (e.g., portion 322 associated with the memory cell 410) of the bipolar semiconductor channel (e.g., the portion of the pillar 405-a-2).

[0079] In some instances, the second operation may include using a fifth voltage (e.g., V) that may be different from the first and fourth voltages. PASS -V PASS This biases one or more activation lines 465 (e.g., activation lines 465-a-1, 465-a-3, and 465-a-4) other than activation line 465-a-2. In some instances, the fifth voltage may also be less than the first voltage (e.g., it may be a negative voltage), but may have a lower value than the second voltage (e.g., -2 V, which may be between the first and fourth voltages). In some other instances, the fifth voltage may be greater than the first voltage (e.g., it may be a positive voltage). In some instances, biasing one or more activation lines 465 (e.g., where the difference between the fifth voltage and the first voltage is also less than a threshold voltage V1, and where the difference between the fifth voltage and the first voltage is greater than a threshold voltage V2) with the fifth voltage can be configured to activate one or more second portions of the bipolar semiconductor channel. In some instances, the fourth voltage (e.g., V...) PRG The absolute difference between the voltage and the first voltage (e.g., 0 V) ​​can be greater than the third voltage (e.g., -V). PASS The absolute difference between the voltage and the first voltage (e.g., used to support changes in the storage electric field at memory cell 410 while also activating other portions of the channel along pillar 405-a-2, for example, having a lower voltage value).

[0080] In some instances, the second operation may include storing charge (e.g., negative charge, representing a logic state, representing a programmed state) in one or more memory materials 320 between the bipolar semiconductor channel of activation line 465-a-2 and pillar 405-a-2. In some instances, storage may be based on biasing pillar 405-a-2 with a first voltage, biasing activation line 465-a-2 with a fourth voltage, and biasing other activation lines 465 with a fifth voltage. In some instances, writing a logic state from memory cell 410 may be based on transferring electrons to charge-trapping storage portion 120-a. That is, the second operation may facilitate electron transfer (e.g., electron injection) into the charge-trapping material of memory cell 410 (e.g., during a threshold duration).

[0081] Alternatively, the second operation may include storing a second polarization (e.g., a dipole polarization) in one or more storage materials 320 between the activation line 465-a-2 and the bipolar semiconductor channel of the pillar 405-a-2 (e.g., oriented the dipole 121 of the ferroelectric storage portion 120-b to support a negative electric field orientation from the activation line 465-a-2 to the pillar 405-a-2). In such an example, the second polarization may create a second dipole, wherein a positive charge concentration may be stored at a first side of the ferroelectric material and a negative charge concentration may be stored at a second side of the ferroelectric material opposite to the first side. In such an example, the first side of the ferroelectric material may be oriented toward the activation line 465-a-2 (e.g., in contact with or toward the dielectric material 325), and the second side of the ferroelectric material may be oriented toward the pillar 405-a-2 (e.g., in contact with or toward the channel 310 (a portion of the bipolar channel)).

[0082] Therefore, by applying one or more of the operations described herein, memory devices can support erase and program operations at the cell-level granularity. Such improvements enable memory devices to implement in-situ write operations where data is written per cell and reduce other memory management operations (e.g., obsolete item collection). For example, data can be written directly to its final location, simplifying the write process and minimizing unnecessary data movement. Thus, such techniques can accelerate programming and reduce latency, supporting high-performance applications such as AI and real-time data processing. The techniques also reduce write amplification effects (e.g., by avoiding obsolete item collection operations), thereby enhancing the overall efficiency and lifespan of the memory system. Furthermore, the reduction in write amplification leads to lower power consumption, making the memory system more energy-efficient.

[0083] Figure 5 A block diagram 500 illustrates a memory device 520 supporting a memory architecture with a bipolar semiconductor channel, based on examples disclosed herein. The memory device 520 may be used as a reference. Figure 1Examples of aspects of the memory system (e.g., memory device) described in section 4. Memory device 520 or its various components may be examples of means for performing various aspects of a memory architecture having a bipolar semiconductor channel, as described herein. For example, memory device 520 may include write operation component 525, erase operation component 530, voltage biasing component 535, storage component 540, isolation component 545, or any combination thereof. Components of each of these components or their sub-components (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0084] Memory device 520 may support operation of the memory device according to the examples disclosed herein. Write operation component 525 may be configured or otherwise support means for writing logic state to memory cells of the memory array. In some instances, for writing, voltage bias component 535 may be configured or otherwise support means for biasing a pillar with a first voltage, the pillar being associated with a bipolar semiconductor channel extending along the length of the pillar through a plurality of active lines of the memory array. Voltage bias component 535 may be configured or otherwise support means for biasing a first active line of a plurality of active lines with a second voltage less than the first voltage, the first active line being coupled to a memory cell. Voltage bias component 535 may also be configured or otherwise support means for biasing one or more second active lines of a plurality of active lines other than the first active line with a third voltage different from the first and second voltages. The storage component 540 may be configured or otherwise support a means for storing an electric field in one or more storage materials, at least in part, based on biasing a pillar with a first voltage, biasing a first activation line with a second voltage, and biasing one or more second activation lines with a third voltage, wherein the one or more storage materials are positioned between the first activation line and the bipolar semiconductor channel.

[0085] In some instances, a first activation line is biased with a second voltage less than the first voltage to activate a first portion of the bipolar semiconductor channel. In some instances, one or more second activation lines are biased with a third voltage different from the first and second voltages to activate one or more second portions of the bipolar semiconductor channel.

[0086] In some instances, the absolute difference between the second voltage and the first voltage is greater than the absolute difference between the third voltage and the first voltage.

[0087] In some instances, the third voltage lies between the first and second voltages.

[0088] In some instances, biasing the pillar with a first voltage is at least in part based on coupling the pillar to the access lines of the memory array biased with the first voltage.

[0089] In some instances, the access line is coupled to a first end of the pillar, and the isolation component 545 may be configured or otherwise supported to provide a component for isolating a second end of the pillar from a second access line of the memory array when the pillar is coupled to the access line.

[0090] In some instances, isolation component 545 may be configured or otherwise support a means for isolating a first end of a second pillar from an access line during a write operation, the second pillar being associated with a second bipolar semiconductor channel extending along the length of the second pillar through a plurality of activation lines. In some instances, isolation component 545 may be configured or otherwise support a means for isolating a second end of a second pillar from a second access line during a write operation.

[0091] In some instances, the erase operation component 530 may be configured or otherwise support a component for erasing memory cells. In some instances, the voltage bias component 535 may be configured or otherwise support a component for biasing a pillar with a first voltage. In some instances, the voltage bias component 535 may be configured or otherwise support a component for biasing a first activation line with a fourth voltage greater than the first voltage. In some instances, the voltage bias component 535 may be configured or otherwise support a component for biasing one or more second activation lines with a fifth voltage different from the first and fourth voltages. In some instances, the storage component 540 may be configured or otherwise support a component for storing a second electric field in one or more storage materials based at least in part on biasing a pillar with a first voltage, biasing a first activation line with a fourth voltage, and biasing one or more second activation lines with a fifth voltage.

[0092] In some instances, a first activation line bias voltage greater than the first voltage is configured to activate a first portion of the bipolar semiconductor channel. In some instances, one or more second activation lines bias voltages different from the first and fourth voltages are configured to activate one or more second portions of the bipolar semiconductor channel.

[0093] In some instances, the absolute difference between the fourth voltage and the first voltage is greater than the absolute difference between the fifth voltage and the first voltage.

[0094] In some instances, the fifth voltage lies between the first and fourth voltages.

[0095] In some instances, erasure is performed in response to a write command before the write operation.

[0096] In some instances, one or more storage materials comprise charge-trapping materials, ferroelectric materials, or both.

[0097] In some instances, the storage electric field comprises a charge trapping material that stores charge in one or more storage materials.

[0098] In some instances, the storage electric field incorporates the polarization of a ferroelectric material that stores one or more storage materials.

[0099] In some instances, the described functionality of memory device 520 or its various components may be supported by or refer to at least a portion of at least one processor, wherein the at least one processor may comprise one or more processing elements (e.g., a controller, microprocessor, microcontroller, digital signal processor, state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some instances, the described functionality of memory device 520 or its various components may be implemented at least in part by instructions executable by the at least one processor (e.g., stored in memory, non-transitory computer-readable medium).

[0100] Figure 6 The flowchart illustrates a method 600 supporting a memory architecture with a bipolar semiconductor channel, based on examples disclosed herein. Operation of method 600 can be implemented by the memory system or its components described herein. For example, operation of method 600 can be achieved by referring to... Figures 1 to 5 The described memory system performs the function. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the memory system may use dedicated hardware to perform aspects of the described function.

[0101] At 605, the method may include writing logical states to memory cells of the memory array. In some instances, aspects operating at 605 may be referenced. Figure 5 The write operation component 525 described is executed.

[0102] At 610, the write operation may involve biasing the pillar with a first voltage, the pillar being associated with a bipolar semiconductor channel of multiple activation lines extending along the length of the pillar through the memory array. In some instances, aspects of operation at 610 may be described by reference. Figure 5 The write operation component 525 described is executed.

[0103] At 615, the write operation may involve biasing a first active line among a plurality of active lines with a second voltage less than a first voltage, the first active line being coupled to a memory cell. In some instances, aspects of operation at 615 may be described by reference. Figure 5 The write operation component 525 described is executed.

[0104] At 620, writing may include biasing one or more second active lines (excluding the first active line) with a third voltage different from the first and second voltages. In some instances, aspects of operating 620 can be found in the reference. Figure 5 The write operation component 525 described is executed.

[0105] At 625, writing may include storing an electric field in one or more memory materials, at least in part, based on biasing the pillar with a first voltage, biasing the first active line with a second voltage, and biasing one or more second active lines with a third voltage, wherein the one or more memory materials are located between the first active line and the bipolar semiconductor channel. In some instances, aspects of operating 625 may be described by reference. Figure 5 The write operation component 525 described is executed.

[0106] In some instances, the device described herein may perform one or more methods, such as method 600. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0107] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for writing a logic state to a memory cell of a memory array, wherein the writing comprises: biasing a pillar with a first voltage, the pillar being associated with a bipolar semiconductor channel of a plurality of activation lines extending along the length of the pillar through the memory array; biasing a first activation line of the plurality of activation lines with a second voltage less than the first voltage, the first activation line being coupled to the memory cell; biasing one or more second activation lines of the plurality of activation lines other than the first activation line with a third voltage different from the first voltage and the second voltage; and storing an electric field in one or more storage materials, the one or more storage materials being positioned between the first activation line and the bipolar semiconductor channel, at least in part based on biasing the pillar with the first voltage, biasing the first activation line with the second voltage, and biasing the one or more second activation lines with the third voltage.

[0108] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to aspect 1, wherein the first activation line bias is configured to activate a first portion of the bipolar semiconductor channel by a second voltage less than the first voltage, and the one or more second activation lines bias is configured to activate one or more second portions of the bipolar semiconductor channel by a third voltage different from the first voltage and the second voltage.

[0109] Aspect 3: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 2, wherein the absolute difference between the second voltage and the first voltage is greater than the absolute difference between the third voltage and the first voltage.

[0110] Aspect 4: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 3, wherein the third voltage is between the first voltage and the second voltage.

[0111] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 4, wherein biasing the pillar with the first voltage is at least partially based on coupling the pillar to an access line of the memory array biased with the first voltage.

[0112] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to aspect 5, wherein the access line is coupled to a first end of the pillar, and the method, apparatus, or non-transitory computer-readable medium further includes an operation, feature, circuit system, logic, component, or instruction or any combination thereof for isolating a second end of the pillar from a second access line of the memory array when the pillar is coupled to the access line.

[0113] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to aspect 6 further includes an operation, feature, circuit system, logic, component, or instruction or any combination thereof for: isolating a first end of a second pillar from the access line during the write operation, the second pillar being associated with a second bipolar semiconductor channel extending along the length of the second pillar through the plurality of activation lines; and isolating a second end of the second pillar from the second access line during the write operation.

[0114] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 7 further comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for: erasing the memory cell, wherein the erasure comprises: biasing the pillar with the first voltage; biasing the first activation line with a fourth voltage greater than the first voltage; biasing the one or more second activation lines with a fifth voltage different from the first voltage and the fourth voltage; and storing a second electric field in the one or more memory materials at least in part based on biasing the pillar with the first voltage, biasing the first activation line with the fourth voltage, and biasing the one or more second activation lines with the fifth voltage.

[0115] Aspect 9: The method, apparatus, or non-transitory computer-readable medium according to aspect 8, wherein the first activation line bias is configured to activate a first portion of the bipolar semiconductor channel with a fourth voltage greater than the first voltage, and the one or more second activation lines bias is configured to activate one or more second portions of the bipolar semiconductor channel with a fifth voltage different from the first voltage and the fourth voltage.

[0116] Aspect 10: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 7 to 9, wherein the absolute difference between the fourth voltage and the first voltage is greater than the absolute difference between the fifth voltage and the first voltage.

[0117] Aspect 11: According to any of aspects 7 to 10, the method, apparatus or non-transitory computer-readable medium, the fifth voltage is between the first voltage and the fourth voltage.

[0118] Aspect 12: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 7 to 11, wherein the erasure is performed in response to a write command prior to the writing.

[0119] Aspect 13: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 12, wherein the one or more storage materials comprise charge-trapping materials, ferroelectric materials, or both.

[0120] Aspect 14: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 13, wherein storing the electric field comprises storing charge in a charge-trapping material of the one or more storage materials.

[0121] Aspect 15: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 14, wherein storing the electric field comprises the polarization of the ferroelectric material storing the one or more storage materials.

[0122] It should be noted that the described method includes possible implementations, and the operation and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more of the method may be combined.

[0123] This describes a device. An overview of aspects of the device described herein is provided below:

[0124] Aspect 16: A memory device comprising: a plurality of conductors distributed from a substrate of the memory device along a direction, each of the plurality of conductors being associated with a corresponding of a plurality of active lines of a memory array; a pillar extending from the substrate along the direction through the plurality of conductors, the pillar comprising a semiconductor material extending along the length of the pillar and associated with a bipolar channel along the length of the pillar; and a plurality of memory portions, each of the plurality of memory portions being associated with a corresponding memory cell of the memory array and comprising one or more memory materials positioned along the length of the pillar between the corresponding of the plurality of conductors and a corresponding portion of the semiconductor material.

[0125] Aspect 17: The memory device according to aspect 16, wherein the conductivity of the bipolar channel is higher than the threshold conductivity in response to an activation voltage below a first threshold voltage, lower than the threshold conductivity in response to an activation voltage between the first threshold voltage and a second threshold voltage, and higher than the threshold conductivity in response to an activation voltage above the second threshold voltage.

[0126] Aspect 18: A memory device according to any one of aspects 16 to 17, wherein the semiconductor material comprises a transition metal dichalcogenide material.

[0127] Aspect 19: A memory device according to any one of aspects 16 to 18, wherein each of the plurality of memory portions comprises a ferroelectric material, a charge trapping material, or a combination thereof.

[0128] Aspect 20: The memory device according to aspect 19, wherein each corresponding memory cell is operable to store a corresponding logic state based at least in part on a charge stored in a corresponding portion of the charge-trapping material of the one or more storage materials, a dipole polarization stored in a corresponding portion of the ferroelectric material of the one or more storage materials, or both.

[0129] Aspect 21: A memory device according to any one of aspects 16 to 20, wherein the one or more memory materials are contained in a continuous composition of the one or more memory materials surrounding the semiconductor material.

[0130] Aspect 22: A memory device according to any one of aspects 16 to 21, wherein the semiconductor material is a semiconductor material layer surrounding the dielectric core of the pillar.

[0131] Aspect 23: A memory device according to any one of aspects 16 to 22, wherein for each of the plurality of memory portions, a memory material of the one or more memory materials is in contact with a corresponding portion of the semiconductor material.

[0132] Aspect 24: The memory device according to any one of aspects 16 to 22 further comprises: one or more dielectric materials positioned between the plurality of conductors and the plurality of memory portions.

[0133] Aspect 25: A memory device according to any one of aspects 16 to 24, further comprising: a first select line operable to couple a first end of the pillar to a first access line of the memory array; and a second select line operable to couple a second end of the pillar to a second access line of the memory array.

[0134] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols referred to throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal can represent a signal bus, where the bus can have various bit widths.

[0135] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to a relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connection, or coupling) if any conductive path exists between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connection, or coupling) may be open or closed based on the operation of the device containing the connected component. The conductive path between connected components may be a direct conductive path between the components, or it may be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, the flow of signals between connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0136] The term "coupling" (e.g., "electrical coupling") can refer to a condition that changes from an open-circuit relationship between components (where signals cannot currently travel between components via conductive paths) to a closed-circuit relationship between components (where signals can travel between components via conductive paths). If, for example, a component of a controller couples other components together, then the component triggers a change that allows signals to flow between other components via conductive paths that were previously not permitted to allow signals.

[0137] The term "isolation" refers to a relationship between components in which signals cannot currently flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, if a switch positioned between two components is turned on, then the components separated by the switch are isolated from each other. If a controller isolates two components, then the controller causes a change that prevents signals from flowing between the components using previously permitted conductive paths.

[0138] As used herein, the term "layer" or "layer step" refers to a layer or sheet of geometry (e.g., relative to a substrate). Each layer or layer step may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or layer step may be a three-dimensional structure in which two dimensions are greater than the third dimension, such as a thin film. A layer or layer step may contain different elements, components, or materials, or combinations thereof. In some instances, a layer or layer step may consist of two or more sublayers or sub-layer steps.

[0139] This document describes various dielectric materials. Each dielectric material may contain silicon oxide, silicon nitride, silicon nitride carbon, tetraethyl orthosilicate (TEOS), some other dielectric materials, or any combination thereof.

[0140] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe the connection between conditional actions, conditional procedures, or parts of a procedure.

[0141] The term "in response to" can refer to a condition or action that occurs at least partially (if not entirely) as a result of a preceding condition or action. For example, a first condition or action may be performed and a second condition or action may occur at least partially as a result of the preceding condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions that occur after the first condition or action).

[0142] Additionally, the terms "directly in response to" or "directly responding to" may refer to a condition or action occurring directly as a result of a preceding condition or action. In some instances, a first condition or action may be performed and a second condition or action may occur directly as a result of a preceding condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed and a second condition or action may occur directly as a result of a preceding condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly responding to" this other condition or action.

[0143] The devices discussed herein (including memory arrays) can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0144] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated." A transistor implemented with a bipolar channel can have two threshold voltages and can be activated when a voltage less than the first threshold voltage or greater than the second threshold voltage is applied to the transistor gate.

[0145] The descriptions presented herein, taken in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" rather than "preferred" or "superior to other instances." The "detailed description" contains specific details used to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concept of the described instances.

[0146] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by adding a hyphen after the reference numeral and a second numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0147] The functions described herein can be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions can be stored as one or more instructions (e.g., code) on or transmitted via a computer-readable medium. Due to the nature of software, the functions described herein can be implemented using software executed by a processing system, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can be physically located at various locations, including distributed portions of the functions implemented at different physical locations.

[0148] The descriptive blocks and modules described herein may be implemented or executed by one or more processors (e.g., DSP, ASIC, FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof) designed to perform the functions described herein. The processor may be an instance of a microprocessor, controller, microcontroller, state machine, or other type of processor. The processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0149] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0150] As used herein (included in the claims), the article “a” preceding a noun is open-ended and should be understood to refer to “at least one” or “one or more” of the nouns. Therefore, the terms “a,” “at least one,” “one or more,” and “at least one of one or more” are interchangeable. For example, if a claim describes a “component” performing one or more functions, then each of the individual functions can be performed by a single component or any combination of components. Therefore, the term “component” having a characteristic or performing a function can refer to “at least one of one or more components” having a particular characteristic or performing a particular function. The subsequent use of the term “the / said” to refer to a component introduced by the article “a” can refer to any or all of one or more components. For example, a component introduced by the article “a” can be understood to mean “one or more components,” and the subsequent reference to “the / said” in a claim can be understood to be equivalent to referring to “at least one of the one or more components.” Similarly, the subsequent use of the term "the / said" to refer to a component introduced as "one or more components" can refer to any or all of the one or more components. For example, the subsequent reference to "the one or more components" in a claim can be understood as equivalent to referring to "at least one of the one or more components".

[0151] Computer-readable media includes both non-transitory computer storage media and communication media, encompassing any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media or combination of media that is accessible by a computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory media or combination of media that can be used to carry or store desired program code elements in the form of instructions or data structures and are accessible by a computer or one or more processors.

[0152] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure are possible, and that the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device comprising: Multiple conductors are distributed along a direction from the substrate of the memory device, each of the multiple conductors being associated with a corresponding one of the multiple activation lines of the memory array; A pillar extending from the substrate along the direction through the plurality of conductors, the pillar comprising semiconductor material extending along the length of the pillar and associated with a bipolar channel along the length of the pillar; and A plurality of storage portions, each of which is associated with a corresponding memory cell of the memory array and includes one or more storage materials positioned along the length of the pillar between the corresponding of the plurality of conductors and a corresponding portion of the semiconductor material.

2. The memory device of claim 1, wherein the conductivity of the bipolar channel is higher than the threshold conductivity in response to an activation voltage below a first threshold voltage, lower than the threshold conductivity in response to an activation voltage between the first threshold voltage and a second threshold voltage, and higher than the threshold conductivity in response to an activation voltage above the second threshold voltage.

3. The memory device of claim 1, wherein the semiconductor material comprises a transition metal dichalcogenide material.

4. The memory device of claim 1, wherein each of the plurality of memory portions comprises a ferroelectric material, a charge trapping material, or a combination thereof.

5. The memory device of claim 4, wherein each corresponding memory cell is operable to store a corresponding logic state based at least in part on a charge stored in a corresponding portion of the charge-trapping material of the one or more storage materials, a dipole polarization stored in a corresponding portion of the ferroelectric material of the one or more storage materials, or a combination thereof.

6. The memory device of claim 1, wherein the one or more memory materials are contained in a continuous composition of the one or more memory materials surrounding the semiconductor material.

7. The memory device of claim 1, wherein the semiconductor material is a layer of semiconductor material surrounding the dielectric core of the pillar.

8. The memory device of claim 1, wherein for each of the plurality of memory portions, a memory material of the one or more memory materials is in contact with a corresponding portion of the semiconductor material.

9. The memory device according to claim 1, further comprising: One or more dielectric materials are positioned between the plurality of conductors and the plurality of storage portions.

10. The memory device of claim 1, further comprising: A first selection line, operable to couple a first end of the pillar to a first access line of the memory array; and A second selection line is operable to couple a second end of the pillar to a second access line of the memory array.

11. A method for operating a memory device, comprising: Writing logical states to memory cells of a memory array, wherein the writing includes: A first voltage is used to bias the pillar, which is associated with a bipolar semiconductor channel that extends along the length of the pillar through a plurality of activation lines in the memory array; The first activation line among the plurality of activation lines is biased by a second voltage less than the first voltage, and the first activation line is coupled to the memory cell. One or more second activation lines, excluding the first activation line, are biased using a third voltage different from the first and second voltages; and The electric field is stored in one or more storage materials, at least in part, by biasing the pillar with the first voltage, the first activation line with the second voltage, and the one or more second activation lines with the third voltage, the one or more storage materials being positioned between the first activation line and the bipolar semiconductor channel.

12. The method according to claim 11, wherein: The first activation line is biased using a second voltage less than the first voltage to activate the first portion of the bipolar semiconductor channel; and The third voltage, which is different from the first voltage and the second voltage, is used to bias the one or more second activation lines to activate one or more second portions of the bipolar semiconductor channel.

13. The method of claim 11, wherein the absolute difference between the second voltage and the first voltage is greater than the absolute difference between the third voltage and the first voltage.

14. The method of claim 11, wherein the third voltage is between the first voltage and the second voltage.

15. The method of claim 11, wherein biasing the pillar with the first voltage is at least partially based on coupling the pillar to an access line of the memory array biased with the first voltage.

16. The method of claim 15, wherein the access line is coupled to a first end of the support post, the method further comprising: When the pillar is coupled to the access line, the second end of the pillar is isolated from the second access line of the memory array.

17. The method of claim 16, further comprising: During the write operation, a first end of the second pillar is isolated from the access line, the second pillar being associated with a second bipolar semiconductor channel extending along the length of the second pillar through the plurality of activation lines; and During the write operation, the second end of the second pillar is isolated from the second access line.

18. The method of claim 11, further comprising: Erasing the memory cell, wherein the erasure includes: The support is biased using the first voltage; The first activation line is biased with a fourth voltage greater than the first voltage; The one or more second activation lines are biased using a fifth voltage different from the first voltage and the fourth voltage; and The second electric field is stored in the one or more storage materials at least in part based on biasing the pillar with the first voltage, biasing the first activation line with the fourth voltage, and biasing the one or more second activation lines with the fifth voltage.

19. The method of claim 18, wherein: The first activation line bias is configured to activate the first portion of the bipolar semiconductor channel using a fourth voltage greater than the first voltage; and The first voltage and the fourth voltage are different from the first voltage and the fourth voltage, which are used to bias the one or more second activation lines to activate one or more second portions of the bipolar semiconductor channel.

20. The method of claim 18, wherein the absolute difference between the fourth voltage and the first voltage is greater than the absolute difference between the fifth voltage and the first voltage.

21. The method of claim 18, wherein the fifth voltage is between the first voltage and the fourth voltage.

22. The method of claim 18, wherein the erase is performed in response to a write command prior to the write.

23. The method of claim 11, wherein the one or more storage materials comprise charge trapping materials, ferroelectric materials, or both.

24. The method of claim 11, wherein storing the electric field comprises storing charge in a charge trapping material of the one or more storage materials.

25. The method of claim 11, wherein storing the electric field includes storing the polarization of the ferroelectric material of the one or more storage materials.

26. A memory device comprising: One or more memory arrays; and A circuit system coupled to and configured to result in the memory device: Writing logical states into memory cells of the memory arrays in one or more memory arrays, wherein the writing includes: A first voltage is used to bias the pillar, which is associated with a bipolar semiconductor channel that extends along the length of the pillar through a plurality of activation lines in the memory array; The first activation line among the plurality of activation lines is biased by a second voltage less than the first voltage, and the first activation line is coupled to the memory cell. One or more second activation lines, excluding the first activation line, are biased using a third voltage different from the first and second voltages; and The electric field is stored in one or more storage materials, at least in part, by biasing the pillar with the first voltage, the first activation line with the second voltage, and the one or more second activation lines with the third voltage, the one or more storage materials being positioned between the first activation line and the bipolar semiconductor channel.

27. The memory device according to claim 26, wherein: The first activation line is biased by a second voltage less than the first voltage to activate the first portion of the bipolar semiconductor channel, and The third voltage, which is different from the first voltage and the second voltage, is used to bias the one or more second activation lines to activate one or more second portions of the bipolar semiconductor channel.

28. The memory device of claim 26, wherein the absolute difference between the second voltage and the first voltage is greater than the absolute difference between the third voltage and the first voltage.

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