Semiconductor device

Abstract

The invention provides a semiconductor device which comprises a bottom layer structure, a first potential barrier structure and a second potential barrier structure which are located on the upper surface of the bottom layer structure, a gate structure located on the upper surface of the first potential barrier structure, and a gate electrode located on the upper surface of the second potential barrier structure, wherein the first potential barrier structure and the second potential barrier structure are arranged side by side and jointly cover the upper surface of the bottom layer structure; the source electrode structure and the drain electrode structure are located on the two opposite sides of the grid electrode structure respectively, and the source electrode structure and the drain electrode structure are arranged at intervals with the grid electrode structure; the polarization effect intensity between the second barrier structure and the channel layer is greater than the polarization effect intensity between the first barrier structure and the channel layer. The device comprises two parts of barrier structures, and the concentration of carriers of a channel can be regulated and controlled in a segmented manner, so that the electric field at the corner of a drain electrode and the corner of a source electrode and the on-resistance of the device are reduced. And through common adjustment of the barrier layer and the stress modulation layer, the threshold voltage of the device is ensured, and the on-resistance is not influenced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device manufacturing technology, and in particular relates to a semiconductor device. Background Technology

[0002] GaN high electron mobility transistors (HEMTs) possess advantages such as wide bandgap, high breakdown field strength, high electron mobility, and high energy conversion efficiency, making them highly promising for high-frequency, high-power electronic applications. However, traditional GaN HEMTs lack effective ion doping and activation methods, making it difficult to independently control the carrier concentration under the gate (i.e., control the threshold voltage of the device) without affecting the carrier concentration in the access region (between the gate and source, and between the gate and drain). This severely limits the flexibility of GaN device design.

[0003] However, to increase the threshold voltage of a device, it is usually necessary to reduce the polarization intensity of the barrier layer and the channel layer to decrease the concentration of channel carriers. However, this increases the on-resistance of the device. How to both increase the threshold voltage and decrease the on-resistance of a device is a pressing problem that needs to be solved in the current technology. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a semiconductor device to solve the technical problem that the prior art devices cannot simultaneously increase the threshold voltage of the device and reduce the on-resistance of the device.

[0005] To achieve the above objectives, the present invention provides a semiconductor device comprising: a bottom layer, the bottom layer including at least a substrate layer and a channel layer above the substrate layer; a first barrier structure and a second barrier structure located on the upper surface of the bottom layer, the first barrier structure and the second barrier structure being arranged side by side and jointly covering the upper surface of the bottom layer; a two-dimensional electron gas being formed between the channel layer and the first barrier structure and the second barrier structure; a gate structure located on the upper surface of the first barrier structure; a source structure and a drain structure located on opposite sides of the gate structure, the source structure and the drain structure being spaced apart from the gate structure; wherein the polarization effect intensity between the second barrier structure and the channel layer is greater than the polarization effect intensity between the first barrier structure and the channel layer.

[0006] In other embodiments, the gate structure includes: a P-type gate covering the upper surface of the first barrier structure and a gate electrode covering the upper surface of the P-type gate.

[0007] In other embodiments, the gate structure includes: a gate dielectric layer covering the upper surface of the first barrier structure and a gate electrode covering the upper surface of the gate dielectric layer.

[0008] In other embodiments, the gate structure includes a gate electrode covering the upper surface of the first barrier structure.

[0009] In other embodiments, the source structure is an ohmic contact source structure, the drain structure is an ohmic contact drain structure, and the lower surfaces of the source structure and the drain structure extend to the channel layer.

[0010] In other embodiments, the first barrier structure includes a first barrier layer, the bandgap width of which is greater than the bandgap width of the channel layer.

[0011] In other embodiments, the material of the first barrier layer comprises a ternary group III nitride.

[0012] In other embodiments, the first barrier structure further includes a first stress modulation layer located between the channel layer and the first barrier layer, wherein the bandgap width of the first barrier layer is smaller than the bandgap width of the first stress modulation layer.

[0013] In other embodiments, the first stress modulation layer is made of a binary group III nitride, and the first barrier layer is made of a ternary group III nitride.

[0014] In other embodiments, the second barrier structure includes a second stress modulation layer located on the upper surface of the channel layer and a second barrier layer located on the upper surface of the second stress modulation layer, wherein the bandgap width of the second barrier layer is greater than the bandgap width of the channel layer, but smaller than the bandgap width of the second stress modulation layer.

[0015] In other embodiments, the second stress modulation layer is made of a binary group III nitride, and the second barrier layer is made of a ternary group III nitride.

[0016] In other embodiments, the second barrier structure further includes a third barrier layer located on the upper surface of the second barrier layer, the third barrier layer being used to prevent the second barrier layer from being oxidized.

[0017] In other embodiments, the second stress modulation layer is made of a binary group III nitride, the second barrier layer is made of a ternary group III nitride, the third barrier layer is made of a binary group III nitride, and the band gap width of the second stress modulation layer is greater than the band gap width of the third barrier layer.

[0018] In other embodiments, the second barrier structure includes a first portion located on a first side of the first barrier structure and a second portion located on a second side of the first barrier structure, wherein the first side and the second side are opposite sides.

[0019] In other embodiments, the second barrier structure includes a first portion located on a first side of the first barrier structure and a second portion located on a second side of the first barrier structure, wherein the first side and the second side are opposite sides.

[0020] In other embodiments, the second barrier structure includes a second stress modulation layer located on the upper surface of the channel layer and a second barrier layer located on the upper surface of the second stress modulation layer, wherein the bandgap width of the second barrier layer is greater than the bandgap width of the channel layer, but smaller than the bandgap width of the second stress modulation layer.

[0021] In other embodiments, the second stress modulation layer is made of a binary group III nitride, and the second barrier layer is made of a ternary group III nitride.

[0022] In other embodiments, the second barrier structure further includes a third barrier layer located on the upper surface of the second barrier layer, the third barrier layer being used to prevent the second barrier layer from being oxidized.

[0023] In other embodiments, the second stress modulation layer is made of a binary group III nitride, the second barrier layer is made of a ternary group III nitride, the third barrier layer is made of a binary group III nitride, and the band gap width of the second stress modulation layer is greater than the band gap width of the third barrier layer.

[0024] In other embodiments, the second barrier structure includes a first portion located on a first side of the first barrier structure and a second portion located on a second side of the first barrier structure, wherein the first side and the second side are opposite sides.

[0025] In other embodiments, the second barrier structure includes a first portion located on a first side of the first barrier structure and a second portion located on a second side of the first barrier structure, wherein the first side and the second side are opposite sides.

[0026] In other embodiments, the thickness of the second barrier structure is greater than the thickness of the first barrier structure.

[0027] In other embodiments, the thickness of the second barrier structure is less than or equal to the thickness of the first barrier structure.

[0028] In other embodiments, the projection of the gate structure onto the underlying structure lies within the projection of the first barrier structure onto the underlying structure.

[0029] In other embodiments, the minimum distance between the gate electrode side and the side of the same side of the first barrier structure is greater than or equal to 20 nm.

[0030] In other embodiments, the thickness of the first stress modulation layer and the second stress modulation layer ranges from 0.2 to 1.2 nm.

[0031] As described above, compared with conventional GaN HEMTs, the semiconductor device of the present invention includes a two-part barrier structure. These two barrier structures can segmentally control the carrier concentration in the channel, ensuring that the 2DEG concentration at the contact surface between the first barrier structure 41 and the channel layer 103 is less than the 2DEG concentration at the contact surface between the second barrier structure 42 and the channel layer 103. This reduces the electric field at the drain and source corners and the device's on-resistance. Furthermore, the introduction of a second stress modulation layer composed of a binary III nitride material below the second barrier structure 42 further improves the electron mobility and electron concentration below the second barrier layer, reducing the device's on-resistance. Similarly, the introduction of a first stress modulation layer composed of a binary III nitride material below the first barrier structure 41 further enhances the electron mobility and electron concentration below the first barrier structure 41, further reducing the device's on-resistance. That is, by jointly adjusting the barrier layer and the stress modulation layer, the carrier concentration below the gate and the carrier concentration in the access region (between the gate and source and between the gate and drain) of the device can be independently controlled, which can ensure the threshold voltage of the device without affecting the on-resistance of the device. Third, since the first barrier structure 41 and the second barrier structure 42 are formed by two separate depositions / growths, when the gate structure 20 includes a P-type gate, the P-type impurity content (peak impurity concentration) in the second barrier structure 42 is significantly lower than that in the first barrier structure 41, which further ensures the concentration and mobility of the two-dimensional electron gas 104 between the channel layer 103 and the second barrier structure 42, and further reduces the on-resistance of the device. Attached Figure Description

[0032] Figure 1 The diagram shown is a structural diagram of a HEMT device according to one embodiment of the present invention;

[0033] Figure 2 The diagram shown is a structural diagram of a HEMT device according to one embodiment of the present invention;

[0034] Figure 3 The diagram shown is a structural diagram of a HEMT device according to one embodiment of the present invention;

[0035] Figure 4 The diagram shown is a structural diagram of a HEMT device according to one embodiment of the present invention;

[0036] Figure 5 The diagram shown is a structural diagram of a HEMT device according to one embodiment of the present invention;

[0037] Figure 6 The diagram shown is a structural diagram of a HEMT device according to one embodiment of the present invention;

[0038] Figure 7 The diagram shown is a structural diagram of a HEMT device according to one embodiment of the present invention;

[0039] Figure 8 The diagram shown is a structural diagram of a HEMT device according to one embodiment of the present invention;

[0040] Figure 9 The diagram shown is a structural diagram of a HEMT device according to one embodiment of the present invention;

[0041] Figure 10 The diagram shown is a structural diagram of a HEMT device according to one embodiment of the present invention;

[0042] Figure 11 The diagram shown is a structural diagram of a HEMT device according to one embodiment of the present invention;

[0043] Figure 12 The diagram shown is a structural diagram of a HEMT device according to one embodiment of the present invention;

[0044] Figure 13 The diagram shown is a structural diagram of a HEMT device according to one embodiment of the present invention;

[0045] Figure 14 The diagram shown illustrates the structure of a HEMT device according to one embodiment of the present invention.

[0046] Figure 15 The diagram shown is a structural diagram of a HEMT device according to one embodiment of the present invention;

[0047] Figure 16 The diagram shown is a structural diagram of a HEMT device according to one embodiment of the present invention;

[0048] Figure 17 The diagram shown is a structural diagram of a HEMT device according to one embodiment of the present invention. Detailed Implementation

[0049] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] like Figure 1 As shown, this application provides a semiconductor device, the device comprising: a bottom structure 10, the bottom structure 10 including at least a substrate layer 101 and a channel layer 103 located above the substrate layer 101, and further including a first barrier structure 41 and a second barrier structure 42 located on the upper surface of the bottom structure 10, the first barrier structure 41 and the second barrier structure 42 being arranged side by side and jointly covering the upper surface of the bottom structure 10, a two-dimensional electron gas 104 being formed between the channel layer and the first barrier structure and the second barrier structure; further including a gate structure 20 located on the upper surface of the first barrier structure 41; and a source structure 21 and a drain structure 22 located on opposite sides of the gate structure 20, the source structure 21 and the drain structure 22 being spaced apart from the gate structure 20; wherein, the polarization effect intensity between the second barrier structure 42 and the channel layer 103 is greater than the polarization effect intensity between the first barrier structure 41 and the channel layer 103. Because the polarization effect intensity between the second barrier structure 42 and the channel layer 103 is greater than that between the first barrier structure 41 and the channel layer 103, the concentration of the two-dimensional electron gas 104 formed between the channel layer 103 and the first barrier structure 41 is less than the concentration of the two-dimensional electron gas 104 formed between the channel layer 103 and the second barrier structure 42. In this embodiment, for example... Figure 1 As shown, the concentration of the two-dimensional electron gas 104 is represented by dashed lines. The higher the concentration of the two-dimensional electron gas 104, the more layers of dashed lines there are. That is, the concentration of the two-dimensional electron gas 104 below the second barrier structure 42 is greater than the concentration of the two-dimensional electron gas 104 below the first barrier structure, in order to reduce the electric field at the drain corner and the on-resistance of the device. In other embodiments, the thickness of the second barrier structure is greater than the thickness of the first barrier structure. The thickness of the second barrier structure is less than or equal to the thickness of the first barrier structure. The thicknesses of the first and second barrier structures are not limited here, as long as the polarization effect intensity between the second barrier structure 42 and the channel layer 103 is greater than the polarization effect intensity between the first barrier structure 41 and the channel layer 103.

[0051] In other embodiments, such as Figure 2As shown, the substrate 101 can be made of materials such as silicon, gallium nitride, sapphire, silicon carbide, or diamond. The channel layer 103 can be made of group III nitride materials such as gallium nitride (GaN), aluminum nitride (AlN), or indium nitride (InN). Furthermore, the bottom layer structure 10 also includes a buffer layer 102 located between the substrate 101 and the channel layer 103, and corresponding to the material of the channel layer 103, to release stress caused by lattice mismatch and thermal mismatch between the channel layer 103 and the substrate 101 during epitaxial growth. Furthermore, the bottom layer structure 10 also includes a nucleation layer (not shown) located between the substrate 101 and the buffer layer 102. This nucleation layer provides uniform and ordered nucleation sites for the subsequent growth of functional layers, reduces lattice mismatch stress, and improves the crystal quality and interface properties of the thin film. When the channel layer 103 is a GaN channel layer, the buffer layer 102 can be made of materials such as Al. x Ga 1-x N buffer layer, etc., and in Al x Ga 1-xThe molar content (x) of Al in the N buffer layer can gradually decrease along the growth direction of the buffer layer 102. Since the polarization effect intensity between the first barrier structure 41 and the channel layer 103 is less than that between the second barrier structure 42 and the channel layer 103, in other words, the 2DEG concentration formed at the contact surface between the first barrier structure 41 and the channel layer 103 is less than the 2DEG concentration formed at the contact surface between the second barrier structure 42 and the channel layer 103. In this embodiment, the first barrier structure 41 and the second barrier structure 42 are arranged side-by-side and jointly cover the upper surface of the bottom layer 10. The first barrier structure 41 only includes a first barrier layer, and the band gap width of the first barrier layer is greater than the band gap width of the channel layer. The material of the first barrier layer includes ternary group III nitrides. For example, the first barrier layer can be an AlGaN barrier layer, InGaN barrier layer, InAlN barrier layer, etc., corresponding to the material of the channel layer 103. The second barrier structure 42 includes a second stress modulation layer 402 located on the upper surface of the channel layer 103 and a second barrier layer 403 located on the upper surface of the second stress modulation layer 402. The bandgap width of the second barrier layer is greater than the bandgap width of the channel layer but smaller than the bandgap width of the second stress modulation layer. The second stress modulation layer 402 is made of a binary group III nitride, such as AlN, InN, or GaN. The second barrier layer 403 is made of a ternary group III nitride. The second barrier layer 403 can be made of a material corresponding to that of the channel layer 103, such as an AlGaN barrier layer, an InGaN barrier layer, or an InAlN barrier layer. The gate structure 20 is located on the upper surface of the first barrier structure 41; the gate structure 20 can be an enhancement-mode gate structure or a depletion-mode gate structure. In this embodiment, an enhancement-mode gate structure is used as an example. Specifically, the gate structure 20 includes a P-type gate 202 covering the upper surface of the first barrier layer and a gate electrode 201 covering the upper surface of the P-type gate 202. The P-type doping of the P-type gate 202 may include, but is not limited to, carbon (C) doping, iron (Fe) doping, magnesium (Mg) doping, and zinc (Zn) doping. The projection of the gate structure onto the underlying structure lies within the projection of the first barrier structure onto the underlying structure. The minimum distance between the side of the gate electrode and the side of the same side of the first barrier structure is greater than or equal to 20 nm. The thickness of the first stress modulation layer and the second stress modulation layer ranges from 0.2 to 1.2 nm.The system also includes a source structure 21 and a drain structure 22 located on opposite sides of the gate structure 20, both of which are spaced apart from the gate structure 20. The source structure 21 is preferably an ohmic contact source structure, and the drain structure 22 is preferably an ohmic contact drain structure. Both the source structure 21 and the drain structure 22 are located on the surface of the channel layer 103. In other embodiments, both the source structure 21 and the drain structure 22 extend into the interior of the channel layer 103. The specific materials and thicknesses of the substrate layer 101, the nucleation layer, the buffer layer 102, the channel layer 103, the first barrier structure 41, and the second barrier structure 42 are not limited here and can be selected as needed. In this embodiment, since the polarization effect intensity between the first barrier structure 41 and the channel layer 103 is less than that between the second barrier structure 42 and the channel layer 103, the concentration of the two-dimensional electron gas 104 formed between the channel layer 103 and the first barrier structure 41 is less than the concentration of the two-dimensional electron gas 104 formed between the channel layer 103 and the second barrier structure 42. Furthermore, since a second stress modulation layer 402 is provided in the second barrier structure 42, the electron mobility and electron concentration of the second barrier structure 42 are further improved, and the electric field at the drain corner and the on-resistance of the device are further reduced. It should be noted that the thickness of the first barrier layer can be greater than the thickness of the second barrier layer 403, the thickness of the first barrier layer can be equal to the thickness of the second barrier layer 403, or the thickness of the first barrier layer can be less than the thickness of the second barrier layer 403. The thicknesses of the first and second barrier layers are not limited here. In addition, in this embodiment, since the first barrier structure 41 and the second barrier structure 42 are formed by two separate depositions / growths, when the gate structure 20 includes a P-type gate, the P-type impurity content (impurity concentration peak) in the second barrier structure 42 is significantly lower than the P-type impurity content in the first barrier structure 41, which further ensures the concentration and mobility of the two-dimensional electron gas 104 between the channel layer 103 and the second barrier structure 42, and further reduces the on-resistance of the device.

[0052] In other embodiments, such as Figure 3 As shown, with Figure 2The example shown differs in that the second barrier structure further includes a third barrier layer 404 located on the upper surface of the second barrier layer. The third barrier layer 404 prevents the second barrier layer 403 from being oxidized. Specifically, the second barrier structure 42 includes a second stress modulation layer 402 located on the upper surface of the channel layer 103, a second barrier layer 403 located on the upper surface of the second stress modulation layer 402, and a third barrier layer 404 located on the upper surface of the second barrier layer 403. The material of the second stress modulation layer 402 includes a binary group III nitride, for example, AlN, InN, or GaN. The material of the second barrier layer 403 includes a ternary group III nitride, and the third barrier layer 404 can be AlN, InN, or GaN. The material of the third barrier layer 404 includes binary group III nitrides. For example, the third barrier layer 404 can be AlN, InN, or GaN. Although the materials of the second stress modulation layer 402 and the third barrier layer 404 both include binary group III nitrides, the band gap width of the second stress modulation layer 403 is greater than that of the third barrier layer 404.

[0053] In other embodiments, such as Figure 4 As shown, with Figure 1 The example shown differs in that the second barrier structure 42 comprises two parts, one part located on the first side of the first barrier structure 41, and the other part located on the second side of the first barrier structure 41, wherein the first side and the second side are opposite sides. Specifically, in this example, the first barrier structure 41 also includes only the first barrier layer, and the second barrier structure 42 similarly includes a second stress modulation layer 402 located on the upper surface of the channel layer 103 and a second barrier layer 403 located on the upper surface of the second stress modulation layer 402. In this example, the first barrier structure 41, the second stress modulation layer 402, and the second barrier layer 403 are... Figure 1 The example is the same and will not be repeated here. Since the polarization effect intensity between the first barrier structure 41 and the channel layer 103 is less than that between the second barrier structure 42 and the channel layer 103, the concentration of the two-dimensional electron gas 104 formed between the channel layer 103 and the first barrier structure 41 is less than the concentration of the two-dimensional electron gas 104 formed between the channel layer 103 and the second barrier structure 42. Furthermore, since the second stress modulation layer 402 is provided in the second barrier structure 42, the electron mobility and electron concentration below the second barrier structure 42 are further improved, and the electric field at the drain and source corners and the on-resistance of the device are further reduced.

[0054] In other embodiments, such as Figure 5 As shown, with Figure 4The example shown differs in that the second barrier structure 42 further includes a third barrier layer 404. Specifically, the second barrier structure 42 includes a second stress modulation layer 402 located on the upper surface of the channel layer 103, a second barrier layer 403 located on the upper surface of the second stress modulation layer 402, and a third barrier layer 404 located on the upper surface of the second barrier layer 403. The third barrier layer 404 is used to prevent the second barrier layer from being oxidized. Figure 3 The example shown differs in that the second barrier structure 42 comprises two parts: a first part located on the first side of the first barrier structure 41, and a second part located on the second side of the first barrier structure 41, wherein the first side and the second side are opposite sides. The second stress modulation layer 402 can be AlN, InN, or GaN, etc. The second barrier layer 403 can be an AlGaN barrier layer, InGaN barrier layer, InAlN barrier layer, etc. The third barrier layer 404 can be AlN, InN, or GaN, etc. Since the polarization effect intensity between the first barrier structure 41 and the channel layer 103 is less than that between the second barrier structure 42 and the channel layer 103, the concentration of the two-dimensional electron gas 104 formed between the channel layer 103 and the first barrier structure 41 is less than that between the channel layer 103 and the second barrier structure 42. Furthermore, since the second stress modulation layer 402 is provided in the second barrier structure 42, the electron mobility and electron concentration below the second barrier structure 42 are further improved, and the electric field at the drain and source corners and the on-resistance of the device are further reduced.

[0055] In other embodiments, such as Figure 6 As shown, with Figure 2The example shown differs in that the first barrier structure 41 includes a first stress modulation layer 405 located on the upper surface of the channel layer and a first barrier layer 401 located on the upper surface of the first stress modulation layer 405. The first stress modulation layer is made of a binary group III nitride, and the first stress modulation layer 405 can be AlN, InN, or GaN, etc. The first barrier layer is made of a ternary group III nitride, and the first barrier layer 401 can be made of materials such as AlGaN, InGaN, or InAlN. It should be noted that the thickness of the first barrier layer 401 can be greater than the thickness of the second barrier layer 403, the thickness of the first barrier layer 401 can be equal to the thickness of the second barrier layer 403, or the thickness of the first barrier layer 401 can be less than the thickness of the second barrier layer 403. No limitations are placed on the thickness of the first barrier layer 401 and the thickness of the second barrier layer 403 here. The thickness of the first stress modulation layer 405 can be greater than the thickness of the second stress modulation layer 402, the thickness of the first stress modulation layer 405 can be equal to the thickness of the second stress modulation layer 402, or the thickness of the first stress modulation layer 405 can be less than the thickness of the second stress modulation layer 402. No limitation is placed on the thickness of the first stress modulation layer 405 or the thickness of the second stress modulation layer 402. In this embodiment, since the polarization effect intensity between the first barrier structure 41 and the channel layer 103 is less than the polarization effect intensity between the second barrier structure 42 and the channel layer 103, the concentration of the two-dimensional electron gas 104 formed between the channel layer 103 and the first barrier structure 41 is less than the concentration of the two-dimensional electron gas 104 formed between the channel layer 103 and the second barrier structure 42. Furthermore, since the second stress modulation layer 402 is disposed in the second barrier structure 42, the electron mobility and electron concentration of the second barrier structure 42 are further improved, and the electric field at the drain corner and the on-resistance of the device are further reduced. In this embodiment, since the first barrier structure 41 and the second barrier structure 42 are formed through two separate depositions / growths, when the gate structure 20 includes a P-type gate, the P-type impurity content (peak impurity concentration) in the second barrier structure 42 is significantly lower than the P-type impurity content in the first barrier structure 41. This further ensures the concentration and mobility of the two-dimensional electron gas 104 between the channel layer 103 and the second barrier structure 42, and further reduces the on-resistance of the device. Figure 2 Compared to the previous embodiment, since the first stress modulation layer 405 is provided in the first barrier structure 41 in this embodiment, the electron mobility and electron concentration below the first barrier structure 41 are further improved, and the on-resistance of the device is further reduced.

[0056] In other embodiments, such as Figure 7 As shown, with Figure 3The example shown differs in that the first barrier structure 41 includes a first stress modulation layer 405 located on the upper surface of the channel layer 103 and a first barrier layer 401 located on the upper surface of the first stress modulation layer 405. In this embodiment, the third barrier layer 404 is used to prevent the second barrier layer 403 from being oxidized. Figure 3 Compared to the previous embodiment, since the first stress modulation layer 405 is provided in the first barrier structure 41 in this embodiment, the electron mobility and electron concentration below the first barrier structure 41 are further improved, and the on-resistance of the device is further reduced.

[0057] As an example, such as Figure 8 As shown, with Figure 4 The example shown differs in that the first barrier structure 41 includes a first stress modulation layer 405 located on the upper surface of the channel layer 103 and a first barrier layer 401 located on the upper surface of the first stress modulation layer 405. (The last sentence appears to be incomplete and possibly contains errors.) Figure 4 Compared to the previous embodiment, since the first stress modulation layer 405 is provided in the first barrier structure 41 in this embodiment, the electron mobility and electron concentration below the first barrier structure 41 are further improved, and the on-resistance of the device is further reduced.

[0058] As an example, such as Figure 9 As shown, with Figure 5 The example shown differs in that the first barrier structure 41 includes a first stress modulation layer 405 located on the upper surface of the channel layer 103 and a first barrier layer 401 located on the upper surface of the first stress modulation layer 405. (The last sentence appears to be incomplete and possibly contains errors.) Figure 5 Compared to the previous embodiment, since the first stress modulation layer 405 is provided in the first barrier structure 41 in this embodiment, the electron mobility and electron concentration below the first barrier structure 41 are further improved, and the on-resistance of the device is further reduced.

[0059] As an example, such as Figure 10 As shown, with Figure 2 The difference in the illustrated example is that the gate structure 20 is different. In this example, the gate structure 20 is a depletion-type gate structure, and the gate structure 20 includes: a gate dielectric layer 203 covering the upper surface of the first barrier structure 41 and a gate electrode 201 covering the upper surface of the gate dielectric layer 203. Figure 10As shown, the two-dimensional electron gas (2DEG) beneath the depletion-type gate structure is continuous; that is, the dashed line is not broken. In other embodiments, the gate dielectric layer may also cover the upper surfaces (not shown) of the first barrier structure 41 and the second barrier structure 42. In other examples, the gate structure 20 only includes a gate electrode 201 (not shown) covering the upper surface of the first barrier structure 41. In this embodiment, the first barrier structure 41 and the second barrier structure 42 are defined respectively. The concentration of the two-dimensional electron gas (2DEG) beneath the first barrier structure 41 is limited by the device threshold voltage (Vth). The first barrier structure 41 has a lower 2DEG concentration, while the second barrier structure 42 has a higher 2DEG concentration to reduce the electric field at the drain corner and the on-resistance of the device. A second stress modulation layer composed of binary group III nitride material is introduced beneath the second barrier structure 42 to further improve the electron mobility and electron concentration beneath the second barrier layer, thereby reducing the on-resistance of the device.

[0060] As an example, such as Figure 11 As shown, with Figure 3 The difference between the examples shown is the gate structure. In this example, the gate structure 20 includes a gate dielectric layer 203 covering the upper surface of the first barrier structure 41 and a gate electrode 201 covering the upper surface of the gate dielectric layer 203. In other examples, the gate structure 20 only includes the gate electrode 201 (not shown in the figure) covering the upper surface of the first barrier structure 41. The third barrier layer is used to prevent the second barrier layer from being oxidized. In this embodiment, the first barrier structure 41 and the second barrier structure 42 are defined respectively. The concentration of the two-dimensional electron gas (2DEG) below the first barrier structure 41 is limited by the device threshold voltage (Vth). The first barrier structure 41 has a lower 2DEG concentration, while the second barrier structure 42 has a higher 2DEG concentration to reduce the electric field at the drain corner and the on-resistance of the device. A second stress modulation layer composed of binary group III nitride material is introduced below the second barrier structure 42 to further improve the electron mobility and electron concentration below the second barrier layer and reduce the on-resistance of the device.

[0061] As an example, such as Figure 12 As shown, with Figure 4The difference between the examples shown is the gate structure. In this example, the gate structure 20 includes a gate dielectric layer 203 covering the upper surface of the first barrier structure 41 and a gate electrode 201 covering the upper surface of the gate dielectric layer 203. In other examples, the gate structure 20 only includes the gate electrode 201 (not shown in the figure) covering the upper surface of the first barrier structure 41. In this embodiment, the first barrier structure 41 and the second barrier structure 42 are defined respectively. The concentration of the two-dimensional electron gas (2DEG) below the first barrier structure 41 is limited by the device threshold voltage (Vth). The first barrier structure 41 has a lower 2DEG concentration, while the second barrier structure 42 has a higher 2DEG concentration to reduce the electric field and the on-resistance of the device at the drain and source corners. A second stress modulation layer composed of a binary group III nitride material is introduced below the second barrier structure 42 to further improve the electron mobility and electron concentration below the second barrier layer and reduce the on-resistance of the device.

[0062] As an example, such as Figure 13 As shown, with Figure 5 The difference between the examples shown is the gate structure. In this example, the gate structure 20 includes a gate dielectric layer 203 covering the upper surface of the first barrier structure 41 and a gate electrode 201 covering the upper surface of the gate dielectric layer 203. In other examples, the gate structure 20 only includes the gate electrode 201 (not shown in the figure) covering the upper surface of the first barrier structure 41. In this embodiment, a first barrier structure 41 and a second barrier structure 42 are defined respectively. The concentration of the two-dimensional electron gas (2DEG) below the first barrier structure 41 is limited by the device threshold voltage (Vth). The first barrier structure 41 has a lower 2DEG concentration, while the second barrier structure 42 has a higher 2DEG concentration to reduce the electric field at the drain corner and the on-resistance of the device. A second stress modulation layer composed of binary group III nitride material is introduced below the second barrier structure 42 to further improve the electron mobility and electron concentration below the second barrier layer and reduce the on-resistance of the device. A first stress modulation layer composed of binary group III nitride material is introduced below the first barrier structure 41 to improve the electron mobility and electron concentration below the first barrier structure 41, which will further reduce the on-resistance of the device.

[0063] As an example, such as Figure 14 As shown, with Figure 6The difference between the examples shown is the gate structure. In this example, the gate structure 20 includes a gate dielectric layer 203 covering the upper surface of the first barrier structure 41 and a gate electrode 201 covering the upper surface of the gate dielectric layer 203. In other examples, the gate structure 20 only includes the gate electrode 201 (not shown in the figure) covering the upper surface of the first barrier structure 41. In this embodiment, a first barrier structure 41 and a second barrier structure 42 are defined respectively. The concentration of the two-dimensional electron gas (2DEG) below the first barrier structure 41 is limited by the device threshold voltage (Vth). The first barrier structure 41 has a lower 2DEG concentration, while the second barrier structure 42 has a higher 2DEG concentration to reduce the electric field at the drain corner and the on-resistance of the device. A second stress modulation layer composed of binary group III nitride material is introduced below the second barrier structure 42 to further improve the electron mobility and electron concentration below the second barrier layer and reduce the on-resistance of the device. A first stress modulation layer composed of binary group III nitride material is introduced below the first barrier structure 41 to improve the electron mobility and electron concentration below the first barrier structure 41, which will further reduce the on-resistance of the device.

[0064] As an example, such as Figure 15 As shown, with Figure 7 The difference between the examples shown is the gate structure. In this example, the gate structure 20 includes a gate dielectric layer 203 covering the upper surface of the first barrier structure 41 and a gate electrode 201 covering the upper surface of the gate dielectric layer 203. In other examples, the gate structure 20 only includes the gate electrode 201 (not shown) covering the upper surface of the first barrier structure 41. The third barrier layer is used to prevent the second barrier layer from being oxidized. In this embodiment, a first barrier structure 41 and a second barrier structure 42 are defined respectively. The concentration of the two-dimensional electron gas (2DEG) below the first barrier structure 41 is limited by the device threshold voltage (Vth). The first barrier structure 41 has a lower 2DEG concentration, while the second barrier structure 42 has a higher 2DEG concentration to reduce the electric field at the drain corner and the on-resistance of the device. A second stress modulation layer composed of binary group III nitride material is introduced below the second barrier structure 42 to further improve the electron mobility and electron concentration below the second barrier layer and reduce the on-resistance of the device. A first stress modulation layer composed of binary group III nitride material is introduced below the first barrier structure 41 to improve the electron mobility and electron concentration below the first barrier structure 41, which will further reduce the on-resistance of the device.

[0065] As an example, such as Figure 16 As shown, with Figure 8The difference between the examples shown is the gate structure. In this example, the gate structure 20 includes a gate dielectric layer 203 covering the upper surface of the first barrier structure 41 and a gate electrode 201 covering the upper surface of the gate dielectric layer 203. In other examples, the gate structure 20 only includes the gate electrode 201 (not shown in the figure) covering the upper surface of the first barrier structure 41. In this embodiment, a first barrier structure 41 and a second barrier structure 42 are defined respectively. The concentration of the two-dimensional electron gas (2DEG) below the first barrier structure 41 is limited by the device threshold voltage (Vth). The first barrier structure 41 has a lower 2DEG concentration, while the second barrier structure 42 has a higher 2DEG concentration to reduce the electric field at the drain and source corners and the on-resistance of the device. A second stress modulation layer composed of binary group III nitride material is introduced below the second barrier structure 42 to further improve the electron mobility and electron concentration below the second barrier layer and reduce the on-resistance of the device. A first stress modulation layer composed of binary group III nitride material is introduced below the first barrier structure 41 to improve the electron mobility and electron concentration below the first barrier structure 41, which will further reduce the on-resistance of the device.

[0066] As an example, such as Figure 17 As shown, with Figure 9 The difference between the examples shown is the gate structure. In this example, the gate structure 20 includes a gate dielectric layer 203 covering the upper surface of the first barrier structure 41 and a gate electrode 201 covering the upper surface of the gate dielectric layer 203. In other examples, the gate structure 20 only includes the gate electrode 201 (not shown in the figure) covering the upper surface of the first barrier structure 41. In this embodiment, a first barrier structure 41 and a second barrier structure 42 are defined respectively. The concentration of the two-dimensional electron gas (2DEG) below the first barrier structure 41 is limited by the device threshold voltage (Vth). The first barrier structure 41 has a lower 2DEG concentration, while the second barrier structure 42 has a higher 2DEG concentration to reduce the electric field at the drain and source corners and the on-resistance of the device. A second stress modulation layer composed of binary group III nitride material is introduced below the second barrier structure 42 to further improve the electron mobility and electron concentration below the second barrier layer and reduce the on-resistance of the device. A first stress modulation layer composed of binary group III nitride material is introduced below the first barrier structure 41 to improve the electron mobility and electron concentration below the first barrier structure 41, which will further reduce the on-resistance of the device.

[0067] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor device, characterized in that, The device includes: The underlying structure includes at least a base layer and a channel layer located above the base layer. A first barrier structure and a second barrier structure are located on the upper surface of the underlying structure. The first barrier structure and the second barrier structure are arranged side by side and together cover the upper surface of the underlying structure. A two-dimensional electron gas is formed between the channel layer and the first barrier structure and the second barrier structure. A gate structure located on the upper surface of the first barrier structure; The source structure and drain structure are located on opposite sides of the gate structure, and the source structure and drain structure are spaced apart from the gate structure. The polarization effect intensity between the second barrier structure and the channel layer is greater than that between the first barrier structure and the channel layer.

2. The semiconductor device according to claim 1, characterized in that, The gate structure includes: a P-type gate covering the upper surface of the first barrier structure and a gate electrode covering the upper surface of the P-type gate.

3. The semiconductor device according to claim 1, characterized in that, The gate structure includes: a gate dielectric layer covering the upper surface of the first barrier structure and a gate electrode covering the upper surface of the gate dielectric layer.

4. The semiconductor device according to claim 1, characterized in that, The gate structure includes a gate electrode covering the upper surface of the first barrier structure.

5. The semiconductor device according to claim 2, 3, or 4, characterized in that, The source structure is an ohmic contact source structure, the drain structure is an ohmic contact drain structure, and the lower surfaces of the source structure and the drain structure extend to the channel layer.

6. The semiconductor device according to claim 5, characterized in that, The first barrier structure includes a first barrier layer, wherein the band gap width of the first barrier layer is greater than the band gap width of the channel layer.

7. The semiconductor device according to claim 6, characterized in that, The material of the first barrier layer includes ternary group III nitrides.

8. The semiconductor device according to claim 6, characterized in that, The first barrier structure further includes a first stress modulation layer located between the channel layer and the first barrier layer, wherein the band gap width of the first barrier layer is smaller than the band gap width of the first stress modulation layer.

9. The semiconductor device according to claim 8, characterized in that, The first stress modulation layer is made of a binary group III nitride, and the first barrier layer is made of a ternary group III nitride.

10. The semiconductor device according to claim 6, characterized in that, The second barrier structure includes a second stress modulation layer located on the upper surface of the channel layer and a second barrier layer located on the upper surface of the second stress modulation layer, wherein the band gap width of the second barrier layer is greater than the band gap width of the channel layer, but smaller than the band gap width of the second stress modulation layer.

11. The semiconductor device according to claim 10, characterized in that, The second stress modulation layer is made of a binary group III nitride, and the second barrier layer is made of a ternary group III nitride.

12. The semiconductor device according to claim 10, characterized in that, The second barrier structure further includes a third barrier layer located on the upper surface of the second barrier layer, the third barrier layer being used to prevent the second barrier layer from being oxidized.

13. The semiconductor device according to claim 12, characterized in that, The second stress modulation layer is made of a binary group III nitride, the second barrier layer is made of a ternary group III nitride, and the third barrier layer is made of a binary group III nitride. The band gap of the second stress modulation layer is greater than the band gap of the third barrier layer.

14. The semiconductor device according to claim 10, characterized in that, The second barrier structure includes a first part located on a first side of the first barrier structure and a second part located on a second side of the first barrier structure, wherein the first side and the second side are opposite sides.

15. The semiconductor device according to claim 12, characterized in that, The second barrier structure includes a first part located on a first side of the first barrier structure and a second part located on a second side of the first barrier structure, wherein the first side and the second side are opposite sides.

16. The semiconductor device according to claim 8, characterized in that, The second barrier structure includes a second stress modulation layer located on the upper surface of the channel layer and a second barrier layer located on the upper surface of the second stress modulation layer, wherein the band gap width of the second barrier layer is greater than the band gap width of the channel layer, but smaller than the band gap width of the second stress modulation layer.

17. The semiconductor device according to claim 16, characterized in that, The second stress modulation layer is made of a binary group III nitride, and the second barrier layer is made of a ternary group III nitride.

18. The semiconductor device according to claim 16, characterized in that, The second barrier structure further includes a third barrier layer located on the upper surface of the second barrier layer, the third barrier layer being used to prevent the second barrier layer from being oxidized.

19. The semiconductor device according to claim 18, characterized in that, The second stress modulation layer is made of a binary group III nitride, the second barrier layer is made of a ternary group III nitride, and the third barrier layer is made of a binary group III nitride. The band gap of the second stress modulation layer is greater than the band gap of the third barrier layer.

20. The semiconductor device according to claim 16, characterized in that, The second barrier structure includes a first part located on a first side of the first barrier structure and a second part located on a second side of the first barrier structure, wherein the first side and the second side are opposite sides.

21. The semiconductor device according to claim 18, characterized in that, The second barrier structure includes a first part located on a first side of the first barrier structure and a second part located on a second side of the first barrier structure, wherein the first side and the second side are opposite sides.

22. The semiconductor device according to claim 1, characterized in that, The thickness of the second barrier structure is greater than the thickness of the first barrier structure.

23. The semiconductor device according to claim 1, characterized in that, The thickness of the second barrier structure is less than or equal to the thickness of the first barrier structure.

24. The semiconductor device according to claim 1, characterized in that, The projection of the gate structure onto the underlying structure lies within the projection of the first barrier structure onto the underlying structure.

25. The semiconductor device according to claim 5, characterized in that, The minimum distance between the side of the gate electrode and the side of the same side of the first barrier structure is greater than or equal to 20 nm.

26. The semiconductor device according to claim 16, characterized in that, The thickness of the first stress modulation layer and the second stress modulation layer ranges from 0.2 to 1.2 nm.

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