Semiconductor device and manufacturing method thereof
By introducing a diffusion barrier layer into a high electron mobility transistor, the Mg diffusion problem caused by Mg doping in the P-GaN layer is solved, thereby reducing gate leakage current and increasing threshold voltage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WUXI CHINA RESOURCES MICROELECTRONICS
- Filing Date
- 2024-11-08
- Publication Date
- 2026-05-12
AI Technical Summary
In high electron mobility transistors, excessive Mg doping concentration in the P-GaN layer causes Mg to diffuse into the two-dimensional electron gas, resulting in increased gate leakage current and ultimately device failure.
A diffusion barrier layer is introduced between the barrier layer and the P-GaN layer, including a compositionally graded AlGaN layer or AlInGaN layer and an undoped/doped GaN superlattice layer, to block Mg from diffusing into the two-dimensional electron gas.
It effectively blocks Mg diffusion in the P-GaN layer, reduces gate leakage current, and improves the threshold voltage stability of the device.
Smart Images
Figure CN122028481A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] High electron mobility transistors (HEMTs) are a type of field-effect transistor. Enhancement-mode HEMTs typically consist of a substrate, a GaN channel layer, an AlGaN barrier layer, and a P-GaN layer. In the GaN channel / AlGaN barrier heterostructure, the different lattice constants of the two materials generate stress at the interface. This stress leads to a polarization effect, resulting in a high concentration of two-dimensional electron gas (2DEG) near the interface. The P-GaN layer is used to modulate the band structure at the GaN channel / AlGaN barrier heterojunction to deplete the 2DEG. When a certain bias voltage is applied to the P-GaN layer, the 2DEG reappears, thus achieving the enhancement-mode performance of the device.
[0003] In the epitaxial growth of P-GaN layers, Mg doping is required, and high concentrations of Mg are needed in high-threshold voltage devices. However, excessively high Mg doping concentrations can cause Mg to easily diffuse to the two-dimensional electron gas at high temperatures, leading to increased gate leakage current and ultimately device failure. Summary of the Invention
[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0005] To at least partially solve the above-mentioned technical problems, this application provides a semiconductor device, comprising:
[0006] Substrate;
[0007] A buffer layer is located on the substrate;
[0008] A channel layer is located on the buffer layer;
[0009] A barrier layer is located on the channel layer;
[0010] A diffusion barrier layer, located on the barrier layer, includes: a compositionally graded AlGaN layer or a compositionally graded AlInGaN layer, and / or, an undoped / Mg-doped GaN superlattice layer.
[0011] A P-GaN layer is located on the diffusion barrier layer.
[0012] For example, when the diffusion barrier layer includes the composition-gradient AlGaN layer or the composition-gradient AlInGaN layer and the GaN superlattice layer including the undoped / doped Mg layer, the composition-gradient AlGaN layer or the composition-gradient AlInGaN layer is located between the barrier layer and the undoped / doped Mg GaN superlattice layer.
[0013] For example, in the direction from the barrier layer to the P-GaN layer, the Al content in the composition-gradient AlGaN layer or the composition-gradient AlInGaN layer gradually decreases.
[0014] For example, in the direction from the barrier layer to the P-GaN layer, the Al content in the composition-gradient AlGaN layer or the composition-gradient AlInGaN layer is reduced from 0.25 to 0.02.
[0015] For example, the thickness of the composition-gradient AlGaN layer or the composition-gradient AlInGaN layer ranges from 1 nm to 10 nm.
[0016] The thickness of each undoped GaN layer in the undoped / Mg-doped GaN superlattice layer ranges from 2 nm to 10 nm, and the thickness of each Mg-doped GaN layer ranges from 3 nm to 10 nm.
[0017] For example, the Mg doping concentration in each Mg-doped GaN layer in the undoped / Mg-doped GaN superlattice layer ranges from 5E18 atoms / cm². 3 -3E19atoms / cm 3 ; and / or,
[0018] The alternation period of the undoped / Mg-doped GaN superlattice layers ranges from 2 to 10.
[0019] For example, it also includes:
[0020] A stress relief layer is located on the buffer layer;
[0021] A high-resistivity layer is located on the stress-relieving layer, and the channel layer is located on the high-resistivity layer;
[0022] An insertion layer is located on the channel layer, and the barrier layer is located on the insertion layer.
[0023] Another aspect of this application provides a method for manufacturing a semiconductor device, comprising:
[0024] Provide substrate;
[0025] A buffer layer is formed on the substrate;
[0026] A channel layer is formed on the buffer layer;
[0027] A barrier layer is formed on the channel layer;
[0028] A diffusion barrier layer is formed on the barrier layer, the diffusion barrier layer comprising: a compositionally graded AlGaN layer or a compositionally graded AlInGaN layer, and / or, an undoped / Mg-doped GaN superlattice layer.
[0029] A P-GaN layer is formed on the diffusion barrier layer.
[0030] For example, the composition-gradient AlGaN layer or the composition-gradient AlInGaN layer is grown in an MOCVD reaction chamber, wherein the carrier gas is N2, H2 or a N2 / H2 mixture, the growth temperature is 1020℃-1080℃, and the growth pressure is 30mbar-150mbar.
[0031] For example, the undoped / Mg-doped GaN superlattice layer is grown in an MOCVD reaction chamber, wherein the carrier gas is N2, H2 or a N2 / H2 mixture, the growth temperature is 900℃-1200℃, and the growth pressure is 200mbar-600mbar.
[0032] The semiconductor device and its manufacturing method disclosed in this application form a diffusion barrier layer between the barrier layer and the P-GaN layer, which can increase the barrier height and thereby prevent Mg in the P-GaN layer from diffusing to the two-dimensional electron gas, thus reducing the gate leakage current of the device. Attached Figure Description
[0033] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.
[0034] In the attached image:
[0035] Figure 1 A schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of this application is shown;
[0036] Figure 2 A schematic cross-sectional view of a semiconductor device according to another exemplary embodiment of this application is shown;
[0037] Figure 3 A schematic cross-sectional view of a semiconductor device according to another exemplary embodiment of this application is shown;
[0038] Figure 4A schematic cross-sectional view of a semiconductor device according to another exemplary embodiment of this application is shown;
[0039] Figure 5 A flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of this application is shown. Detailed Implementation
[0040] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.
[0041] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0042] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0044] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures). Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the application.
[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be construed as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as interpreted in an ideal or overly formal sense, unless expressly defined herein.
[0046] To fully understand this application, a detailed structure will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.
[0047] In related technologies, to reduce gate leakage current in HEMTs, a common solution is to reduce the Mg doping concentration in the P-GaN layer, as well as the growth and annealing temperatures of the P-GaN layer. However, these solutions can lead to problems such as decreased device threshold voltage, reduced P-GaN layer crystal quality, increased defect density, and increased dynamic threshold voltage drift.
[0048] Therefore, in view of the aforementioned technical problems, this application proposes a semiconductor device, comprising:
[0049] Substrate;
[0050] A buffer layer is located on the substrate;
[0051] A channel layer is located on the buffer layer;
[0052] A barrier layer is located on the channel layer;
[0053] A diffusion barrier layer, located on the barrier layer, includes: a compositionally graded AlGaN layer or a compositionally graded AlInGaN layer, and / or, an undoped / Mg-doped GaN superlattice layer.
[0054] A P-GaN layer is located on the diffusion barrier layer.
[0055] The semiconductor device of this application has a diffusion barrier layer formed between the barrier layer and the P-GaN layer, which can increase the barrier height and thus prevent Mg in the P-GaN layer from diffusing to the two-dimensional electron gas, thereby reducing the gate leakage current of the device.
[0056] Example 1
[0057] Below, for reference Figures 1 to 4 The semiconductor devices in the embodiments of this application are described. Wherein, Figure 1 A schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of this application is shown. Figure 2 A schematic cross-sectional view of a semiconductor device according to another exemplary embodiment of this application is shown. Figure 3 A schematic cross-sectional view of a semiconductor device according to another exemplary embodiment of this application is shown. Figure 4 A schematic cross-sectional view of a semiconductor device according to another exemplary embodiment of this application is shown.
[0058] In one example, such as Figures 1 to 4 As shown, the semiconductor device of this application includes a substrate 100, a buffer layer 101, a channel layer 102, a barrier layer 103, a diffusion barrier layer, and a P-GaN layer 106, wherein: the buffer layer 101 is located on the substrate 100; the channel layer 102 is located on the barrier layer 103; the diffusion barrier layer is located on the channel layer 102 and includes: a compositionally graded AlGaN layer or a compositionally graded AlInGaN layer 104, and / or an undoped / Mg-doped GaN superlattice layer 105; the P-GaN layer 106 is located on the diffusion barrier layer.
[0059] The semiconductor device can be any suitable device known to those skilled in the art, such as an enhanced HEMT, and this application does not limit it.
[0060] In one example, substrate 100 is a bulk silicon substrate, which may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. Although several examples of materials that can form substrate 100 have been described herein, any material that can serve as a semiconductor substrate falls within the spirit and scope of this application.
[0061] In one example, the material of the buffer layer 101 includes, but is not limited to, AlN, and the buffer layer 101 is used to solve the problem of lattice mismatch between the substrate 100 and the epitaxial layer formed on the substrate 100.
[0062] In one example, the channel layer 102 is made of materials including, but not limited to, GaN, and the barrier layer 103 is made of materials including, but not limited to, AlGaN. In the GaN channel layer / AlGaN barrier layer heterostructure, stress is generated at the interface due to the difference in lattice constants between the two materials. This stress leads to a polarization effect, which in turn forms a high concentration of two-dimensional electron gas near the interface.
[0063] In one example, the P-GaN layer 106 is used to modulate the band structure at the GaN channel / AlGaN barrier heterojunction to deplete the two-dimensional electron gas. When a certain bias voltage is applied to the P-GaN layer 106, the two-dimensional electron gas reappears, thereby achieving enhanced device performance. The P-GaN layer 106 requires Mg doping during epitaxial growth.
[0064] In one example, the diffusion barrier layer comprises: a compositionally graded AlGaN layer or a compositionally graded AlInGaN layer 104, and / or, an undoped / Mg-doped GaN superlattice layer 105. Specifically, as Figure 1 As shown, the diffusion barrier layer may consist only of a compositionally graded AlGaN layer or a compositionally graded AlInGaN layer 104; or, as... Figure 2 As shown, the diffusion barrier layer may consist only of an undoped / Mg-doped GaN superlattice layer 105; or, as... Figure 3 and Figure 4As shown, the diffusion barrier layer may include a compositionally graded AlGaN layer or a compositionally graded AlInGaN layer 104 and an undoped / Mg-doped GaN superlattice layer 105. The compositionally graded AlGaN layer or the compositionally graded AlInGaN layer 104 and the undoped / Mg-doped GaN superlattice layer 105 can all increase the barrier height, thereby preventing Mg in the P-GaN layer 106 from diffusing to the two-dimensional electron gas, reducing gate leakage current of the device, and without causing a decrease in the device's threshold voltage. Exemplarily, the Mg-doped GaN layer in the undoped / Mg-doped GaN superlattice layer 105 can further increase the device's threshold voltage. It is worth noting that... Figures 2 to 4 The alternation period of the undoped / Mg-doped GaN superlattice layer 105 shown is 2, but the undoped / Mg-doped GaN superlattice layer 105 can also be any other suitable alternation period.
[0065] In one example, such as Figure 3 As shown, when the diffusion barrier layer includes a composition-gradient AlGaN layer or a composition-gradient AlInGaN layer 104 and an undoped / Mg-doped GaN superlattice layer 105, the composition-gradient AlGaN layer or the composition-gradient AlInGaN layer 104 is located between the barrier layer 103 and the undoped / Mg-doped GaN superlattice layer 105.
[0066] In another example, such as Figure 4 As shown, when the diffusion barrier layer includes a composition-gradient AlGaN layer or a composition-gradient AlInGaN layer 104 and an undoped / Mg-doped GaN superlattice layer 105, the undoped / Mg-doped GaN superlattice layer 105 is located between the barrier layer 103 and the composition-gradient AlGaN layer or the composition-gradient AlInGaN layer 104.
[0067] In one example, the undoped GaN layer in the undoped / Mg-doped GaN superlattice layer 105 is close to the barrier layer 103. Specifically, taking the diffusion barrier layer as an example where the only component is the undoped / Mg-doped GaN superlattice layer 105, the undoped GaN layer in the undoped / Mg-doped GaN superlattice layer 105 is in contact with the barrier layer 103, which can prevent Mg from extending into the barrier layer 103.
[0068] In one example, the Al content in the composition-gradient AlGaN layer or composition-gradient AlInGaN layer 104 gradually decreases in the direction from the barrier layer 103 to the P-GaN layer 106. Exemplarily, when the composition-gradient AlGaN layer or composition-gradient AlInGaN layer 104 is located between the barrier layer 103 and the undoped / Mg-doped GaN superlattice layer 105, the composition-gradient AlGaN layer or composition-gradient AlInGaN layer 104 with gradually decreasing Al content in the direction from the barrier layer 103 to the P-GaN layer 106 can reduce the lattice mismatch between the AlGaN material barrier layer 103 and the undoped / Mg-doped GaN superlattice layer 105.
[0069] In one example, the Al composition in the composition-gradient AlGaN layer or the composition-gradient AlInGaN layer 104 is reduced from 0.25 to 0.02 in the direction from the barrier layer 103 to the P-GaN layer 106.
[0070] In one example, the thickness of the composition-gradient AlGaN layer or the composition-gradient AlInGaN layer 104 ranges from 1 nm to 10 nm, or it can be any other suitable thickness range.
[0071] In one example, the thickness of each undoped GaN layer in the undoped / Mg-doped GaN superlattice layer 105 ranges from 2 nm to 10 nm, the thickness of each Mg-doped GaN layer ranges from 3 nm to 10 nm, or any other suitable thickness range.
[0072] In one example, the Mg doping concentration in each Mg-doped GaN layer of the undoped / Mg-doped GaN superlattice layer 105 ranges from 5E18 atoms / cm². 3 -3E19atoms / cm 3 ; and / or, the alternation period of the undoped / Mg-doped GaN superlattice layer 105 ranges from 2 to 10.
[0073] In one example, such as Figures 1 to 4As shown, the semiconductor device of this application further includes: a stress relief layer 107 located on a buffer layer 101; a high-resistivity layer 108 located on the stress relief layer 107, a channel layer 102 located on the high-resistivity layer 108; an insertion layer 109 located on the channel layer 102, and a barrier layer 103 located on the insertion layer 109. Exemplarily, the stress relief layer 107 is a compositionally graded AlGaN layer or an AlN / AlGaN superlattice layer, and the stress relief layer 107 can be used to relieve stress. Exemplarily, the high-resistivity layer 108 is made of C-doped GaN, and the high-resistivity layer 108 can improve the breakdown voltage performance of the device. Exemplarily, the insertion layer 109 is made of AlN, and the insertion layer 109 can improve mobility and suppress current collapse effects.
[0074] In one example, the semiconductor device of this application may further include a gate, a source, and a drain (not shown), wherein the gate is located on a P-GaN layer, and the source and drain are connected when a bias voltage greater than a threshold voltage is applied to the gate.
[0075] This concludes the introduction to the structure of the semiconductor device of this application. A complete semiconductor device may also include other components, which will not be elaborated here.
[0076] In summary, the semiconductor device of this application has a diffusion barrier layer formed between the barrier layer and the P-GaN layer, which can increase the barrier height and thus prevent Mg in the P-GaN layer from diffusing to the two-dimensional electron gas, thereby reducing the gate leakage current of the device.
[0077] Example 2
[0078] In another embodiment of this application, a method for manufacturing a semiconductor device is also provided, the method being used to manufacture the semiconductor device described in Embodiment 1.
[0079] The following reference Figures 1 to 5 A method for manufacturing a semiconductor device according to an embodiment of this application is described. First, step S1 is performed, in which a substrate 100 is provided.
[0080] The semiconductor device can be any suitable device known to those skilled in the art, such as an enhanced HEMT, and this application does not limit it.
[0081] In one example, substrate 100 is a bulk silicon substrate, which may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. Although several examples of materials that can form substrate 100 have been described herein, any material that can serve as a semiconductor substrate falls within the spirit and scope of this application.
[0082] Next, step S2 is performed to form a buffer layer 101 on the substrate 100. Exemplarily, the material of the buffer layer 101 includes, but is not limited to, AlN, and the buffer layer 101 is used to solve the problem of lattice mismatch between the substrate 100 and the epitaxial layer formed on the substrate 100.
[0083] Next, step S3 is performed to form a channel layer 102 on the buffer layer 101.
[0084] In one example, after forming the buffer layer 101 and before forming the channel layer 102, the steps of forming a stress relief layer 107 and a high-resistivity layer 108 are included. Exemplarily, the stress relief layer 107 is a compositionally graded AlGaN layer or an AlN / AlGaN superlattice layer, and the stress relief layer 107 can be used to alleviate stress. Exemplarily, the high-resistivity layer 108 is made of C-doped GaN, and the high-resistivity layer 108 can improve the breakdown voltage performance of the device.
[0085] Next, step S4 is performed to form a barrier layer 103 on the channel layer 102.
[0086] In one example, after forming the channel layer 102 and before forming the barrier layer 103, an insertion layer 109 is also formed. Exemplarily, the insertion layer 109 is made of AlN and is capable of improving mobility and suppressing current collapse effects.
[0087] In one example, the channel layer 102 is made of materials including, but not limited to, GaN, and the barrier layer 103 is made of materials including, but not limited to, AlGaN. In the GaN channel layer / AlGaN barrier layer heterostructure, stress is generated at the interface due to the difference in lattice constants between the two materials. This stress leads to a polarization effect, which in turn forms a high concentration of two-dimensional electron gas near the interface.
[0088] Next, step S5 is performed to form a diffusion barrier layer on the barrier layer 103. The diffusion barrier layer includes: a compositionally graded AlGaN layer or a compositionally graded AlInGaN layer 104, and / or an undoped / Mg-doped GaN superlattice layer 105.
[0089] In one example, such as Figure 1 As shown, the diffusion barrier layer may consist only of a compositionally graded AlGaN layer or a compositionally graded AlInGaN layer 104; or, as... Figure 2 As shown, the diffusion barrier layer may consist only of an undoped / Mg-doped GaN superlattice layer 105; or, as... Figure 3 and Figure 4 As shown, the diffusion barrier layer may include a composition-gradient AlGaN layer or a composition-gradient AlInGaN layer 104 and an undoped / Mg-doped GaN superlattice layer 105. The composition-gradient AlGaN layer or the composition-gradient AlInGaN layer 104 and the undoped / Mg-doped GaN superlattice layer 105 can all increase the barrier height, thereby preventing Mg in the P-GaN layer 106 from diffusing to the two-dimensional electron gas, reducing gate leakage current of the device without causing a decrease in the device's threshold voltage. Exemplarily, the Mg-doped GaN layer in the undoped / Mg-doped GaN superlattice layer 105 can further increase the device's threshold voltage.
[0090] In one example, the undoped GaN layer in the undoped / Mg-doped GaN superlattice layer 105 is close to the barrier layer 103. Specifically, taking the diffusion barrier layer as an example where the only component is the undoped / Mg-doped GaN superlattice layer 105, the undoped GaN layer in the undoped / Mg-doped GaN superlattice layer 105 is in contact with the barrier layer 103.
[0091] In one example, the Al content in the composition-gradient AlGaN layer or composition-gradient AlInGaN layer 104 gradually decreases in the direction from the barrier layer 103 to the P-GaN layer 106. Exemplarily, when the composition-gradient AlGaN layer or composition-gradient AlInGaN layer 104 is located between the barrier layer 103 and the undoped / Mg-doped GaN superlattice layer 105, the composition-gradient AlGaN layer or composition-gradient AlInGaN layer 104 with gradually decreasing Al content in the direction from the barrier layer 103 to the P-GaN layer 106 can reduce the lattice mismatch between the AlGaN material barrier layer 103 and the undoped / Mg-doped GaN superlattice layer 105.
[0092] In one example, the Al composition in the composition-gradient AlGaN layer or the composition-gradient AlInGaN layer 104 is reduced from 0.25 to 0.02 in the direction from the barrier layer 103 to the P-GaN layer 106.
[0093] In one example, the thickness of the composition-gradient AlGaN layer or the composition-gradient AlInGaN layer 104 ranges from 1 nm to 10 nm, for example, thicknesses of 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 8 nm, 9 nm, or 10 nm, or any other suitable thickness range.
[0094] In one example, the thickness of each undoped GaN layer in the undoped / Mg-doped GaN superlattice layer 105 ranges from 2 nm to 10 nm, and the thickness of each Mg-doped GaN layer ranges from 3 nm to 10 nm. For example, the thickness of each undoped GaN layer is 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 6.5 nm, 7 nm, 8 nm, 9 nm, or 10 nm, and the thickness of each Mg-doped GaN layer is 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 7.5 nm, 8 nm, 9 nm, or 10 nm, or any other suitable thickness range.
[0095] In one example, the Mg doping concentration in each Mg-doped GaN layer of the undoped / Mg-doped GaN superlattice layer 105 ranges from 5E18 atoms / cm². 3 -3E19atoms / cm 3 ; and / or, the alternation period of the undoped / Mg-doped GaN superlattice layer 105 ranges from 2 to 10.
[0096] In one example, a compositionally graded AlGaN layer or a compositionally graded AlInGaN layer 104 is grown in a metal-organic chemical vapor deposition (MOCVD) reaction chamber, wherein the carrier gas is N2, H2, or a N2 / H2 mixture, the growth temperature is 1020℃-1080℃, and the growth pressure is 30mbar-150mbar. Exemplarily, trimethylgallium (TMGa) is used as the Ga source, trimethylaluminum (TMAl) as the Al source, and trimethylindium (TMIn) as the In source.
[0097] In one example, an undoped / Mg-doped GaN superlattice layer 105 is grown in an MOCVD reaction chamber, wherein the carrier gas is N2, H2 or a N2 / H2 mixture, the growth temperature is 900℃-1200℃, and the growth pressure is 200mbar-600mbar.
[0098] Finally, step S6 is performed to form a P-GaN layer 106 on the diffusion barrier layer. Exemplarily, the P-GaN layer 106 is used to modulate the band structure at the GaN channel layer / AlGaN barrier layer heterojunction to deplete the two-dimensional electron gas. When a certain bias voltage is applied to the P-GaN layer 106, the two-dimensional electron gas reappears, thereby achieving enhanced device performance. The P-GaN layer 106 requires Mg doping during epitaxial growth.
[0099] This concludes the description of the key steps in the manufacturing method of the semiconductor device of this application. The manufacturing of a complete semiconductor device may also include other steps, such as the steps of forming the gate, source and drain, which will not be elaborated here.
[0100] In summary, the semiconductor device manufacturing method of this application forms a diffusion barrier layer between the barrier layer and the P-GaN layer, which can increase the barrier height and thus prevent Mg in the P-GaN layer from diffusing to the two-dimensional electron gas, thereby reducing the gate leakage current of the device.
[0101] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.
Claims
1. A semiconductor device, characterized in that, include: Substrate; A buffer layer is located on the substrate; A channel layer is located on the buffer layer; A barrier layer is located on the channel layer; A diffusion barrier layer, located on the barrier layer, includes: a compositionally graded AlGaN layer or a compositionally graded AlInGaN layer, and / or, an undoped / Mg-doped GaN superlattice layer. A P-GaN layer is located on the diffusion barrier layer.
2. The semiconductor device according to claim 1, characterized in that, When the diffusion barrier layer comprises the composition-gradient AlGaN layer or the composition-gradient AlInGaN layer and the GaN superlattice layer comprising the undoped / doped Mg layer, the composition-gradient AlGaN layer or the composition-gradient AlInGaN layer is located between the barrier layer and the undoped / doped Mg GaN superlattice layer.
3. The semiconductor device according to claim 1, characterized in that, In the direction from the barrier layer to the P-GaN layer, the Al content in the composition-gradient AlGaN layer or the composition-gradient AlInGaN layer gradually decreases.
4. The semiconductor device according to claim 3, characterized in that, In the direction from the barrier layer to the P-GaN layer, the Al content in the composition-gradient AlGaN layer or the composition-gradient AlInGaN layer is reduced from 0.25 to 0.
02.
5. The semiconductor device according to claim 1, characterized in that, The thickness range of the composition-gradient AlGaN layer or the composition-gradient AlInGaN layer is 1 nm to 10 nm. The thickness of each undoped GaN layer in the undoped / Mg-doped GaN superlattice layer ranges from 2 nm to 10 nm, and the thickness of each Mg-doped GaN layer ranges from 3 nm to 10 nm.
6. The semiconductor device according to claim 1, characterized in that, The Mg doping concentration in each Mg-doped GaN layer of the undoped / Mg-doped GaN superlattice layers ranges from 5E18 atoms / cm². 3 -3E19 atoms / cm 3 ; and / or, The alternation period of the undoped / Mg-doped GaN superlattice layers ranges from 2 to 10.
7. The semiconductor device according to claim 1, characterized in that, Also includes: A stress relief layer is located on the buffer layer; A high-resistivity layer is located on the stress-relieving layer, and the channel layer is located on the high-resistivity layer; An insertion layer is located on the channel layer, and the barrier layer is located on the insertion layer.
8. A method for manufacturing a semiconductor device, characterized in that, The method includes: Provide substrate; A buffer layer is formed on the substrate; A channel layer is formed on the buffer layer; A barrier layer is formed on the channel layer; A diffusion barrier layer is formed on the barrier layer, the diffusion barrier layer comprising: a compositionally graded AlGaN layer or a compositionally graded AlInGaN layer, and / or, an undoped / Mg-doped GaN superlattice layer. A P-GaN layer is formed on the diffusion barrier layer.
9. The manufacturing method according to claim 8, characterized in that, The composition-gradient AlGaN layer or the composition-gradient AlInGaN layer is grown in an MOCVD reaction chamber, wherein the carrier gas is N2, H2 or a N2 / H2 mixture, the growth temperature is 1020℃-1080℃, and the growth pressure is 30mbar-150mbar.
10. The manufacturing method according to claim 8, characterized in that, The undoped / Mg-doped GaN superlattice layer is grown in an MOCVD reaction chamber, wherein the carrier gas is N2, H2 or N2 / H2 mixture, the growth temperature is 900℃-1200℃, and the growth pressure is 200mbar-600mbar.