Laterally diffused metal oxide semiconductor and manufacturing method thereof

Abstract

The invention discloses a laterally diffused metal oxide semiconductor and a manufacturing method thereof, the laterally diffused metal oxide semiconductor comprises a plurality of fin parts which are arranged at intervals, each fin part is provided with a concave area, a shallow trench isolation structure located on the concave areas forms a thick oxide layer, a grid electrode crosses the fin parts, and the grid electrode is connected with the shallow trench isolation structure. Wherein the thick oxide layer is close to one side of the grid electrode and partially overlaps with the grid electrode, a source electrode and a drain electrode are respectively arranged on each fin part at two sides of the grid electrode, and the thick oxide layer extends from the grid electrode to the drain electrode.

Description

Technical Field

[0001] This invention relates to a laterally diffused metal oxide semiconductor (LDMOS), and more specifically, to a LDMOS with different fin heights and a method for manufacturing the same. Background Technology

[0002] Laterally diffused metal-oxide-semiconductor (LDMOS) is a power field-effect transistor (FET) primarily used in high-voltage, high-power radio frequency (RF) applications, such as power amplifiers in mobile communication system base stations. It maintains stable operation and reliability even at extremely high breakdown voltages. A key feature of LDMOS is the presence of a thick oxide layer, such as a field oxide layer or shallow trench isolation (STI), beneath the gate near the drain terminal. This prevents breakdown caused by electric field concentration on the drift region surface at the channel end. Furthermore, by controlling the doping concentration of the lateral and longitudinal PN junctions and the thickness of the drift region in the LDMOS, the drift region can be completely depleted before the lateral junction reaches the critical breakdown voltage, effectively reducing the surface electric field and significantly increasing the drain breakdown voltage.

[0003] However, fabricating LDMOS into a FinFET (Fin Field-Effect Transistor) presents challenges in forming the aforementioned thick oxide layer structure. This is because the thick oxide layer is typically created by thermal oxidation, where the silicon substrate surface reacts with oxygen. Fin structures, compared to planar structures, have more boundaries and corners, resulting in a more complex stress distribution. These factors make it extremely difficult to form a uniformly thick oxide layer on the fin structure. Therefore, those skilled in the art need to improve the existing LDMOS structure and fabrication process to address these issues. Summary of the Invention

[0004] In view of the problems encountered in the prior art, the present invention proposes a novel laterally diffused metal-oxide-semiconductor (LDMOS) structure, characterized by achieving the formation of the thick oxide layer through a deposition process by reducing the fin height of the thick oxide layer region. The thick oxide layer formed by this method has a uniform thickness, meeting the requirements of high-voltage or high-power field-effect transistors. Furthermore, the thickness of the thick oxide layer can be easily fine-tuned during the fabrication process by changing the fin height and the deposition thickness, making it easier to fabricate LDMOS devices with different on-resistances (RDS(on)) and breakdown voltages (BVD) to meet the diverse applications of LDMOS devices.

[0005] One aspect of the present invention is to provide a laterally diffused metal-oxide semiconductor, comprising: a substrate having a plurality of fins spaced apart in a first direction and extending in a second direction, wherein each fin has a recessed region; a shallow trench isolation structure surrounding the fins, wherein the shallow trench isolation structure located on the recessed regions forms a thick oxide layer; a gate extending in the first direction across the fins, the gate having a first side and a second side on both sides in the second direction, wherein the thick oxide layer is close to the second side, and the gate partially overlaps with the thick oxide layer on each fin in a direction perpendicular to the substrate; and a source and a drain located in each of the fins on the first side and the second side, respectively, wherein the thick oxide layer extends from the second side of the gate to the drain.

[0006] Another aspect of the present invention is to provide a method for fabricating a laterally diffused metal-oxide-semiconductor, comprising: providing a substrate having a plurality of fins spaced apart in a first direction and extending in a second direction; performing a first photolithography process to reduce the height of the fins in a recessed region; forming a dielectric layer on the fins, wherein the dielectric layer on the fins in the recessed region constitutes a thick oxide layer; performing a second photolithography process to reduce the height of the dielectric layer not located in the recessed region, such that the dielectric layer becomes a shallow trench isolation structure, and the fins not located in the recessed region protrude from the shallow trench isolation structure; forming a gate extending in the first direction across the fins, wherein the gate has a first side and a second side on both sides in the second direction, wherein the thick oxide layer is close to the second side, and the gate partially overlaps with the thick oxide layer on each fin in a direction perpendicular to the substrate; and forming a source and a drain in each fin on the first side and the second side, respectively.

[0007] These and other objects of the present invention should become more apparent to the reader after reading the detailed description of the preferred embodiments, which are illustrated in various figures and drawings below. Attached Figure Description

[0008] Figure 1 This is a layout diagram of the LDMOS according to Embodiment 1 of the present invention;

[0009] Figure 2 This is a schematic cross-sectional view of the LDMOS along the X-X' section in Embodiment 1 of the present invention;

[0010] Figure 3 This is a schematic cross-sectional view of the LDMOS along the Y1-Y1', Y2-Y2', and Y3-Y3' lines in Embodiment 1 of the present invention.

[0011] Figure 4This is a complete cross-sectional schematic diagram of an LDMOS according to Embodiment 1 of the present invention;

[0012] Figure 5 This is a cross-sectional schematic diagram of an LDMOS with a metal gate according to another embodiment of the present invention;

[0013] Figures 6 to 11 This is a cross-sectional schematic diagram of the fabrication process of LDMOS according to Embodiment 1 of the present invention.

[0014] It should be noted that all illustrations in this specification are for illustrative purposes. For clarity and ease of illustration, the size and scale of the components in the illustrations may be exaggerated or reduced. Generally, the same reference symbols in the illustrations are used to indicate corresponding or similar component features in modified or different embodiments.

[0015] Symbol Explanation

[0016] 100 base

[0017] 102 Shallow trench isolation structure

[0018] 104 Gate oxide layer

[0019] 106 thick oxide layer

[0020] 108 P-type trap

[0021] 110 N-type drift zone

[0022] 112 partition wall

[0023] 116 Interface Layer

[0024] 118 High Dielectric Constant Layer

[0025] 120 Barrier Layer

[0026] 122 First photoresist

[0027] 124 dielectric layer

[0028] 126 Second photoresist

[0029] B base

[0030] d1 First direction

[0031] d2 Second direction

[0032] D drain

[0033] F fin

[0034] G gate

[0035] MG filled metal layer

[0036] R-shaped depression area

[0037] S source pole

[0038] t thickness Detailed Implementation

[0039] Exemplary embodiments of the present invention will now be described in detail below, with reference to the accompanying drawings illustrating the described features to enable the reader to understand and achieve the technical effects. The reader will understand that the descriptions herein are merely illustrative and are not intended to limit the scope of the invention. Various embodiments of the invention and various non-conflicting features thereof can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the invention will be understood by those skilled in the art without departing from the spirit and scope of the invention, and are intended to be included within the scope of the invention.

[0040] Readers should readily understand that the meanings of "on," "above," and "above" in this context should be interpreted broadly. "On" not only means "directly on" something, but also includes being "on" something with an intervening feature or layering structure. Similarly, "above" or "above" not only means "above" or "above" something, but also includes being "above" or "above" something without an intervening feature or layering structure (i.e., directly on something). Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," and "upper part" may be used herein to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.

[0041] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a extent smaller than that of the structure below or above. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any opposing horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along an inclined surface. A substrate may be a layered structure, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0042] Readers can generally understand the terminology used in this invention, at least in part, from its usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a," "an," "the," or "described" can also be understood to convey either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0043] Readers will better understand that when words such as "comprising" and / or "containing" are used in this specification, they expressly define the presence of the stated features, areas, wholes, steps, operations, elements and / or components, but do not preclude the possibility of the presence or addition of one or more other features, areas, wholes, steps, operations, elements, components and / or combinations thereof.

[0044] The text uses designations such as "N" and "P," generally referring to "N-type" and "P-type" to indicate donor and acceptor dopants that promote electron-hole exchange as the primary carriers. Examples include P-type boron (B) atoms and N-type phosphorus (P) and arsenic (As) atoms. A dopant type ending in "++" indicates a higher doping concentration than dopants ending in "+". Conversely, a dopant type ending in "-" indicates a lower doping concentration than dopants without a suffix.

[0045] First, please refer to... Figure 1This is a layout diagram of a laterally diffused metal-oxide semiconductor (LDMOS) according to an embodiment of the present invention. As shown, the LDMOS of the present invention is generally composed of multiple fins F and a gate G. The fins F are arranged in parallel at intervals in a first direction d1, and their long axes extend in a second direction d2, which is preferably orthogonal to the first direction d1. The gate G extends in the first direction d1 past the fins F, and the fins F are exposed on both sides of the gate G in the second direction d2. The fins F exposed on one side serve as the source S of the LDMOS, and the fins F exposed on the other side serve as the drain D of the LDMOS. In this embodiment of the present invention, the LDMOS has a recessed region R on the side near the drain D. This recessed region R is the area where the thick oxide layer required for the LDMOS of the present invention is pre-formed. This thick oxide layer can be a shallow trench isolation (STI) structure. The recessed region R encompasses the overlapping area of ​​the gate G and fin F on the drain side, as well as a portion of the fin F extending from that side, i.e., the so-called lateral diffusion region. In subsequent embodiments, the structure and components of the LDMOS of the present invention will be illustrated using cross-sections made by the three slits X-X', Y1-Y1', Y2-Y2', and Y3-Y3' shown in the figures. The cross-section X-X' covers the LDMOS structure along the long axis of the fin F; the cross-section Y1-Y1' covers the fin F structure generally not covered by the gate G; the cross-section Y2-Y2' covers the structure at the overlapping portion of the gate G and fin F; and the cross-section Y3-Y3' covers the structure with the aforementioned thick oxide layer to be formed.

[0046] Please refer to Figure 2 This is a schematic cross-sectional view of the LDMOS element described above along the X-X' line according to an embodiment of the present invention. It should be noted that this figure only shows the shape of the fin F and the gate G components and their relative relationship; the various doped regions of other components will be described in subsequent figures.

[0047] like Figure 2As shown, the LDMOS of the present invention includes a substrate 100 as the basis for the components to be formed thereon. The substrate 100 is preferably made of silicon, such as a P-type doped (P-) silicon substrate, but other silicon-containing substrates, such as silicon-on-insulator (SOI) substrates, or other doped substrates, may also be used, without limitation. A fin F protrudes upward on the substrate 100, and the fin is surrounded by a shallow trench isolation structure 102. The portion of the fin exposed from the shallow trench isolation structure 102 serves as the active region of the device. The shallow trench isolation structure 102 may be made of silicon oxide, which defines and isolates different fins F. A gate G is disposed above the fin F, and the fins F exposed on both sides of the gate G are the source S and drain D of the device, respectively. A gate oxide layer 104 is provided between the gate G and the fin F to isolate them. The gate oxide layer 104 can be made of silicon oxide (as in the case of a polysilicon gate) or a high dielectric constant material (as in the case of a metal gate). In this embodiment, the gate G can be made of polysilicon.

[0048] It should be noted that in this embodiment of the invention, the fin F has a recessed region R located on the side near the drain D, which partially overlaps with the gate G in the vertical direction. A thick oxide layer 106 is formed in the recessed region R, which may be composed of a portion of the shallow trench isolation structure 102, but its height is higher than the surrounding shallow trench isolation structure 102. One side of the thick oxide layer 106 overlaps with the gate G in the vertical direction, and the other side extends beyond the gate G and connects to the drain D. The portion of the thick oxide layer 106 that overlaps with the gate G also connects to the gate oxide layer 104 near the source end, and the two together serve as an insulating layer between the gate G and the substrate 100. As can be seen from the figure, due to the presence of the thick oxide layer 106 extending beyond the gate G, the distance between the drain D and the gate G is greater than the distance between the source S and the gate G, which helps to improve the breakdown voltage of the LDMOS device, thereby improving the power performance and reliability of the device. Furthermore, the thick oxide layer 106 has a thickness t in the vertical direction, which is greater than the thickness of the adjacent gate oxide layer 104 in the vertical direction. Since the thick oxide layer 106 is formed due to the presence of the recessed region R in this invention, its thickness t is preferably greater than or equal to the depth of the recessed region R, as will be further explained in subsequent fabrication process embodiments. The thick oxide layer 106 can prevent the LDMOS device from experiencing breakdown due to the concentration of the surface electric field in the drift region at the channel end.

[0049] Next, please refer to Figure 3 It shows from left to right the components from... Figure 1The LDMOS structure is shown in the figure, with cross-sections Y1-Y1', Y2-Y2', and Y3-Y3'. As shown, the fin F protrudes upward from the substrate 100 beyond the surrounding shallow trench isolation structure 102 to form the active region. In this embodiment of the invention, it should be noted that the height of the fin F in the Y3-Y3' cross-section is lower than the height of the fin F in the Y1-Y1' and Y2-Y2' cross-sections, which is where the aforementioned recessed region R is located. The shallow trench isolation structure 102 located above the lower fin F (Y3-Y3' cross-section) serves as the thick oxide layer 106 of the LDMOS element, which can be connected to the shallow trench isolation structure 102 surrounding the fin F below, and the two can be considered as the same dielectric structure. The portion of the thick oxide layer 106 overlapping with the gate G can be considered as a field plate structure, which makes the electric field on the surface of the depletion region of the element more dispersed, which is beneficial to increasing the width of the depletion region. On the other hand, the oxide layer located above the general fin F (Y2-Y2' section) is the gate oxide layer 104, which is conformally formed on the exposed surface of the fin F and is in contact with the thick oxide layer 106 in the Y3-Y3' section (see...). Figure 2 The thickness of the thick oxide layer 106 is t, which may be greater than or equal to the depth of the recessed region R. Depending on the fabrication process used, the height of the thick oxide layer 106 may be less than, equal to, or greater than the height of the adjacent gate oxide layer 104, and is not limited thereto. For example, in Figure 3 In one embodiment, the height of the thick oxide layer 106 is equal to the height of the gate oxide layer 104. Figure 4 In this embodiment, the height of the thick oxide layer 106 is lower than the height of the gate oxide layer 104. As can also be seen from the figure, the gate G located on the thick oxide layer 106 (i.e., on the recessed region R) does not extend downward into the space between the fins F to form a three-dimensional channel structure.

[0050] Next, please refer to Figure 4 This is a cross-sectional schematic diagram of a complete LDMOS according to Embodiment 1 of the present invention. In addition to the components and features described in the foregoing embodiments, the LDMOS structure of the present invention also includes a P-well 108 and an N-drift region 110, which are respectively located in the fins F on both sides of the gate G. More specifically, the P-well 108 is located in the fin F on the source S side of the gate G, and it can overlap with part of the gate in the vertical direction and extend horizontally to the trench isolation structure outside the fin F. The P-well 108 can be formed by P-type doping of this region, such as doping with boron (B), with a doping concentration higher than that of the P-type substrate 100. The function of the P-well 108 is to help more effectively control the current flow in the N-type LDMOS element channel, avoid interference between different elements, and adjust the critical voltage of the NMOS.

[0051] On the other hand, the N-type drift region 110 is located in the fin F on the side of the gate G near the drain D. It can overlap with part of the gate G in the vertical direction and extends horizontally to the trench isolation structure outside the fin F. Its extension range is greater than that of the aforementioned P-type well 108, so as to lengthen the channel distance between the gate G and the drain D. It should be noted that, although Figure 4 The boundary 110a of the N-type drift region 110 is located between the gate oxide layer 104 and the thick oxide layer 106. However, in some embodiments, the boundary 110a of the N-type drift region 110 may be located below the gate oxide layer 104 or below the thick oxide layer 106, as shown by the dashed line in the figure, and is not limited thereto. In some embodiments, the N-type drift region 110 may be connected to the P-type well 108. The N-type drift region 110 can be formed by lightly doping the region with N-type dopant, such as by doping with phosphorus (P) or arsenic (As). In embodiments, the N-type drift region 110 may form a lateral and longitudinal PN junction with the adjacent P-type substrate 100 and / or P-type well 108. In this way, during high-voltage operation, the N-type drift region 110 can be completely depleted before the lateral PN junction reaches the critical breakdown voltage, thereby reducing the surface electric field (RESURF) and significantly increasing the breakdown voltage of the drain terminal.

[0052] Rereference Figure 4 The drain (D) and source (S) of the LDMOS are formed on the aforementioned N-type drift region 110 and P-type well 108, respectively. A thick oxide layer 106 separates the drain (D) from the gate (G), increasing the distance between them. The source (S) is connected to the other side of the gate (G) (or separated by a spacer wall 112). Both the drain (D) and source (S) can be heavily N-type doped regions (N+), with a doping concentration greater than that of the N-type drift region 110. The source (S) is the current input terminal, and the drain (D) is the current output terminal. Furthermore, in this embodiment, the outer fin F of the source (S) also has a base (bulk) B, which is also formed in the P-type well 108 and can be connected to the source (S). In some embodiments, the base (B) and source (S) can also be separated by an isolation structure (such as a shallow trench isolation structure). The base B can be a heavily p-type doped region (P+), with a doping concentration greater than that of the p-type well 108, serving as a pick-up terminal for the p-type well 108. Furthermore, in some embodiments, to increase carrier mobility in the channel, the drain D, source S, and base B can be formed on a strained silicon structure. For example, the N-type drain D and source S are formed on a tensile-stressed silicon phosphide (SiP) epitaxial layer, and the p-type base B is formed on a compressive-stressed silicon-germanium (SiGe) epitaxial layer. Additionally, to reduce contact resistance, metal silicide structures, such as cobalt silicide (CoSi) or nickel silicide (NiSi), can be additionally formed on the drain D, source S, and base B. During operation, the drain D terminal is connected to the device's operating voltage (V... DDThe source (S) and base (B) are connected together to a reference voltage (V). SS For example, ground voltage (GND) can range from 0 to V. DD The potential between them. The gate G is related to the circuit's supply voltage (V). CC Connections are allowed, but not limited to these.

[0053] Please refer to now. Figure 5 This is a cross-sectional schematic diagram of an LDMOS according to another embodiment of the present invention. Unlike the polysilicon gate G of the aforementioned embodiments, the LDMOS structure of the present invention can also be used in the design of metal gates. For example... Figure 5 As shown, the original polysilicon gate G in the LDMOS structure can be replaced with a metal gate structure using a metal gate replacement fabrication process. This structure can sequentially include an interface layer 116, a high-k dielectric layer 118, a barrier layer 120, and a filler metal layer MG. Preferably, the interface layer 116, the high-k dielectric layer 118, and the barrier layer 120 are formed conformally on the surface of the gate trench, while the filler metal layer MG fills the remaining trench space. In this embodiment, the interface layer 116 can be made of silicon oxide, which helps improve the interface quality between the metal gate and surrounding components and reduces defect density. The high-k dielectric layer 118 can be made of hafnium oxide (HfO2), which provides higher capacitance and improves the switching speed and performance of the device. The barrier layer 120, in addition to blocking the diffusion of the filler metal, can also serve as a work function layer to adjust the work function of the metal gate, achieving precise control of the critical voltage. Depending on the type and application, the material of a field-effect transistor (FET) can be a metal nitride, including tantalum nitride, molybdenum nitride, tungsten nitride, tantalum carbide, tantalum nitride carbide, titanium aluminum nitride, or a combination of the above materials. It may also have a multilayer structure, and is not limited thereto. The filler metal layer (MG) serves as the main contact area between the metal gate and the external circuitry. It can reduce contact resistance and improve the overall strength of the gate structure. Tungsten can be used as the material for this filler metal layer.

[0054] Having described the structure of the LDMOS of the present invention above, the following embodiments will be referred to in sequence. Figures 6 to 11 The fabrication process of the LDMOS of this invention will be explained below. These illustrations will use the Y2-Y2' cross-section (the general overlap of the gate G and fin F) and the Y3-Y3' cross-section (the overlap of the gate G and fin F to form a thick oxide layer) as examples to illustrate the evolution and formation of the fin F and the thick oxide layer 106 spanned by the gate G in the LDMOS of this invention during the fabrication process. It should be noted that the fabrication processes for the various doped regions mentioned above will be omitted in these illustrations to avoid obscuring the focus of this invention.

[0055] First, please refer to... Figure 6The fabrication process begins with a substrate 100 as the basis for the LDMOS device of this invention. The substrate 100 is preferably made of silicon, such as a P-doped (P-) silicon substrate. Next, multiple fins F are formed on the substrate 100, these fins F being arranged in parallel at intervals and extending in the same direction. The fins F can be formed by a photolithography process on the substrate 100, for example, using a photoresist with a fin pattern as an etching mask to perform an anisotropic dry etching process on the substrate 100, which can be reactive ion etching or plasma etching. In this step, the fins F formed in both cross-sectional regions will have the same height. After the fins F are formed, an ion implantation process can be performed to form the aforementioned P-type well and N-type drift region (not shown) in the fins F.

[0056] Please refer to Figure 7 After the fins F are formed, a first photolithography process P1 is performed to remove a portion of the fins F in the Y3-Y3' cross-sectional region, thereby reducing the height of these fins F. This first photolithography process P1 may include first forming a first photoresist 122 on the Y2-Y2' cross-sectional region, and then performing an anisotropic dry etching process on the Y3-Y3' cross-sectional region not covered by the first photoresist 122, thus reducing the height of the fins F in this region. The reduced fins F will form as shown in the image. Figure 2 The recessed region R shown has a depth approximately equal to the thickness t of the subsequent thick oxide layer 106 to be formed. Thus, the fins F in the two cross-sectional regions have different heights. This invention allows for precise control of the descent depth of the fins F in the Y3-Y3' cross-sectional region through this step, thereby determining the thickness of the subsequent thick oxide layer to be formed. This is one of the advantages of this invention.

[0057] Please refer to Figure 8 After the recessed region R is formed, a dielectric layer 124, such as a silicon oxide layer, is then formed on the fins F. The dielectric layer 124 covers the entire fins F and fills the space between them. The dielectric layer 124 can be formed by depositing dielectric material using a CVD process followed by a CMP process. For the Y3-Y3' cross-sectional region, depending on the extent to which the dielectric layer 124 is removed by the CMP process, the height of the formed dielectric layer 124 can be equal to or higher than the height of the fins F in the Y3-Y3' cross-sectional region. These dielectric layers 124 will subsequently become shallow trench isolation structures that isolate each fin F. On the other hand, for the Y3-Y3' cross-sectional region, in addition to serving as a shallow trench isolation structure, since the height of the fins F is relatively low there, a dielectric layer 124 of a certain thickness will be located above the top surface of the fins F after this step. This portion of the dielectric layer 124 serves as the thick oxide layer required for the LDMOS of this invention, and its thickness can be precisely controlled in this step, which is one of the advantages of this invention.

[0058] Please refer to Figure 9 After the dielectric layer 124 is formed, a second photolithography process P2 is performed to remove a portion of the dielectric layer 124 in the Y2-Y2' cross-sectional region, thereby reducing the height of the dielectric layer 124 and forming a shallow trench isolation structure 102 located between and around the fins F. This second photolithography process P2 may include first forming a second photoresist 126 on the Y3-Y3' cross-sectional region, and then performing an anisotropic dry etching process on the Y2-Y2' cross-sectional region not covered by the second photoresist 126, thus reducing the height of the dielectric layer 124 to below the fins F and forming the shallow trench isolation structure 102. For the Y3-Y3' cross-sectional region, since it is covered by the second photoresist 126, the dielectric layer 124 on the Y3-Y3' cross-sectional region is not affected by the second photolithography process P2. Thus, for this region, the dielectric layer 124 located between and around the fins F serves as a shallow trench isolation structure 102, with a height higher than the shallow trench isolation structure 102 on the Y2-Y2' cross-sectional area, while the dielectric layer 124 located above the top surface of the fins F serves as a thick oxide layer 106 for the LDMOS.

[0059] Please refer to Figure 10 After the thick oxide layer 106 is formed, the gate dielectric layer 104 of the LDMOS device is then formed on the fin F surface in the Y2-Y2' cross-sectional region. The gate dielectric layer 104 can be made of silicon oxide (as in the case of a polysilicon gate) or a high-dielectric-constant material (as in the case of a metal gate). It can be formed by thermal oxidation, whereby the silicon fin F surface reacts with oxygen, or by deposition methods such as CVD. The gate dielectric layer 104 formed in this step may also be formed on the surface of the thick oxide layer 106 and integrated with it. The gate dielectric layer 104 formed in the Y2-Y2' cross-sectional region is connected to the thick oxide layer 106 in the Y3-Y3' cross-sectional region, such as... Figure 2 As shown. It should be noted that if the previous CMP fabrication process grinds the thick oxide layer 106 on the Y3-Y3' cross-sectional region to a height flush with the fin F on the Y2-Y2' cross-sectional region, the height of the gate dielectric layer 104 formed on the Y2-Y2' cross-sectional region in this step will be higher than the height of the thick oxide layer 106. Furthermore, in the metal gate replacement fabrication process, the gate dielectric layer 104 is formed only after the polysilicon gate has been removed.

[0060] Please refer to Figure 11After the gate dielectric layer 104 is formed, the gate G is then formed on the gate dielectric layer 104 and the thick oxide layer 106. The gate G can be made of polysilicon, which is formed by first depositing a polysilicon material layer using an LPCVD process, and then patterning the polysilicon material layer into a gate pattern using a photolithography process. As can be seen from the figure, the gate G in the Y2-Y2' cross-sectional region extends into the space between the fins F to form a three-dimensional channel structure, while the gate G in the Y3-Y3' cross-sectional region is located on the thick oxide layer 106.

[0061] As can be seen from the structure and method described in the foregoing embodiments, the present invention reduces the fin height in a specific area and simultaneously forms a thick oxide layer with a shallow trench isolation structure. The thickness of the thick oxide layer formed can be precisely controlled and uniformly consistent in the manufacturing process of reducing the fin height and the manufacturing process of depositing the shallow trench isolation structure. This overcomes many disadvantages of the prior art in forming a thick oxide layer by oxidizing the fin with thermal oxidation, which is the novelty and progress of the present invention.

[0062] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A laterally diffused metal-oxide semiconductor, comprising: A base having a plurality of fins spaced apart in a first direction and extending in a second direction, wherein each of the fins has a recessed area; Shallow groove isolation structures surround the fins, wherein the shallow groove isolation structures located on the recessed areas constitute a thick oxide layer; A gate extending in the first direction across the fins, the gate having a first side and a second side on either side in the second direction, wherein the thick oxide layer is close to the second side, and the gate partially overlaps with the thick oxide layer on each fin in a direction perpendicular to the substrate; and The source and drain are located in each of the fins on the first side and the second side, respectively, wherein the thick oxide layer extends from the second side of the gate to the drain.

2. The laterally diffused metal-oxide semiconductor of claim 1, further comprising a P-type well located in each of the fins near the first side.

3. The laterally diffused metal-oxide semiconductor of claim 1, further comprising an N-type drift region located in each of the fins near the second side.

4. The laterally diffused metal oxide semiconductor of claim 3, wherein the boundary of the N-type drift region is located below the thick oxide layer.

5. The laterally diffused metal-oxide semiconductor of claim 1, further comprising a base located in each of the fins outside the source electrode.

6. The laterally diffused metal-oxide semiconductor of claim 5, further comprising a source epitaxial layer and a base epitaxial layer located on each of the fins on the first side, the source epitaxial layer being located between the gate and the base epitaxial layer, the source being located in the source epitaxial layer, and the base being located in the base epitaxial layer.

7. The laterally diffused metal-oxide semiconductor of claim 1, further comprising a drain epitaxial layer located in each of the fins on the second side, the thick oxide layer located between the gate and the drain epitaxial layer, and the drain located in the drain epitaxial layer.

8. The laterally diffused metal oxide semiconductor of claim 1, further comprising a gate oxide layer located between the gate and the fins, the gate oxide layer being directly connected to the thick oxide layer.

9. The laterally diffused metal-oxide semiconductor of claim 8, wherein the top surface height of the gate oxide layer is higher than the top surface height of the thick oxide layer.

10. The laterally diffused metal-oxide semiconductor of claim 8, wherein the top surface height of the gate oxide layer is lower than the top surface height of the thick oxide layer.

11. The laterally diffused metal oxide semiconductor of claim 8, wherein the top surface of the gate oxide layer is flush with the top surface of the thick oxide layer.

12. The laterally diffused metal-oxide semiconductor of claim 8, further comprising an N-type drift region located in each of the fins near the second side, wherein the boundary of the N-type drift region is located below the gate oxide layer.

13. The laterally diffused metal-oxide semiconductor of claim 1, wherein the gate material is polycrystalline silicon or metal.

14. A method for fabricating a laterally diffused metal-oxide-semiconductor, comprising: A base is provided on which multiple fins are spaced apart in a first direction and extend toward a second direction; The first photolithography process is used to reduce the height of these fins in the recessed area; A dielectric layer is formed on these fins, wherein the dielectric layer on these fins located in the recessed region constitutes a thick oxide layer; A second photolithography process is performed to reduce the height of the dielectric layer that is not located in the recessed area, so that the dielectric layer becomes a shallow trench isolation structure, and the fins that are not located in the recessed area protrude from the shallow trench isolation structure. A gate is formed extending in the first direction across the fins, wherein the gate has a first side and a second side on both sides in the second direction, wherein the thick oxide layer is close to the second side, and the gate partially overlaps with the thick oxide layer on each fin in the direction perpendicular to the substrate; and A source electrode and a drain electrode are formed in each of the fins on the first side and the second side, respectively.

15. The method for fabricating a laterally diffused metal-oxide-semiconductor as claimed in claim 14, further comprising forming P-type wells and N-type drift regions in the fins, wherein the P-type wells are close to the first side and the N-type drift regions are close to the second side.

16. The method for fabricating a laterally diffused metal-oxide semiconductor as described in claim 14, further comprising forming a base in each of the fins outside the source electrode.

17. The method for fabricating a laterally diffused metal-oxide semiconductor as claimed in claim 16, further comprising forming a source epitaxial layer and a base epitaxial layer on each of the fins on the first side, the source epitaxial layer being located between the gate and the base epitaxial layer, the source being formed in the source epitaxial layer, and the base being formed in the base epitaxial layer.

18. The method of fabricating a laterally diffused metal-oxide semiconductor as claimed in claim 14, further comprising forming a drain epitaxial layer in each of the fins on the second side, the thick oxide layer being located between the gate and the drain epitaxial layer, the drain being formed in the drain epitaxial layer.

19. The method for fabricating a laterally diffused metal-oxide semiconductor as claimed in claim 14, further comprising forming a gate oxide layer on the surface of the fins before forming the gate, the gate oxide layer being directly connected to the thick oxide layer.

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