Array substrate and display device

Abstract

An array substrate and a display device, the array substrate having a display area (AA) and a non-display area (NAA), the non-display area (NAA) comprising a binding area (BOD), the array substrate comprising: a substrate (1); the first conductive layer group (2) is arranged on one side of the substrate (1), and the first conductive layer group (2) comprises a first wire (21); the insulating layer group (3) is arranged on the side, away from the substrate (1), of the first conductive layer group (2), a concave part (31) located in the non-display area (NAA) is arranged on the insulating layer group (3), the orthographic projection of the binding area (BOD) on the substrate (1) and the orthographic projection of the concave part (31) on the substrate (1) are at least partially overlapped, a first via hole (32) is formed in the insulating layer group (3), and the first via hole (32) is communicated with the first conductive layer group (2). The first via hole (32) is located on one side, close to the display area (AA), of the sunken part (31), and the first wire (21) at least extends to the binding area (BOD) from the first via hole (32); the second conducting layer (4) is arranged on the side, away from the substrate (1), of the insulating layer set (3), the second conducting layer (4) comprises a second wire (41), and the second wire (41) is located on the side, close to the display area (AA), of the concave part (31), electrically connected to the display area (AA) and connected to the first wire (21) through the first via hole (32). The second wire (41) of the array substrate is not easy to break.

Description

Array substrate and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to an array substrate and a display device. Background Technology

[0002] Liquid crystal displays (LCDs) are widely used in various display fields, such as homes, public places, offices, and personal electronic products. As requirements for LCD products continue to increase and cost requirements decrease, there is a growing demand for lighter, thinner designs and lower costs.

[0003] However, current LCD monitors are prone to display problems after the driver is re-bonded.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0005] Summary of the Invention

[0006] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide an array substrate and a display device.

[0007] According to one aspect of this disclosure, an array substrate is provided having a display area and a non-display area, the non-display area including a bonding region, the array substrate comprising:

[0008] Substrate;

[0009] A first conductive layer group is disposed on one side of the substrate, and the first conductive layer group includes a first trace;

[0010] An insulating layer group is disposed on the side of the first conductive layer group away from the substrate. The insulating layer group has a recessed portion located in the non-display area. The orthographic projection of the bonding area on the substrate and the orthographic projection of the recessed portion on the substrate at least partially overlap. The insulating layer group has a first via located on the side of the recessed portion closer to the display area. The first trace extends at least from the first via to the bonding area.

[0011] A second conductive layer is disposed on the side of the insulating layer group away from the substrate. The second conductive layer includes a second trace, which is located on the side of the recess near the display area and is electrically connected to the display area. The second trace is connected to the first trace through the first via.

[0012] In an example embodiment of the present disclosure, a distance between the first via and the edge of the display region is greater than or equal to 10 μm.

[0013] In an example embodiment of the present disclosure, the first conductive layer group includes:

[0014] a first sub-conductive layer disposed on one side of the substrate;

[0015] a first insulating layer disposed on a side of the first sub-conductive layer away from the substrate;

[0016] a second sub-conductive layer disposed on a side of the first insulating layer away from the substrate, the second sub-conductive layer including the first trace.

[0017] In an example embodiment of the present disclosure, the first conductive layer group includes:

[0018] a first sub-conductive layer disposed on one side of the substrate, the first sub-conductive layer including a first connection trace;

[0019] a first insulating layer disposed on a side of the first sub-conductive layer away from the substrate, the first insulating layer having a second via disposed thereon;

[0020] a second sub-conductive layer disposed on a side of the first insulating layer away from the substrate, the second sub-conductive layer including a second connection trace, the second connection trace being electrically connected to the first connection trace through the second via to form the first trace, the second trace being connected to the second connection trace through the first via.

[0021] In an example embodiment of the present disclosure, a projection of the second connection trace on the substrate is located between a projection of the recess on the substrate and the display region, and the first connection trace extends at least from the second via to the binding area.

[0022] In an example embodiment of the present disclosure, the first sub-conductive layer further includes a third trace and a fourth trace, the third trace extending from the binding area to the display region; the second sub-conductive layer further includes a fifth trace, a projection of the fifth trace on the substrate being located on a side of a projection of the recess on the substrate close to the display region, and the fifth trace being electrically connected to the display region; the first insulating layer has a third via disposed thereon, the third via being located on a side of the recess close to the display region; the fourth trace extends at least from the third via to the binding area, and the fifth trace is connected to the fourth trace through the third via.

[0023] In an example embodiment of the present disclosure, the first sub-conductive layer includes a third trace extending from the binding area to the display area; and the second sub-conductive layer includes a sixth trace extending from the binding area to the display area.

[0024] In an example embodiment of the present disclosure, the insulating layer group includes:

[0025] A first protective layer is disposed on a side of the first conductive layer group away from the substrate, and a first sub-via is disposed on the first protective layer;

[0026] A first planarization layer is disposed on a side of the first protective layer away from the substrate, and a second sub-via and a first opening portion are disposed on the first planarization layer, and the second conductive layer is disposed on a side of the first planarization layer away from the substrate;

[0027] A second protective layer is disposed on a side of the first planarization layer away from the substrate, and a third sub-via is disposed on the second protective layer, and the second conductive layer is disposed on a side of the second protective layer away from the substrate;

[0028] The third sub-via, the second sub-via, and the first sub-via are sequentially communicated to form the first via, and a normal projection of the recess portion on the substrate is located within a normal projection of the first opening portion on the substrate.

[0029] In an example embodiment of the present disclosure, in the display area, the array substrate further includes:

[0030] A first electrode is disposed between the first planarization layer and the second protective layer;

[0031] A third protective layer is disposed on a side of the second conductive layer away from the substrate;

[0032] A second electrode is disposed on a side of the third protective layer away from the substrate.

[0033] In an example embodiment of the present disclosure, the insulating layer group includes:

[0034] A first protective layer is disposed on a side of the first conductive layer group away from the substrate, and a first sub-via is disposed on the first protective layer;

[0035] A first planarization layer is disposed on a side of the first protective layer away from the substrate, and a second sub-via and a first opening portion are disposed on the first planarization layer, and the second conductive layer is disposed on a side of the first planarization layer away from the substrate;

[0036] The second sub-via and the first sub-via are sequentially communicated to form the first via, and a projection of the recess on the substrate substrate is located within a projection of the first opening on the substrate substrate.

[0037] In an example embodiment of the present disclosure, the array substrate further comprises:

[0038] A second planarization layer is disposed on a side of the second conductive layer away from the substrate substrate, and a second opening is disposed on the second planarization layer, and a projection of the second opening on the substrate substrate is located within a projection of the first opening on the substrate substrate.

[0039] A second protection layer is disposed on a side of the second planarization layer away from the substrate substrate.

[0040] In an example embodiment of the present disclosure, in the display area, the array substrate further comprises:

[0041] A first electrode is disposed between the second planarization layer and the second protection layer.

[0042] A second electrode is disposed on a side of the second protection layer away from the substrate substrate.

[0043] In an example embodiment of the present disclosure, the first conductive layer group comprises:

[0044] A first sub-conductive layer is disposed on a side of the substrate substrate, and the first sub-conductive layer comprises the first trace.

[0045] In an example embodiment of the present disclosure, the insulating layer group comprises:

[0046] A first insulating layer is disposed on a side of the first sub-conductive layer away from the substrate substrate, and a fourth sub-via is disposed on the first insulating layer.

[0047] A first protection layer is disposed on a side of the first insulating layer away from the substrate substrate, and a first sub-via is disposed on the first protection layer.

[0048] A first planarization layer is disposed on a side of the first protection layer away from the substrate substrate, and a second sub-via and a first opening are disposed on the first planarization layer.

[0049] A second protection layer is disposed on a side of the first planarization layer away from the substrate substrate, and a third sub-via is disposed on the second protection layer, and the second conductive layer is disposed on a side of the second protection layer away from the substrate substrate.

[0050] The third sub-via, the second sub-via, the first sub-via and the fourth sub-via are sequentially communicated to form the first via, and a projection of the recess on the substrate substrate is located within a projection of the first opening on the substrate substrate.

[0051] In an example embodiment of the present disclosure, the first sub-conductive layer includes a third trace extending from the binding area to the display area; and the array substrate further includes:

[0052] A second sub-conductive layer is disposed between the first insulating layer and the first protective layer, and the second sub-conductive layer includes a sixth trace extending from the binding area to the display area.

[0053] In an example embodiment of the present disclosure, in the display area, the array substrate further includes:

[0054] A first electrode is disposed between the first planarization layer and the second protective layer.

[0055] A third protective layer is disposed on a side of the second conductive layer away from the substrate substrate.

[0056] A second electrode is disposed on a side of the third protective layer away from the substrate substrate.

[0057] In an example embodiment of the present disclosure, the insulating layer group includes:

[0058] A first insulating layer is disposed on a side of the first sub-conductive layer away from the substrate substrate, and a fourth sub-via is disposed on the first insulating layer.

[0059] A first protective layer is disposed on a side of the first conductive layer group away from the substrate substrate, and a first sub-via is disposed on the first protective layer.

[0060] A first planarization layer is disposed on a side of the first protective layer away from the substrate substrate, and a second sub-via and a first opening are disposed on the first planarization layer, and the second conductive layer is disposed on a side of the first planarization layer away from the substrate substrate.

[0061] The second sub-via, the first sub-via and the fourth sub-via are sequentially communicated to form the first via, and a projection of the recess on the substrate substrate is located within a projection of the first opening on the substrate substrate.

[0062] In an example embodiment of the present disclosure, the array substrate further includes:

[0063] a second planarization layer disposed on a side of the second conductive layer away from the substrate, the second planarization layer having a second opening portion disposed thereon, a projection of the second opening portion on the substrate being within a projection of the first opening portion on the substrate;

[0064] a second protection layer disposed on a side of the second planarization layer away from the substrate.

[0065] In an exemplary embodiment of the present disclosure, the array substrate further comprises, in the display region:

[0066] a gate layer disposed on a side of the substrate, the gate layer comprising a gate electrode;

[0067] a gate insulating layer disposed on a side of the gate layer away from the substrate;

[0068] an active layer disposed on a side of the gate insulating layer away from the substrate, the active layer comprising a first conductive connection portion, a channel portion and a second conductive connection portion connected in sequence;

[0069] a source-drain layer disposed on a side of the active layer away from the substrate, the source-drain layer comprising a source electrode and a drain electrode, the source electrode being connected to the first conductive connection portion, the drain electrode being connected to the second conductive connection portion, the insulating layer set being disposed on a side of the source-drain layer away from the substrate;

[0070] a touch function layer disposed on a side of the insulating layer set away from the substrate;

[0071] wherein the touch function layer and the second conductive layer are disposed in the same layer and of the same material, the gate layer and the first sub-conductive layer are disposed in the same layer and of the same material, the source-drain layer and the second sub-conductive layer are disposed in the same layer and of the same material, and the gate insulating layer and the first insulating layer are disposed in the same layer and of the same material.

[0072] According to another aspect of the present disclosure, there is provided a display device comprising the array substrate as described in any one of the above.

[0073] It should be understood that the general description above and the following detailed description are merely exemplary and explanatory, and are not intended to limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0074] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure. It is readily apparent to one skilled in the art that the following description in the drawings is merely exemplary and other drawings can be obtained from the drawings without any creative effort.

[0075] FIG. 1 is a schematic diagram of a basic circuit structure of an array substrate according to the present disclosure.

[0076] FIG. 2 is a schematic diagram of a structure of a non-display region of a display panel according to the related art.

[0077] FIG. 3 is a schematic diagram of a cross-sectional view taken along A-A in FIG. 2.

[0078] FIG. 4 is a schematic diagram of a structure of a portion of a non-display region of a first example embodiment of an array substrate according to the present disclosure.

[0079] FIG. 5 is a schematic diagram of a structure of another portion of the non-display region of the first example embodiment of the array substrate according to the present disclosure.

[0080] FIG. 6 is a schematic diagram of a cross-sectional view taken along B-B in FIG. 4.

[0081] FIG. 7 is a schematic diagram of a structure of a portion of a non-display region of a second example embodiment of an array substrate according to the present disclosure.

[0082] FIG. 8 is a schematic diagram of a structure of another portion of the non-display region of the second example embodiment of the array substrate according to the present disclosure.

[0083] FIG. 9 is a schematic diagram of a cross-sectional view taken along C-C in FIG. 7.

[0084] FIG. 10 is a schematic diagram of a structure of a portion of a non-display region of a third example embodiment of an array substrate according to the present disclosure.

[0085] FIG. 11 is a schematic diagram of a structure of a portion of a non-display region of a fourth example embodiment of an array substrate according to the present disclosure.

[0086] FIG. 12 is a schematic diagram of a cross-sectional view taken along D-D in FIG. 11.

[0087] FIG. 13 is a schematic diagram of a structure of a display region of the first, second, third, and fourth example embodiments of the array substrate according to the present disclosure.

[0088] FIG. 14 is a schematic diagram of a cross-sectional view of a fifth example embodiment of an array substrate according to the present disclosure.

[0089] FIG. 15 is a schematic diagram of a cross-sectional view of a sixth example embodiment of an array substrate according to the present disclosure.

[0090] FIG. 16 is a schematic diagram of a cross-sectional view of a seventh example embodiment of an array substrate according to the present disclosure.

[0091] FIG. 17 is a schematic diagram of a structure of a display region of the fifth, sixth, and seventh example embodiments of the array substrate according to the present disclosure.

[0092] FIG. 18 is a schematic diagram of a structure of a display region of an eighth example embodiment of an array substrate according to the present disclosure.

[0093] FIG. 19 is a structural schematic diagram of a non-display region of an array substrate of an eighth example embodiment of the present disclosure.

[0094] FIG. 20 is a top view schematic diagram of a non-display region of an array substrate of the eighth example embodiment of the present disclosure.

[0095] FIG. 21 is a structural schematic diagram of a display region of an array substrate of a ninth example embodiment of the present disclosure.

[0096] BRIEF DESCRIPTION OF DRAWINGS 1, substrate; 2, first conductive layer group; 21, first trace; 22, first sub-conductive layer; 221, first connection trace; 222, third trace; 223, fourth trace; 23, first insulating layer; 231, second via hole; 232, third via hole; 233, fourth sub-via hole; 24, second sub-conductive layer; 241, second connection trace; 242, fifth trace; 243, sixth trace; 3, insulating layer group; 31, recessed part; 32, first via hole; 33, first protective layer; 331, first sub-via hole; 34, first planarization layer; 341, second sub-via hole; 342, first opening part; 35, second protective layer; 351, third sub-via hole; 4, second conductive layer; 41, second trace; 5, first electrode; 6, third protective layer; 7, second electrode; 8, second planarization layer; 81, second opening part; 9, gate layer; 91, gate; 92, first lead wire; 10, gate insulating layer; 11, active layer; 111, first conductive connection part; 112, channel part; 113, second conductive connection part; 12, source-drain layer; 121, source; 122, drain; 123, second lead wire; 13, touch function layer; 131, third lead wire; 14, glue frame; 15, color filter substrate; AA, display region; NAA, non-display region; BOD, binding area; BOD1, first binding area; BOD2, second binding area; Fanout, fanout area; Fanout1, first fanout area; Fanout2, second fanout area; ACF, anisotropic conductive film; IC, driver; X, first direction; Y, second direction. DETAILED DESCRIPTION

[0097] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided as part of the disclosure to convey the principles of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the drawings, and descriptions of the same or similar elements can be omitted from the descriptions of the drawings. Furthermore, the drawings are to be understood only as illustrative and not as limiting.

[0098] Although relative terms are used herein, such as "upper", "lower", to describe one component's relationship to another component, these terms are used herein solely to convey such relative positional relationship in the drawings, as exemplified by the examples shown in the drawings. It is understood that if the device of the icon is turned upside down, the component described as "upper" will become the component described as "lower". When a structure is "on" another structure, it can mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0099] The terms "one", "a", "an", "the", and "at least one" are used to indicate that there is one or more of the elements / components / etc.; the terms "comprising" and "having" are used to indicate an open-ended inclusion of one or more elements / components / etc. in the description of a process, a method, an article, or a composition of matter; the terms "a first", "a second", "a third" etc. are merely used to identify one of a number of elements / components / etc., and do not limit the number of such elements / components / etc.

[0100] In this application, unless otherwise clearly indicated and limited, the term "connection" should be interpreted broadly, for example, "connection" can be fixed connection, can also be detachable connection, or integral; can be directly connected, can also be indirectly connected through an intermediate medium. "And / or", is only a description of the relationship between the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, B exists alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects have an "or" relationship.

[0101] The example embodiments of the present disclosure provide an array substrate, as shown in FIGS. 1-17, having a display area AA and a non-display area NAA, the non-display area NAA including a binding area BOD, the array substrate comprising a substrate substrate 1, a first conductive layer group 2, an insulating layer group 3, and a second conductive layer 4; the first conductive layer group 2 is provided on one side of the substrate substrate 1, the first conductive layer group 2 comprising a first trace 21; the insulating layer group 3 is provided on the side of the first conductive layer group 2 away from the substrate substrate 1, the insulating layer group 3 being provided with a recess 31, the recess 31 being located in the non-display area NAA, the recess 31 and the binding area BOD on the substrate substrate 1 at least partially overlapping, the insulating layer group 3 being provided with a first via 32, the first via 32 being located on the side of the recess 31 close to the display area AA, the first trace 21 extending from at least the first via 32 to the binding area BOD; the second conductive layer 4 is provided on the side of the insulating layer group 3 away from the substrate substrate 1, the second conductive layer 4 comprising a second trace 41, the second trace 41 being located on the side of the recess 31 close to the display area AA, and the second trace 41 being electrically connected to the display area AA, the second trace 41 being connected to the first trace 21 through the first via 32.

[0102] The array substrate of the present disclosure, on the one hand, the insulating layer group 3 can alleviate or even eliminate the height difference formed by the first trace 21, the second trace 41 is arranged on the side of the insulating layer group 3 away from the substrate substrate 1, so that the base surface of the second trace 41 is relatively flat, so that the wiring of the second trace 41 is relatively arbitrary, thereby facilitating the design of the array substrate; on the other hand, the second trace 41 is not arranged on the edge of the recess 31, so that in the process of peeling off the anisotropic conductive adhesive film ACF, even if the insulating layer group 3 around the recess 31 is scratched, the second trace 41 will not be damaged, and the second trace 41 will not be caused. circuit break; on the other hand, the second trace 41 is connected to the first trace 21 through the first via 32, so that the second trace 41 and the first trace 21 can be connected in conduction, thereby realizing the electrical connection between the binding area BOD and the display area AA through the first trace 21 and the second trace 41, and realizing the signal transmission between the binding area BOD and the display area AA through the first trace 21 and the second trace 41.

[0103] Referring to FIG. 1, the array substrate has a display area AA and a non-display area NAA, specifically, the non-display area NAA can be arranged around the outer periphery of the display area AA, the non-display area NAA can include a fanout area Fanout and a binding area BOD, the fanout area Fanout can be a part of the non-display area NAA close to the display area AA, and the binding area BOD can be a part of the non-display area NAA away from the display area AA, that is, the fanout area Fanout is connected between the binding area BOD and the display area AA.

[0104] The two binding areas BOD can be a first binding area BOD1 and a second binding area BOD2. The first binding area BOD1 can be arranged on one side of the display area AA in the first direction X, and the second binding area BOD2 can be arranged on one side of the display area AA in the second direction Y. The two fanout areas Fanout can be a first fanout area Fanout1 and a second fanout area Fanout2. The first fanout area Fanout1 is connected between the first binding area BOD1 and the display area AA, and the second fanout area Fanout2 is connected between the second binding area BOD2 and the display area AA.

[0105] The first binding area BOD1 can bind the gate-level driver GateIC. Specifically, the gate-level driver GateIC can be bound to the first binding area BOD1 through an anisotropic conductive film ACF. The second binding area BOD2 can bind the data driver DataIC. Specifically, the data driver DataIC can be bound to the second binding area BOD2 through the anisotropic conductive film ACF. The first fanout area Fanout1 and the second fanout area Fanout2 are both used to arrange the lines connecting the display area AA and the driver IC.

[0106] The data driver DataIC sequentially latches the input display data and clock signal, converts the analog signal, and inputs the analog signal to the data line Data Line of the array substrate. The gate-level driver GateIC converts the input clock signal through a shift register (SR), switches it to an on / off voltage, and sequentially applies it to the gate line Gate Line of the array substrate. The shift register in the gate-level driver GateIC is used to generate a scanning signal in the scanning gate line.

[0107] With the proposal of high-definition display of liquid crystal displays, i.e., the resolution of liquid crystal displays is getting higher and higher, the number of driver ICs (gate-level driver GateIC and data driver DataIC) is also increasing. With the increasing requirements of liquid crystal displays and the decreasing cost requirements, the appearance of lighter and thinner and the cost requirements are getting higher and higher. The wiring space of the lines of the driver ICs (gate-level driver GateIC and data driver DataIC) to the display area AA is also required to be smaller and smaller.

[0108] Each row of sub-pixels corresponds to the same gate line Gate Line, and each column of sub-pixels corresponds to the same data line Data Line. With the increasingly narrow product frame requirement, the wiring space is also required to be smaller and smaller.

[0109] In the example embodiment, the material of the substrate 1 can include inorganic materials, for example, the inorganic materials can be glass, quartz or metal, etc. The material of the substrate 1 can also include organic materials, for example, the organic materials can be polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate, etc. The substrate 1 can be formed by multiple layers of materials, for example, the substrate 1 can include multiple layers of base material, and the material of the base material can be any of the above materials. Of course, the substrate 1 can also be provided as a single layer, which can be any of the above materials.

[0110] Referring to FIGS. 2 and 3, an insulating layer group 3 is provided on one side of the substrate 1, and a recess 31 is provided on the insulating layer group 3, and the recess 31 is located in the non-display area NAA.

[0111] A second conductive layer 4 is provided on the side of the insulating layer group 3 away from the substrate 1, and the second conductive layer 4 can include a second trace 41, and the second trace 41 extends from the display area AA to the binding area BOD, for example, a part of the second trace 41 extends from the display area AA to the first binding area BOD1; that is, one end of the second trace 41 is located in the first binding area BOD1, and the first binding area BOD1 can be connected with the gate driver Gate IC, and the opposite end of the second trace 41 is located in the display area AA, and the second trace 41 can realize signal transmission between the gate driver Gate IC and the display area AA; another part of the second trace 41 extends from the display area AA to the second binding area BOD2; that is, one end of the second trace 41 is located in the second binding area BOD2, and the second binding area BOD2 can be connected with the data driver Data IC, and the opposite end of the second trace 41 is located in the display area AA, and the second trace 41 can realize signal transmission between the data driver Data IC and the display area AA.

[0112] The inventor found that the main reason for the display failure is that when the gate driver Gate IC has a binding failure (alignment failure, conduction failure, etc.), the gate driver Gate IC needs to be removed, the cause of the failure needs to be checked, and the binding needs to be performed again. In the process of removing the gate driver Gate IC, the anisotropic conductive film ACF needs to be removed, and the anisotropic conductive film ACF is generally peeled off by a bamboo stick, and in this process, the insulating layer group 3 around the gate driver Gate IC is scratched, thereby causing the second trace 41 provided on the side of the insulating layer group 3 away from the substrate 1 to fall off, causing the second trace 41 to be open, thereby affecting the signal transmission between the gate driver Gate IC and the display area AA, and causing display failure.

[0113] Similarly, in the case of poor binding (poor alignment, poor conduction, etc.) of the data driver Data IC, the data driver Data IC needs to be removed, the cause of the poor binding is checked, and the data driver Data IC is bound again. In the process of removing the data driver Data IC, the anisotropic conductive film ACF needs to be removed, and the anisotropic conductive film ACF is generally peeled off by a bamboo stick. In this process, the insulating layer group 3 around the data driver Data IC is scratched, causing the second trace 41 provided on the side of the insulating layer group 3 away from the substrate 1 to fall off, causing the second trace 41 to be disconnected, and causing the signal transmission between the data driver Data IC and the display area AA to be affected, thereby causing display defects.

[0114] In the present example embodiment, as shown in FIGS. 4-6, a first conductive layer group 2 is provided on one side of the substrate 1, and the first conductive layer group 2 can include a first trace 21.

[0115] An insulating layer group 3 is provided on the side of the first conductive layer group 2 away from the substrate 1, and a recess 31 is provided on the insulating layer group 3. The recess 31 is located in the non-display area NAA, and the orthographic projection of the binding area BOD on the substrate 1 at least partially overlaps the orthographic projection of the recess 31 on the substrate 1. For example, the edge line of the orthographic projection of the binding area BOD on the substrate 1 can coincide with the edge line of the orthographic projection of the recess 31 on the substrate 1, or the orthographic projection of the recess 31 on the substrate 1 can cover the orthographic projection of the binding area BOD on the substrate 1, and the area of the orthographic projection of the recess 31 on the substrate 1 is greater than the area of the orthographic projection of the binding area BOD on the substrate 1. Thus, the orthographic projection of the binding area BOD on the substrate 1 is located within the orthographic projection of the recess 31 on the substrate 1.

[0116] Of course, in some other example embodiments of the present disclosure, a part of the orthographic projection of the binding area BOD on the substrate 1 can overlap a part of the orthographic projection of the recess 31 on the substrate 1.

[0117] A first via hole 32 is provided on the insulating layer group 3, and the first via hole 32 is located on the side of the recess 31 close to the display area AA, i.e., the first via hole 32 is provided between the recess 31 and the display area AA, and the first via hole 32 is not provided within the recess 31.

[0118] The first trace 21 is located in the non-display area NAA, and the first trace 21 extends at least from the first via hole 32 to the binding area BOD, so that the first trace 21 extends from the side of the recess 31 close to the display area AA to the binding area BOD; specifically, the first via hole 32 can be provided in multiple, and the first trace 21 can be provided in multiple, a part of the first via hole 32 is arranged in the first fanout area Fanout1, and a part of the first trace 21 can extend from the first via hole 32 to the first binding area BOD1, and the part of the first trace 21 can be bound and connected with the gate level driver GateIC; another part of the first via hole 32 is arranged in the second fanout area Fanout2, and another part of the first trace 21 can extend from the first via hole 32 to the second binding area BOD2, and the part of the first trace 21 can be bound and connected with the data driver DataIC.

[0119] The second conductive layer 4 is arranged on the side of the insulating layer group 3 away from the substrate substrate 1, and the second conductive layer 4 can include a second trace 41. The first trace 21 can be formed to reduce or even eliminate the difference. The second trace 41 is arranged on the side of the insulating layer group 3 away from the substrate substrate 1, so that the base surface of the second trace 41 is relatively flat, the wiring of the second trace 41 is relatively arbitrary, and the design of the array substrate is facilitated.

[0120] The second trace 41 is located on the side of the recess 31 close to the display area AA, that is, the second trace 41 is not arranged on the edge of the recess 31, so that in the process of peeling off the anisotropic conductive adhesive film ACF, even if the insulating layer group 3 around the recess 31 is scratched, the second trace 41 will not be damaged, and the second trace 41 will not be caused. The second trace 41 is not caused to be open.

[0121] Moreover, the second trace 41 is electrically connected to the display area AA, specifically, the second trace 41 extends to the display area AA and is connected with some functional layers of the display area AA. The second trace 41 is connected to the first trace 21 through the first via hole 32, so that the second trace 41 and the first trace 21 can be connected in conduction, so as to realize the electrical connection between the binding area BOD and the display area AA through the first trace 21 and the second trace 41, and realize the signal transmission between the binding area BOD and the display area AA through the first trace 21 and the second trace 41.

[0122] Moreover, the distance between the first via hole 32 and the edge of the recess 31 close to the display area AA is greater than or equal to 10μm, for example, the distance between the first via hole 32 and the edge of the recess 31 close to the display area AA can be 12μm, 15μm, 17μm, 20μm, 23μm, 25μm, 28μm, 30μm, 32μm, 35μm, 37μm, 40μm, etc.

[0123] If the distance between the first via hole 32 and the edge of the recess 31 close to the display area AA is too small, the hole wall close to the recess 31 of the first via hole 32 can be dug through in the process of peeling the anisotropic conductive adhesive film ACF, thereby causing the second wire 41 in the first via hole 32 to be disconnected, and further causing display failure.

[0124] The above numerical range will not dig through the hole wall close to the recess 31 of the first via hole 32 in the process of peeling the anisotropic conductive adhesive film ACF, the second wire 41 in the first via hole 32 will not be disconnected, and the display effect is guaranteed.

[0125] The first wire 21 can be a single-layer structure or a multi-layer connection structure.

[0126] Specifically, in some example embodiments of the present disclosure, referring to FIGS. 4-6, the first conductive layer group 2 can include a first sub-conductive layer 22, a first insulating layer 23, and a second sub-conductive layer 24; the first sub-conductive layer 22 is arranged on one side of the substrate substrate 1; the first insulating layer 23 is arranged on the side of the first sub-conductive layer 22 away from the substrate substrate 1; the second sub-conductive layer 24 is arranged on the side of the first insulating layer 23 away from the substrate substrate 1, and the second sub-conductive layer 24 can include the first wire 21, so that the first wire 21 is a single-layer structure; the insulating layer group 3 is arranged on the side of the second sub-conductive layer 24 away from the substrate substrate 1.

[0127] In this case, the first sub-conductive layer 22 can include a third wire 222 extending from the binding area BOD to the display area AA, and the third wire 222 can realize signal transmission between the binding area BOD and the display area AA. The third wire 222 is arranged on a different conductive layer from the first wire 21 and the second wire 41, so that the spacing between the third wire 222 and the first wire 21 and the second wire 41 can be arranged to be narrower, and more preferably the third wire 222 and the first wire 21 and the second wire 41 can be arranged in a stacked manner, thereby making the width of the non-display area NAA of the array substrate can be arranged to be narrower, thereby facilitating the narrow frame setting of the display panel.

[0128] The second sub-conductive layer 24 can include a sixth wire 243 extending from the binding area BOD to the display area AA, and the sixth wire 243 can realize signal transmission between the binding area BOD and the display area AA. The sixth wire 243 is arranged on a different conductive layer from the first wire 21 and the second wire 41, so that the spacing between the sixth wire 243 and the first wire 21 and the second wire 41 can be arranged to be narrower, and more preferably the sixth wire 243 and the first wire 21 and the second wire 41 can be arranged in a stacked manner, thereby making the width of the non-display area NAA of the array substrate can be arranged to be narrower, thereby facilitating the narrow frame setting of the display panel.

[0129] In some example embodiments of the present disclosure, referring to FIGS. 7-9, the first conductive layer set 2 can include a first sub-conductive layer 22, a first insulating layer 23, and a second sub-conductive layer 24; the first sub-conductive layer 22 is arranged on one side of the substrate 1, and the first sub-conductive layer 22 can include a first connecting trace 221; the first insulating layer 23 is arranged on the side of the first sub-conductive layer 22 away from the substrate 1, and the first insulating layer 23 is provided with a second via hole 231; the second sub-conductive layer 24 is arranged on the side of the first insulating layer 23 away from the substrate 1, and the second sub-conductive layer 24 can include a second connecting trace 241, which is electrically connected to the first connecting trace 221 through the second via hole 231 to form the first trace 21, i.e., the first trace 21 is formed by connecting the first connecting trace 221 arranged on the first sub-conductive layer 22 and the second connecting trace 241 arranged on the second sub-conductive layer 24. The insulating layer set 3 is arranged on the side of the second sub-conductive layer 24 away from the substrate 1, and the second trace 41 is connected to the second connecting trace 241 through the first via hole 32, so that the first connecting trace 221, the second connecting trace 241, and the second trace 41 are sequentially connected to realize signal transmission between the binding area BOD and the display area AA.

[0130] Moreover, the second connecting trace 241 is arranged on the side of the recess 31 close to the display area AA, i.e., the second connecting trace 241 is not arranged at the recess 31, so that the bottom of the recess 31 is relatively flat, which is conducive to binding with the driver IC.

[0131] In this case, the first sub-conductive layer 22 can further include a third trace 222 and a fourth trace 223, the third trace 222 extends from the binding area BOD to the display area AA, and the third trace 222 can realize signal transmission between the binding area BOD and the display area AA.

[0132] The second sub-conductive layer 24 can further include a fifth trace 242, the orthogonal projection of the fifth trace 242 on the substrate 1 is located on the side of the orthogonal projection of the recess 31 on the substrate 1 close to the display area AA, i.e., the fifth trace 242 is not arranged at the recess 31; moreover, the fifth trace 242 is electrically connected to the display area AA.

[0133] The first insulating layer 23 can be provided with a third via hole 232, which is located on the side of the recess 31 close to the display area AA; i.e., the third via hole 232 is arranged between the recess 31 and the display area AA, and the third via hole 232 is not arranged in the recess 31.

[0134] The fourth trace 223 extends at least from the third via hole 232 to the binding area BOD. For example, the fourth trace 223 can extend from the third via hole 232 to the binding area BOD, or the fourth trace 223 can extend from the third via hole 232 to the binding area BOD and protrude from the third via hole 232. The fifth trace 242 can be connected to the fourth trace 223 through the third via hole 232, so that the fifth trace 242 and the fourth trace 223 can be conductively connected, thereby realizing electrical connection between the binding area BOD and the display area AA through the fifth trace 242 and the fourth trace 223, and realizing signal transmission between the binding area BOD and the display area AA through the fifth trace 242 and the fourth trace 223.

[0135] In this way, the traces of the binding area BOD are only the first connection trace 221, the third trace 222 and the fourth trace 223 of the first sub-conductive layer 22, so that the traces of the binding area BOD are substantially located in the same plane, which is conducive to the binding with the driver IC. Moreover, the fourth trace 223, the third trace 222 and the first connection trace 221 are arranged in sequence to form a group of trace groups, and a plurality of groups of trace groups are arranged in sequence.

[0136] Of course, in some other example embodiments of the present disclosure, referring to FIG. 10, the first sub-conductive layer 22 can include a third trace 222 extending from the binding area BOD to the display area AA, and the third trace 222 can realize signal transmission between the binding area BOD and the display area AA. The third trace 222 is arranged on a different conductive layer from the first trace 21 and the second trace 41, so that the spacing between the third trace 222 and the first trace 21 and the second trace 41 can be arranged to be narrower, and more preferably, the third trace 222 can be arranged in a stacked manner with the first trace 21 and the second trace 41, so that the width of the non-display area NAA of the array substrate can be arranged to be narrower, thereby facilitating the narrow frame setting of the display panel.

[0137] The second sub-conductive layer 24 can include a sixth trace 243 extending from the binding area BOD to the display area AA, and the sixth trace 243 can realize signal transmission between the binding area BOD and the display area AA. The sixth trace 243 is arranged on a different conductive layer from the first trace 21 and the second trace 41, so that the spacing between the sixth trace 243 and the first trace 21 and the second trace 41 can be arranged to be narrower, and more preferably, the sixth trace 243 can be arranged in a stacked manner with the first trace 21 and the second trace 41, so that the width of the non-display area NAA of the array substrate can be arranged to be narrower, thereby facilitating the narrow frame setting of the display panel.

[0138] Moreover, the first trace 21, the third trace 222 and the sixth trace 243 are arranged in sequence to form a group of trace groups, and a plurality of groups of trace groups are arranged in sequence.

[0139] Further, referring to FIG. 6 and FIG. 9, the insulating layer group 3 can include a first protective layer 33, a first planarization layer 34, and a second protective layer 35; the first protective layer 33 is disposed on the side of the first conductive layer group 2 away from the substrate 1, the first protective layer 33 is provided with a first sub-via hole 331, and the material of the first protective layer 33 can be an inorganic material, for example, silicon nitride, silicon oxide, silicon oxynitride, etc. The first planarization layer 34 is disposed on the side of the first protective layer 33 away from the substrate 1, the first planarization layer 34 is provided with a second sub-via hole 341 and a first opening part 342, and the material of the first planarization layer 34 can be an organic material, for example, polyimide (PI), polycarbonate, polyacrylate, polyetherimide, etc. The second protective layer 35 is disposed on the side of the first planarization layer 34 away from the substrate 1, the second protective layer 35 is provided with a third sub-via hole 351, and the material of the second protective layer 35 can be an inorganic material, for example, silicon nitride, silicon oxide, silicon oxynitride, etc.; the second conductive layer 4 is disposed on the side of the second protective layer 35 away from the substrate 1.

[0140] The third sub-via hole 351, the second sub-via hole 341, and the first sub-via hole 331 are sequentially communicated to form the first via hole 32; the orthographic projection of the recess 31 on the substrate 1 is located within the orthographic projection of the first opening part 342 on the substrate 1, specifically, because the sidewall of the first opening part 342 is covered with the second protective layer 35, the orthographic projection of the first opening part 342 on the substrate 1 covers the orthographic projection of the recess 31 on the substrate 1, and the area of the orthographic projection of the first opening part 342 on the substrate 1 is greater than the area of the orthographic projection of the recess 31 on the substrate 1. Of course, the sidewall of the first opening part 342 can not cover the second protective layer 35, in this case, the edge line of the orthographic projection of the recess 31 on the substrate 1 coincides with the edge line of the orthographic projection of the first opening part 342 on the substrate 1.

[0141] Further, the first example embodiment shown in FIG. 4-FIG. 6 requires about nine times of mask process, and the second example embodiment shown in FIG. 7-FIG. 9 requires about ten times of mask process, and the frame width of the first example embodiment can be reduced by about 0.06mm relative to the frame width of the second example embodiment.

[0142] In still some example embodiments of the present disclosure, referring to FIG. 11 and FIG. 12, the first conductive layer group 2 can include a first sub-conductive layer 22, the first sub-conductive layer 22 is disposed on one side of the substrate 1, and the first sub-conductive layer 22 can include the first trace 21.

[0143] In this case, the insulating layer group 3 can include the first insulating layer 23, the first protective layer 33, the first planarization layer 34, and the second protective layer 35; the first insulating layer 23 is arranged on the side of the first sub-conductive layer 22 away from the substrate base plate 1; the fourth sub-via hole 233 is arranged on the first insulating layer 23, and the material of the first insulating layer 23 can be an inorganic material, for example, silicon nitride, silicon oxide, silicon oxynitride, etc. The first protective layer 33 is arranged on the side of the first insulating layer 23 away from the substrate base plate 1, the first sub-via hole 331 is arranged on the first protective layer 33, and the material of the first protective layer 33 can be an inorganic material, for example, silicon nitride, silicon oxide, silicon oxynitride, etc. The first planarization layer 34 is arranged on the side of the first protective layer 33 away from the substrate base plate 1, the second sub-via hole 341 and the first opening part 342 are arranged on the first planarization layer 34, and the material of the first planarization layer 34 can be an organic material, for example, polyimide (PI), polycarbonate, polyacrylate, polyetherimide, etc. The second protective layer 35 is arranged on the side of the first planarization layer 34 away from the substrate base plate 1, the third sub-via hole 351 is arranged on the second protective layer 35, and the material of the second protective layer 35 can be an inorganic material, for example, silicon nitride, silicon oxide, silicon oxynitride, etc. The second conductive layer 4 is arranged on the side of the second protective layer 35 away from the substrate base plate 1.

[0144] The third sub-via hole 351, the second sub-via hole 341, the first sub-via hole 331, and the fourth sub-via hole 233 are sequentially communicated to form the first via hole 32; the orthographic projection of the recess part 31 on the substrate base plate 1 is located within the orthographic projection of the first opening part 342 on the substrate base plate 1, specifically, because the sidewall of the first opening part 342 is covered with the second protective layer 35, the orthographic projection of the first opening part 342 on the substrate base plate 1 covers the orthographic projection of the recess part 31 on the substrate base plate 1, and the area of the orthographic projection of the first opening part 342 on the substrate base plate 1 is greater than the area of the orthographic projection of the recess part 31 on the substrate base plate 1. Of course, the sidewall of the first opening part 342 can not cover the second protective layer 35, in this case, the edge line of the orthographic projection of the recess part 31 on the substrate base plate 1 coincides with the edge line of the orthographic projection of the first opening part 342 on the substrate base plate 1.

[0145] Further, the first sub-conductive layer 22 can include a third trace 222 extending from the binding area BOD to the display area AA, and the third trace 222 can realize signal transmission between the binding area BOD and the display area AA. The third trace 222 is arranged on a different conductive layer from the first trace 21 and the second trace 41, so that the spacing between the third trace 222 and the first trace 21 and the second trace 41 can be arranged to be narrower, and more preferably, the third trace 222 and the first trace 21 and the second trace 41 can be arranged in a stacked manner, so that the width of the non-display area NAA of the array substrate can be arranged to be narrower, thereby facilitating the narrow frame arrangement of the display panel.

[0146] The array substrate can further include a second sub-conductive layer 24 arranged between the first insulating layer 23 and the first protective layer 33, and the second sub-conductive layer 24 can include a sixth trace 243 extending from the binding area BOD to the display area AA, and the sixth trace 243 can realize signal transmission between the binding area BOD and the display area AA. The sixth trace 243 is arranged on a different conductive layer from the first trace 21 and the second trace 41, so that the spacing between the sixth trace 243 and the first trace 21 and the second trace 41 can be arranged to be narrower, and more preferably, the sixth trace 243 and the first trace 21 and the second trace 41 can be arranged in a stacked manner, so that the width of the non-display area NAA of the array substrate can be arranged to be narrower, thereby facilitating the narrow frame arrangement of the display panel.

[0147] Further, the third trace 222, the sixth trace 243, and the first trace 21 are arranged in sequence to form a group of traces, and a plurality of groups of traces are arranged in sequence.

[0148] Referring to FIG. 13, in the display region AA of the above example embodiment, the array substrate can further include a first electrode 5, a third protective layer 6, and a second electrode 7; the first electrode 5 is disposed between the first planarization layer 34 and the second protective layer 35, and the material of the first electrode 5 can include a transparent conductive material, for example, the material of the first electrode 5 can include indium-tin-oxide (ITO), indium-zinc-oxide (IZO), or the like, and the first electrode 5 can be a pixel electrode, which can be connected to the drain 122 through a via hole on the first protective layer 33 and a via hole on the first planarization layer 34, and through which a display signal can be input to the first electrode 5. The third protective layer 6 is disposed on the side of the second conductive layer 4 away from the substrate 1; the material of the third protective layer 6 can be an inorganic material, for example, silicon nitride, silicon oxide, silicon oxynitride, or the like; and the second electrode 7 is disposed on the side of the third protective layer 6 away from the substrate 1, and the material of the second electrode 7 can include a transparent conductive material, for example, the material of the second electrode 7 can include indium-tin-oxide (ITO), indium-zinc-oxide (IZO), or the like, and the second electrode 7 can be a common electrode.

[0149] The film layers included in the insulating layer group are not limited to the above description, referring to FIG. 14 and FIG. 15, in some other example embodiments of the present disclosure, the insulating layer group 3 can include a first protective layer 33 and a first planarization layer 34; the first protective layer 33 is disposed on the side of the first conductive layer group 2 away from the substrate 1, and a first sub-via hole 331 is provided on the first protective layer 33; the material of the first protective layer 33 can be an inorganic material, for example, silicon nitride, silicon oxide, silicon oxynitride, or the like. The first planarization layer 34 is disposed on the side of the first protective layer 33 away from the substrate 1, and a second sub-via hole 341 and a first opening part 342 are provided on the first planarization layer 34, and the material of the first planarization layer 34 can be an organic material, for example, polyimide (PI), polycarbonate, polyacrylate, polyetherimide, or the like. The second conductive layer 4 is disposed on the side of the first planarization layer 34 away from the substrate 1.

[0150] The second sub-via hole 341 and the first sub-via hole 331 are sequentially communicated to form a first via hole 32; the orthographic projection of the recess 31 on the substrate 1 is located within the orthographic projection of the first opening part 342 on the substrate 1, and specifically, since the sidewall of the first opening part 342 is not covered, in this case, the edge line of the orthographic projection of the recess 31 on the substrate 1 coincides with the edge line of the orthographic projection of the first opening part 342 on the substrate 1.

[0151] In this case, the array substrate can further include a second planarization layer 8 and a second protective layer 35. The second planarization layer 8 is arranged on the side of the second conductive layer 4 away from the substrate 1, and the second planarization layer 8 is provided with a second opening part 81. The orthogonal projection of the second opening part 81 on the substrate 1 is located within the orthogonal projection of the first opening part 342 on the substrate 1. For example, the orthogonal projection of the first opening part 342 on the substrate 1 can cover the orthogonal projection of the second opening part 81 on the substrate 1, and the area of the orthogonal projection of the first opening part 342 on the substrate 1 can be larger than the area of the orthogonal projection of the second opening part 81 on the substrate 1. Alternatively, the edge line of the orthogonal projection of the first opening part 342 on the substrate 1 can coincide with the edge line of the orthogonal projection of the second opening part 81 on the substrate 1. The second protective layer 35 is arranged on the side of the second planarization layer 8 away from the substrate 1.

[0152] The first planarization layer 34 and the second conductive layer 4 can be protected by the second planarization layer 8 and the second protective layer 35. In the process of peeling off the anisotropic conductive adhesive film ACF, the first planarization layer 34 and the second conductive layer 4 will not be damaged, the hole wall of the first via hole 32 close to the recessed part 31 will not be dug through, the second trace 41 in the first via hole 32 will not be disconnected, and the display effect is ensured. Moreover, the second planarization layer 8 can planarize the first via hole 32, and provide a relatively flat plane for the subsequently formed film layer.

[0153] Moreover, the fifth example embodiment shown in FIG. 14 needs to perform about ten times of mask processes, and the sixth example embodiment shown in FIG. 15 needs to perform about eleven times of mask processes. The frame width of the fifth example embodiment can be reduced by about 0.06 mm relative to the frame width of the sixth example embodiment.

[0154] Of course, referring to FIG. 16, in the case where the first conductive layer group 2 includes the first sub-conductive layer 22, and the first sub-conductive layer 22 includes the first trace 21, the insulating layer group 3 can include the first insulating layer 23, the first protective layer 33, and the first planarization layer 34; the first insulating layer 23 is arranged on the side of the first sub-conductive layer 22 away from the substrate 1; the fourth sub-via 233 is arranged on the first insulating layer 23; and the material of the first insulating layer 23 can be an inorganic material, for example, silicon nitride, silicon oxide, silicon oxynitride, etc. The first protective layer 33 is arranged on the side of the first insulating layer 23 away from the substrate 1, the first sub-via 331 is arranged on the first protective layer 33, and the material of the first protective layer 33 can be an inorganic material, for example, silicon nitride, silicon oxide, silicon oxynitride, etc. The first planarization layer 34 is arranged on the side of the first protective layer 33 away from the substrate 1, the second sub-via 341 and the first opening 342 are arranged on the first planarization layer 34, and the material of the first planarization layer 34 can be an organic material, for example, polyimide (PI), polycarbonate, polyacrylate, polyetherimide, etc.

[0155] In this case, the second sub-via 341, the first sub-via 331, and the fourth sub-via 233 sequentially communicate to form the first via 32; the orthographic projection of the recess 31 on the substrate 1 is located within the orthographic projection of the first opening 342 on the substrate 1, and specifically, because the sidewall of the first opening 342 is covered with the second protective layer 35, the orthographic projection of the first opening 342 on the substrate 1 covers the orthographic projection of the recess 31 on the substrate 1, and the area of the orthographic projection of the first opening 342 on the substrate 1 is greater than the area of the orthographic projection of the recess 31 on the substrate 1. Of course, the sidewall of the first opening 342 can not cover the second protective layer 35, in which case the edge line of the orthographic projection of the recess 31 on the substrate 1 coincides with the edge line of the orthographic projection of the first opening 342 on the substrate 1.

[0156] In this case, the array substrate can further include the second planarization layer 8 and the second protective layer 35; the second planarization layer 8 is arranged on the side of the second conductive layer 4 away from the substrate 1, the second opening 81 is arranged on the second planarization layer 8, the orthographic projection of the second opening 81 on the substrate 1 is located within the orthographic projection of the first opening 342 on the substrate 1, for example, the orthographic projection of the first opening 342 on the substrate 1 can cover the orthographic projection of the second opening 81 on the substrate 1, and the area of the orthographic projection of the first opening 342 on the substrate 1 is greater than the area of the orthographic projection of the second opening 81 on the substrate 1; or the edge line of the orthographic projection of the first opening 342 on the substrate 1 can coincide with the edge line of the orthographic projection of the second opening 81 on the substrate 1. The second protective layer 35 is arranged on the side of the second planarization layer 8 away from the substrate 1.

[0157] The first planarization layer 34 and the second conductive layer 4 can be protected by the second planarization layer 8 and the second protective layer 35, and the first planarization layer 34 and the second conductive layer 4 will not be damaged in the process of stripping the anisotropic conductive film ACF, the hole wall of the first via hole 32 close to the recessed part 31 will not be dug through, the second trace 41 in the first via hole 32 will not be disconnected, and the display effect is guaranteed; moreover, the second planarization layer 8 can planarize the first via hole 32 to provide a relatively flat plane for the subsequent film layer.

[0158] In the case of the above-mentioned second planarization layer 8, as shown in FIG. 17, the array substrate can further include a first electrode 5 and a second electrode 7 in the display area AA, the first electrode 5 is arranged between the second planarization layer 8 and the second protective layer 35; the material of the first electrode 5 can include a transparent conductive material, for example, the material of the first electrode 5 can include indium-tin-oxide (ITO), indium-zinc-oxide (IZO), etc., and the first electrode 5 can be a pixel electrode. The second electrode 7 is arranged on the side of the second protective layer 35 away from the substrate 1, and the material of the second electrode 7 can include a transparent conductive material, for example, the material of the second electrode 7 can include indium-tin-oxide (ITO), indium-zinc-oxide (IZO), etc., and the second electrode 7 can be a common electrode.

[0159] As shown in FIG. 13 and FIG. 17, the array substrate can further include a gate layer 9, a gate insulating layer 10, an active layer 11, a source-drain layer 12 and a touch function layer 13 in the display area AA; the gate layer 9 is arranged on one side of the substrate 1, and the gate layer 9 can include a gate 91 and a gate line, or part of the gate line can be reused as the gate 91; the gate line can extend along the second direction Y. The gate layer 9 can include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu), and the gate layer 9 can be a single-layer film or a multi-layer film.

[0160] The gate insulating layer 10 is provided on the side of the gate layer 9 facing away from the substrate 1, and can include a silicon compound, a metal oxide, or the like. For example, the gate insulating layer 10 can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. These can be used alone or in combination with one another. The gate insulating layer 10 can be a single layer film or a multi-layer film formed as a stacked structure of layers of different materials. The gate insulating layer 10 can be provided only on the side of the gate layer 9 facing away from the substrate 1, but can of course also be arranged over the entire surface of the substrate 1.

[0161] The active layer 11 is provided on the side of the gate insulating layer 10 facing away from the substrate 1, and can include polycrystalline silicon. However, the present disclosure is not limited to this, and the active layer 11 can include single-crystal silicon, low-temperature polycrystalline silicon, amorphous silicon, an oxide semiconductor, or the like. The active layer 11 can include a first conductive connection portion 111, a channel portion 112, and a second conductive connection portion 113 connected in this order, for example, with the first and second conductive connection portions 111 and 113 connected to opposite ends of the channel portion 112.

[0162] The source-drain layer 12 is provided on the side of the active layer 11 facing away from the substrate 1, and can include at least one metal selected from aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The source-drain layer 12 can be a single layer film or a multi-layer film. For example, the source-drain layer 12 can be formed as a stacked structure having Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu. The source-drain layer 12 can include a data line, a source electrode 121, and a drain electrode 122, the source electrode 121 can be part of the data line or can be connected to the data line. The source electrode 121 is connected to the first conductive connection portion 111, the drain electrode 122 is connected to the second conductive connection portion 113, and the insulating layer group 3 is provided on the side of the source-drain layer 12 facing away from the substrate 1. Furthermore, the first electrode 5 is connected to the drain electrode 122, so that a display driving signal can be input to the first electrode 5 through the drain electrode 122.

[0163] The touch function layer 13 is provided on the side of the insulating layer group 3 facing away from the substrate 1, and can include a plurality of touch electrodes and touch leads. In this case, a touch driving circuit can be integrated in the data driver DataIC, so that the data driver DataIC can output a touch driving signal and receive a touch sensing signal to realize a touch function.

[0164] The touch function layer 13 can be arranged in the same layer and of the same material as the second conductive layer 4, the gate layer 9 can be arranged in the same layer and of the same material as the first sub-conductive layer 22, the source-drain layer 12 can be arranged in the same layer and of the same material as the second sub-conductive layer 24, and the gate insulation layer 10 can be arranged in the same layer and of the same material as the first insulation layer 23.

[0165] Of course, in some other example embodiments of the present disclosure, the touch function layer 13 can not include a touch electrode, i.e., the touch function layer 13 does not play a touch role, but only serves as a connection trace.

[0166] It should be noted that the same layer and the same material are formed by the same patterning process; for the conductive layer, since different signals need to be conducted, the two conductive layers arranged in the same layer and of the same material can be connected or not connected according to the functional requirements; for the insulation layer, it is generally connected as a whole.

[0167] Referring to FIGS. 18-20, in some example embodiments of the present disclosure, the gate layer 9 can include a first lead wire 92 extending from the binding area BOD to the display area AA, and the first lead wire 92 can realize signal transmission between the binding area BOD and the display area AA. The source-drain layer 12 can include a second lead wire 123 extending from the binding area BOD to the display area AA, and the second lead wire 123 can realize signal transmission between the binding area BOD and the display area AA.

[0168] A first protection layer 33 is arranged on the side of the source-drain layer 12 away from the substrate 1, a touch function layer 13 is arranged on the side of the first protection layer 33 away from the substrate 1, the touch function layer 13 can include a third lead wire 131 extending from the binding area BOD to the display area AA, and the third lead wire 131 can realize signal transmission between the binding area BOD and the display area AA.

[0169] A first planarization layer 34 is arranged on the side of the touch function layer 13 away from the substrate 1, and a first opening part 342 is arranged on the first planarization layer 34, the first opening part 342 being arranged in the non-display area NAA.

[0170] A first electrode 5 is arranged on the side of the first planarization layer 34 away from the substrate 1, the first electrode 5 can be connected to the drain 122 through a via hole on the first protection layer 33 and a via hole on the first planarization layer 34, and a display signal can be input to the first electrode 5 through the drain 122. A second protection layer 35 is arranged on the side of the first electrode 5 away from the substrate 1. In the non-display area NAA, the second protection layer 35 covers the first planarization layer 34 and covers the first opening part 342 to form a recessed part 31. A second electrode 7 is arranged on the side of the second protection layer 35 away from the substrate 1.

[0171] The touch function layer 13 is arranged on the side of the first planarization layer 34 close to the substrate 1, so that the first lead 92, the second lead 123 and the third lead 131 of the touch function layer 13 do not cover the edge of the recess 31, so that in the process of peeling the anisotropic conductive adhesive film ACF, even if the insulating layer group 3 around the recess 31 is scratched, the first lead 92, the second lead 123 and the third lead 131 will not be damaged, and the first lead 92, the second lead 123 and the third lead 131 will not be caused to be broken, so as to ensure the display effect.

[0172] The line width of the first lead 92 is about 1.8 mm, and the line width of the second lead 123 is about 1.8 mm.

[0173] The line width of the third lead 131 is greater than or equal to 4 mm, for example, the line width of the third lead 131 can be 4.2 mm, 4.5 mm, 4.7 mm, 5 mm, 5.3 mm, 5.5 mm, 5.8 mm, etc.

[0174] Since no planarization layer is arranged on the side of the touch function layer 13 close to the substrate 1, the base surface formed by the third lead 131 is not flat, that is, the base surface formed by the third lead 131 is a convex-concave surface, generally the positions where the first lead 92 and the second lead 123 are arranged are convex structures, and the other positions are concave structures; if the line width of the third lead 131 is set to be relatively narrow, the third lead 131 is prone to be broken at the climbing position; if the line width of the third lead 131 is set to be relatively wide, the strength of the third lead 131 is relatively large, and the third lead 131 is not prone to be broken at the climbing position.

[0175] Of course, in some other example embodiments, the extension direction of the first lead 92 can be the same as the extension direction of the second lead 123, and the extension direction of the third lead 131 can also be the same as the extension direction of the second lead 123, that is, the extension directions of the first lead 92, the second lead 123 and the third lead 131 are all the same. Moreover, the orthographic projection of the third lead 131 on the substrate 1 does not overlap the orthographic projection of the first lead 92 on the substrate 1, and the orthographic projection of the third lead 131 on the substrate 1 does not overlap the orthographic projection of the second lead 123 on the substrate 1, so that the third lead 131 is not arranged to cross the first lead 92 and the second lead 123, so that the third lead 131 does not need to climb and will not be broken at the climbing position. For example, the orthographic projection of the third lead 131 on the substrate 1 can be located between the orthographic projection of the first lead 92 on the substrate 1 and the orthographic projection of the second lead 123 on the substrate 1.

[0176] In this case, the line width of the third lead 131 is about 1.8 mm.

[0177] In addition, the example embodiment does not increase the number of masks relative to the prior art, merely adjusts the process flow, and has a small increase in cost.

[0178] Furthermore, the first lead 92, the second lead 123, and the third lead 131 are arranged in sequence to form a group of leads, and a plurality of groups of leads are arranged in sequence.

[0179] Referring to FIG. 21, in some example embodiments of the present disclosure, a third protective layer 6 can be provided between the touch function layer 13 and the first planarization layer 34 on the basis of that shown in FIG. 18. The third protective layer 6 can be made of an inorganic material, for example, silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0180] In the non-display area NAA, the third protective layer 6 can cover a portion of the third lead 131 close to the display area AA, and only expose the binding pins of the third lead 131. The third lead 131 can be protected by the third protective layer 6 to avoid corrosion caused by the third lead 131 being exposed to air for a long time during subsequent processes such as preparation of the first electrode 5 and the like. In addition, during binding, the problem of short circuit caused by contact between the anisotropic conductive adhesive film ACF and the exposed third lead 131 can be avoided.

[0181] In addition, the example embodiment does not increase the number of masks relative to the prior art, merely adjusts the process flow, and has a small increase in cost.

[0182] Based on the same inventive concept, the example embodiments of the present disclosure provide a display device, which can include the array substrate of any one of the above. The specific structure of the array substrate has been described in detail above, and thus will not be described again here.

[0183] The display device can be a liquid crystal display panel, an OLED (Organic Electroluminescence Display) display panel, a QLED (Quantum Dot Light Emitting Diodes) display panel, a micro-LED (micro-Light Emitting Diode) display panel, a mini-LED (mini-Light Emitting Diode) display panel, or the like.

[0184] In the case where the display device can be a liquid crystal display panel, the display device can further include a color filter substrate 15, and the color filter substrate 15 and the array substrate are bonded by a frame 14.

[0185] The specific type of the display device is not particularly limited, and any type of display device commonly used in the art can be used, such as a mobile device such as a mobile phone, a wearable device such as a watch, a VR device, and the like. The specific type of the display device can be selected by a person skilled in the art according to the specific use of the display device, and will not be described here.

[0186] It should be noted that the display device further includes other necessary components and components in addition to the array substrate. For example, a display device includes a housing, a circuit board, a power line, and the like. The specific use requirements of the display device can be supplemented by a person skilled in the art, and will not be described here.

[0187] Compared with the prior art, the display device provided by the example embodiment of the present application has the same beneficial effects as the array substrate provided by the example embodiment described above, and will not be described here.

[0188] Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon considering the specification and practicing the present disclosure disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common general knowledge or conventional technical means in the art that are not disclosed in the present disclosure. The specification and examples are only considered to be exemplary, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. An array substrate having a display area and a non-display area, the non-display area including a bonding area, wherein, The array substrate comprises: a substrate substrate; a first conductive layer group provided on one side of the substrate substrate, the first conductive layer group comprising a first trace; an insulating layer group provided on the side of the first conductive layer group away from the substrate substrate, the insulating layer group being provided with a recess, the recess being located in the non-display area, a normal projection of the binding area on the substrate substrate at least partially overlapping a normal projection of the recess on the substrate substrate, the insulating layer group being provided with a first via, the first via being located on the side of the recess close to the display area, the first trace extending from at least the first via to the binding area; a second conductive layer provided on the side of the insulating layer group away from the substrate substrate, the second conductive layer comprising a second trace, the second trace being located on the side of the recess close to the display area, and the second trace being electrically connected to the display area, the second trace being connected to the first trace through the first via.

2. The array substrate according to claim 1, wherein, The distance between the first via and the edge of the recess close to the display area is greater than or equal to 10 μm.

3. The array substrate of claim 1, wherein, The first conductive layer group comprises: a first sub-conductive layer provided on one side of the substrate substrate; a first insulating layer provided on the side of the first sub-conductive layer away from the substrate substrate; a second sub-conductive layer provided on the side of the first insulating layer away from the substrate substrate, the second sub-conductive layer comprising the first trace.

4. The array substrate of claim 1, wherein, The first conductive layer group comprises: a first sub-conductive layer provided on one side of the substrate substrate, the first sub-conductive layer comprising a first connection trace; a first insulating layer provided on the side of the first sub-conductive layer away from the substrate substrate, the first insulating layer being provided with a second via; a second sub-conductive layer provided on the side of the first insulating layer away from the substrate substrate, the second sub-conductive layer comprising a second connection trace, the second connection trace being electrically connected to the first connection trace through the second via to form the first trace, the second trace being connected to the second connection trace through the first via.

5. The array substrate according to claim 4, wherein, A normal projection of the second connection trace on the substrate substrate is located between a normal projection of the recess on the substrate substrate and the display area, and the first connection trace extends from at least the second via to the binding area.

6. The array substrate according to claim 4, wherein, The first sub-conductive layer further comprises a third trace and a fourth trace, the third trace extending from the binding area to the display area; the second sub-conductive layer further comprises a fifth trace, a normal projection of the fifth trace on the substrate substrate being located on the side of the normal projection of the recess on the substrate substrate close to the display area, and the fifth trace being electrically connected to the display area; the first insulating layer is provided with a third via, the third via being located on the side of the recess close to the display area; the fourth trace extends from at least the third via to the binding area, and the fifth trace is connected to the fourth trace through the third via.

7. The array substrate according to claim 3 or 4, wherein, The first sub-conductive layer comprises a third trace extending from the binding area to the display area; and the second sub-conductive layer comprises a sixth trace extending from the binding area to the display area.

8. The array substrate according to any one of claims 2 to 6, wherein The insulating layer group comprises: a first protective layer disposed on a side of the first conductive layer group away from the substrate, the first protective layer being provided with a first sub-via hole; a first planarization layer disposed on a side of the first protective layer away from the substrate, the first planarization layer being provided with a second sub-via hole and a first opening portion; a second protective layer disposed on a side of the first planarization layer away from the substrate, the second protective layer being provided with a third sub-via hole, and the second conductive layer being disposed on a side of the second protective layer away from the substrate; wherein the third sub-via hole, the second sub-via hole and the first sub-via hole are sequentially communicated to form the first via hole, and a normal projection of the recess portion on the substrate is located within a normal projection of the first opening portion on the substrate.

9. The array substrate of claim 8, wherein, In the display area, the array substrate further comprises: a first electrode disposed between the first planarization layer and the second protective layer; a third protective layer disposed on a side of the second conductive layer away from the substrate; a second electrode disposed on a side of the third protective layer away from the substrate.

10. The array substrate according to any one of claims 2 to 6, wherein, The insulating layer group comprises: a first protective layer disposed on a side of the first conductive layer group away from the substrate, the first protective layer being provided with a first sub-via hole; a first planarization layer disposed on a side of the first protective layer away from the substrate, the first planarization layer being provided with a second sub-via hole and a first opening portion, and the second conductive layer being disposed on a side of the first planarization layer away from the substrate; wherein the second sub-via hole and the first sub-via hole are sequentially communicated to form the first via hole, and a normal projection of the recess portion on the substrate is located within a normal projection of the first opening portion on the substrate. The array substrate further comprises:

11. The array substrate of claim 10, wherein, a second planarization layer disposed on a side of the second conductive layer away from the substrate, the second planarization layer being provided with a second opening portion, and a normal projection of the second opening portion on the substrate being located within a normal projection of the first opening portion on the substrate; a second protective layer disposed on a side of the second planarization layer away from the substrate. In the display area, the array substrate further comprises:

12. The array substrate of claim 11, wherein, a first electrode disposed between the second planarization layer and the second protective layer; a second electrode disposed on a side of the second protective layer away from the substrate. The first conductive layer group comprises:

13. The array substrate of claim 1, wherein, a first sub-conductive layer disposed on a side of the substrate, the first sub-conductive layer comprising the first trace. The insulating layer group comprises:

14. The array substrate of claim 13, wherein, a first insulating layer disposed on a side of the first sub-conductive layer away from the substrate, the first insulating layer being provided with a fourth sub-via hole; a first protective layer disposed on a side of the first insulating layer away from the substrate, the first protective layer being provided with a first sub-via hole; ​ A first planarization layer is arranged on a side of the first protection layer away from the substrate, and a second sub-via and a first opening are arranged on the first planarization layer. A second protection layer is arranged on a side of the first planarization layer away from the substrate, and a third sub-via is arranged on the second protection layer, and the second conductive layer is arranged on a side of the second protection layer away from the substrate. The third sub-via, the second sub-via, the first sub-via, and the fourth sub-via are sequentially connected to form the first via, and a projection of the recess on the substrate is located within a projection of the first opening on the substrate.

15. The array substrate of claim 14, wherein, The first sub-conductive layer includes a third trace extending from the binding area to the display area. The array substrate further includes:

16. The array substrate of claim 14, wherein, A second sub-conductive layer is arranged between the first insulation layer and the first protection layer, and the second sub-conductive layer includes a sixth trace extending from the binding area to the display area. In the display area, the array substrate further includes: A first electrode is arranged between the first planarization layer and the second protection layer. A third protection layer is arranged on a side of the second conductive layer away from the substrate.

17. The array substrate of claim 13, wherein, A second electrode is arranged on a side of the third protection layer away from the substrate. The insulation layer group includes: A first insulation layer is arranged on a side of the first sub-conductive layer away from the substrate, and a fourth sub-via is arranged on the first insulation layer. A first protection layer is arranged on a side of the first conductive layer group away from the substrate, and a first sub-via is arranged on the first protection layer. A first planarization layer is arranged on a side of the first protection layer away from the substrate, and a second sub-via and a first opening are arranged on the first planarization layer.

18. The array substrate of claim 17, wherein, The second sub-via, the first sub-via, and the fourth sub-via are sequentially connected to form the first via, and a projection of the recess on the substrate is located within a projection of the first opening on the substrate. The array substrate further includes: A second planarization layer is arranged on a side of the second conductive layer away from the substrate, and a second opening is arranged on the second planarization layer, and a projection of the second opening on the substrate is located within a projection of the first opening on the substrate.

19. The array substrate according to any one of claims 3 to 6, 14 to 18, wherein, A second protection layer is arranged on a side of the second planarization layer away from the substrate. In the display area, the array substrate further includes: A gate layer is arranged on a side of the substrate, and the gate layer includes a gate. A gate insulation layer is arranged on a side of the gate layer away from the substrate. An active layer is arranged on a side of the gate insulation layer away from the substrate, and the active layer includes a first conductive connection, a channel, and a second conductive connection connected in sequence. A source-drain layer is arranged on a side of the active layer away from the substrate, and the source-drain layer includes a source a source and a drain, the source being connected to the first conductive connection part, the drain being connected to the second conductive connection part, and the insulating layer group being arranged on a side of the source and drain layer away from the substrate; a touch function layer arranged on a side of the insulating layer group away from the substrate; wherein the touch function layer and the second conductive layer are arranged in the same layer and of the same material, the gate layer and the first sub-conductive layer are arranged in the same layer and of the same material, the source and drain layer and the second sub-conductive layer are arranged in the same layer and of the same material, and the gate insulating layer and the first insulating layer are arranged in the same layer and of the same material.

20. A display device comprising: An array substrate comprising any one of claims 1-19.

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