Circuit board and semiconductor package including same

Abstract

One embodiment of the present invention discloses a circuit board comprising: a glass layer; and an insulating layer surrounding at least a portion of the glass layer, in which an outer surface of the glass layer includes a first surface located on the same plane as an outer surface of the insulating layer and a second surface covered by the insulating layer.

Description

Technical Field

[0001] An embodiment of the present invention relates to a circuit board and a semiconductor package. Background Technology

[0002] With advancements in the performance of electrical / electronic products, techniques for attaching mass packages to substrates of finite size have been proposed and researched. However, since typical packaging is based on mounting a single semiconductor chip, there are limitations in achieving the desired performance.

[0003] A general-purpose circuit board or packaging substrate has the following form: a processor package containing a processor chip and a memory package containing a memory chip attached thereto are integrated into one unit. The advantage of this packaging substrate is that by manufacturing the processor chip and memory chip as a single integrated package, the chip mounting area can be reduced, and high-speed signal transmission can be achieved through a shortened path. Due to these advantages, the aforementioned packaging substrate is widely used in mobile devices and the like.

[0004] On the other hand, in recent years, as electronic devices such as mobile devices have become more sophisticated in specifications and have adopted high-bandwidth memory (HBM), package sizes have increased. Furthermore, as the functionality required by application processors increases, a separate processor chip needs to be formed for each function, and a circuit board needs to be set up on which the processor chip can be mounted. In this case, even when the application processor is divided into two processor chips for each function, the number of (input / output) terminals set in each processor chip is increasing.

[0005] Furthermore, due to advancements in 5G, the Internet of Things (IoT), higher display resolutions, and increased communication speeds, the number of power lines and signal lines has increased, leading to a trend towards more terminals on processor chips. Consequently, the area and thickness of circuit boards, as well as the density of circuit patterns, are also increasing. Increased circuit board area or thickness can lead to issues such as difficulties in product miniaturization, reliability problems like board warping, and increased product costs. Therefore, increasing circuit pattern density rather than increasing circuit board area or thickness is more advantageous in terms of product cost, reliability (e.g., warping), and miniaturization. This necessitates finer circuit patterns and through-electrodes.

[0006] In particular, as circuit boards become thinner, deformations such as warping and twisting that occur during circuit board manufacturing increase. To prevent this, a glass core structure in which a glass plate is formed in the core portion of the circuit board has been proposed. Summary of the Invention

[0007] Technical issues

[0008] Embodiments of the present invention provide a circuit board that suppresses crack initiation and crack propagation through a glass layer structure, and a semiconductor package including the circuit board.

[0009] Furthermore, embodiments may provide a circuit board whose reliability is further improved by arranging a glass layer and an insulating layer disposed outside the glass layer, as well as a semiconductor package including the circuit board.

[0010] Furthermore, embodiments may provide a circuit board that suppresses warping by using a glass layer with high stiffness and a low coefficient of thermal expansion, and a semiconductor package including the circuit board.

[0011] The objectives to be addressed by the embodiments are not limited to those described above, and the objectives described above will include objectives and effects that can be illustrated by the solutions for the objectives and the embodiments described below.

[0012] Technical solution

[0013] The circuit board according to an embodiment of the present invention includes a glass layer and an insulating layer surrounding at least a portion of the glass layer, wherein the outer side surface of the glass layer includes a first surface located coplanar with the outer side surface of the insulating layer and a second surface covered by the insulating layer.

[0014] The outer side surface of the glass layer may include: a first outer side surface disposed in a first horizontal direction; a second outer side surface disposed in a second horizontal direction; a first groove surface disposed in a step-like manner along the second horizontal direction in a region adjacent to the first and second outer side surfaces; and a second groove surface contacting the second outer side surface and disposed in a step-like manner along the first horizontal direction in a region of the first outer side surface disposed in a step-like manner along the second horizontal direction. The glass layer may include a first protrusion located between the first groove surface and the second groove surface.

[0015] The first horizontal direction and the second horizontal direction can be perpendicular to each other, and the first protrusion can extend along a third horizontal direction having a predetermined angle relative to the first horizontal direction and the second horizontal direction.

[0016] The first protrusion may include an outwardly extending sub-protrusion, the sub-protrusion may further include a first sub-outer side surface disposed in a first horizontal direction, and the first sub-outer side surface may be located in a position coplanar with the outer side surface of the insulating layer.

[0017] The first outer side surface of the sub-protrusion can be located at a position further outward than the first outer side surface or the second outer side surface.

[0018] The distance between the first outer side surface of the protrusion and the first outer side surface in the second horizontal direction can be equal to the thickness of the insulating layer in the second horizontal direction.

[0019] Sub-protrusions may include: The first sub-protrusion extends from the first protrusion in a second horizontal direction; and The second protrusion extends from the first protrusion in the first horizontal direction.

[0020] The first sub-external side surface of the first sub-protrusion can be configured to be spaced apart from the first external side surface in the second horizontal direction, and the first sub-external side surface of the second sub-protrusion can be configured to be spaced apart from the second external side surface in the second horizontal direction.

[0021] The first sub-external side surface of the first sub-protrusion can be located at a position further outward than the first external side surface, and the first sub-external side surface of the second sub-protrusion can be located at a position further outward than the second external side surface.

[0022] The insulating layer may include a first insulating layer disposed on the glass layer and a second insulating layer disposed on the outside of the glass layer, and the first insulating layer may be disposed on the second insulating layer.

[0023] The outer side surface of the second insulating layer can be formed to be coplanar with the first outer side surface of the sub-protrusion.

[0024] The second insulating layer may include a first sub-insulating layer that contacts the first outer side surface and a second sub-insulating layer that contacts the second outer side surface.

[0025] The first sub-insulating layer may overlap with the first sub-protrusion in the second horizontal direction, and the first sub-insulating layer may overlap with the second sub-protrusion in the second horizontal direction.

[0026] The second insulating layer may include a third insulating layer surrounded by the first sub-protrusion and the second sub-protrusion.

[0027] The third sub-insulating layer can be spaced apart from the first and second sub-insulating layers.

[0028] The spacing between the first outer side surface and the outer side surface of the second insulating layer adjacent to the first outer side surface in the second horizontal direction may be different from the spacing between the second outer side surface and the outer side surface of the second insulating layer adjacent to the second outer side surface in the first horizontal direction.

[0029] The surface of the first groove can contact the first outer side surface and the first protrusion, and the surface of the second groove can contact the second outer side surface and the protrusion.

[0030] The first protrusion and the surface of the first groove or the surface of the second groove can form an angle of 40 to 50 degrees.

[0031] The length of the first protrusion in the second horizontal direction can be greater than the length of the surface of the first groove in the second horizontal direction.

[0032] The extension directions of the first and second sub-protrusions may not be parallel to each other.

[0033] The protrusion may include a second protrusion facing the first protrusion relative to the center of the glass layer.

[0034] The second protrusion may be asymmetrical with respect to the center of the glass layer compared to the first protrusion.

[0035] The extension lengths of the first protrusion and the second protrusion can be different.

[0036] It may include a connecting member disposed on the glass layer, and the connecting member may be disposed on the first protrusion.

[0037] The glass layer may include through holes, and the through holes may be disposed in the first protrusion.

[0038] The insulating layer can be placed in the through hole.

[0039] The circuit board according to an embodiment includes: a glass layer comprising glass; an insulating layer and an electrode layer disposed on the glass layer, wherein the glass layer includes a first protrusion protruding outward in a region where adjacent outer side surfaces contact each other, the insulating layer includes a first insulating layer disposed on the glass layer and a second insulating layer disposed outside the glass layer, and the outer side surface of the second insulating layer is at least partially coplanar with the outer side surface of the first protrusion.

[0040] Beneficial effects

[0041] Embodiments of the present invention provide a circuit board that can suppress crack initiation and crack propagation through a glass layer structure, as well as a semiconductor package including the circuit board.

[0042] Furthermore, the embodiments implement a circuit board whose reliability is further improved by arranging a glass layer and an insulating layer disposed on the outside of the glass layer, as well as a semiconductor package including the circuit board.

[0043] Furthermore, the embodiments implement a circuit board that suppresses warping by using a glass layer with high stiffness and low coefficient of thermal expansion, and a semiconductor package including the circuit board.

[0044] The various advantages and effects of the present invention are not limited to those described above, and can be more easily understood through the description of specific embodiments of the present invention. Attached Figure Description

[0045] Figure 1 This is a plan view of a circuit board according to a first embodiment of the present invention.

[0046] Figure 2 It is along Figure 1 A sectional view of line A-A'.

[0047] Figure 3 This is a plan view of the glass layer and the first insulating layer in a circuit board according to a first embodiment of the present invention.

[0048] Figure 4 This is a perspective view of a portion of the glass layer in a circuit board according to a first embodiment of the present invention.

[0049] Figure 5 This is a perspective view of a portion of the glass layer and a portion of the insulating layer in a circuit board according to a first embodiment of the present invention.

[0050] Figures 6 to 10 This is a view illustrating a method for manufacturing a circuit board according to a first embodiment of the present invention.

[0051] Figure 11 This is a view showing the glass layer in a circuit board according to a modified example.

[0052] Figure 12 This is a plan view of a circuit board according to a second embodiment of the present invention.

[0053] Figure 13 It is along Figure 12 A sectional view of line B-B'.

[0054] Figure 14 This is a plan view of a circuit board according to a third embodiment of the present invention.

[0055] Figure 15 It is along Figure 14 A sectional view of line C-C'.

[0056] Figure 16 This is a plan view of the glass layer in a circuit board according to the fourth embodiment of the present invention.

[0057] Figure 17 It is along Figure 16 A sectional view of line D-D'.

[0058] Figure 18 yes Figure 16 The modified example.

[0059] Figure 19 It is based on Figure 18 A cross-sectional view of the modified example circuit board.

[0060] Figure 20 This is a cross-sectional view of a circuit board according to a fifth embodiment of the present invention. Detailed Implementation

[0061] While the invention is readily adaptable to various modifications and alternative forms, specific embodiments thereof are illustrated by way of example in the accompanying drawings and will be described in detail herein. However, it should be understood that the invention is not intended to be limited to the specific forms disclosed, but rather, the invention encompasses all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

[0062] It should be understood that although the terms "second," "first," etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope of the invention, a first component may be referred to as a second component, and a second component may similarly be referred to as a first component. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0063] It should be understood that when a component is referred to as "connected" or "joined" to another component, it can be directly connected or joined to the other component, or there may be intermediate components. Conversely, when a component is referred to as "directly connected" or "directly joined" to another component, there are no intermediate components.

[0064] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood in this application that, when used in this specification, the terms “comprise,” “comprising,” “include,” and / or “including” indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0065] Terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the relevant context and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. It should be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the relevant context and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0066] In the following description, embodiments will be described in detail with reference to the accompanying drawings. Regardless of the reference numerals used in the drawings, the same reference numerals will be assigned to refer to the same parts, and redundant descriptions will be omitted.

[0067] Before describing the embodiments, an electronic device using a semiconductor package will be briefly described. The electronic device includes a motherboard (not shown). The motherboard may be physically and / or electrically connected to various components. For example, the motherboard may be connected to the semiconductor package of the embodiments. Various connection members (e.g., semiconductor devices) may be mounted on the semiconductor package.

[0068] The connection components may include active and / or passive devices. Active devices may be semiconductor chips in the form of integrated circuits (ICs), where hundreds to millions of devices are integrated into a single chip. Connection components may be logic chips, memory chips, etc. Logic chips may be central processing units (CPUs), graphics processing units (GPUs), etc. For example, a logic chip may be an application processor (AP) chip that includes at least one of a CPU, GPU, digital signal processor, cryptographic processor, microprocessor, and microcontroller; it may be an analog-to-digital converter, an application-specific integrated circuit (ASIC), etc.; or it may be a chipset that includes a specific combination of the components listed so far.

[0069] Memory chips can be stacked memories such as high-bandwidth memory (HBM). Furthermore, memory chips can include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.

[0070] On the other hand, the product group of semiconductor packaging using this embodiment can be any one of chip-scale packaging (CSP), flip chip-to-chip-scale packaging (FC-CSP), flip chip ball grid array (FC-BGA), package-on-package (PoP), and system-in-package (SiP), but the present invention is not limited thereto.

[0071] In addition, electronic devices can be smartphones, personal digital assistants, digital cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video game consoles, smartwatches, automotive electronics, etc. However, electronic devices are not limited to these and can be any other electronic device that processes data.

[0072] In the following description, in a circuit board according to an embodiment of the present invention, the insulating layer may include multiple insulating layers. The insulating layer may include a core layer (a glass layer described later) and an insulating layer. Additionally, the circuit board may be divided into an outer stacked region and an inner stacked region, and the inner stacked region may correspond to the core layer.

[0073] Figure 1 This is a plan view of a circuit board according to a first embodiment of the present invention. Figure 2 It is along Figure 1 A sectional view of line A-A'. Figure 3 This is a plan view of the glass layer and the first insulating layer in the circuit board according to the first embodiment of the present invention. Figure 4 This is a perspective view of a portion of the glass layer in a circuit board according to a first embodiment of the present invention. Figure 5 This is a perspective view of a portion of the glass layer and a portion of the insulating layer in a circuit board according to a first embodiment of the present invention.

[0074] Reference Figure 1 and Figure 2 The circuit board 100 according to the first embodiment may include a glass layer 110, an insulating layer 120, a protective layer 130, and an electrode portion 150. Additionally, the circuit board 100 according to the embodiment may include a semiconductor device SD and conductive members CB1 and CB2 located on one side (e.g., the upper side).

[0075] Glass layer 110 can be a "core layer" or a "substrate layer". Glass layer 110 can suppress warping that may occur when the circuit board becomes thinner. In other words, warping can be reduced by arranging a glass layer (or glass core) with high stiffness and low coefficient of thermal expansion (CTE) at the center or core of the circuit board. For example, glass layer 110 can have higher stiffness and lower coefficient of thermal expansion than insulating or protective layers.

[0076] Additionally, the glass layer 110 can be formed from a glass material. For example, the glass layer 110 can contain pure silica (approximately 100% SiO2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc. The glass layer 110 is not limited to silica-based glass compositions, and alternative glass materials such as fluoride glass, phosphate glass, and chalcogenide glass can also be used. Furthermore, the glass layer 110 can further contain additional additives to form a glass with specific physical properties. Such additives can contain calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda ash), as well as magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and can contain carbonates and / or oxides of these elements and other elements.

[0077] In addition, the glass layer 110 can be formed of an insulating material. Therefore, the glass layer 110 can be referred to as an "insulating layer" or the like.

[0078] Additionally, the glass layer 110 may be disposed in the center of the insulating layer 120. Furthermore, as will be described later, the glass layer 110 may include vias 110h. The vias 110h may have various shapes and may be formed in various locations, and their number and structure are not limited to those shown in the figures.

[0079] The insulating layer 120 may surround at least a portion of the glass layer 110. For example, the insulating layer 120 may be located outside the glass layer 110, or it may be located above or below the glass layer 110. In embodiments, the insulating layer 120 may contact the outer side surface, upper surface, or lower surface of the glass layer 110.

[0080] In this embodiment, the insulating layer 120 may be formed of multiple insulating layers. These multiple insulating layers may be formed of the same insulating material or different insulating materials.

[0081] In an embodiment, the insulating layer 120 may include a first insulating layer 122 disposed above or below the glass layer 110 and a second insulating layer 121 disposed outside the glass layer 110.

[0082] The first insulating layer 122 may be located on (above or below) the second insulating layer 121 and on (above or below) the glass layer 110. For example, the first insulating layer 122 may be in contact with the upper (or lower) surface of the second insulating layer 121 and the upper (or lower) surface of the glass layer 110.

[0083] As described above, depending on the structure or design of the circuit board 100, the insulating layer 120 can be formed from multiple layers. Furthermore, multiple circuit patterns, vias, etc., can be located on the insulating layer 120. For example, a via in the insulating layer 120 can be connected to a via in the glass layer 110.

[0084] The insulation layer 120 may comprise a thermosetting resin such as epoxy resin and a thermoplastic resin such as polyimide. In addition to the resin, the insulation layer 120 may further comprise a reinforcing material. The reinforcing material may be, for example, a fabric reinforcement, an inorganic filler, etc. The fabric reinforcement may be glass fiber, and the glass fiber may be impregnated with resin to form a prepreg (PPG).

[0085] For example, the insulating layer 120 can be formed of an insulating resin, such as a thermosetting resin and / or a photocurable resin. As a thermosetting resin, Ajinomoto laminated film (ABF), a product released by Ajinomoto Co., Ltd., can be used, or a prepreg (PPG) containing glass fibers can be used. As a photocurable resin, an insulating resin such as a photosensitive dielectric (PID) resin can be used. Examples of the aforementioned insulating resins can be epoxy resin, bismaleimide triazine (BT) resin, phenolic resin, etc., and may contain inorganic fillers such as silica. When the insulating resin is used as a core, the insulating resin can contain reinforcing materials such as glass fibers or aramid fibers. For example, as an example of the insulating layer 120, Ajinomoto laminated film (ABF), a product released by Ajinomoto Co., Ltd., can be used, and FR-4, BT, PID resin, BT, etc., can also be used. For example, the insulating layer 120 may include multiple layers composed of ABF.

[0086] The protective layer 130 may be located above or below the insulating layer 120. For example, the protective layer 130 may include a first protective layer 131 located above the first insulating layer 122 and a second protective layer 132 located below the first insulating layer 122.

[0087] Protective layer 130 can be used to protect pads from external moisture or contaminants and to prevent short circuits during the bonding of semiconductor devices and / or motherboards to circuit boards. As an example, protective layer 130 can be formed of solder resist. Specifically, the semiconductor devices and / or motherboards can have multiple terminals to be connected to the circuit board. Furthermore, the multiple terminals can be arranged in a high density. Solder can be used as an example when the multiple terminals of the circuit board are bonded to the pads. When using solder, solder short circuits (bridging) may occur between the high-density terminals, and to solve this short circuit problem, a solder resist with poor solder wetting properties can be provided. Additionally, protective layer 130 can be formed of a material with insulating properties for electrical connection. Therefore, protective layer 130 can be referred to as an "insulating layer" and can be one of the components of the aforementioned insulating layer 120. Protective layer 130 can contain resins, curing agents, photoinitiators, pigments, solvents, fillers, additives, acryloyl monomers, etc. Additionally, a third insulating layer (not shown) can include any one of a photoresist layer, a capping layer, and a polymer material.

[0088] Additionally, the insulating or protective layer 130 located in the outer stacked area of ​​the circuit board may have openings. These openings allow for electrical connection to another semiconductor device, circuit board, or similar device.

[0089] For the aforementioned electrical connections, conductive members CB1 and CB2 can be located above or below the circuit board 100. The conductive member CB1, located above the circuit board 100, can be electrically connected to the semiconductor device SD and the electrode portion 140. Conversely, the conductive member CB2, located below the circuit board 100, can be electrically connected to another board, etc.

[0090] In this embodiment, the wiring or electrode portion 140 may be configured for electrical connection between a motherboard or the like and a chip (e.g., a semiconductor device SD or chip). Additionally, the electrode portion 140 may include circuit patterns (or circuit pattern layers), pads, and through electrodes. The term "wiring" may correspond to "electrode pattern," "pattern," "line," etc.

[0091] In the electrode section 140, the circuit pattern can be designed in various forms for signal and / or power transmission with the semiconductor device, and can be provided in each stacked insulating layer 120.

[0092] In electrode section 140, through electrodes 141 and 142 are configured to pass through a portion of each vertically stacked insulating layer, thereby providing a vertical connection between circuit patterns disposed in the respective insulating layers. That is, the insulating layer may include vias (e.g., 110h) for arranging the through electrodes described above. In addition, for impedance optimization or heat dissipation, the through electrodes may have a width larger than the width of the circuit pattern, but are not limited thereto and can be freely designed.

[0093] In the electrode section 140, pads (e.g., 143) can be provided on each insulating layer. Furthermore, the pads (e.g., 143) can be electrically connected to circuit patterns. Additionally, the pads (e.g., 143) can be electrically connected to semiconductor devices and / or motherboards, substrates, etc.

[0094] Specifically, in the pads, the pads located on the outer side can be bonded to semiconductor devices, substrates, boards, etc., using solder, wires, conductive adhesives, etc., and can be configured to have a width larger than the width of the circuit pattern to address issues such as ensuring yield. However, the invention is not limited thereto, and depending on the technical limitations of the bonding process, the pads can have the same width as the circuit pattern.

[0095] Additionally, pads on the inner layer are used to connect the through-electrode to the circuit pattern. When the through-electrode is configured to have a width greater than the width of the circuit pattern, pads with a width greater than the width of the circuit pattern are provided to ensure alignment during the manufacturing process that requires the through-electrode to be placed on each circuit pattern. Therefore, each through-electrode may have an upper surface configured to be coplanar with the lower surface of the upper pad that directly contacts it, and a lower surface configured to be coplanar with the upper surface of the lower pad that directly contacts it. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean flat surfaces, but should be understood to include concave or convex surfaces depending on various manufacturing processes.

[0096] The semiconductor device SD can be mounted on the circuit board 100. The semiconductor device SD can be a logic chip, a memory chip, etc. The logic chip can be a central processing unit (CPU), a graphics processing unit (GPU), etc. For example, the logic chip can be an application processor (AP), which includes at least one of a CPU, GPU, digital signal processor, cryptographic processor, microprocessor, and microcontroller. Alternatively, the logic chip can be an analog-to-digital converter, an application-specific integrated circuit (ASIC), etc., or a chipset including a specific combination of the components listed so far. Additionally, the memory chip can be a stacked memory such as HBM. Furthermore, the memory chip can include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.

[0097] The electrode section 140 can be electrically connected to another plate via the aforementioned conductive member CB2.

[0098] Circuit boards can be classified into package substrates or interposers based on their function. Package substrates are used to mount semiconductor devices and / or interposers. Due to increasing data volume, circuit board yield can significantly decrease due to increased board area or an increased number of stacked insulating layers. Therefore, to improve the yield of circuit boards with a large number of stacked layers, circuit boards can be divided into interposers and package substrates, thereby improving overall circuit board yield. Additionally, as the density of semiconductor device terminals increases, it may be difficult to achieve package substrate pads with an area corresponding to the semiconductor device terminals. Therefore, interposers can act as a buffer between the pad size of the package substrate and the fine pattern size of the semiconductor device terminals.

[0099] The aforementioned packaging substrate and interposer can be classified as core-based substrates or coreless substrates based on the configuration of the insulating layers. In the case of a core-based substrate, the insulating layer may include a core layer, and the core layer may refer to a layer in the stacked insulating layers that includes reinforcing members. The reinforcing members may refer to glass fibers. The core layer may be set to be thicker than other insulating layers to prevent warping of the circuit board during processing. However, the core layer may cause problems such as voltage drop and signal loss, or may make it difficult to achieve thinness. Therefore, depending on the application, a coreless substrate in which the insulating layer of the circuit board does not include a core layer may be used.

[0100] In the circuit board 100 according to an embodiment of the present invention, the glass layer 110 can suppress cracking in the cut area of ​​the glass layer due to the brittleness of the glass during the manufacturing process of cutting the circuit board, and can suppress structural reliability problems (e.g., board separation defects) that occur only due to impacts applied to the external exposed portion of the glass layer.

[0101] Furthermore, the glass layer 110 according to the embodiment may have a structure that will be described later in order to suppress the formation of the aforementioned cracks.

[0102] Reference Figure 3 and Figure 4 In the circuit board 100 according to the embodiment, the glass layer 110 may have an outer side surface. The outer side surface of the glass layer 110 may include a first surface S1 disposed or formed as coplanar with the outer side surface 120S of the insulating layer 120 (e.g., the second insulating layer 121) and a second surface S2 covered by the insulating layer 120. For example, the second surface S2 may be located inwardly than the outer side surface 120S of the insulating layer. Here, "inwardly" may refer to a direction toward the center of the circuit board 100, and "outwardly" may refer to a direction opposite to the inwardly direction.

[0103] Alternatively, the outer surface of the glass layer 110 may include a first outer surface SF1 disposed in the first horizontal direction (X-axis direction) and a second outer surface SF2 disposed in the second horizontal direction (Y-axis direction). Or, the second surface S2 of the glass layer 110 may include the first outer surface SF1 and the second outer surface SF2.

[0104] In the following description, the structure of glass layer 110 will be described with reference to the structure on one side shown in the accompanying drawings. Therefore, the description of one side or region of glass layer 110 can be applied in the same way to the corresponding side or region.

[0105] More specifically, the outer surface of the glass layer 110 may include a first outer surface SF1, a second outer surface SF2, a first groove surface GS1, and a second groove surface GS2. Alternatively, the second surface S2 may include the first outer surface SF1, the second outer surface SF2, the first groove surface GS1, and the second groove surface GS2.

[0106] The first outer side surface SF1 can be disposed in the first horizontal direction (X-axis direction). In addition, the second outer side surface SF2 can be disposed in the second horizontal direction (Y-axis direction).

[0107] Furthermore, the first groove surface GS1 may extend in a direction different from the first outer side surface SF1. The first groove surface GS1 may contact the first outer side surface SF1, and the first outer side surface SF1 may be stepped along the second horizontal direction (Y-axis direction) in the region adjacent to the first outer side surface SF1 and the second outer side surface SF2. The first groove surface GS1 may be positioned along the second horizontal direction (Y-axis direction).

[0108] Furthermore, the second groove surface GS2 can extend in a direction different from the direction in which the second outer side surface SF2 extends. The second groove surface GS2 can contact the second outer side surface SF2. Additionally, the second groove surface GS2 can be configured to be adjacent to a stepped region of the first outer side surface SF1 in the second horizontal direction (Y-axis direction). The second groove surface GS2 can also be stepped in the first horizontal direction (X-axis direction). Furthermore, the second groove surface GS2 can be located in the first horizontal direction (X-axis direction).

[0109] Additionally, glass layer 110 may include a protrusion located in a corner region where adjacent outer side surfaces contact each other. For example, glass layer 110 may include a protrusion located between a first outer side surface SF1 and a second outer side surface SF2. In an embodiment, glass layer 110 may include a first protrusion PR1 located between a first groove surface GS1 and a second groove surface GS2. In glass layer 110, protrusion PR1 may be located in a corner region where outer side surfaces contact each other.

[0110] Furthermore, the first horizontal direction (X-axis direction) can be perpendicular to the second horizontal direction (Y-axis direction). Additionally, the third horizontal direction (K-axis direction) can have a predetermined angle relative to the first horizontal direction (X-axis direction) and the second horizontal direction (Y-axis direction). As described above, the third horizontal direction (K-axis direction) can be parallel to the direction extending toward the corner where adjacent outer side surfaces contact each other.

[0111] Furthermore, the glass layer 110 may include a first groove GR1 located in a corner region where adjacent outer side surfaces contact each other. The first groove surface GS1 and the second groove surface GS2 may correspond to the inner surface of the first groove GR. Additionally, a first protrusion PR1 may also be provided in the first groove GR1.

[0112] In an embodiment, the first protrusion PR1 may include outwardly extending sub-protrusions. The sub-protrusions may include a first sub-protrusion SPR1 and a second sub-protrusion SPR2 extending in different directions. The first sub-protrusion SPR1 may extend in a second horizontal direction. The second sub-protrusion SPR2 may extend in a first horizontal direction. In other words, the extending directions of the first sub-protrusion SPR1 and the second sub-protrusion SPR2 may not be parallel to each other. Therefore, even if a crack occurs at the first and second sub-protrusions in contact with the sawing line of the glass layer 110, the crack is less likely to propagate into the glass layer 110.

[0113] The sub-protrusion may include a first sub-outer side surface SSF1 disposed in a first horizontal direction and a second sub-outer side surface SSF2 disposed in a second horizontal direction. For example, the first sub-protrusion SPR1 may include the first sub-outer side surface SSF1 as the outermost side surface. The second sub-protrusion SPR2 may include the second sub-outer side surface SSF2 as the outermost side surface.

[0114] Furthermore, the first sub-outer side surface SSF1 can be configured to be coplanar with the outer side surface 120S of the insulating layer. In other words, the first sub-outer side surface SSF1 can be formed to be coplanar with the outer side surface 120S of the adjacent insulating layer.

[0115] Similarly, the second sub-outer side surface SSF2 can be configured to be coplanar with the outer side surface 120S of the insulating layer. In other words, the second sub-outer side surface SSF2 can be formed to be coplanar with the outer side surface 120S of the adjacent insulating layer.

[0116] The first sub-outer side surface SSF1 can be configured to be coplanar with the outer side surface 120S of the insulating layer adjacent to the first outer side surface SF1. Similarly, the second sub-outer side surface SSF2 can be configured to be coplanar with the outer side surface 120S of the insulating layer adjacent to the second outer side surface SF2. For example, the first sub-outer side surface SSF1 and the second sub-outer side surface SSF2 can be formed to be coplanar with the outer side surface 120S of the insulating layer perpendicular to each other. In other words, in the circuit board according to the embodiment, the outer side surface 120S of the second insulating layer 121 can be at least partially coplanar with the outer side surface of the first protrusion PR.

[0117] The first and second sub-outer side surfaces of the first and second sub-protrusions can be disposed further outward relative to the first and second outer side surfaces, respectively. For example, the first sub-outer side surface SSF1 of the first sub-protrusion SPR1 can be disposed at a position further outward than the first outer side surface SF1.

[0118] Further reference Figure 5 The first sub-outer side surface SSF1 of the first sub-protrusion SPR1 can be configured to be spaced apart from the first outer side surface SF1 in the second horizontal direction. Therefore, the first sub-outer side surface SSF1 and the first outer side surface SF1 can have a first spacing distance gap1 between them in the second horizontal direction (Y-axis direction).

[0119] Furthermore, the second sub-outer side surface SSF2 of the second sub-protrusion SPR2 can be positioned further outward than the second outer side surface SF2. The second sub-outer side surface SSF2 of the second sub-protrusion SPR2 can be spaced apart from the second outer side surface SF2 in the first horizontal direction. Therefore, the second sub-outer side surface SSF2 and the second outer side surface SF2 can have a second spacing distance gap2 between them in the first horizontal direction (X-axis direction).

[0120] Furthermore, the spacing distances (e.g., the first spacing distance and the second spacing distance) can each be equal to the thickness of the insulating layer. That is, the spacing distance between the outer surface of the sub-protrusion and the outer surface of the insulating layer can correspond to the thickness of the insulating layer in contact with the outer surface. For example, the first spacing distance gap1 is the spacing distance between the first sub-outer surface SSF1 and the first outer surface SF1. Therefore, the first spacing distance gap1 can correspond to the thickness of the second insulating layer 121 located outside the first outer surface SF1 in the second horizontal direction (Y-axis direction). Furthermore, the second spacing distance gap2 is the spacing distance between the second sub-outer surface SSF2 and the second outer surface SF2. Therefore, the second spacing distance gap2 can correspond to the thickness of the second insulating layer 121 located outside the second outer surface SF2 in the first horizontal direction (X-axis direction). With this configuration, during the circuit board cutting process, a portion of the outer surface of the glass layer 110 can avoid contact with the cutting line.

[0121] Furthermore, the first gap distance gap1 can be the gap distance between the first outer side surface SF1 and the outer side surface 120S of the second insulating layer adjacent to the first outer side surface SF1 in the second horizontal direction. Furthermore, the second gap distance gap2 can correspond to the gap distance between the second outer side surface SF2 and the outer side surface 120S of the second insulating layer adjacent to the second outer side surface SF2 in the first horizontal direction.

[0122] The first spacing gap1 and the second spacing gap2 can be the same or different from each other. With this configuration, the insulating layer or the second insulating layer 121 can easily protect at least a portion of the glass layer 110 surrounded by the second insulating layer 121. That is, the reliability of the circuit board 100 according to the embodiment can be improved.

[0123] The second insulating layer 121 may include a first sub-insulating layer 121a that contacts the first outer side surface SF1 and a second sub-insulating layer 121b that contacts the second outer side surface SF2.

[0124] The first sub-insulating layer 121a may overlap with the first sub-protrusion SPR1 in the first horizontal direction (X-axis direction). The second sub-insulating layer 121b may overlap with the second sub-protrusion SPR2 in the second horizontal direction (Y-axis direction).

[0125] Furthermore, the second insulating layer 121 may include a third sub-insulating layer 121c. The third sub-insulating layer 121c may be surrounded by a first sub-protrusion SPR1 and a second sub-protrusion SPR2. The third sub-insulating layer 121c may overlap with the first sub-protrusion SPR1 and the first sub-insulating layer 121a in a first horizontal direction. Additionally, the third sub-insulating layer 121c may overlap with the second sub-protrusion SPR2 and the second sub-insulating layer 121b in a second horizontal direction.

[0126] Even if a crack occurs during the manufacturing process, the circuit board 100 according to the embodiment can easily suppress the crack from propagating into the glass layer 110 via the first sub-protrusion SPR1 and the second sub-protrusion SPR2. In other words, the first sub-protrusion SPR1 and the second sub-protrusion SPR2 can easily prevent the crack from propagating into the glass layer, thereby improving the reliability of the glass layer 110.

[0127] Furthermore, the first sub-protrusion SPR1 and the second sub-protrusion SPR2 have a structure extending along a first horizontal direction and a second horizontal direction, rather than along a third horizontal direction, in the corner region where the outer side surfaces contact each other. This easily reduces the occurrence of cracks or damage caused by impacts in the corner region. In addition, the third sub-insulating layer 121c can suppress damage to the glass layer caused by impacts in the corner region, thereby further improving the reliability of the circuit board.

[0128] The third sub-insulating layer 121c can be spaced apart from the first sub-insulating layer 121a and the second sub-insulating layer 121b. The third sub-insulating layer 121c can be spaced apart from the first sub-insulating layer 121a through the first sub-protrusion SPR1. In addition, the third sub-insulating layer 121c can be spaced apart from the second sub-insulating layer 121b through the second sub-protrusion SPR2.

[0129] Furthermore, according to the embodiment, the first groove surface GS1 can contact the first outer side surface SF1 and the first protrusion PR1. Additionally, the second groove surface GS2 can contact the second outer side surface SF2 and the first protrusion PR1.

[0130] As described above, the first protrusion PR1 can form a predetermined angle relative to the first groove surface GS1 or the second groove surface GS2. For example, the first protrusion PR1 can form an angle of 40 to 50 degrees relative to the first groove surface GS1 or the second groove surface GS2.

[0131] Furthermore, the length L1 of the first sub-protrusion SPR1 of the first protrusion PR1 in the second horizontal direction (Y-axis direction) can be less than the length L2 of the first groove surface GS1 in the second horizontal direction (Y-axis direction).

[0132] Furthermore, the length L3 of the second sub-protrusion SPR2 of the first protrusion PR1 in the first horizontal direction (X-axis direction) can be less than the length L4 of the second groove surface GS2 in the first horizontal direction (X-axis direction).

[0133] With this configuration, during the cutting process, the first or second outer side surface can be spaced apart from the cutting line, making it less likely for cracks caused by the cutting to propagate into the glass layer 110. Furthermore, cracks generated at the first and second sub-protrusions will not propagate inwards.

[0134] Figures 6 to 10 This is a view illustrating a method for manufacturing a circuit board according to a first embodiment of the present invention. Figure 11 This is a view showing the glass layer in a circuit board according to a modified example.

[0135] The method for manufacturing a circuit board according to the first embodiment includes: arranging a glass layer; forming holes in the glass layer; arranging an insulating layer and an electrode layer on the glass layer; forming a protective layer; and arranging conductive components and semiconductor devices.

[0136] In this invention, the circuit board according to the embodiments can correspond to a unit circuit board. That is, during the manufacturing process, the mother circuit board may include a unit circuit board. The mother circuit board can be divided into multiple unit circuit boards along a cutting line.

[0137] To form the master circuit board, a glass layer can be first laid. In the following text, each component can be referred to as a "mother" component before the master circuit board is cut into unit circuit boards. That is, the glass layer can correspond to the "mother glass layer".

[0138] Reference Figures 6 to 8A glass layer 110M can be set. The glass layer 110M can include multiple unit glass layers 110.

[0139] Holes or grooves can be formed in multiple unit glass layers 110. For example, in the mother glass layer 110M, through holes for arranging through electrodes, protrusions for joining adjacent unit glass layers, and grooves for forming a first outer side surface and a second outer side surface can be formed. Grooves or holes can be formed by various etching methods, such as mechanical etching or chemical etching.

[0140] Through such grooves or holes, each unit glass layer 110 can be connected to adjacent unit glass layers via protrusions located in corner areas where the outer side surfaces of adjacent unit glass layers contact each other. More specifically, adjacent unit glass layers can be connected to each other via sub-protrusions of the protrusions.

[0141] Additionally, as described above, the first protrusion may be located between the first outer side surface SF1 and the second outer side surface SF2. Multiple first protrusions may be provided in a unit glass layer. For example, the protrusions may be formed symmetrically in the unit glass layer relative to the center C1 of the unit glass layer, or relative to a bisector extending in a first horizontal direction, or a bisector extending in a second horizontal direction. For example, the unit glass layer may include protrusions provided in four regions between the first outer side surface SF1 and the second outer side surface SF2. Among the protrusions, the protrusion located on one side relative to the center C1 is referred to as the first protrusion PR1, and the protrusion located on the other side relative to the center C1 is referred to as the second protrusion PR1'.

[0142] Each of the first protrusion PR1 and the second protrusion PR1' can be connected to an adjacent unit glass layer. Additionally, each of the first protrusion PR1 and the second protrusion PR1' can contact a different unit glass layer.

[0143] In this embodiment, the first unit glass layer 110a, the second unit glass layer 110b, the third unit glass layer 110c, and the fourth unit glass layer 110d can be connected to each other via protrusions. For example, the first unit glass layer 110a and the fourth unit glass layer 110d can be connected to each other via protrusions extending in directions parallel to each other. Therefore, the first unit glass layer 110a and the fourth unit glass layer 110d can face each other. Similarly, the second unit glass layer 110b and the third unit glass layer 110c can be connected to each other via protrusions extending in directions parallel to each other. Therefore, the second unit glass layer 110b and the third unit glass layer 110c can face each other.

[0144] Further reference Figure 9An insulating layer and an electrode layer can be disposed on the glass layer 110M. For example, through electrodes can be formed in vias or holes in the glass layer. In the electrode section, a circuit pattern layer can be formed using printed circuit board manufacturing processes, such as additive processes, subtractive processes, modified semi-additive processes (MSAP), and semi-additive processes (SAP). Alternatively, patterns can be formed using dry film or the like.

[0145] In addition, the second insulating layer can be disposed on the outside of the glass layer 110M.

[0146] Furthermore, the insulating layer can be disposed above or below the glass layer 110M. In other words, the first insulating layer can be formed above or below the glass layer 110M. Additionally, a protective layer can be formed on the insulating layer, and conductive components, semiconductor devices, etc., can be disposed thereon. However, it is possible to perform dicing first without arranging conductive components and semiconductor devices.

[0147] Additionally, the motherboard can be cut along the dicing line into unit glass layers or unit circuit boards. Multiple unit circuit boards can be manufactured through cutting.

[0148] In this case, the thicknesses of the second insulating layers 121 of adjacent unit circuit boards can differ from each other. For example, depending on the location of the cut line, the spacing distances gapa and gapb between the outer side surface of the glass layer 110 and the outer side surface of the second insulating layer adjacent to the outer side surface of the glass layer can vary. Therefore, in a unit circuit board, the spacing distances between an outer side surface and the outer side surface of the second insulating layer adjacent to (or outside) that outer side surface can differ from each other.

[0149] In addition, in multiple unit circuit boards, the spacing distances gapa and gapb between an outer side surface of a unit circuit board and the outer side surface of a second insulating layer adjacent to (or to the outside of) that outer side surface can be different from each other.

[0150] Furthermore, the length L2 of the first groove surface GS1 in the second horizontal direction (Y-axis direction) (or the length L4 of the second groove surface GS2 in the first horizontal direction (X-axis direction)) can be greater than or equal to the width L5 of the cutting line. This configuration can reduce the occurrence of cracks due to cutting, or limit the occurrence of cracks to the protrusion side.

[0151] Additionally, the first protrusion PR1 can form an angle θ of 40 to 50 degrees relative to the first groove surface GS1 or the second groove surface GS2. Furthermore, the length L6 of the third sub-insulating layer in the first horizontal direction or the second horizontal direction can be greater than half the width L5 of the cutting line.

[0152] With this configuration, the propagation of cracks caused by cutting in the glass layer can be suppressed within a single circuit board. Furthermore, cracks may only exist in the first and second sub-protrusions in contact with the cut line, and their propagation to the inner side of the glass layer 110 can be easily prevented.

[0153] The cutting line can be configured to be spaced apart from the first outer side surface or the second outer side surface. Alternatively, the cutting line can contact the first sub-protrusion and the second sub-protrusion of the first protrusion (or the first outer side surface and the second outer side surface).

[0154] Reference Figure 10 The mother circuit board 100M may include multiple unit circuit boards 100. As described above, semiconductor devices, etc., may be placed before or after the mother circuit board is cut into unit circuit boards.

[0155] Based on the state after setting up semiconductor devices, etc., each unit circuit board can be connected to the above-mentioned... Figure 2 The circuit board corresponds to the circuit board according to another embodiment described later.

[0156] Reference Figure 11 According to the modified example, the glass layer 110 may include a plurality of protrusions located between the first outer side surface SF1 and the second outer side surface SF2, as described above. For example, the protrusions may be formed symmetrically in the glass layer with respect to the center C1 of the glass layer or with respect to a bisector extending in a first horizontal direction or a bisector extending in a second horizontal direction. For example, the glass layer may include protrusions disposed in four regions between the first outer side surface SF1 and the second outer side surface SF2. Among the plurality of protrusions, the protrusion located on one side with respect to the center C1 is the first protrusion PR1, and the protrusion located on the other side with respect to the center C1 is the second protrusion PR1'.

[0157] In an embodiment, the first protrusion PR1 and the second protrusion PR1' may face each other relative to the center (or bisector) of the glass layer 110.

[0158] For example, the first protrusion PR1 and the second protrusion PR1' may be asymmetrical with respect to the center C1 of the glass layer 110. In addition, the first protrusion PR1 and the second protrusion PR1' may be asymmetrical with respect to the bisector of the glass layer 110 (e.g., a bisector extending in a first horizontal direction or a bisector extending in a second horizontal direction).

[0159] In an embodiment, the extension length La of the first protrusion PR1 may differ from the extension length Lb of the second protrusion PR1'. This asymmetry effectively suppresses cracks (caused by cutting or impact) occurring in corner areas.

[0160] Figure 12 This is a plan view of a circuit board according to a second embodiment of the present invention, and Figure 13 It is along Figure 12 A sectional view of line B-B'.

[0161] Further reference Figure 12 and Figure 13 According to the second embodiment, the circuit board 100A may include a glass layer 110, an insulating layer 120, a protective layer 130, and an electrode portion 150. Additionally, the circuit board 100A may include a semiconductor device SD located on one side (e.g., the upper side), and conductive members CB1 and CB2. Except as described later, the descriptions of various embodiments can be applied to this embodiment.

[0162] According to an embodiment, the spacing between the second surface S2 of the glass layer and the outer side surface 120S of the second insulating layer 121 adjacent to the second surface S2 can vary or be different.

[0163] For example, the outer side surface of glass layer 110 may include a first outer side surface SF1 facing each other and a second outer side surface SF2 facing each other. The second outer side surface SF2 may be located between the first outer side surfaces SF1 facing each other and may be adjacent to the first outer side surface SF1.

[0164] Furthermore, for the first outer side surfaces SF1 facing each other, the spacing distance (corresponding to the first spacing distance) between the outer side surfaces 120s of the second insulating layer 121 adjacent to or located on the outer side of each first outer side surface SF1 can be different from each other.

[0165] Furthermore, for the second outer side surfaces SF2 facing each other, the spacing distance (corresponding to the second spacing distance) between the outer side surfaces 120s of the second insulating layer 121 adjacent to or located on the outer side of the corresponding second outer side surface SF2 can be different from each other.

[0166] Furthermore, the gap 3 between the first outer side surface SF1 and the outer side surface 120s of the second insulating layer 121 located adjacent to or outside the first outer side surface SF1 may be different from the gap 4 between the second outer side surface SF2 and the outer side surface 120s of the second insulating layer 121 located adjacent to or outside the second outer side surface SF2.

[0167] This configuration prevents cracks caused by cutting from propagating into the glass layer, while suppressing warping caused by concentrated areas such as wiring. Furthermore, it readily enables protection of internal electrode patterns or semiconductor devices within the glass layer, which will be described later.

[0168] Figure 14 This is a plan view of a circuit board according to a third embodiment of the present invention, and Figure 15 It is along Figure 14 A sectional view of line C-C'.

[0169] Reference Figure 14 and Figure 15 According to the third embodiment, the circuit board 100B may include a glass layer 110, an insulating layer 120, a protective layer 130, and an electrode portion 150. Additionally, the circuit board 100B may include a semiconductor device SD located on one side (e.g., the upper side), and conductive members CB1 and CB2. Except as described later, the descriptions of various embodiments can be applied to this embodiment.

[0170] In this embodiment, the glass layer 110 may have an asymmetrical structure relative to its center. As described above, the plurality of first protrusions may be asymmetrical relative to the center of the glass layer 110 (or relative to the bisector of the glass layer extending in the first horizontal direction / second horizontal direction).

[0171] For example, in glass layer 110, the first protrusion may be located only on one side of the bisector extending in the first horizontal direction. With this configuration, the first protrusion may be located on one side of glass layer 110, and the first protrusion may not exist on the other side of glass layer 110. Therefore, one side of glass layer 110 may be partially surrounded by the second insulating layer, while the other side of glass layer 110 may be configured such that the outer surface of the glass layer is completely covered by the second insulating layer. For example, multiple wirings, such as electrode portions, may be provided on one or the other side of glass layer 110. That is, the glass layer according to the embodiment can improve reliability and provide enhanced integration density. Furthermore, space can be easily secured for arranging bridging portions (e.g., semiconductor devices) mounted inside the circuit board.

[0172] Figure 16This is a plan view of the glass layer in a circuit board according to the fourth embodiment of the present invention. Figure 17 It is along Figure 16 A cross-sectional view of line D-D'. Figure 18 yes Figure 16 The modified example, and Figure 19 It is based on Figure 18 A cross-sectional view of the modified example circuit board.

[0173] Reference Figure 16 and Figure 17 According to the fourth embodiment, the circuit board 100C may include a glass layer 110, an insulating layer 120, a protective layer 130, and an electrode portion 150. Additionally, the circuit board 100C may include a semiconductor device SD located on one side (e.g., the upper side), and conductive members CB1 and CB2. Except as described later, the descriptions of various embodiments can be applied to this embodiment. According to modifications, such descriptions can also be applied to the circuit board.

[0174] In the circuit board according to the embodiment, the connecting member BR may be disposed in the glass layer 110.

[0175] A connecting member BR may be disposed in the glass layer 110. The connecting member BR may be interchangeably referred to as a "semiconductor device," "chip," "die," etc. The connecting member BR may be disposed in a cavity within the glass layer 110, including a cavity with recesses and / or holes, and may be electrically connected to multiple other semiconductor devices disposed on the upper side of the circuit board 100C. The connecting member BR may be formed of silicon (Si) and may be referred to as a bridging portion. In this way, the connecting member BR can be considered as a bridging substrate. For example, the connecting member BR may include a redistribution layer. The connecting member BR can be used to electrically connect multiple semiconductor devices to each other in the horizontal direction. As an example, since the area required for semiconductor devices is typically too large, the connecting member BR may include a redistribution layer. Because semiconductor packages and semiconductor devices have significant differences in the width of their circuit patterns, the circuit patterns used for electrical connections are needed to act as a buffer. The buffering function may refer to a circuit pattern that provides an intermediate dimension (e.g., width) between the circuit patterns of the semiconductor package and the circuit patterns of the semiconductor device, and the redistribution layer may include such a buffering function.

[0176] Additionally, the connecting member BR can be an organic bridging component. For example, the connecting member BR can contain organic materials. For instance, the connecting member BR can include an organic substrate containing organic materials instead of a silicon substrate.

[0177] Additionally, the connecting member BR may include a connection portion for electrical connection on one of its surfaces. Furthermore, a filler member may be disposed within the cavity. The filler member may surround the connecting member BR. The filler member can secure the connecting member BR disposed within the cavity to the cavity. The filler member may be formed of an insulating material.

[0178] Reference Figure 18 and Figure 19 In the circuit board 100C' according to the modified example, the connecting member BR can be located in the first protrusion PR1 of the glass layer 110. A cavity (groove or hole) for mounting the connecting member BR can also be located in the first protrusion PR1 of the glass layer 110. For example, a through-hole can be located in the first protrusion PR1 of the glass layer 110. With this configuration, the electrical path to one side or one device can be reduced. In other words, when it is necessary to reduce noise or power loss, the connecting member BR, as a bridging substrate, can be located in the first protrusion PR1 of the glass layer 110.

[0179] Figure 20 This is a cross-sectional view of a circuit board according to a fifth embodiment of the present invention.

[0180] The circuit board 100D according to the fifth embodiment may include a glass layer 110, an insulating layer 120, a protective layer 130, and an electrode portion 150. Additionally, the circuit board 100D may include a semiconductor device SD located on one side (e.g., the upper side), and conductive members CB1 and CB2. Except as described later, the descriptions of various embodiments can be applied to this embodiment.

[0181] An additional insulating layer 121' may be provided in the glass layer 110 according to this embodiment. For example, the glass layer 110 may include a through hole or a via 110h. In addition, a via electrode 141 may be provided in the via 110h. In this case, the insulating layer 121' may be provided on the inner surface or inner wall of the via 110h.

[0182] Furthermore, the insulating layer 121' can be located on the inner surface or inner wall of the through-hole or via of the first insulating layer 122. With this configuration, phenomena such as cracks occurring at the interface between different materials or between layers of the same material can be easily suppressed, and adhesion between the glass layer 110 and the through electrode 141 can be ensured. In other words, the reliability of the circuit board according to this embodiment can be further improved.

[0183] In various semiconductor packages, the circuit board according to the above embodiments can be disposed in a portion of the semiconductor package, or it can correspond to a single substrate.

[0184] On the other hand, when a circuit board having the above-described features of the present invention is used in IT devices or home appliances (e.g., smartphones, server computers, or TVs), it can reliably perform functions such as signal transmission and / or power supply. For example, when a circuit board having the features of the present invention is used as a semiconductor package, the circuit board can safely protect the semiconductor chip from external moisture or contaminants, and can solve problems such as leakage current, electrical short circuits between terminals, and open circuit faults at the terminals supplying the semiconductor chip. Additionally, when the circuit board is used for signal transmission, it can solve noise problems. Therefore, a circuit board having the above-described features of the present invention can help maintain the stable operation of IT devices or home appliances, and the entire product and circuit board using the present invention can achieve functional integration or technological linkage.

[0185] When a circuit board with the features of the present invention described above is used in transportation equipment such as vehicles, the circuit board can resolve signal distortion in signals sent to the transportation equipment. Alternatively, the circuit board can further improve the reliability of the transportation equipment by safely protecting the semiconductor chips configured to control the transportation equipment from external influences and by addressing problems such as leakage current, electrical short circuits between terminals, and open circuit faults at the terminals supplying the semiconductor chips. Therefore, the transportation equipment and circuit board to which the present invention is applied can achieve functional integration or technical linkage with each other.

[0186] The features, structures, effects, etc., described in the above embodiments are included in at least one embodiment, and are not necessarily limited to one embodiment. Furthermore, the features, structures, effects, etc., shown in each embodiment can be combined with or modified by those skilled in the art to which the embodiments pertain. Therefore, content related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0187] Although embodiments have been described above, these embodiments are merely examples and are not intended to limit the invention. It will be apparent that those skilled in the art can make various modifications and applications not described above without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be implemented in a modified form. Furthermore, differences associated with such modifications and applications should be interpreted as including within the scope of the embodiments set forth in the appended claims.

Claims

1. A circuit board, comprising: Glass layer; as well as An insulating layer, the insulating layer surrounding at least a portion of the glass layer, The outer surface of the glass layer includes a first surface that is coplanar with the outer surface of the insulating layer and a second surface that is covered by the insulating layer.

2. The circuit board according to claim 1, wherein, The outer side surface of the glass layer includes: A first outer side surface, wherein the first outer side surface is disposed in a first horizontal direction; A second outer side surface, wherein the second outer side surface is disposed in a second horizontal direction; A first groove surface, wherein the first groove surface is stepped along the second horizontal direction in the region adjacent to the first outer side surface and the second outer side surface; and The second groove surface contacts the second outer side surface and is disposed along the first horizontal direction in a stepped area along the second horizontal direction on the first outer side surface. The glass layer includes a first protrusion located between the surface of the first groove and the surface of the second groove.

3. The circuit board according to claim 2, wherein, The first horizontal direction and the second horizontal direction are perpendicular to each other, and The first protrusion extends along a third horizontal direction having a predetermined angle relative to the first horizontal direction and the second horizontal direction.

4. The circuit board according to claim 2, wherein, The first protrusion includes outwardly extending sub-protrusions. The sub-protrusion further includes a first sub-outer side surface disposed along the first horizontal direction, and The first sub-outer surface is configured to be coplanar with the outer surface of the insulating layer.

5. The circuit board according to claim 4, wherein, The first sub-outer side surface of the sub-protrusion is positioned outside the first outer side surface or the second outer side surface.

6. The circuit board according to claim 4, wherein, The distance between the first sub-outer side surface and the first outer side surface of the sub-protrusion in the second horizontal direction is equal to the thickness of the insulating layer in the second horizontal direction.

7. The circuit board according to claim 4, wherein, The sub-protrusion includes: A first sub-protrusion, the first sub-protrusion extending from the first protrusion in the second horizontal direction; and The second sub-protrusion extends from the first protrusion in the first horizontal direction.

8. The circuit board according to claim 7, wherein, The first outer side surface of the first sub-protrusion is configured to be spaced apart from the first outer side surface in the second horizontal direction, and The first sub-outer side surface of the second sub-protrusion is configured to be spaced apart from the second outer side surface in the second horizontal direction.

9. The circuit board according to claim 7, wherein, The first outer surface of the first protrusion is positioned further outward than the first outer surface, and The first sub-outer side surface of the second sub-protrusion is located at a position further outward than the second outer side surface.

10. The circuit board according to claim 7, wherein, The insulating layer includes a first insulating layer disposed on the glass layer and a second insulating layer disposed on the outer side of the glass layer, and The first insulating layer is disposed on the second insulating layer.

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