Managing isolation structures in semiconductor devices

Abstract

The invention relates to a method, a device and a system for managing isolation structures in a semiconductor device. An exemplary semiconductor device includes a first stack of conductive layers and isolation layers extending in a first direction and alternating with each other in a second direction perpendicular to the first direction. The semiconductor device further includes a gate slot structure extending through the first stack in the second direction, and a first isolation structure extending in the first direction. The first isolation structure includes a first portion in the first stack and a second portion in the gate gap structure. In the second direction, the size of the first portion is larger than that of the second portion.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive due to their ability to increase array density by stacking more layers within a similar footprint. 3D memory devices typically include a memory array of memory cells and peripheral circuitry to facilitate the operation of the memory array. Summary of the Invention

[0003] This disclosure describes methods, apparatus, systems, and techniques for managing isolation structures in semiconductor devices.

[0004] One aspect of this disclosure is a semiconductor device. The semiconductor device includes a first stack of conductive and insulating layers extending along a first direction and alternating with each other along a second direction perpendicular to the first direction. The semiconductor device also includes a gate gap structure extending through the first stack along the second direction and a first isolation structure extending along the first direction. The first isolation structure includes a first portion located in the first stack and a second portion located in the gate gap structure. Along the second direction, the first portion is larger than the second portion.

[0005] In some implementations, along the second direction, the size of the first portion is larger than the size of the isolation layer of the first stack.

[0006] In some implementations, the first isolation structure is located between two conductive layers of the first stack.

[0007] In some embodiments, the semiconductor device further includes: a second stack of conductive and insulating layers extending along a first direction and alternating with each other along a second direction; and a second isolation structure extending along the first direction between the first and second stacks. The second stack is adjacent to the first stack along the second direction.

[0008] In some implementations, the first isolation structure includes a dielectric material or a semiconductor material.

[0009] In some embodiments, a portion of the gate slot structure extends through a second portion of the first isolation structure. The portion of the gate slot structure includes a plurality of cylinders arranged along a third direction, which is perpendicular to both the first and second directions.

[0010] In some embodiments, the gate slot structure also includes a structure having a surface comprising a series of curves.

[0011] In some implementations, the surface of the gate slot structure includes a series of curves.

[0012] Another aspect of this disclosure features a semiconductor device. The semiconductor device includes: a first stack of conductive and insulating layers extending along a first direction and alternating with each other along a second direction perpendicular to the first direction; a channel structure extending through the first stack along the second direction; a gate slot structure extending through the first stack along the second direction; and a first isolation structure extending along the first direction. The first isolation structure includes a first portion located in the first stack and a second portion located in the gate slot structure. The first portion of the gate slot structure is located above the first isolation structure along the second direction. Along the first direction, the dimension of the first portion of the gate slot structure is larger than the dimension of one of the channel structures in the channel structure.

[0013] In some embodiments, a second portion of the gate slot structure penetrates the first isolation structure. Along the first direction, the dimension of the second portion of the gate slot structure is larger than the dimension of one of the channel structures in the channel structure.

[0014] In some implementations, the first isolation structure is located between two conductive layers of the first stack.

[0015] In some embodiments, the semiconductor device further includes: a second stack of conductive and insulating layers extending along a first direction and alternating with each other along a second direction; and a second isolation structure extending along the first direction between the first and second stacks. The second stack is adjacent to the first stack along the second direction.

[0016] In some implementations, the first isolation structure includes a dielectric material or a semiconductor material.

[0017] In some embodiments, the second part of the grid slot structure includes a plurality of cylinders arranged along a third direction, which is perpendicular to the first and second directions.

[0018] In some embodiments, the second part of the gate slot structure also includes a structure having a surface comprising a series of curves.

[0019] In some implementations, the surface of the first portion of the gate slot structure includes a series of curves.

[0020] Another aspect of this disclosure is a method of forming a semiconductor device. The method includes: forming a first stack of conductive and insulating layers extending along a first direction and alternating with each other along a second direction perpendicular to the first direction; forming a gate gap structure extending through the first stack along the second direction; and forming an isolation structure extending along the first direction. The isolation structure includes a first portion located in the first stack and a second portion located in the gate gap structure. Along the second direction, the size of the first portion is larger than the size of the second portion.

[0021] In some embodiments, the method further includes: forming a stack of dielectric layers and isolation layers alternating with each other along a second direction, wherein, along the second direction, the size of a first isolation layer in the isolation layers is larger than the size of a second isolation layer in the isolation layers; forming gate line vias extending through the stack of dielectric layers and isolation layers, wherein the gate line vias are arranged along a third direction perpendicular to the first and second directions; and forming a gate line space by extending the gate line vias, wherein the gate line vias in the second isolation layer are connected to each other along the third direction to form the gate line space. At least a portion of the gate line vias in the first isolation layer are spaced apart from each other.

[0022] In some embodiments, forming a first stack comprising a conductive layer and an isolation layer includes replacing the dielectric layer of the stack with a conductive layer. Forming a gate gap structure includes filling the gate line space with a semiconductor material.

[0023] In some implementations, the isolation structure includes the remainder of the first isolation layer after the extended gate line via.

[0024] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. Attached Figure Description

[0025] Figures 1A-1C An exemplary semiconductor device is shown.

[0026] Figures 2A-2C It shows the manufacturing process. Figures 1A-1C An exemplary semiconductor structure at a certain stage during the manufacturing process of an exemplary semiconductor device.

[0027] Figure 3A An exemplary isolation structure is shown.

[0028] Figure 3B Another exemplary isolation structure is shown.

[0029] Figures 4A-4G An exemplary process for manufacturing a semiconductor device is shown.

[0030] Figure 5 Another exemplary semiconductor device is shown.

[0031] Figure 6 A flowchart illustrating an exemplary process for manufacturing a semiconductor device is shown.

[0032] Figure 7 A block diagram of an exemplary system is shown.

[0033] Similar reference numerals and names in the various figures indicate similar elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale. Detailed Implementation

[0034] Due to the demand for higher-density memory devices, memory devices (e.g., 3D NAND flash memory) may include stacks with a large number of layers along a vertical direction. As the number of layers in the stack increases, the stack becomes more prone to collapse. For example, during the manufacturing process of the memory device, the stack may collapse toward the gate line space that extends vertically through the stack. This gate line space can be used to form a gate slot structure that divides the stack into memory blocks.

[0035] This disclosure provides techniques for preventing the collapse of a stack of memory devices. In some embodiments, the memory device may include: a stack of conductive and insulating layers extending horizontally and alternating with each other in a vertical direction, and a gate slot structure extending vertically through the stack. The memory device may also include an isolation structure extending horizontally. The isolation structure has a first portion located in the stack (e.g., between two conductive layers of the stack) and a second portion located in the gate slot structure. The isolation structure can act as a bridging structure, thereby providing mechanical support to the stack, making it less likely for the stack to collapse toward the gate line space during the manufacturing process.

[0036] In some implementations, the isolation structure may be formed based on an isolation layer that is thicker than other isolation layers in the stack. For example, when forming gate line spaces extending through the stack, thinner isolation layers are etched away in the gate line spaces, while thicker isolation layers are at least partially retained in the gate line spaces. The retained portion of the thicker isolation layer can be the isolation structure.

[0037] The technology disclosed herein can provide one or more of the following technical advantages and / or benefits. For example, by providing mechanical support to the isolation structure, the stack is more stable and less prone to collapse. As another example, compared to techniques that stabilize the stack by changing the shape of the gate gap structure, the technology disclosed herein does not require additional space on the memory die, which is more cost-effective. In some embodiments, different or more technical advantages can be achieved.

[0038] The described technology can be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices) or non-volatile memory (NVM) devices (e.g., NAND flash memory, NOR flash memory), resistive random access memory (RRAM), phase-change memory (PCM) (e.g., PCRAM), spin-transfer torque (STT) magnetoresistive random access memory (MRAM), etc. This technology can also be applied to charge-trap-based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating-gate-based memory devices. This technology can be applied to three-dimensional (3D) memory devices. This technology can be applied to various memory types, such as SLC (single-layer memory) devices, MLC (multi-layer cell) devices (e.g., 2-layer memory devices, TLC (triple-layer memory) devices, QLC (quadruple-layer memory) devices, or PLC (five-layer memory) devices). Alternatively or concurrently, this technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, etc.

[0039] It should be noted that, Figures 1A-3B The X, Y, and Z axes (also referred to as the X, Y, and Z directions) are included to further illustrate the spatial relationships of the various components in the semiconductor device. The substrate of the semiconductor device may include two lateral surfaces extending laterally in the XY plane: a top surface on the front side of the substrate on which components of the semiconductor device may be formed, and a bottom surface on the back side opposite the front side of the substrate. The Z direction is perpendicular to both the X and Y directions. As used in this disclosure, when the substrate is located in the lowest plane of the semiconductor device in the Z direction, whether a component (e.g., a layer or device) of the semiconductor device is “on,” “above,” or “below” another component (e.g., a layer or device) is determined relative to the substrate of the semiconductor device in the Z direction (a direction perpendicular to the XY plane, such as the thickness direction of the substrate). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0040] Figure 1A A top view of an exemplary semiconductor device 100 is shown. In some embodiments, the semiconductor device 100 may be a memory device, such as a three-dimensional (3D) NAND memory device. The semiconductor device 100 may include one or more array regions and one or more connection regions configured to provide conductive connections to the one or more array regions. In some embodiments, such as Figure 1A As shown, the semiconductor device 100 includes an array region 102 and a connection region 104 adjacent to the array region 102 along a first horizontal direction (e.g., the X direction). It should be understood that... Figure 1A The examples provided are for illustrative purposes only and are not intended to be interpreted in a limiting sense. In practice, any suitable arrangement of the various regions in the semiconductor device 100 may be applied. In some cases, the semiconductor device 100 may have two connecting regions 104 and an array region 102 arranged along the X direction between the two connecting regions 104. In some other cases, the semiconductor device 100 may have two array regions 102 and a connecting region 104 located along the X direction between the two array regions 102.

[0041] Semiconductor device 100 includes alternating conductive layers and insulating layers (e.g., as shown in the image). Figure 1B The diagram shows a stack 106 of conductive layer 106A and insulating layer 106B. In some embodiments, a portion of the stack 106 may be located in array region 102, and another portion of the stack 106 may be located in connection region 104. The semiconductor device 100 also includes a stack 108 of alternating dielectric and insulating layers. In some embodiments, the stack 108 may be located in connection region 104. The stack 106 is connected to the stack 108.

[0042] Semiconductor device 100 may include an array of channel structures 110 extending through a stack 106 in array region 102. Each channel structure 110 may be used to form a string of memory cells serially coupled in a vertical direction (e.g., the Z direction) perpendicular to a first horizontal direction. In some embodiments, semiconductor device 100 may include dummy channel structures 112 (also referred to as dummy memory strings) for process variable control during manufacturing and / or for additional mechanical support. Dummy channel structures 112 may extend through the stack 106 in connection region 104. In some embodiments, dummy channel structures 112 may be located in one or more dummy regions or peripheral regions. Figure 1A (Not shown in the text)

[0043] The semiconductor device 100 may include a contact structure 116 in the connection region 104. The contact structure 116 may be configured to connect a corresponding conductive layer of the conductive layers of the stack 106 to a control circuit.

[0044] Semiconductor device 100 may include one or more gate slot structures 120. Each gate slot structure 120 may extend along the X direction. The gate slot structure 120 may extend into both the array region 102 and the interconnect region 104. In some embodiments, the gate slot structure 120 may divide the array region 102 into a plurality of memory blocks. For example, memory blocks (such as...) Figure 1A As shown, two memory blocks can be arranged in array region 102 along a second horizontal direction (e.g., the Y direction). Figure 1ABetween (not shown), the gate slot structure 120 is a boundary that separates adjacent memory blocks. In some embodiments, the gate slot structure 120 may serve as a common source contact for the channel structure 110 in the array region 102.

[0045] like Figure 1A As shown, each gate slot structure 120 may include multiple segments separated and spaced apart by a separation structure 122. The separation structure 122 can eliminate or reduce stress accumulated in the gate slot structure 120 during the manufacturing process, thereby preventing the gate slot structure 120 from bending or cracking. In some embodiments, the separation structure 122 can separate a first portion of the gate slot structure 120 located in the array region 102 from a second portion of the gate slot structure 120 located in the connection region 104, allowing different etching processes to be performed on different portions of the gate slot structure 120. For example, a first etching process can be performed to etch away the sacrificial layer 106D in the array region 102 through the first portion of the gate slot structure 120. A second etching process can be performed to etch away the sacrificial layer 106D in the connection region 104 through the second portion of the gate slot structure 120. A conductive layer 106A can be formed to replace the sacrificial layer 106D in the array region 102 and a portion of the connection region 104.

[0046] In some implementation methods ( Figure 1A In (not shown), the gate slot structure 120 may further include one or more segments extending along a second horizontal direction. In some embodiments, the gate slot structure 120 may include multiple segments connected in an H-shape or T-shape. In some embodiments, the segments of each gate slot structure 120 may have similar or identical widths (e.g., measured along the Y direction). In some other embodiments, the segments of each gate slot structure 120 may have different widths (e.g., measured along the Y direction). In some embodiments, along the Y direction, the width of the segment of the gate slot structure 120 located in the connecting region 104 is greater than the width of the segment of the gate slot structure 120 located in the array region 102. For example, the width of the segment located in the connecting region 104 may be approximately 1.5 to 2 times the width of the segment located in the array region 102.

[0047] Figure 1B The edge of the semiconductor device 100 is shown. Figure 1AThe image shows a cross-sectional view of the cut line AA'. The semiconductor device 100 includes a substrate 101, a surface layer 107 made of a dielectric material (e.g., silicon oxide), and a stack 106 of alternating conductive layers 106A and insulating layers 106B. Each conductive layer 106A and each insulating layer 106B extends along the X direction. The conductive layers 106A and insulating layers 106B alternate with each other along the Z direction. In some embodiments, the semiconductor device 100 may further include an oxide layer 105 and a polysilicon layer 103 located between the substrate 101 and the stack 106. The semiconductor device may include a plurality of channel structures 110 extending through the stack 106 along the Z direction. Each channel structure 110 may include, from its outer edge to its center, an insulating layer (e.g., a silicon oxide layer), a dielectric layer (e.g., a silicon nitride layer), an insulating layer (e.g., a silicon oxide layer), and a channel layer (e.g., a polysilicon layer). The plurality of channel structures 110 may be arranged along the X and / or Y directions.

[0048] Semiconductor device 100 includes one or more gate slot structures 120 extending along the Z-direction through a stack 106. The gate slot structure 120 may include one of a semiconductor material (e.g., polysilicon), a high-k dielectric material (e.g., hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof), a dielectric material (e.g., silicon oxide), or a sacrificial material (e.g., carbon). The gate slot structure 120 may divide the stack 106 in the array region 102 into multiple memory blocks. For example, as... Figure 1B As shown, the gate gap structure 120 is the boundary between the first memory block 132a and the second memory block 132b.

[0049] Figure 1C It shows Figures 1A-1B An enlarged view of the slit structure 120 in the image. (See image for reference.) Figure 1C As shown, the grid slot structure 120 may have at least two non-planar surfaces 148a and 148b opposite to each other (e.g., along the Y direction). Each of the two surfaces 148a and 148b includes a series of curves connected together. For example, surface 148a includes curves 150 connected to each other along the X direction. In other words, surfaces 148a and 148b are wavy or track-like. In some embodiments, the cross-section of the grid slot structure 120 has a partially circular shape arranged in rows and connected together. The cross-section of the grid slot structure 120 is in the XY plane (e.g., perpendicular to the vertical direction).

[0050] Return to reference Figure 1BThe semiconductor device 100 includes an isolation structure 130 extending along the Y direction. The isolation structure 130 can act as a bridge structure across a first memory block 132a and a second memory block 132b, allowing for greater stability of the stack 106 structure. The isolation structure 130 may include a dielectric material (e.g., silicon oxide). The isolation structure 130 has a first portion 130a located within the stack 106 (e.g., between two conductive layers 106A of the stack 106) and a second portion 130b located within a gate gap structure 120. A channel structure 110 may extend through the first portion 130a of the isolation structure 130. The gate gap structure 120 may extend through the second portion 130b of the isolation structure 130. In some embodiments, because the second portion 130b undergoes more etching processes than the first portion 130a during the fabrication of the semiconductor device 100, the size of the first portion 130a is larger than the size of the second portion 130b along the Z direction. For example, as... Figure 1B As shown, the length d1 of the first portion 130a is greater than the length d2 of the second portion 130b. Furthermore, in some embodiments, the length d1 of the first portion 130a is greater than the length d3 of the isolation layer 106B of the stack 106. Lengths d1, d2, and d3 are measured along the Z-direction.

[0051] The gate slot structure 120 extends through the isolation structure 130, such that a portion of the gate slot structure 120 passes through an opening in the second portion 130b (e.g., Figure 2A The via 230 penetrates the second portion 130b of the isolation structure 130. In some embodiments, along the Y direction, the dimension of the portion of the gate slot structure 120 penetrating the second portion 130b is larger than the dimension of the channel structure 110. For example, as... Figure 1B As shown, the length a2 of this portion of the gate slot structure 120 is greater than the diameter a3 of the channel structure 110. Furthermore, the length a1 of the gate slot structure 120 located above or below the isolation structure 130 is greater than the length a2. Lengths a1 and a2 are measured along the Y direction. In some embodiments, the length a2 is the same as or substantially the same as the diameter of the opening 230 located in the second portion 130b of the isolation structure 130.

[0052] Stack 106 is disposed on substrate 101. Substrate 101 can be any suitable semiconductor substrate having any suitable semiconductor material (e.g., single crystal, polycrystalline, or single-crystal semiconductor). For example, substrate 101 can include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. In some embodiments, substrate 101 is held within semiconductor device 100. In some embodiments, substrate 101 can be removed from semiconductor device 100 in a subsequent process to expose the ends of channel structure 110. Furthermore, isolation layers, dielectric layers, and isolation layers located at the exposed ends of channel structure 110 can be removed to expose the channel layer of channel structure 110. Semiconductor layer ( Figure 1B (Not shown) can be deposited to contact the exposed channel layer of different channel structures 110 (e.g., all channel structures 110 of the memory block) to form a common source.

[0053] The stack 106 may extend in a second horizontal direction (e.g., the Y direction), which is parallel to the top surface of the substrate 101 and perpendicular to the first horizontal direction (e.g., the X direction). The conductive layer 106A and the insulating layer 106B may alternate in a vertical direction (e.g., the Z direction) perpendicular to the second horizontal direction. The conductive layer 106A may be the same or different from each other in thickness (e.g., ranging from 10-500 nm, e.g., about 35 nm). The insulating layer 106B may also be the same or different from each other in thickness (e.g., ranging from 10-500 nm, e.g., about 25 nm). It should be noted that... Figure 1B The number of conductive layers 106A and insulating layers 106B shown is for illustrative purposes only, and any suitable number of conductive layers 106A and insulating layers 106B may be included in the stack 106. Conductive layer 106A may include any suitable conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon, doped silicon, silicides, or any combination thereof. Insulating layer 106B may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, insulating layer 106B may also include a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof.

[0054] Figures 2A-2C It shows the manufacturing process. Figures 1A-1CThe semiconductor structure 200 is a semiconductor structure 200 at a certain stage during the manufacturing process of the semiconductor device 100. The semiconductor structure 200 includes a stack 206 of alternating isolation layers 106B and sacrificial layers 106D along the Z-direction. The sacrificial layer 106D may be made of a dielectric material (e.g., silicon nitride). In a subsequent process, the sacrificial layer 106D is removed to form a conductive layer 106A, thereby replacing the sacrificial layer 106D, allowing the stack 206 to be formed based on it. Additionally, the semiconductor structure 200 has a gate line space 221 extending through the stack 206 along the Z-direction. In a later stage of the manufacturing process, a filler material (e.g., polysilicon, high-k dielectric material, silicon oxide, carbon, etc.) may be filled into the gate line space 221 to form a gate gap structure 120.

[0055] Semiconductor structure 200 includes one or more isolation structures 130. Each isolation structure 130 has a first portion located in a stack 206 (e.g., between two sacrificial layers 106D) and a second portion located in a gate line space 221. The second portion of isolation structure 130 may have multiple openings 230. Thus, when gate gap structure 120 is formed, filler material can fill gate line space 221 through openings 230, allowing gate gap structure 120 to extend through isolation structure 130.

[0056] In some implementations, such as Figure 3A As shown, the plurality of openings 230 in the second part of the isolation structure 130 are in the shape of circular holes arranged along the X direction. Thus, the portion of the gate slot structure 120 that penetrates the isolation structure 130 through the openings 230 is in the shape of a plurality of cylinders arranged along the X direction.

[0057] In some other implementations, such as Figure 3B As shown, the first portion of the opening 230a in the second part of the isolation structure 130 is in the shape of a circular hole, and the second portion of the opening 230b is in the shape of a groove. Each opening 230b may have two surfaces, which include a series of curves connected together along the X direction. In other words, the opening 230b may have a wavy or track-like surface. In some embodiments, the cross-section of the opening 230b (e.g., in the XY plane) has a partially circular shape arranged in a row and connected together. In some embodiments, the opening 230b is formed by first arranging a set of circular holes along the X direction and separating them from each other, and then expanding the circular holes so that they are connected to each other. Thus, the portion of the gate slot structure 120 that penetrates the isolation structure 130 through the opening 230a is cylindrical, while the portion of the gate slot structure 120 that penetrates the isolation structure 130 through the opening 230b has a surface including a series of curves (similar to the surface of the opening 230b).

[0058] Return to reference Figure 2A The semiconductor structure 200 may have one or more stacks 206 between the surface layer 107 and the substrate 101. Each stack 206 may be provided with one or more isolation structures 130 to stabilize the stack 206. After replacing the sacrificial layer 106D with a conductive layer 106A, one or more stacks 206 may form one or more stacks 106, such that each stack 106 may be provided with one or more isolation structures 130.

[0059] In some implementations, such as Figure 2B As shown, the semiconductor structure 200a may include a stack 206 between the surface layer 107 and the substrate 101. The stack 206 includes an isolation layer 106B and a sacrificial layer 106D alternating with each other along the Z direction. An isolation structure 130 is disposed between two sacrificial layers 106D of the stack 206. In some embodiments, more than one isolation structure 130 is provided for the stack 206. In some other embodiments, such as Figure 2C As shown, the semiconductor structure 200b may include a first stack 206-1 and a second stack 206-2 between the surface layer 107 and the substrate 101. Each of the first stack 206-1 and the second stack 206-2 includes an isolation layer 106B and a sacrificial layer 106D alternating with each other along the Z direction. A first isolation structure 130-1 is disposed between the two sacrificial layers 106D of the stack 206-1, and a second isolation structure 130-2 is disposed between the first stack 206-1 and the second stack 206-2. In some embodiments, one or more isolation structures 130 may also be disposed between the sacrificial layers 106D of the second stack 206-2. It should be noted that Figures 2A-2C For illustrative purposes only. The semiconductor structure 200 may include any appropriate number of stacks 206, and each stack 206 may be provided with any appropriate number of isolation structures 130.

[0060] Figures 4A-4G This illustrates the manufacture of semiconductor devices (e.g.) Figures 1A-1B An exemplary process for the semiconductor device shown. Figures 4A-4G The illustration shows exemplary semiconductor structures at various stages of the manufacturing process. Figure 1A The cross-sectional view of the cutting line AA' in the diagram.

[0061] like Figure 4AAs shown, a semiconductor structure 400a is formed. The semiconductor structure 400a includes a substrate 401 and a stack 406 disposed on the substrate 401, consisting of alternating sacrificial layers 406D and isolation layers 406B. The sacrificial layers 406D and isolation layers 406B may alternate with each other along a vertical direction (e.g., the Z direction). The isolation layer 306B may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the sacrificial layer 406D may include a dielectric material different from the dielectric material of the isolation layer 406B. For example, the isolation layer 406B may include silicon oxide, and the sacrificial layer 406D may include silicon nitride. In some embodiments, the semiconductor structure 400a may also include an oxide layer 405 and a polysilicon layer 403 located vertically between the stack 406 and the substrate 401. In some embodiments, the stack 406 includes an isolation layer 430 having a larger dimension along the Z direction than the other isolation layers 406B. For example, as... Figure 4A As shown, the isolation layer 430 is thicker than the other isolation layers 406B.

[0062] like Figure 4A As shown, multiple rows of channel vias 410 are formed through the stack 406. Each channel via 410 extends through the stack 406 into the substrate 401 along the Z direction. The channel vias 410 arranged in a row are arranged along the X direction. The multiple rows of channel vias 410 are arranged along the Y direction. Additionally, gate vias 420 are formed through the stack 406. Each gate via 420 extends through the stack 406 and the isolation layer 430 into the substrate 401 along the Z direction. The gate vias 420 are arranged in a row along the X direction. In some embodiments, a sacrificial material (e.g., carbon) is filled in the channel vias 410 and the gate vias 420 to provide mechanical support. In some embodiments, the size (e.g., diameter) of the gate via 420 is larger than the size (e.g., diameter) of the channel via 410. The gate vias 420 and the channel vias 410 can be formed in the same photolithography process.

[0063] like Figure 4B As shown in the semiconductor structure 400b, sacrificial material in the channel via 410 can be removed, and a first dielectric material (e.g., silicon oxide), a second dielectric material (e.g., silicon nitride), and a semiconductor material (e.g., polysilicon) can be sequentially deposited on the inner surface of each channel via 410. Thus, a channel structure 110 can be formed. Each channel structure 110 may include, from its outer edge to its center, an isolation layer (e.g., a silicon oxide layer), a dielectric layer (e.g., a silicon nitride layer), an isolation layer (e.g., a silicon oxide layer), and a channel layer (e.g., a polysilicon layer). Figure 4BAs shown, a cap oxide layer 422 is deposited on top of the semiconductor structure 400b. In some embodiments, the cap oxide layer 422 and the adjacent oxide layer 424 (e.g., formed at an earlier stage of the manufacturing process) may be a combination of oxide layers with no boundary between them.

[0064] like Figure 4C As shown in the semiconductor structure 400c, the gate line hole 420 is exposed by removing portions of the cap oxide layer 422 and oxide layer 424 that cover the gate line hole 420. In some embodiments, portions of the cap oxide layer 422 and oxide layer 424 are removed by a photolithography process, wherein the portions covered by the photomask 435 are retained, and the portions exposed by the photomask 435 are removed. In some embodiments, after exposing the gate line hole, the sacrificial material in the gate line hole 420 is removed.

[0065] Figure 4D A semiconductor structure 400d is shown, which can be formed by forming a gate line space 221 based on a gate line via 420. The gate line space 221 is formed by removing portions of the sacrificial layer 406D and the isolation layer 406B near the gate line via 420. First, the portion of the sacrificial layer 406D near the gate line via 420 is removed by a first etching process (e.g., wet etching using a first etchant (e.g., hydrofluoric acid or hydrochloric acid)). The first etchant can contact the sacrificial layer 406D from the gate line via 420. During the first etching process, the gate line via 420 in the sacrificial layer 406D is extended such that the extended gate line vias connect to each other to form a gate line space 221 having a surface including a series of curves (e.g., Figure 1C (As shown).

[0066] Then, the portion of the isolation layer 406B near the gate line via 420 is removed by a second etching process (e.g., wet etching using a second etchant (e.g., phosphoric acid)). Since the sacrificial layer 406D near the gate line via 420 has been removed, the second etchant can contact the isolation layer 406B from the top and bottom surfaces of each isolation layer 406B. By controlling the amount of the second etchant, the isolation layer 406B near the gate line via 420 is removed, while the isolation layer 430 (which is thicker than the isolation layer 406B) is at least partially retained. For example, the gate line via 420 in the isolation layer 406B is expanded during the second etching process such that the expanded gate line vias connect to each other to form a gate line space 221 having a surface including a series of curves (e.g., Figure 1C(As shown). The gate line vias 420 in the isolation layer 430 are also extended during the second etching process, but because the isolation layer 430 is thicker, at least a portion of the gate line vias 420 in the isolation layer 430 are separated from each other. Thus, the remaining portion of the isolation layer 430 is not disconnected at the gate line space 221. The remaining portion of the isolation layer 430 can therefore serve as an isolation structure 130, acting as a bridging structure to stabilize the stack 406. In some embodiments, the stack 406 is less likely to collapse toward the gate line space 221 compared to a scenario without the isolation structure 130, especially during heat treatment in later stages of the manufacturing process.

[0067] Figure 4E A semiconductor structure 400e is shown, which can be formed by replacing the sacrificial layer 406D with an isolation layer 406A. In some embodiments, the sacrificial layer 406D is removed by an etching process, wherein the etchant contacts the sacrificial layer 406D via the gate line space 221. A conductive material can be deposited between the isolation layers 406B via the gate line space 221. The conductive material can be tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polysilicon (polycrystalline silicon), doped silicon, silicide, or any combination thereof. In some embodiments, the conductive material is also deposited on the top surface of the semiconductor structure 400e, the surface of the isolation structure 130, and the sidewalls of the gate line space 221.

[0068] like Figure 4F As shown in the semiconductor structure 400f, the conductive material on the top surface of the semiconductor structure 400e, the surface of the isolation structure 130, and the sidewalls of the gate line space 221 is removed.

[0069] like Figure 4G As shown in the semiconductor structure 400g, the gate line space 221 is filled with a filler material to form a gate gap structure 120. The filler material can be a semiconductor material (e.g., polysilicon), a high-k dielectric material (e.g., hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof), a dielectric material (e.g., silicon oxide), or a sacrificial material (e.g., carbon).

[0070] Figure 5 A cross-sectional view of semiconductor device 500 is shown. Similar to semiconductor device 100, semiconductor device 500 includes a stack 106 of alternating conductive layers 106A and insulating layers 106B, a gate slot structure 120 extending through the stack 106 in the Z direction, and a channel structure 110 extending through the stack 106 in the Z direction. Unlike Figures 1A-1CSemiconductor device 100 (which includes one or more isolation structures 130 made of a dielectric material (e.g., silicon oxide)) and semiconductor device 500 include one or more isolation structures 530 made of a semiconductor material (e.g., polysilicon). Each isolation structure 530 has a first portion 530a located in a stack 106 (e.g., between two conductive layers 106A of the stack 106) and a second portion 530b located in a gate gap structure 120.

[0071] In some embodiments, since the second portion 130b is not etched during the etching process (e.g., as shown in the image), Figure 4D As shown, a portion of the isolation layer 106B is removed, therefore, along the Z direction, the size of the first portion 530a is equal to the size of the second portion 530b. For example, as... Figure 5 As shown, the length d4 of the first portion 530a is equal to the length d5 ​​of the second portion 530b. Furthermore, in some embodiments, the length d4 of the first portion 530a need not be greater than the length d3 of the isolation layer 106B of the stack 106. d4 can be equal to or less than d3. Lengths d3, d4, and d5 are measured along the Z-direction.

[0072] Figure 6 A flowchart of an exemplary process 600 is shown. Process 600 can be performed to form a semiconductor device (e.g., Figures 1A-1B Semiconductor device 100 or Figure 5 Semiconductor device 500 in the middle). It can be based on... Figures 4A-4G To describe process 600. Process 600 may include Figures 4A-4G This refers to one or more steps in the manufacturing process for forming a semiconductor structure. It should be understood that the operations shown in process 600 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some of these operations may be performed simultaneously or in conjunction with... Figure 6 The different orders shown are executed sequentially.

[0073] At position 602, a first stack is formed (e.g., Figures 1A-1B The first stack includes a conductive layer extending along a first direction (e.g., the Y direction). Figure 1B The conductive layer 106A and the insulating layer (e.g., Figure 1B The conductive layer and the isolation layer alternate with each other along a second direction perpendicular to the first direction (e.g., the Z direction). The first stack can be arranged in an array region of the semiconductor device (e.g., ...). Figure 1A In the array region 102).

[0074] At position 604, a gate slot structure is formed (e.g., Figures 1A-1C The gate slot structure 120 extends through the first stack in a second direction. Forming the gate slot structure includes: forming a structure extending through the stack (e.g., Figure 4A Gate line vias (e.g., in the stacked body 406) Figure 4A Gate line via 420), forming a gate line space by expanding the gate line via (e.g., Figure 4D The gate line space 221 in the middle is used to connect the gate line holes to each other, and the gate line space is filled with a filling material.

[0075] At position 606, an isolation structure is formed (e.g., Figure 1B The isolation structure 130 extends along a first direction. The isolation structure includes a first portion located within the first stack (e.g., Figure 1B The first part 130a) and the second part located in the gate slot structure (e.g., Figure 1B The second part 130b). Along the second direction, the dimensions of the first part (e.g., Figure 1B d1) is larger than the size of the second part (e.g., Figure 1B (d2 in the text). The grid slot structure extends through the isolation structure.

[0076] In some embodiments, forming the isolation structure includes: forming a first isolation layer (e.g., thicker than other isolation layers in the stack (e.g., isolation layer 406B)). Figure 4A (Isolation layer 430 in the stack). When forming the gate line space extending through the stack, the thinner other isolation layers are etched away in the gate line space, while the thicker first isolation layer is at least partially retained in the gate line space. The retained portion of the first isolation layer can be an isolation structure.

[0077] In some embodiments, a portion of the gate gap structure penetrates a second portion of the first isolation structure (e.g., via a structure located in the first isolation structure). Figures 3A-3B (Opening 230 in the middle). A portion of the gate slot structure includes a plurality of cylinders arranged along a third direction (e.g., the X direction) perpendicular to the first and second directions. In some embodiments, a portion of the gate slot structure includes a surface having a series of curves (e.g., similar to...). Figure 3B The structure of the surface of the opening 230b in the middle.

[0078] Figure 7A block diagram of an exemplary system 700 is shown. System 700 may have one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of this disclosure. System 700 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device with storage devices. Figure 5 As shown, system 700 may include a host device 708 and a memory system 702 having one or more memory devices 704 and a memory controller 706. The host device 708 may include a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host device 708 may be configured to send data to or receive data from one or more memory devices 704.

[0079] Memory device 704 can be any memory device disclosed in this disclosure, such as Figures 1A-1B The semiconductor device shown is an example of a NAND flash memory. A memory controller 706 (also referred to as controller circuitry) is coupled to the memory device 704 and the host device 708. Consistent with embodiments of this disclosure, the memory device 704 may include a plurality of conductive interconnects that pass through a cover layer and contact conductive pads located in a conductive pad layer, and the memory controller 706 may be coupled to the memory device 704 through at least one of the plurality of conductive interconnects. The memory controller 706 is configured to control the memory device 704. For example, the memory controller 706 may be configured to operate a plurality of channel structures via word lines. The memory controller 706 may manage data stored in the memory device 704 and communicate with the host device 708.

[0080] In some embodiments, the memory controller 706 is designed / configured to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 706 is designed / configured to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. The memory controller 706 may be configured to control the operation of the memory device 704 (e.g., read, erase, and program (or write) operations). The memory controller 706 may also be configured to manage various functions regarding data stored or to be stored in the memory device 704, including but not limited to: bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 706 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 704. The memory controller 706 can also perform any other appropriate functions, such as formatting the memory device 704.

[0081] The memory controller 706 can communicate with external devices (e.g., host device 708) according to a specific communication protocol. For example, the memory controller 706 can communicate with external devices through at least one of a variety of interface protocols, such as: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0082] The memory controller 706 and one or more memory devices 704 can be integrated into various types of memory devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 702 can be implemented and packaged into different types of end electronic products. Figure 5 In one example shown, the memory controller 706 and the single memory device 704 can be integrated into the memory card. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc.

[0083] The embodiments, actions, and operations of the subject matter described in this disclosure can be implemented in digital electronic circuits, tangibly embodied computer software or firmware, computer hardware (including the structures disclosed in this disclosure and their structural equivalents), or combinations thereof. Embodiments of the subject matter described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier for execution by or control of the operation of a data processing device. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagation signal, such as a machine-generated electrical signal, optical signal, or electromagnetic signal, generated to encode information for transmission to a suitable receiving device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination thereof, or a portion thereof. The computer storage medium is not a propagation signal.

[0084] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some implementations," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment must include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other implementations is within the knowledge of those skilled in the art.

[0085] Generally, terms can be understood at least partly from their usage in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage. Additionally, again depending at least partly on the context, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described.

[0086] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” not only means “directly on something,” but also includes the meaning of “on something” with an intermediate feature or layer between them. Furthermore, “above” or “on top of” not only means “above something” or “on top of something,” but can also include the meaning of “above something” or “on top of something” without an intermediate feature or layer between them (i.e., directly on something).

[0087] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another (or more) elements or features as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the apparatus during use or process steps. The apparatus may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0088] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore, the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0089] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper overlay structure, or may have a range smaller than that of the lower or upper overlay structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnect lines, and / or vertical interconnect channels (VIAs) are formed) and one or more dielectric layers.

[0090] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter set for a component or process step during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. As used herein, the range of values ​​may be due to minor variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" or "about" may indicate a value of a given quantity that varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30%). As used herein, the term "substantially" means majority or majority, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or greater.

[0091] In this disclosure, the terms "horizontal / horizontally / laterally" mean nominally parallel to the lateral surface of the substrate, and the term "vertical / vertically" means nominally perpendicular to the lateral surface of the substrate.

[0092] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having strings of vertically oriented memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate.

[0093] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features can be in direct contact, and may also include embodiments where an additional feature can be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or constructions discussed.

[0094] The descriptions of specific implementation methods described above can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance provided herein, such adjustments and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementation methods.

[0095] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of the claims as defined by the claims themselves, but rather as descriptions of features that may be implemented for specific embodiments of a particular invention. In the context of individual embodiments, certain features described in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, one or more features from the claimed combination may be removed from the combination in some cases, and the claims may be for sub-combinations or variations thereof.

[0096] Similarly, although operations are depicted in a specific order in the accompanying drawings and referenced in the claims, this should not be construed as requiring the operations to be performed in the specific order or sequence shown, or requiring all shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0097] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the following claims. For example, the actions cited in the claims can be performed in a different order and still achieve the desired result. As an example, the process depicted in the drawings does not necessarily require the specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0098] The breadth and scope of this disclosure should not be limited to any of the embodiments described above, but should be defined solely by the following claims and their equivalents.

Claims

1. A semiconductor device, comprising: A first stack of conductive and insulating layers extending along a first direction and alternating with each other along a second direction perpendicular to the first direction; A gate slot structure that extends through the first stack along the second direction; as well as A first isolation structure extends along a first direction, wherein the first isolation structure includes a first portion located in the first stack and a second portion located in the gate gap structure, wherein, along the second direction, the size of the first portion is larger than the size of the second portion.

2. The semiconductor device according to claim 1, wherein, Along the second direction, the size of the first portion is larger than the size of the isolation layer of the first stack.

3. The semiconductor device according to claim 1 or 2, wherein, The first isolation structure is located between the two conductive layers of the first stack.

4. The semiconductor device according to any one of claims 1 to 3, further comprising: A second stack of conductive and insulating layers extending along the first direction and alternating with each other along the second direction, wherein the second stack is adjacent to the first stack along the second direction; and A second isolation structure extends along the first direction between the first stack and the second stack.

5. The semiconductor device according to any one of claims 1 to 4, wherein, The first isolation structure includes a dielectric material or a semiconductor material.

6. The semiconductor device according to any one of claims 1 to 5, wherein, A portion of the gate slot structure penetrates the second portion of the first isolation structure, and The portion of the gate slot structure includes a plurality of cylinders arranged along a third direction, which is perpendicular to the first direction and the second direction.

7. The semiconductor device according to claim 6, wherein, The portion of the gate slot structure also includes a structure having a surface comprising a series of curves.

8. The semiconductor device according to any one of claims 1 to 7, wherein, The surface of the gate slot structure includes a series of curves.

9. A semiconductor device, comprising: A first stack of conductive and insulating layers extending along a first direction and alternating with each other along a second direction perpendicular to the first direction; A channel structure that extends through the first stack body along the second direction; A gate slot structure that extends through the first stack along the second direction; as well as A first isolation structure extends along the first direction, wherein the first isolation structure includes a first portion located in the first stack and a second portion located in the gate gap structure. Wherein, the first portion of the gate slot structure is located above the first isolation structure along the second direction, wherein, along the first direction, the size of the first portion of the gate slot structure is larger than the size of one of the channel structures in the channel structure.

10. The semiconductor device according to claim 9, wherein, The second portion of the gate slot structure penetrates the first isolation structure, wherein, along the first direction, the size of the second portion of the gate slot structure is larger than the size of one of the channel structures in the channel structure.

11. The semiconductor device according to claim 9 or 10, wherein, The first isolation structure is located between the two conductive layers of the first stack.

12. The semiconductor device according to any one of claims 9 to 11, further comprising: A second stack of conductive and insulating layers extending along the first direction and alternating with each other along the second direction, wherein the second stack is adjacent to the first stack along the second direction; and A second isolation structure extends along the first direction between the first stack and the second stack.

13. The semiconductor device according to any one of claims 9 to 12, wherein, The first isolation structure includes a dielectric material or a semiconductor material.

14. The semiconductor device according to any one of claims 9 to 13, wherein, The second part of the grid slot structure includes a plurality of cylinders arranged along a third direction, which is perpendicular to the first direction and the second direction.

15. The semiconductor device according to claim 14, wherein, The second part of the gate slot structure also includes a structure having a surface comprising a series of curves.

16. The semiconductor device according to any one of claims 9 to 15, wherein, The surface of the first portion of the gate slot structure includes a series of curves.

17. A method of forming a semiconductor device, comprising: A first stack of conductive and insulating layers is formed, extending along a first direction and alternating with each other along a second direction perpendicular to the first direction; Forming a grid slot structure that extends through the first stack body along the second direction; as well as An isolation structure is formed extending along the first direction, wherein the isolation structure includes a first portion located in the first stack and a second portion located in the gate gap structure, wherein, along the second direction, the size of the first portion is larger than the size of the second portion.

18. The method of claim 17, further comprising: A stack of dielectric layers and isolation layers alternating with each other along the second direction is formed, wherein, along the second direction, the size of the first isolation layer in the isolation layer is larger than the size of the second isolation layer in the isolation layer; Forming gate line vias extending through the dielectric layer and the isolation layer of the stack, wherein the gate line vias are arranged along a third direction perpendicular to the first direction and the second direction; and A gate line space is formed by expanding the gate line vias, wherein the gate line vias in the second isolation layer are connected to each other along the third direction to form the gate line space, and wherein at least a portion of the gate line vias in the first isolation layer are separated from each other.

19. The method according to claim 18, wherein, The first stack forming a conductive layer and an insulating layer includes: replacing the dielectric layer of the stack with a conductive layer, and The formation of the gate gap structure includes filling the gate line space with a semiconductor material.

20. The method according to claim 18 or 19, wherein, The isolation structure includes the remaining portion of the first isolation layer after the gate line via has been extended.

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