Semiconductor device
By constructing multi-layered transistors and power lines in semiconductor devices, the uncertainty of CFET power switch circuit layout is resolved, and the stability and scale of the circuit are optimized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SOCIONEXT INC
- Filing Date
- 2023-10-13
- Publication Date
- 2026-05-12
AI Technical Summary
The existing technology has not discussed in detail how the wiring of the source/drain of the CFET to the BPR is used for the layout of the power switching circuit.
In a semiconductor device, first, second, and third power lines are formed, and multiple semiconductor layers and gates are formed on a substrate to construct first, second, third, and fourth transistors. The source/drain terminals of these transistors are connected to the wiring of the BPR to form a suitable power switch circuit layout.
This approach achieves a reasonable layout of the CFET power switch circuit, stabilizes the source and drain potentials of the transistor, suppresses characteristic fluctuations and charging/discharging current, and reduces the circuit size.
Smart Images
Figure CN122029958A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor device. Background Technology
[0002] CFET (Complementary Field Effect Transistor) technology, which is formed by stacking transistors, is known. BPR (Buried Power Rail) technology is also known, which uses buried wiring formed in trenches on the surface of a semiconductor substrate to supply power or ground potential to the transistor. A power switching circuit for controlling the supply of power potential by providing on / off switching in a standard cell or similar component is also known.
[0003] Patent Document 1: U.S. Patent Application Publication No. 2023 / 0178435
[0004] Patent Document 2: U.S. Patent Application Publication No. 2023 / 0067311
[0005] Patent Document 3: U.S. Patent Application Publication No. 2022 / 0123023
[0006] Patent Document 4: U.S. Patent Application Publication No. 2022 / 0181258
[0007] Patent Document 5: International Publication No. 2020 / 065916
[0008] Patent Document 6: International Publication No. 2020 / 066797
[0009] Patent Document 7: International Publication No. 2020 / 217396
[0010] Patent Document 8: International Publication No. 2020 / 217400
[0011] Patent Document 9: U.S. Patent Application Publication No. 2021 / 0366902
[0012] Patent Document 10: U.S. Patent Application Publication No. 2022 / 0102479
[0013] Patent Document 11: U.S. Patent Application Publication No. 2021 / 0210600 Summary of the Invention
[0014] <Problem to be solved by this invention>
[0015] In the case of connecting the source / drain of the CFET to the wiring of the BPR to form a power switch circuit, the layout of the power switch circuit has not been discussed in detail.
[0016] The object of this invention is to properly layout a power switch circuit formed by a CFET using wiring with the source / drain connected to the BPR.
[0017] <Methods for solving problems>
[0018] In one aspect of the invention, a semiconductor device includes: a substrate; a first power line, a second power line, and a third power line formed in the substrate; a first semiconductor layer and a second semiconductor layer formed above the substrate; a third semiconductor layer formed on the first semiconductor layer; a fourth semiconductor layer formed on the second semiconductor layer; a first gate formed between the first semiconductor layer and the second semiconductor layer and between the third semiconductor layer and the fourth semiconductor layer; and a first transistor formed between the first power line and the second power line, and having the first semiconductor layer, the second semiconductor layer, and the first gate, or having the third semiconductor layer. The fourth semiconductor layer and the first gate; a fifth semiconductor layer and a sixth semiconductor layer formed on the substrate; a seventh semiconductor layer formed on the fifth semiconductor layer; an eighth semiconductor layer formed on the sixth semiconductor layer; a second gate formed between the fifth semiconductor layer and the sixth semiconductor layer and between the seventh semiconductor layer and the eighth semiconductor layer; and a second transistor and a third transistor formed between the first power line and the third power line, and having the fifth semiconductor layer, the sixth semiconductor layer, the seventh semiconductor layer, the eighth semiconductor layer and the second gate, wherein the output of the second transistor is electrically connected to the first gate.
[0019] <The Effects of the Invention>
[0020] According to the technology disclosed herein, power switching circuits formed by CFETs using source / drain wiring connected to the BPR can be appropriately laid out. Attached Figure Description
[0021] Figure 1 This is a top view showing an example of the layout of the semiconductor device according to the first embodiment.
[0022] Figure 2 It is shown Figure 1 A cross-sectional view of an example of the cross-sectional structure of a semiconductor device.
[0023] Figure 3 It shows the configuration in Figure 1A circuit diagram of an example of a circuit in a standard unit block.
[0024] Figure 4 It is shown Figure 3 A three-dimensional diagram of an example layout of a power switch circuit.
[0025] Figure 5 This is a perspective view showing an example of a connection method between the top wiring and the wiring of the BPR layer formed on the back side of the substrate.
[0026] Figure 6 It is shown Figure 4 A top view of an example of a power switch circuit and standard unit, viewed from the top wiring side of the substrate SUB.
[0027] Figure 7 It is shown in Figure 4 A top view of an example of a power switch circuit and standard unit, viewed from the bottom wiring side of the substrate.
[0028] Figure 8 It shows along Figure 6 and Figure 7 A cross-sectional view of an example of the section along line X1-X1'.
[0029] Figure 9 It shows along Figure 6 and Figure 7 A cross-sectional view of an example of the section along line X2-X2'.
[0030] Figure 10 It shows along Figure 6 and Figure 7 A cross-sectional view of an example of the section along line Y1-Y1'.
[0031] Figure 11 This is a top view showing an example of the top view of the power switch circuit and standard unit in the second embodiment, taken from the top wiring side of the substrate SUB.
[0032] Figure 12 It is shown in Figure 11 A top view of an example of a power switch circuit and standard unit, viewed from the bottom wiring side of the substrate. Detailed Implementation
[0033] The embodiments will now be described using the accompanying drawings. Hereinafter, the symbols representing signals are also used to represent signal lines or signal terminals. The symbols representing power supply potential are also used to represent power lines or power terminals to which power supply potential is supplied.
[0034] (First Implementation)
[0035] Figure 1 An example of the layout of the semiconductor device in the first embodiment is shown. For example, Figure 1 The semiconductor device 100 shown may be a SoC (System on Chip), a single FPGA (Field-Programmable Gate Array), etc.
[0036] Semiconductor device 100 includes multiple I / O units IOC, IOCP, and internal circuit region INTR. I / O units IOC are interface circuits for signals SGNL such as input signals, output signals, or input / output signals. I / O units IOCP are interface circuits for power supply potentials or ground potentials.
[0037] Each I / O unit (IOC) and IOCP is connected to the internal circuitry region (INTR). For example, the internal circuitry region (INTR) includes one or more standard cell blocks (SCBs) containing standard cells. Note that logic circuits other than standard cells, as well as memory, can be installed in the internal circuitry region (INTR). Memory can be installed within the standard cell blocks (SCBs).
[0038] Figure 2 It shows Figure 1 This is an example of the cross-sectional structure of a semiconductor device 100. The semiconductor device 100 includes a substrate SUB and a wiring layer WL1 formed on the surface FS side of the substrate SUB. On the surface FS of the substrate SUB, source / drain electrodes S / D, which are part of a CFET, are formed on the bottom side, which is the side closest to the substrate SUB, and on the top side, which is the side furthest from the substrate SUB. The source / drain electrodes S / D of the CFET can be connected to wiring W1 formed on the wiring layer WL1. A trench is formed on the surface FS of the substrate SUB, and a buried wiring BPR of a conductor is formed in the trench.
[0039] Figure 3 It shows the configuration in Figure 1 An example of a circuit in a standard cell block SCB. The power switch circuit PSW includes a control circuit CNTL and a switching transistor SWT controlled by the control circuit CNTL.
[0040] For example, the control circuit CNTL is a buffer circuit with inverters INV1 and INV2 connected in series between the input signal line IN1 and the output signal line OUT2. Each inverter INV1 and INV2 operates by connecting to the power supply line TVDD and the ground line VSS. Inverter INV1 inverts the logic of the input signal IN1 and outputs it as the output signal OUT1. Inverter INV2 inverts the logic of the output signal OUT1 from inverter INV1 and outputs it as the output signal OUT2.
[0041] The switching transistor SWT consists of a PMOS transistor PM and an NMOS transistor NM. The source of the PMOS transistor PM is connected to the power supply line TVDD, and its drain is connected to the dummy power supply line VVDD. The source and drain of the NMOS transistor NM are connected to the ground line VSS. The gates of both the PMOS transistor PM and the NMOS transistor NM receive the control signal OUT1 output from the control circuit CNTL.
[0042] Note that the source and drain of the NMOS transistor NM in the SWT switching transistor can be connected to the virtual power line VVDD. By connecting the source and drain of the transistor to a voltage line with a fixed potential without opening the source and drain, the potentials of the source and drain of the transistor can be stabilized, thereby suppressing fluctuations in the transistor's characteristics. Additionally, it can suppress the charging and discharging current (leakage current) in the source and drain regions.
[0043] Additionally, the source and drain of the NMOS transistor NM can be set to floating if there are no problems during the operation of the power switching circuit PSW. In this case, the source and drain of the NMOS transistor NM can be interconnected via wiring.
[0044] Figure 3 An example of a standard cell SC with an inverter configured between the virtual power line VVDD and the ground line VSS is shown. The PMOS transistor included in the inverter of the standard cell SC is an example of a fourth transistor. For example, the transistors in the power switch circuit PSW and the standard cell SC are CFETs.
[0045] Figure 4 It shows Figure 3 An example of the layout of a power switch circuit (PSW). Figure 4 The diagram of the interlayer insulating film is omitted, and the substrate SUB is simply shown with thick dashed lines. (Refer to...) Figure 6 Describe the routing of routing layers FSM1 and FSM2.
[0046] exist Figure 4In the illustrated layout, the source / drain S / D of the PMOS transistor PM in the CFET is formed in a bottom-side semiconductor layer disposed on the substrate SUB, and the source / drain S / D of the NMOS transistor NM in the CFET is formed in a top-side semiconductor layer disposed on the bottom-side semiconductor layer. In the CFET, the two bottom-side semiconductor layers are interconnected via nanosheets NS, and the two top-side semiconductor layers are interconnected via top-side nanosheets NS. In the CFET, the gate of the PMOS transistor is shared with the gate of the NMOS transistor. The symbols S and D assigned to the source / drain S / D of the NMOS transistor NM and the PMOS transistor PM represent the source and drain of the transistor, respectively. The source / drain S / D of the NMOS transistor NM has an N-type conductivity type, and the source / drain S / D of the PMOS transistor PM has a P-type conductivity type. In this invention, the semiconductor layer is sometimes referred to as the source / drain S / D, including when it does not function as a transistor. In addition, including cases where it does not function as a transistor, depending on the conductivity type of the semiconductor layer, a portion of the CFET structure is sometimes referred to as an NMOS transistor (NM) or a PMOS transistor (PM).
[0047] exist Figure 4 In this configuration, the PMOS transistor group and the NMOS transistor group are arranged along the Y direction in the order of drain, gate, source, gate, drain. For example... Figure 3 As shown, the source and drain of the NMOS transistor in the switching transistor SWT are connected to the ground line VSS.
[0048] In the region of the power switch circuit PSW, the control circuit CNTL is formed by source / drain S / D transistors sandwiching the gate located on the near side in the Y direction. Furthermore, in the region of the power switch circuit PSW, the switching transistor SWT is formed by source / drain S / D transistors sandwiching the gate located on the far side in the Y direction.
[0049] The PMOS and NMOS transistor groups are positioned on the substrate SUB at locations corresponding to the power line TVDD and virtual power line VVDD of the BPR layer when viewed from above. That is, the PMOS and NMOS transistor groups are positioned offset along the X-direction relative to the power line TVDD and virtual power line VVDD of the BPR layer when viewed from above.
[0050] Furthermore, the inverter INV1 and switching transistor SWT of the control circuit CNTL are formed by a group of PMOS transistors and a group of NMOS transistors located between the virtual power line VVDD and the ground line VSS when viewed from above. Similarly, the inverter INV2 and switching transistor SWT of the control circuit CNTL are formed by a group of PMOS transistors and a group of NMOS transistors located between the power line TVDD and the virtual power line VVDD when viewed from above.
[0051] Figure 5 An example of a connection method between the top wiring (TOP) and the wiring formed on the BPR layer on the substrate (SUB) is shown. Figure 5 As shown in (a), with Figure 4 The wiring of the power switch circuit PSW is the same, and the wiring of the top wiring (TOP) and BPR layer can be directly connected via vias (VIA) without going through the bottom wiring (BTM). For example... Figure 5 As shown in (b), the top wiring (TOP) and BPR layer wiring can be connected via the bottom wiring (BTM). Figure 5 The wiring method in (b) can be applied to other implementations. Note that the bottom wiring BTM has a portion in the same position in the Z direction as the transistor on the bottom side of the CFET. Note that the top wiring TOP has a portion in the same position in the Z direction as the transistor on the top side of the CFET.
[0052] Figure 6 It shows in Figure 4 An example of a top-down view of the substrate SUB side when observing the top wiring from the TOP side of the power switch circuit PSW and the standard cell SC. Figure 6 The diagram shows an NMOS transistor NM without either of the symbols S or D, where the source and drain are either open or connected to ground VSS, and it does not function as a transistor.
[0053] The wiring represented by the thick solid line extending in the Y direction represents the wiring of the wiring layer FSM1 (FSM stands for Frontside Metal) located above the power switch circuit PSW and the standard cell SC (in the Z direction from the substrate SUB towards the location where the CFET is placed). The wiring of the wiring layer FSM1 is located above the top wiring TOP and is formed using any one of the multiple wiring layers on the top wiring TOP. Hereinafter, the wiring layer FSM1 will also be referred to as the FSM1 layer.
[0054] The NMOS transistor NM in the power switch circuit PSW and the standard cell SC is positioned offset along the X-direction from the power line TVDD, virtual power line VVDD, and ground line VSS of the BPR layer when viewed from above. The source and drain of the NMOS transistor NM are positioned in the Z-direction corresponding to the formation region of the top wiring TOP. The source and drain of the NMOS transistor NM are positioned on both sides of the gate GT in the Y-direction.
[0055] In the NMOS transistor NM of the switching transistor SWT, one of the source and drain is an example of one of the third and fourth semiconductor layers, and the other of the source and drain is an example of the other of the third and fourth semiconductor layers. The gate GT of the switching transistor SWT is an example of the first gate. In the NMOS transistor NM of the inverters INV1 and INV2 of the control circuit CNTL, one of the source and drain is an example of one of the seventh and eighth semiconductor layers, and the other of the source and drain is an example of the other of the seventh and eighth semiconductor layers. The gate GT of the inverters INV1 and INV2 is an example of the second gate. The NMOS transistor NM of the inverter INV1 is an example of the third transistor.
[0056] In a switched-mode transistor (SWT), the source / drain (S / D) terminals of adjacent NMOS transistors (NM) in the X direction are interconnected via top wiring (TOP). Furthermore, in a switched-mode transistor (SWT), Figure 6 The source / drain (S / D) of the NMOS transistor NM on the right side is connected to the ground line VSS of the BPR layer via the top wiring TOP and via VIA. Thus, the source / drain (S / D) of the NMOS transistor NM of the switching transistor SWT is fixed to the ground potential VSS.
[0057] By connecting the source and drain of the NMOS transistor NM to a voltage line with a fixed potential without opening the source and drain of the NMOS transistor NM, the potentials of the source and drain of the NMOS transistor NM can be stabilized, thereby suppressing variations in the characteristics of the NMOS transistor NM. Furthermore, it can suppress the charging and discharging current (leakage current) in the source / drain region.
[0058] The gate GT of inverter INV1 is connected to the input signal line IN1 of FSM1 layer via via VIA. The source S of the NMOS transistor NM of inverter INV1 is shared with the source S of the NMOS transistor NM of switching transistor SWT, and is connected to the ground line VSS via via VIA on the shared top wiring TOP and bottom wiring BTM side. By sharing the source S and the top wiring TOP, the increase in the layout size of the power switch circuit PSW can be suppressed.
[0059] The drain (D) of the NMOS transistor NM in inverter INV1 is connected to the via VIA on the bottom wiring side (BTM) via the top wiring (TOP), and is connected to the output signal line OUT1 of the FSM1 layer via the upper via VIA. The output signal line OUT1 of the FSM1 layer is connected to the gate GT of the switching transistor SWT via the via (indicated by the black circle), the wiring (OUT1) of wiring layer FSM2, the via VIA (indicated by the black circle), the wiring (OUT1) of FSM1 layer, and the via VIA. Furthermore, the output signal line OUT1 of wiring layer FSM2 is connected to the gate of inverter INV2 via the via VIA (indicated by the black circle), the wiring of FSM1 layer, and the via VIA.
[0060] Below, the routing layer FSM2 is also referred to as the FSM2 layer. The routing of the routing layer FSM2 is located above the top routing layer TOP, and is formed by using any of the multiple routing layers on the top routing layer that is not the FSM1 layer.
[0061] The source S of the NMOS transistor NM in inverter INV2 is shared with the source S of the NMOS transistor NM in switching transistor SWT, and is connected to the source S of the adjacent NMOS transistor NM via a shared top wiring TOP. The drain D of the NMOS transistor NM in inverter INV2 is connected to the via VIA on the bottom wiring BTM side via the top wiring TOP, and is connected to the output signal line OUT2 of the FSM1 layer via the upper via VIA.
[0062] When an inverter is formed in a standard cell SC, the drain (D) of the inverter's NMOS transistor NM is connected to the output signal line OUT of the FSM1 wiring layer via the top wiring TOP and the upper via VIA, and is connected to the bottom wiring BTM via the top wiring TOP and the lower via VIA. The source (S) of the inverter's NMOS transistor NM is connected to the ground line VSS of the BPR layer via the top wiring TOP and the bottom wiring BTM via VIA. The gate of the inverter is connected to the input signal line IN of the FSM1 layer via via VIA.
[0063] Figure 7 It shows Figure 4 This is an example of a top-down view of the power switch circuit PSW and the standard unit SC, taken from the bottom wiring BTM side of the substrate SUB side. Figure 7 The diagram shows a PMOS transistor PM without either the additional symbols S or D, where the source and drain are in an open-circuit state and the transistor does not function as a transistor.
[0064] The PMOS transistor PM in the power switch circuit PSW and the standard cell SC is positioned offset along the X direction relative to the power line TVDD, virtual power line VVDD, and ground line VSS of the BPR layer when viewed from above. The source and drain of the PMOS transistor PM are positioned in the Z direction corresponding to the formation area of the bottom wiring BTM. The source and drain of the PMOS transistor PM, sandwiching the gate GT, are positioned on both sides in the Y direction.
[0065] In the PMOS transistor PM of the SWT switching transistor, one of the source and drain is an example of one of the first semiconductor layer and the second semiconductor layer, and the other of the source and drain is an example of the other of the first semiconductor layer and the second semiconductor layer. The PMOS transistor PM of the SWT switching transistor is an example of the first transistor.
[0066] In the PMOS transistor PM of inverters INV1 and INV2 in the control circuit CNTL, one of the source and drain is an example of one of the fifth and sixth semiconductor layers, and the other of the source and drain is an example of the other of the fifth and sixth semiconductor layers. The PMOS transistor PM of inverter INV1 is an example of the second transistor.
[0067] In the switching transistor SWT, the drains (D) of adjacent PMOS transistors (PM) in the X direction are interconnected via the bottom wiring BTM and connected to the virtual power line VVDD of the BPR layer via via VIA. In the switching transistor SWT and the control circuit CNTL, the common source (S) of adjacent PMOS transistors (PM) in the X direction is interconnected via the bottom wiring BTM. Furthermore, in the switching transistor SWT and the control circuit CNTL, located at... Figure 7 The common source S of the PMOS transistor PM on the left is connected to the power line TVDD of the BPR layer via the bottom wiring BTM and via VIA.
[0068] The drain D of the PMOS transistor PM in inverter INV1 is connected to the via VIA on the top side of the top wiring via the bottom wiring BTM, and is connected to... Figure 6 The output signal line OUT1. The drain D of the PMOS transistor PM of inverter INV2 is connected to the via VIA on the TOP side of the top wiring via the bottom wiring BTM, and is connected to... Figure 6 The output signal line OUT2.
[0069] like Figure 7As shown, when the switching transistor SWT has multiple PMOS transistors PM, the sources S of the multiple PMOS transistors PM can be connected to the power line TVDD of the BPR layer via a common bottom wiring BTM. Furthermore, when the dummy power line VVDD of the BPR layer is configured between columns of PMOS transistors PM spaced apart along the X direction in a top view, the drains D of the columns of multiple PMOS transistors PM can be connected to the dummy power line VVDD of the BPR layer via a common bottom wiring BTM. This reduces the number of bottom wiring BTMs connected to the drains D of the PMOS transistors PM.
[0070] Figure 8 It shows along Figure 6 and Figure 7 An example of the cross-section of the X1-X1' line. The gate GT of each transistor is connected to the wiring of the FSM1 layer via a via VIA. Furthermore, the gate GT of each transistor is disposed on the substrate SUB via an insulating film and is disposed between the wirings of the BPR layer spaced apart along the X direction. A nanosheet NS is disposed through the gate GT.
[0071] Figure 9 It shows along Figure 6 and Figure 7 An example of the cross-section of the X2-X2' line. In the power switch circuit PSW, the drains (D) of the NMOS transistors (NM) of inverters INV1 and INV2 are connected to the output signal line OUT1 or OUT2 of the FSM1 layer via the top wiring (TOP) and via (VIA). In the power switch circuit PSW, the drains (D) of the PMOS transistors (PM) of inverters INV1 and INV2 are connected to the top wiring (TOP) connected to the output signal line OUT1 or OUT2 via the bottom wiring (BTM) and via (VIA).
[0072] In the standard cell SC, the source S of the NMOS transistor NM is connected to the ground line VSS of the BPR layer via the top wiring TOP and the via VIA. The source S of the PMOS transistor PM is connected to the virtual power line VVDD of the BPR layer via the bottom wiring BTM and the via VIA.
[0073] Figure 10 It shows along Figure 6 and Figure 7 An example of the cross-section of the Y1-Y1' line. The gate GT of the switching transistor SWT is connected to the wiring of the FSM1 layer via via VIA, and is also connected to the wiring of the FSM2 layer via via VIA. Nanosheets NS are formed between the source / drain S / D of the NMOS transistor NM and between the source / drain S / D of the PMOS transistor PM.
[0074] As described above, in the first embodiment, by connecting the source and drain of the CFET to the power line TVDD and the virtual power line VVDD formed in the BPR layer on the surface of the substrate SUB, the power switch circuit PSW employing the CFET can be appropriately laid out. As a result, the power switch circuit PSW with a suppressed circuit size can be mounted on the semiconductor device 100.
[0075] By connecting the source and drain of the NMOS transistor NM in the SWT switching transistor to ground VSS, the potentials of the source and drain can be stabilized, thereby suppressing variations in transistor characteristics. Furthermore, it can suppress charging and discharging currents (leakage current) in the source and drain regions.
[0076] (Second Implementation)
[0077] Figure 11 An example of a top view of the substrate SUB observed from the top wiring side in the power switch circuit and standard unit of the second embodiment is shown. Figure 12 An example of a top view of the substrate side from the bottom wiring side is shown in the power switch circuit PSW and standard cell SC of the second embodiment. (Regarding...) Figure 4 , Figure 6 and Figure 7 The same elements are assigned the same symbols, and detailed descriptions are omitted.
[0078] For example, with Figure 1 same, Figure 11 and Figure 12 The power switch circuit PSW and the standard cell SC shown are mounted in the standard cell block SCB of the semiconductor device 100. Mounted with... Figure 11 and Figure 12 The cross-sectional structure of the power switching circuit PSW and the semiconductor device 100 of the standard unit SC is similar to Figure 2 same. Figure 11 and Figure 12 The example circuits shown are of the power switch circuit PSW and the standard unit SC. Figure 3 same.
[0079] Figure 11 and Figure 12 and Figure 4 The difference in layout lies in the fact that, in each CFET, the positions of the PMOS transistor PM and NMOS transistor NM in the Z direction are relative to... Figure 4 It's the opposite. That is, in Figure 11 and Figure 12 In the PMOS transistor PM, the source / drain S / D is located on the top side, while the NMOS transistor NM has its source / drain S / D located on the bottom side.
[0080] exist Figure 11 In the circuit, the drain D of the PMOS transistor PM of the switching transistor SWT is connected to the virtual power line VVDD of the BPR layer via the top wiring TOP and the via VIA. The common source S of the PMOS transistor PM of the switching transistor SWT and the PMOS transistor PM of the inverters INV1 and INV2 is connected to the power line TVDD of the BPR layer via the top wiring TOP and the via VIA.
[0081] The drains (D) of the PMOS transistors PM in inverters INV1 and INV2 are connected to the bottom-side via VIA via top wiring (output signal line OUT1 or output signal line OUT2), and also to the top-side via VIA. The gate GT of inverter INV1 is connected to the input signal line IN1 via via VIA. The gate GT of inverter INV2 and the gate GT of switching transistor SWT are connected to the output signal line OUT1 via via VIA.
[0082] In the standard cell SC, the source S of the PMOS transistor PM is connected to the virtual power line VVDD of the BPR layer via the top wiring TOP and the via VIA. In the standard cell SC, the drain D of the PMOS transistor PM is connected to the via VIA on the bottom side via the top wiring TOP, and also connected to the via VIA on the top side.
[0083] exist Figure 12 In the circuit, the common source S of the NMOS transistor NM of the switching transistor SWT and the NMOS transistor NM of the inverters INV1 and INV2 is connected to the ground line VSS of the BPR layer via the top wiring TOP and the via VIA.
[0084] The drain (D) of the NMOS transistor NM in the switching transistor SWT is connected to the ground line VSS of the BPR layer via the bottom wiring BTM and via VIA. Note that in the switching transistor SWT, the connection is located at... Figure 12 The bottom wiring BTM of the drain (D) of the NMOS transistor NM on the left side is connected to the ground line VSS of the BPR layer via a via VIA in an area not shown.
[0085] The drains (D) of the NMOS transistors (NM) in inverters INV1 and INV2 are connected to the bottom wiring (BTM, output signal line OUT1 or output signal line OUT2) and via VIA, respectively. Figure 11 Top wiring.
[0086] In the standard cell SC, the drain D of the NMOS transistor NM is connected to the bottom wiring BTM and via VIA. Figure 11The top wiring (TOP) is used. In the standard cell SC, the source (S) of the NMOS transistor NM is connected to the ground line (VSS) of the BPR layer via the bottom wiring (BTM) and the via (VIA).
[0087] As described above, in the second embodiment, similarly to the first embodiment, by connecting the source and drain of the CFET to the power line TVDD and the virtual power line VVDD formed in the BPR layer on the surface of the substrate SUB, the power switch circuit PSW employing the CFET can be appropriately laid out. As a result, the power switch circuit PSW with a suppressed circuit size can be mounted on the semiconductor device 100.
[0088] By connecting the source and drain of the NMOS transistor NM in the SWT switching transistor to ground VSS, the potentials of the source and drain can be stabilized, thereby suppressing variations in transistor characteristics. Furthermore, it can suppress charging and discharging currents (leakage current) in the source and drain regions.
[0089] Note that the first and second embodiments described above illustrate examples of a layout where the inverter and other circuitry of the standard cell SC are connected to the virtual power line VVDD and the virtual ground line VSS, and the virtual power potential VVDD is generated by the power switch circuit PSW. However, in other examples, a layout can also be applied where the inverter and other circuitry of the standard cell SC are connected to the power line VDD and the virtual ground line VVSS, and the virtual ground potential VVSS is generated by the power switch circuit PSW.
[0090] In this configuration, the switching transistor SWT of the power switch circuit PSW can have an NMOS transistor NM that connects the ground line VSS to the virtual ground line VVSS, and a PMOS transistor PM whose source and drain are connected to the power line VDD or the virtual ground line VVSS. The source and drain of the PMOS transistor PM in the switching circuit PSW can be set to an open-circuit state. Alternatively, the switching transistor SWT can be formed solely by the NMOS transistor NM, without forming the PMOS transistor PM.
[0091] The present invention has been described above based on various embodiments, but the present invention is not limited to the requirements shown in the above embodiments. These points can be modified without prejudice to the spirit of the invention and can be appropriately determined according to their application.
[0092] Explanation of reference numerals in the attached figures
[0093] 100: Semiconductor devices
[0094] BPR: Embedded cabling
[0095] BTM: Bottom Wiring
[0096] CNTL: Control Circuit
[0097] COUT, / COUT: Control signals
[0098] D: Drain electrode
[0099] FSM1: Cabling Layer
[0100] GT: Gate
[0101] IN: Input signal line
[0102] INTR: Internal circuit area
[0103] IOC, IOCP: I / O Unit
[0104] NM: NMOS transistor
[0105] NS: Nanosheet
[0106] OUT: Output signal line
[0107] PAD: solder pad
[0108] PM: PMOS transistor
[0109] PSW: Power Switch Circuit
[0110] S: Source
[0111] SC: Standard Unit
[0112] SCB: Standard Cell Block
[0113] SGNL: Signal
[0114] SUB: Substrate
[0115] SWT: Switching Transistor
[0116] TOP: Top wiring
[0117] TVDD: Power cord
[0118] TVSS: Grounding wire
[0119] VDD: Power cord
[0120] VIA: Through-hole
[0121] VSS: Grounding wire
[0122] VVDD: Virtual power line
[0123] VVSS: Virtual grounding wire
[0124] W1, W2, W3: Wiring
[0125] WL1, WL2: Wiring layers
Claims
1. A semiconductor device, comprising: substrate; A first power line, a second power line, and a third power line are formed in the substrate; A first semiconductor layer and a second semiconductor layer are formed above the substrate; A third semiconductor layer is formed on the first semiconductor layer; A fourth semiconductor layer is formed on the second semiconductor layer; A first gate is formed between the first semiconductor layer and the second semiconductor layer and between the third semiconductor layer and the fourth semiconductor layer; A first transistor is formed between the first power line and the second power line, and has a first semiconductor layer, a second semiconductor layer and a first gate, or has a third semiconductor layer, a fourth semiconductor layer and a first gate; A fifth semiconductor layer and a sixth semiconductor layer are formed on the substrate; A seventh semiconductor layer is formed on the fifth semiconductor layer; An eighth semiconductor layer is formed on the sixth semiconductor layer; A second gate is formed between the fifth semiconductor layer and the sixth semiconductor layer and between the seventh semiconductor layer and the eighth semiconductor layer; as well as The second and third transistors are formed between the first and third power lines, and have the fifth, sixth, seventh, and eighth semiconductor layers and the second gate. The output of the second transistor is electrically connected to the first gate.
2. The semiconductor device according to claim 1, wherein, The first transistor has a first semiconductor layer, a second semiconductor layer, and a first gate. The third semiconductor layer is electrically connected to the fourth semiconductor layer.
3. The semiconductor device according to claim 1, wherein, The conductivity types of the first and second semiconductor layers are different from those of the third and fourth semiconductor layers.
4. The semiconductor device according to claim 3, wherein, The semiconductor device includes a plurality of the first transistors. The third and fourth semiconductor layers of the plurality of first transistors are electrically connected to each other.
5. The semiconductor device according to claim 1, wherein, The third semiconductor layer and the fourth semiconductor layer are electrically connected to the third power line.
6. The semiconductor device according to claim 1, wherein, The semiconductor device includes: Wiring, which is connected to either the first semiconductor layer or the second semiconductor layer of the first transistor; and A standard cell having a fourth transistor formed between the second power line and the third power line. The wiring is connected to the source of the fourth transistor.
7. The semiconductor device according to claim 1, wherein, One of the fifth semiconductor layer and the sixth semiconductor layer is integrally formed with the first semiconductor layer. One of the seventh semiconductor layer and the eighth semiconductor layer is integrally formed with the third semiconductor layer.