Semiconductor device

Abstract

The semiconductor device includes first, second, and third power supply lines formed on a substrate, first and second semiconductor layers formed over the substrate, and third and fourth semiconductor layers formed on the first and second semiconductor layers, respectively. Further, the semiconductor device includes a first gate electrode formed between the first semiconductor layer and the second semiconductor layer and between the third semiconductor layer and the fourth semiconductor layer, and a switching transistor formed between the first power supply line and the second power supply line, the switching transistor has first and second semiconductor layers and a first gate, or has third and fourth semiconductor layers and a first gate.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] CFET (Complementary Field Effect Transistor) technology, which is formed by stacking transistors, is known. BPR (Buried Power Rail) technology is also known, which uses buried wiring formed in trenches on the surface of a semiconductor substrate to supply power or ground potential to the transistor. A power switching circuit for controlling the supply of power potential by providing on / off switching in a standard cell or similar component is also known.

[0003] Patent Document 1: U.S. Patent Application Publication No. 2023 / 0178435

[0004] Patent Document 2: U.S. Patent Application Publication No. 2023 / 0067311

[0005] Patent Document 3: U.S. Patent Application Publication No. 2022 / 0123023

[0006] Patent Document 4: U.S. Patent Application Publication No. 2022 / 0181258

[0007] Patent Document 5: International Publication No. 2020 / 065916

[0008] Patent Document 6: International Publication No. 2020 / 066797

[0009] Patent Document 7: International Publication No. 2020 / 217396

[0010] Patent Document 8: International Publication No. 2020 / 217400

[0011] Patent Document 9: U.S. Patent Application Publication No. 2021 / 0366902

[0012] Patent Document 10: U.S. Patent Application Publication No. 2022 / 0102479

[0013] Patent Document 11: U.S. Patent Application Publication No. 2021 / 0210600 Summary of the Invention

[0014] <Problem to be solved by this invention>

[0015] In the case of connecting the source / drain of the CFET to the wiring of the BPR to form a power switch circuit, the layout of the power switch circuit has not been discussed in detail.

[0016] The object of this invention is to properly layout a power switch circuit formed by a CFET using wiring with the source / drain connected to the BPR.

[0017] <Methods for solving problems>

[0018] In one aspect of the present invention, a semiconductor device includes: a substrate; a first power line, a second power line, and a third power line formed in the substrate; a first semiconductor layer and a second semiconductor layer formed above the substrate; a third semiconductor layer formed on the first semiconductor layer; a fourth semiconductor layer formed on the second semiconductor layer; a first gate formed between the first semiconductor layer and the second semiconductor layer and between the third semiconductor layer and the fourth semiconductor layer; and a switching transistor formed between the first power line and the second power line, having the first semiconductor layer, the second semiconductor layer, and the first gate, or having the third semiconductor layer, the fourth semiconductor layer, and the first gate.

[0019] <The Effects of the Invention>

[0020] According to the technology disclosed herein, power switching circuits formed by CFETs using source / drain wiring connected to the BPR can be appropriately laid out. Attached Figure Description

[0021] Figure 1 This is a top view showing an example of the layout of the semiconductor device according to the first embodiment.

[0022] Figure 2 It is shown Figure 1 A cross-sectional view of an example of the cross-sectional structure of a semiconductor device.

[0023] Figure 3 It shows the configuration in Figure 1 A circuit diagram of an example of a circuit in a standard unit block.

[0024] Figure 4 It is shown Figure 3 A circuit diagram of an example of a power switch circuit.

[0025] Figure 5 It is shown Figure 3 A three-dimensional diagram of an example of the layout of a power switch circuit and a standard unit.

[0026] Figure 6This is a perspective view illustrating an example of a connection method between the top wiring and the wiring formed on the BPR layer on the substrate.

[0027] Figure 7 It is shown in Figure 5 A top view of an example of a power switch circuit and standard unit, viewed from the top wiring side of the substrate SUB.

[0028] Figure 8 It is shown in Figure 5 A top view of an example of a power switch circuit and standard unit, viewed from the bottom wiring side of the substrate.

[0029] Figure 9 It shows along Figure 7 and Figure 8 A cross-sectional view of an example of the section along line X1-X1'.

[0030] Figure 10 It shows along Figure 7 and Figure 8 A cross-sectional view of an example of the section along line X2-X2'.

[0031] Figure 11 It shows along Figure 7 and Figure 8 A cross-sectional view of an example of the section along line Y1-Y1'.

[0032] Figure 12 This is a perspective view showing an example of the layout of the power switch circuit and standard unit in the second embodiment.

[0033] Figure 13 This is a circuit diagram showing an example of the power switch circuit and standard unit in the third embodiment.

[0034] Figure 14 It is shown Figure 13 A three-dimensional diagram of an example of the layout of a power switch circuit and a standard unit.

[0035] Figure 15 It is shown in Figure 14 A top view of an example of a power switch circuit and standard unit, viewed from the top wiring side of the substrate SUB.

[0036] Figure 16 It is shown in Figure 14 A top view of an example of a power switch circuit and standard unit, viewed from the bottom wiring side of the substrate.

[0037] Figure 17 This is a circuit diagram showing an example of the power switch circuit and standard unit in the fourth embodiment.

[0038] Figure 18 It is shown Figure 17 A three-dimensional diagram of an example of the layout of a power switch circuit and a standard unit.

[0039] Figure 19 This is a circuit diagram showing an example of the power switch circuit and standard unit in the fifth embodiment.

[0040] Figure 20 It is shown Figure 19 A three-dimensional diagram of an example of the layout of a power switch circuit and a standard unit. Detailed Implementation

[0041] The embodiments will now be described using the accompanying drawings. Hereinafter, the symbols representing signals are also used to represent signal lines or signal terminals. The symbols representing power supply potential are also used to represent power lines or power terminals to which power supply potential is supplied.

[0042] (First Implementation)

[0043] Figure 1 An example of the layout of the semiconductor device in the first embodiment is shown. For example, Figure 1 The semiconductor device 100 shown may be a SoC (System on Chip), a single FPGA (Field-Programmable Gate Array), etc.

[0044] Semiconductor device 100 includes multiple I / O units IOC, IOCP, and internal circuit region INTR. I / O units IOC are interface circuits for signals SGNL such as input signals, output signals, or input / output signals. I / O units IOCP are interface circuits for power supply potentials or ground potentials.

[0045] Each I / O unit (IOC) and IOCP is connected to the internal circuitry region (INTR). For example, the internal circuitry region (INTR) includes one or more standard cell blocks (SCBs) containing standard cells. Note that logic circuits other than standard cells, as well as memory, can be installed in the internal circuitry region (INTR). Memory can be installed within the standard cell blocks (SCBs).

[0046] Figure 2 It shows Figure 1This is an example of the cross-sectional structure of a semiconductor device 100. The semiconductor device 100 includes a substrate SUB and a wiring layer WL1 formed on the surface FS side of the substrate SUB. On the surface FS of the substrate SUB, source / drain electrodes S / D, which are part of a CFET, are formed on the bottom side, which is the side closest to the substrate SUB, and on the top side, which is the side furthest from the substrate SUB. The source / drain electrodes S / D of the CFET can be connected to wiring W1 formed on the wiring layer WL1. A trench is formed on the surface FS of the substrate SUB, and a buried wiring BPR of a conductor is formed in the trench.

[0047] Figure 3 It shows the configuration in Figure 1 This is an example of a circuit in a standard cell block (SCB). The standard cell block (SCB) includes a power switch circuit (PSW) and standard cells (SC). The standard cells (SC) are connected to a virtual power line (VVDD) and a ground line (VSS), and operate by receiving a virtual power potential (VVDD) from the virtual power line (VVDD). The standard cells (SC) contain various logic circuits.

[0048] The power switch circuit PSW operates by connecting to the power supply line TVDD and the ground line VSS. The power switch circuit PSW includes a control circuit CNTL and a switching transistor SWT. For example, the control circuit CNTL generates a control signal COUT for controlling the switching transistor SWT based on an input signal (not shown). The power supply line TVDD is an example of a first power supply line, the virtual power supply line VVDD is an example of a second power supply line, and the ground line VSS is an example of a third power supply line.

[0049] The switching transistor SWT is a PMOS transistor whose source is connected to the power supply line TVDD and whose drain is connected to the dummy power supply line VVDD. It operates by receiving a voltage from the control signal COUT from the control circuit CNTL as its gate potential. When the switching transistor SWT is turned on, the power supply line TVDD and the dummy power supply line VVDD are electrically connected, and the power supply potential TVDD is supplied to the standard cell SC via the dummy power supply line VVDD. When the switching transistor SWT is turned off, the electrical connection between the power supply line TVDD and the dummy power supply line VVDD is broken, and the dummy power supply line VVDD is set to a floating state.

[0050] Figure 4 It shows Figure 3 An example of a power switching circuit (PSW). The PSW includes a switching transistor SWT, which comprises a PMOS transistor PM and an NMOS transistor NM. The source of the PMOS transistor PM is connected to the power line TVDD, and its drain is connected to the dummy power line VVDD. Both the source and drain of the NMOS transistor NM are floating. The gates of the PMOS transistor PM and the NMOS transistor NM receive power from... Figure 3 The control signal COUT is output by the CNTL control circuit. Note that the source and drain of the NMOS transistor NM in the power switch circuit PSW can also be set to floating by interconnection via wiring.

[0051] Figure 4 An example is shown where a standard cell SC has an inverter configured between the virtual power line VVDD and the ground line VSS. For example, the transistors in the power switch circuit PSW and the standard cell SC are CFETs.

[0052] Figure 5 It shows Figure 3 An example of the layout of the power switch circuit PSW and the standard cell SC. Figure 5 The diagram of the interlayer insulating film is omitted; the substrate SUB is simply shown as a thick dashed line. Figure 5 In the layout shown, the source / drain S / D of a PMOS transistor PM (CFET) is formed in the semiconductor layer on the bottom side of the substrate SUB, and the source / drain S / D of an NMOS transistor NM (CFET) is formed in the semiconductor layer on the top side of the semiconductor layer on the bottom side. In the CFET, the two semiconductor layers on the bottom side are interconnected by a nanosheet NS, and the two semiconductor layers on the top side are interconnected by a nanosheet NS on the top side. In the CFET, the gate of the PMOS transistor is shared with the gate of the NMOS transistor. The source / drain S / D of the NMOS transistor NM has an N-type conductivity, and the source / drain S / D of the PMOS transistor PM has a P-type conductivity. In this invention, the semiconductor layer is sometimes referred to as the source / drain S / D, including cases where it does not function as a transistor. Furthermore, depending on the conductivity type of the semiconductor layer, a portion of the CFET structure is sometimes referred to as an NMOS transistor NM or a PMOS transistor PM, including cases where it does not function as a transistor.

[0053] The symbols S and D for the source / drain S / D of an NMOS transistor NM and a PMOS transistor PM represent the source and drain of the transistor, respectively. An NMOS transistor NM without either the S or D symbol has its source / drain S / D in an open-circuit state, indicating that it does not function as a transistor.

[0054] Figure 5 In a power switching circuit (PSW), the PMOS transistor group and the NMOS transistor group are arranged along the Y direction in the order of drain, gate, source, gate, drain. The Y direction is an example of the first direction. Figure 4 As shown, the source and drain of the NMOS transistor in the SWT switching transistor are in an open-circuit state.

[0055] The PMOS and NMOS transistor groups of the power switch circuit PSW are positioned on the substrate SUB at locations corresponding to the power line TVDD and virtual power line VVDD of the BPR layer when viewed from above. That is, the PMOS and NMOS transistor groups of the power switch circuit PSW are positioned offset in the X direction relative to the power line TVDD and virtual power line VVDD of the BPR layer when viewed from above. The X direction is an example of a second direction.

[0056] In the power switching circuit PSW, the source of the PMOS transistor in the switching transistor SWT is connected to the power line TVDD of the BPR layer via a bottom wiring BTM extending in the X direction and a via VIA. The drain of the PMOS transistor in the switching transistor SWT is connected to the virtual power line VVDD of the BPR layer via a bottom wiring BTM extending in the X direction and a via VIA. The bottom wiring BTM has a portion in the same position in the Z direction as the transistor on the substrate SUB side (bottom side) in the CFET.

[0057] In the standard cell SC, the source of the NMOS transistor is connected to the ground line VSS of the BPR layer via a top wiring TOP extending in the X direction and a via VIA. In the standard cell SC, the drain of the NMOS transistor is connected to the upper layer wiring (not shown) via a top wiring TOP extending in the X direction and a via VIA. Furthermore, in the standard cell SC, the drain of the NMOS transistor is connected to the bottom wiring BTM via a via VIA. The top wiring TOP has the same position in the Z direction as the transistor on the side opposite to the substrate SUB (top side) in the CFET.

[0058] In the standard cell SC, the source of the PMOS transistor is connected to the virtual power line VVDD of the BPR layer via a bottom wiring BTM and a via VIA that extend in the X direction and are shared with the drain D of the PMOS transistor PM in the power switching circuit PSW. In the standard cell SC, the drain of the PMOS transistor is connected to the top wiring TOP via a bottom wiring BTM and a via VIA that extend in the X direction. Note that in the PMOS and NMOS transistors of the standard cell SC, Figure 5 The gate and source on the far side in the Y direction are set to an open circuit state and are not used.

[0059] In the switching transistor SWT and the standard cell SC, the gate GT of each transistor is connected to the upper layer wiring (not shown) via a via VIA formed on the gate GT. The gate GT of the switching transistor SWT is an example of the first gate.

[0060] Note that in Figure 5In this circuit, the virtual power line VVDD of the BPR layer, located at the boundary between the power switch circuit PSW and the standard cell SC, is shared and connected to both the power switch circuit PSW and the standard cell SC. However, different virtual power lines VVDD can also be set separately. Furthermore, in the power switch circuit PSW, the positions of the power line TVDD of the BPR layer and the virtual power line VVDD can be interchanged.

[0061] Figure 6 An example of a connection method between the top wiring (TOP) and the wiring formed on the BPR layer of the substrate (SUB) is shown. Figure 6 As shown in (a), with Figure 5 The standard cell SC has the same routing. The top routing (TOP) and the BPR layer routing can be directly connected via vias (VIA) without going through the bottom routing (BTM). Figure 6 As shown in (b), the top routing (TOP) and the routing of the BPR layer can be connected via the bottom routing (BTM). Note that... Figure 6 The wiring method in (b) can also be applied to other implementation methods.

[0062] Figure 7 It shows Figure 5 An example of a top-down view of the power switch circuit PSW and the standard unit SC, taken from the top wiring side of the substrate SUB side. Figure 7 The diagram shows an NMOS transistor NM without either the S or D symbol, where the source and drain are in an open-circuit state and the transistor does not function as a transistor.

[0063] The wiring, represented by the thick solid line extending in the Y direction, represents the wiring of the wiring layer FSM1 (FSM stands for Frontside Metal) located above the switching transistor SWT and the standard cell SC (in the Z direction from the substrate SUB towards the location where the CFET is placed). The wiring of the wiring layer FSM1 is located above the top wiring TOP and is formed using any one of the multiple wiring layers on the top wiring TOP.

[0064] The NMOS transistor NM in the power switch circuit PSW and the standard cell SC is positioned offset along the X-direction from the power line TVDD, virtual power line VVDD, and ground line VSS of the BPR layer when viewed from above. The source and drain of the NMOS transistor NM are positioned in the Z-direction corresponding to the formation region of the top wiring TOP. The source and drain of the NMOS transistor NM are positioned on both sides of the gate GT in the Y-direction.

[0065] In the NMOS transistor NM of the power switching circuit PSW, one of the source and drain is an example of one of the third semiconductor layer and the fourth semiconductor layer, and the other of the source and drain is an example of the other of the third semiconductor layer and the fourth semiconductor layer.

[0066] When an inverter is formed in the standard cell SC, the drain (D) of the inverter's NMOS transistor NM is connected to the output signal line OUT of the wiring layer FSM1 via the top wiring TOP and the upper via VIA, and to the bottom wiring BTM via the top wiring TOP and the lower via VIA. Hereinafter, the wiring layer FSM1 is also referred to as the FSM1 layer. The source (S) of the inverter's NMOS transistor NM is connected to the ground line VSS of the BPR layer via the top wiring TOP and the via VIA on the bottom wiring BTM side. The gate of the inverter is connected to the input signal line IN of the FSM1 layer via via VIA.

[0067] Figure 8 It shows Figure 5 This is an example of a top-down view of the power switch circuit PSW and the standard unit SC, taken from the bottom wiring BTM side of the substrate SUB side. Figure 8 The diagram shows a PMOS transistor PM without either the S or D symbol, where the source and drain are in an open-circuit state and the transistor does not function as a transistor.

[0068] The PMOS transistor PM in the power switch circuit PSW and the standard cell SC is positioned offset along the X-direction from the power line TVDD, virtual power line VVDD, and ground line VSS of the BPR layer when viewed from above. The source and drain of the PMOS transistor PM are positioned in the Z-direction corresponding to the formation area of ​​the bottom wiring BTM. The source and drain of the PMOS transistor PM are positioned on both sides of the gate GT in the Y-direction.

[0069] In the PMOS transistor PM of the power switch circuit PSW, one of the source and drain is an example of one of the first semiconductor layer and the second semiconductor layer, and the other of the source and drain is an example of the other of the first semiconductor layer and the second semiconductor layer.

[0070] In the power switching circuit PSW, the source (S) of the PMOS transistor PM is connected to the power line TVDD of the BPR layer via the bottom wiring BTM and via VIA. The drain (D) of the PMOS transistor PM is connected to the virtual power line VVDD of the BPR layer via the bottom wiring BTM and via VIA.

[0071] like Figure 8As shown, when the switching transistor SWT includes multiple PMOS transistors PM, the sources S of the multiple PMOS transistors PM can be connected to the power line TVDD of the BPR layer via a common bottom wiring BTM. Furthermore, when the dummy power line VVDD of the BPR layer is configured between columns of PMOS transistors PM spaced apart along the X direction in a top view, the drains D of the columns of multiple PMOS transistors PM can be connected to the dummy power line VVDD of the BPR layer via a common bottom wiring BTM. This reduces the number of bottom wiring BTMs connected to the drains D of the PMOS transistors PM.

[0072] When an inverter is formed in a standard cell SC, the drain D of the PMOS transistor PM is connected to the bottom wiring BTM and via VIA. Figure 7 The drain (D) of the NMOS transistor NM and the output signal line OUT are shown. The source (S) of the PMOS transistor PM in the inverter is connected to the virtual power line VVDD of the BPR layer via the bottom wiring BTM and via VIA.

[0073] Note that in Figure 8 In the example shown, the bottom wiring BTM, which connects the source S of the inverter's PMOS transistor PM to the virtual power line VVDD of the BPR layer, is also connected to the drain D of the switching transistor SWT's PMOS transistor PM. The shared bottom wiring BTM, which interconnects the source S of the standard cell SC's inverter's PMOS transistor PM with the drain D of the switching transistor SWT's PMOS transistor PM, is an example of the fourth wiring.

[0074] Figure 9 It shows along Figure 7 and Figure 8 An example of the cross-section of the X1-X1' line is shown. The gate GT of each transistor is connected to the wiring of the FSM1 layer via a via VIA. Furthermore, the gate GT of each transistor is disposed on the substrate SUB with an insulating film between the wirings of the BPR layer spaced apart along the X direction. A nanosheet NS is disposed through the gate GT.

[0075] Figure 10 It shows along Figure 7 and Figure 8 An example of the cross-section of the X2-X2' line. In the power switch circuit PSW, the source / drain S / D of the NMOS transistor NM is set to the open circuit state, and the drain D of the PMOS transistor PM is connected to the virtual power line VVDD of the BPR layer via the bottom wiring BTM and the via VIA.

[0076] In the standard cell SC, the source S of the NMOS transistor NM is connected to the ground line VSS of the BPR layer via the top wiring TOP and the via VIA. The source S of the PMOS transistor PM is connected to the virtual power line VVDD of the BPR layer via the bottom wiring BTM and the via VIA, which is shared with the drain D of the PMOS transistor PM in the power switching circuit PSW.

[0077] Figure 11 It shows along Figure 7 and Figure 8 An example of the cross-section of line Y1-Y1' in the diagram. The source / drain S / D of the NMOS transistor NM is in an open-circuit state and does not function as a transistor. The gates GT of each transistor are connected to the wiring of the FSM1 layer via vias VIA. Nanosheets NS are formed between the source / drain S / D of the NMOS transistor NM and between the source / drain S / D of the PMOS transistor PM.

[0078] As described above, in the first embodiment, by connecting the source and drain of the CFET to the power line TVDD and the virtual power line VVDD formed in the BPR layer on the surface of the substrate SUB, the power switch circuit PSW using the CFET can be appropriately laid out. As a result, the power switch circuit PSW with a suppressed circuit size can be mounted on the semiconductor device 100.

[0079] (Second Implementation)

[0080] Figure 12 An example of the layout of the power switch circuit and standard unit in the second embodiment is shown. Regarding... Figure 5 The same elements are assigned the same symbols, and detailed descriptions are omitted. For example, with Figure 1 same, Figure 12 The power switch circuit PSW and the standard cell SC shown are mounted in the standard cell block SCB of the semiconductor device 100. Mounted with... Figure 12 The cross-sectional structure of the semiconductor device 100 in the power switch circuit PSW and standard unit SC shown is similar to... Figure 2 The circuitry configured in the standard cell block SCB is the same. Figure 3 same. Figure 12 The example circuits shown are of the power switch circuit PSW and the standard unit SC. Figure 4 same.

[0081] Figure 12 and Figure 5 The difference in layout lies in the position of the PMOS transistor PM and NMOS transistor NM in the Z direction within each CFET. Figure 5 On the contrary. That is, in Figure 12In the PMOS transistor PM, the source / drain S / D is located on the top side, and the source / drain S / D of the NMOS transistor NM is located on the bottom side.

[0082] The drain (D) of the PMOS transistor PM in the power switch circuit PSW is connected to the virtual power line VVDD of the BPR layer via the top wiring (TOP) and via VIA. Similarly, the source (S) of the PMOS transistor PM in the power switch circuit PSW is connected to the power line TVDD of the BPR layer via the top wiring (TOP) and via VIA.

[0083] In the standard cell SC, the source S of the PMOS transistor PM is connected to the virtual power line VVDD of the BPR layer via the top wiring TOP and via VIA, which are shared with the drain D of the PMOS transistor PM in the power switching circuit PSW. In the standard cell SC, the source of the NMOS transistor NM is connected to the ground line VSS of the BPR layer via the bottom wiring BTM and via VIA.

[0084] Note that in Figure 12 In the circuit, the virtual power line VVDD of the BPR layer, located at the boundary between the power switch circuit PSW and the standard cell SC, is shared and connected to both the power switch circuit PSW and the standard cell SC. However, different virtual power lines VVDD can also be set separately. Furthermore, in the power switch circuit PSW, the positions of the power line TVDD of the BPR layer and the virtual power line VVDD can be interchanged.

[0085] As described above, in the second embodiment, similarly to the first embodiment, by connecting the source and drain of the CFET to the power line TVDD and the virtual power line VVDD formed in the BPR layer on the surface of the substrate SUB, the power switch circuit PSW employing the CFET can be appropriately laid out. As a result, the power switch circuit PSW with a suppressed circuit size can be mounted in the semiconductor device 100.

[0086] (Third implementation method)

[0087] Figure 13 An example of the power switch circuit and standard unit in the third embodiment is shown. (Regarding...) Figure 4 The same elements are assigned the same symbols, and detailed descriptions are omitted. For example, with Figure 1 same, Figure 13 The power switch circuit PSW and the standard cell SC shown are mounted in the standard cell block SCB of the semiconductor device 100. Mounted with... Figure 13 The cross-sectional structure of the semiconductor device 100 in the power switch circuit PSW and standard unit SC shown is similar to... Figure 2 The circuitry installed in the standard cell block SCB is the same as... Figure 3Same. Except that the source / drain of the NMOS transistor NM is connected to the dummy power line VVDD. Figure 13 and Figure 4 The circuit structures are the same.

[0088] Figure 14 It shows Figure 13 An example of the layout of the power switch circuit PSW and the standard cell SC. For... Figure 5 The same elements are assigned the same symbols, and detailed descriptions are omitted. Figure 14 In the power switch circuit PSW, the source / drain (S / D) of the NMOS transistor NM is connected to the virtual power line VVDD of the FSM1 layer via the top wiring (TOP) and via VIA. Additionally, the drain (D) of the PMOS transistor PM in the power switch circuit PSW is connected not only to the virtual power line VVDD of the BPR layer, but also via the bottom wiring (BTM), via VIA, the top wiring (TOP), and via VIA. The layout of the standard cell SC is similar to... Figure 5 same.

[0089] By connecting the source / drain S / D of the NMOS transistor NM to the dummy power line VVDD in the switching transistor SWT, without opening the source / drain S / D of the NMOS transistor NM, the potential of the source / drain S / D of the NMOS transistor NM can be stabilized. This suppresses fluctuations in the characteristics of the power switching circuit PSW. Furthermore, it suppresses the charging and discharging current (leakage current) in the source and drain regions.

[0090] Note that, as Figure 14 A variation of the layout can be achieved by reversing the positions of the PMOS transistor PM and the NMOS transistor NM in the Z direction. That is, the source / drain S / D of the PMOS transistor PM can be located on the top side, while the source / drain S / D of the NMOS transistor NM can be located on the bottom side.

[0091] Figure 15 It shows Figure 14 This is an example of a top-down view of the substrate SUB, taken from the top wiring side, within the power switch circuit PSW and standard cell SC. (For...) Figure 7 The same elements are assigned the same symbols, and detailed descriptions are omitted.

[0092] The source / drain (S / D) of the NMOS transistor NM in the switching transistor SWT is connected to the virtual power line VVDD on the FSM1 layer via top wiring (TOP) and via VIA. The layout of the standard cell SC is similar to... Figure 7 same.

[0093] The top wiring TOP, which interconnects the source / drain S / D of adjacent NMOS transistors NM in the X direction, is an example of the first or second wiring. The virtual power line VVDD of the FSM1 layer, connected to the source / drain S / D of the NMOS transistor NM via the top wiring TOP and the via VIA, is an example of the third wiring.

[0094] Figure 16 It shows Figure 14 An example of a top-view observation of the substrate side from the bottom wiring side in a power switch circuit (PSW) and a standard cell (SC). (For...) Figure 8 The same elements are assigned the same symbols, and detailed descriptions are omitted.

[0095] The drain (D) of the PMOS transistor PM in the SWT switching transistor is connected to the virtual power line VVDD of the BPR layer via the bottom wiring BTM and the lower via VIA, and is also connected to the virtual power line VVDD via the bottom wiring BTM and the upper via VIA. Figure 15 The virtual power line VVDD of the FSM1 layer. The layout of the standard cell SC and... Figure 8 same.

[0096] As described above, in the third embodiment, similarly to the first and second embodiments, by connecting the source and drain of the CFET to the power line TVDD and the virtual power line VVDD formed in the BPR layer on the surface of the substrate SUB, the power switch circuit PSW using the CFET can be appropriately laid out. As a result, the power switch circuit PSW with a suppressed circuit size can be mounted on the semiconductor device 100.

[0097] Furthermore, in the third embodiment, by connecting the source and drain of the NMOS transistor NM to the virtual power line VVDD in the switching transistor SWT, without opening the source and drain of the NMOS transistor NM, the potentials of the source and drain of the NMOS transistor NM can be stabilized. This suppresses fluctuations in the characteristics of the switching transistor SWT. Additionally, it suppresses the charging and discharging current (leakage current) in the source and drain regions.

[0098] (Fourth Implementation)

[0099] Figure 17 An example of the power switch circuit and standard unit in the fourth embodiment is shown. (Regarding...) Figure 4 The same elements are assigned the same symbols, and detailed descriptions are omitted. For example, with Figure 1 same, Figure 17 The power switch circuit PSW and the standard cell SC shown are mounted in the standard cell block SCB of the semiconductor device 100. Mounted with... Figure 17The cross-sectional structure of the semiconductor device 100 in the power switch circuit PSW and standard unit SC shown is similar to... Figure 2 The circuitry configured in the standard cell block SCB is the same. Figure 3 The same. Except that the switching transistor SWT in the power switch circuit PSW does not include NMOS transistors (NM) but only PMOS transistors (PM), Figure 17 and Figure 4 The circuit structure is the same as that in the previous one.

[0100] Figure 18 It shows Figure 17 An example of the layout of the power switch circuit PSW and the standard cell SC. For... Figure 5 The same elements are assigned the same symbols, and detailed descriptions are omitted. Figure 18 In the layout area of ​​the power switch circuit PSW, the source / drain S / D of the PMOS transistor PM is formed on both the bottom and top sides.

[0101] The wiring of the source / drain S / D connected to the bottom side of the PMOS transistor PM is similar to... Figure 5 Same. The source S of the top-side PMOS transistor PM is connected to the power line TVDD of the BPR layer via the top wiring TOP and via VIA, and the bottom wiring BTM and via VIA shared with the source S of the bottom-side PMOS transistor PM.

[0102] The drain D of the top-side PMOS transistor PM is connected to the virtual power line VVDD of the BPR layer via the top wiring TOP and via VIA, and the bottom wiring BTM and via VIA shared with the drain D of the bottom-side PMOS transistor PM. The layout of other elements of the power switch circuit PSW is similar to... Figure 5 The layout of the standard cell SC is the same. Figure 8 same.

[0103] As described above, in the fourth embodiment, similarly to the first to third embodiments, by connecting the source and drain of the CFET to the power line TVDD and the virtual power line VVDD formed in the BPR layer on the surface of the substrate SUB, the power switch circuit PSW using the CFET can be appropriately laid out. As a result, the power switch circuit PSW with a suppressed circuit size can be mounted on the semiconductor device 100.

[0104] Furthermore, in the fourth embodiment, since the source / drain S / D of the PMOS transistor PM is formed on both the top and bottom sides of the power switch circuit PSW, it is compatible with... Figure 5 Compared to other methods, this can improve the supply capability of the virtual power supply potential VVDD based on the power switching circuit PSW.

[0105] (Fifth Implementation)

[0106] Figure 19 An example of the power switch circuit and standard unit in the fifth embodiment is shown. (Regarding...) Figure 4 The same elements are assigned the same symbols, and detailed descriptions are omitted. For example, with Figure 1 same, Figure 19 The power switch circuit PSW and the standard cell SC shown are mounted in the standard cell block SCB of the semiconductor device 100. Mounted with... Figure 19 The cross-sectional structure of the semiconductor device 100 in the power switch circuit PSW and standard unit SC shown is similar to... Figure 2 same.

[0107] exist Figure 19 In this circuit, the switching transistor SWT of the power switch circuit PSW is formed by an NMOS transistor NM, and each circuit of the standard cell SC is connected to the power line VDD and the virtual ground line VVSS to operate. For example, when an inverter is formed in the standard cell SC, the source of the inverter's PMOS transistor is connected to the power line VDD, while the source of the inverter's NMOS transistor is connected to the virtual ground line VVSS.

[0108] The switching transistor SWT has an NMOS transistor NM, whose source is connected to ground (TVSS) and drain is connected to a virtual ground (VVSS). For example, the gate of the NMOS transistor NM in the switching transistor SWT receives and receives from... Figure 3 The control signal COUT output by the control circuit CNTL is logically opposite to the control signal / COUT. The ground wire TVSS is an example of the first power line, the virtual ground wire VVSS is an example of the second power line, and the power line VDD is an example of the third power line.

[0109] Figure 20 It shows Figure 19 An example of the layout of the power switch circuit PSW and the standard cell SC. For... Figure 5 The same elements are assigned the same symbols, and detailed descriptions are omitted. Figure 20 In the layout area of ​​the power switch circuit PSW, source / drain S / D terminals of NMOS transistors NM are formed on both the bottom and top sides. Additionally, in the BPR layer, virtual ground line VVSS, ground line TVSS, and power line VDD extending in the Y direction are formed spaced apart along the X direction.

[0110] The drain (D) of the bottom-side NMOS transistor NM is connected to the virtual ground line VVSS of the BPR layer via the bottom wiring BTM and via VIA. The source (S) of the bottom-side NMOS transistor NM is connected to the ground line TVSS of the BPR layer via the bottom wiring BTM and via VIA.

[0111] The drain D of the top-side NMOS transistor NM is connected to the virtual ground line VVSS of the BPR layer via the top wiring TOP and via VIA, and the bottom wiring BTM and via VIA shared with the drain D of the bottom-side NMOS transistor NM. The source S of the top-side NMOS transistor NM is connected to the ground line TVSS of the BPR layer via the top wiring TOP and via VIA, and the bottom wiring BTM and via VIA shared with the source S of the bottom-side NMOS transistor NM.

[0112] In the standard cell SC, the source of the NMOS transistor is connected to the virtual ground line VVSS of the BPR layer via a top wiring TOP, via VIA, bottom wiring BTM, and via VIA shared with the drain D of the NMOS transistor NM of the switching transistor SWT. In the standard cell SC, the drain of the NMOS transistor is connected to the upper layer wiring (not shown) via the top wiring TOP and the upper via VIA, and is connected to the bottom wiring BTM via the lower VIA.

[0113] In the standard cell SC, the source of the PMOS transistor is connected to the power line VDD of the BPR layer via the bottom wiring BTM and via VIA. In the standard cell SC, the drain of the PMOS transistor is connected to the top wiring TOP via the bottom wiring BTM and via VIA. Note that in the PMOS and NMOS transistors of the standard cell SC, Figure 20 The gate and source on the far side in the Y direction are set to an open circuit state and are not used.

[0114] As described above, in the fifth embodiment, the source and drain of the CFET disposed in the power switch circuit PSW are connected to the ground line TVSS and the virtual ground line VVSS formed in the BPR layer on the surface of the substrate SUB. Furthermore, the source and drain of the CFET disposed in the standard cell SC are connected to the power line VDD and the virtual ground line VVSS formed in the BPR layer on the surface of the substrate SUB.

[0115] Therefore, even when the switching transistor SWT, which has its source connected to ground (TVSS) and its drain connected to virtual ground (VVSS), and the circuits of the standard cell SC are connected to the power supply line (VDD) and the virtual ground (VVSS), the power switch circuit PSW using CFET can be appropriately laid out. As a result, the power switch circuit PSW with a limited circuit size can be mounted in the semiconductor device 100.

[0116] The present invention has been described above according to various embodiments, but the present invention is not limited to the requirements shown in the above embodiments. Modifications can be made to these points without prejudice to the spirit of the invention, and can be appropriately determined according to the application method.

[0117] Symbol Explanation

[0118] 100: Semiconductor devices

[0119] BPR: Embedded cabling

[0120] BTM: Bottom Wiring

[0121] CNTL: Control Circuit

[0122] COUT, / COUT: Control signals

[0123] D: Drain electrode

[0124] FSM1: Cabling Layer

[0125] GT: Gate

[0126] IN: Input signal line

[0127] INTR: Internal circuit area

[0128] IOC, IOCP: I / O Unit

[0129] NM: NMOS transistor

[0130] NS: Nanosheet

[0131] OUT: Output signal line

[0132] PAD: solder pad

[0133] PM: PMOS transistor

[0134] PSW: Power Switch Circuit

[0135] S: Source

[0136] SC: Standard Unit

[0137] SCB: Standard Cell Block

[0138] SGNL: Signal

[0139] SUB: Substrate

[0140] SWT: Switching Transistor

[0141] TOP: Top wiring

[0142] TVDD: Power cord

[0143] TVSS: Grounding wire

[0144] VDD: Power cord

[0145] VIA: Through-hole

[0146] VSS: Grounding wire

[0147] VVDD: Virtual power line

[0148] VVSS: Virtual grounding wire

[0149] W1, W2, W3: Wiring

[0150] WL1, WL2: Wiring layers

Claims

1. A semiconductor device, comprising: substrate; A first power line, a second power line, and a third power line are formed in the substrate; A first semiconductor layer and a second semiconductor layer are formed above the substrate; A third semiconductor layer is formed on the first semiconductor layer; A fourth semiconductor layer is formed on the second semiconductor layer; A first gate is formed between the first semiconductor layer and the second semiconductor layer and between the third semiconductor layer and the fourth semiconductor layer; as well as A switching transistor is formed between the first power line and the second power line, having a first semiconductor layer, a second semiconductor layer and a first gate, or having a third semiconductor layer, a fourth semiconductor layer and a first gate.

2. The semiconductor device according to claim 1, wherein, The switching transistor has a first semiconductor layer, a second semiconductor layer, and a first gate. The third semiconductor layer is electrically connected to the fourth semiconductor layer.

3. The semiconductor device according to claim 1, wherein, The conductivity types of the first and second semiconductor layers are different from those of the third and fourth semiconductor layers.

4. The semiconductor device according to claim 3, wherein, The semiconductor device includes a plurality of the switching transistors; The third and fourth semiconductor layers of the plurality of switching transistors are electrically connected to each other.

5. The semiconductor device according to claim 4, wherein, The semiconductor device includes: A first wiring interconnects a plurality of third semiconductor layers adjacent to each other in a second direction, which is different from the first direction in which the first power line, the second power line and the third power line extend; A second wiring interconnects the plurality of fourth semiconductor layers adjacent in the second direction; and A third wiring extends in the first direction above the first and second wirings and interconnects the first and second wirings.

6. The semiconductor device according to claim 1, wherein, The third semiconductor layer and the fourth semiconductor layer are electrically connected to the second power line.

7. The semiconductor device according to claim 1, wherein, A fourth wiring is connected to either the first semiconductor layer or the second semiconductor layer of the switching transistor; as well as A standard cell having a PMOS transistor formed between the second power line and the third power line. The fourth wiring is connected to the source of the PMOS transistor.

8. The semiconductor device according to claim 1, wherein, The first and second semiconductor layers have the same conductivity type as the third and fourth semiconductor layers.

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