Substrate processing method, semiconductor device manufacturing method, hard mask forming method, substrate processing apparatus, and program

Abstract

The present invention is provided with a step for depositing an initial film by exposing a substrate to a raw material gas, and is provided with: (a) a step for preparing a substrate in which a multilayer film having a predetermined thickness in which the grain size is controlled is formed on the substrate by performing a cycle a predetermined number of times, and the multilayer film is patterned to form a multilayer film having a predetermined thickness in which the grain size is controlled; the cycle includes a step of depositing a first film by exposing the substrate to a raw material gas, and a step of exposing the substrate to a crystal growth inhibiting gas or a predetermined gas for forming a second film having a different film quality from the first film; and (b) a step for performing ion implantation using the patterned multilayer film as a hard mask.

Description

Technical Field

[0001] This invention relates to a substrate processing method, a semiconductor device manufacturing method, a hard mask forming method, a substrate processing apparatus and process. Background Technology

[0002] As a step in the manufacturing process of a semiconductor device, a process of forming a polycrystalline film on a substrate is sometimes performed (see, for example, Patent Documents 1-8). In addition, as another step, a process of ion implantation is sometimes performed using a silicon film or the like formed on the substrate as a hard mask (see, for example, Patent Document 9).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2020-43262

[0006] Patent Document 2: Japanese Patent Application Publication No. 2016-1760

[0007] Patent Document 3: Japanese Patent Application Publication No. 2009-81457

[0008] Patent Document 4: Japanese Patent Application Publication No. 2013-197307

[0009] Patent Document 5: Japanese Patent Application Publication No. 2009-147388

[0010] Patent Document 6: Japanese Patent Application Publication No. 2018-160516

[0011] Patent Document 7: International Publication No. 2022 / 064578

[0012] Patent Document 8: International Publication No. 2024 / 024166

[0013] Patent Document 9: International Publication No. 2015 / 060069 Summary of the Invention

[0014] The problem that the invention aims to solve

[0015] The greater the desired energy level for implanting impurities deeper into the substrate, the greater the required mask thickness. Furthermore, to prevent irreversible crystal damage, ion implantation is performed on SiC (silicon carbide) substrates at high temperatures. In such cases, it is sometimes difficult to maintain the required mask quality at a low cost.

[0016] This invention provides a mask technique that can be used for high-energy ion implantation.

[0017] Solution for solving the problem

[0018] According to one aspect of the present invention, a technology is provided, comprising:

[0019] (a) A process for preparing a substrate, comprising forming a multilayer film of a predetermined thickness with controlled grain size on the substrate by performing a predetermined number of cycles, and patterning the multilayer film, the cycles including a process of exposing the substrate to a raw material gas to deposit a first film, and a process of exposing the substrate to a crystal growth inhibiting gas or a predetermined gas for forming a second film with a different film composition than the first film; and

[0020] (b) The process of using the patterned multilayer film as a hard mask for ion implantation.

[0021] The effects of the invention

[0022] According to the present invention, masks can be used in high-energy ion implantation. Attached Figure Description

[0023] Figure 1 This is a cross-sectional view of a SiC superjunction MOSFET (metal-oxide-semiconductor field-effect transistor).

[0024] Figure 2 This is a flowchart of a method for manufacturing a SiC superjunction MOSFET.

[0025] Figure 3A It is a cross-sectional view of a substrate during a manufacturing process of a certain method.

[0026] Figure 3B It is a cross-sectional view of a substrate during a manufacturing process of a certain method.

[0027] Figure 3C It is a cross-sectional view of a substrate during a manufacturing process of a certain method.

[0028] Figure 3D It is a cross-sectional view of a substrate during a manufacturing process of a certain method.

[0029] Figure 4 This is a structural diagram of a substrate processing apparatus for forming a polycrystalline silicon layer in a manufacturing method.

[0030] Figure 5 This is a functional block diagram of the control unit of a substrate processing apparatus.

[0031] Figure 6 This is a diagram illustrating the sequence of processes for forming a polysilicon layer in one manner.

[0032] Figure 7A It is a TEM (transmission electron microscope) image of a cross-section of a polycrystalline silicon layer that has formed as a multilayer film.

[0033] Figure 7B This is a cross-sectional TEM image of a single-layer polysilicon layer formed through the substrate processing steps of a comparative example.

[0034] Figure 8 This is a graph showing the measurement results of the residual stress of the film formed on the substrate in a substrate processing procedure with and without an annealing process.

[0035] Figure 9 This is a depth curve of impurity concentration after ion implantation using a polysilicon layer as a mask in one method and a comparative example. Detailed Implementation

[0036] Hereinafter, an example of forming a superjunction structure of a SiC power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) by ion implantation will be described with reference to the accompanying drawings, according to one aspect of the present invention. Furthermore, the drawings used in the following description are schematic, and the dimensional relationships and ratios of the components shown in the drawings may not necessarily correspond to reality. Additionally, the dimensional relationships and ratios of the components may not be consistent between the various drawings.

[0037] (1) Structure of superjunction MOSFET

[0038] Figure 1 The image shows a longitudinal cross-section of a unit cell of the superjunction MOSFET in semiconductor device 10. The starting substrate 11 is n... + A single-crystal silicon carbide wafer is fabricated. The drift layer 12 is an n-type silicon carbide layer epitaxially grown on the starting substrate 11. - The n-type single-crystal SiC film is the region that is depleted and bears the electric field when a voltage is applied between the source and drain of the semiconductor device 10. The n-type region 13 is an n-type single-crystal SiC film epitaxially grown on the drift layer 12, which functions as a so-called current spreading layer (CSL) to reduce the spreading resistance of charge carriers.

[0039] The p-type base region 14 is a p-type single-crystal SiC film epitaxially grown on the n-type region 13, providing a channel along the gate described later. + The source region 15 is an n-type single-crystal SiC film disposed on the p-type base region 14 around (on both sides) the gate trench 17. ++ Type contact region 16 is disposed on the p-type base region 14 where no n is disposed. +The p-type single-crystal SiC film is located in the source region 15, in other words, in the region separated from the gate trench 17 of any unit cell. The starting substrate 11 to n... + Type source region 15 and p ++ The portion of the contact area 16 composed of single-crystal SiC is called the semiconductor substrate 40. + Type source region 15, p ++ One side of the contact area 16 is the surface (first surface) of the semiconductor substrate 40. Furthermore, in this specification, when referred to simply as "substrate," it sometimes means the starting substrate 11 or a substrate on which a certain film is laminated. In this specification, when described as "forming a predetermined layer on a substrate," it sometimes means forming the predetermined layer directly on the surface of the starting substrate 11, and sometimes it also means forming the predetermined layer on a layer or the like formed on the starting substrate 11. In this specification, the term "wafer" is used synonymously with the term "substrate."

[0040] Gate trench 17 is a channel extending from the surface of semiconductor substrate 40. + The source region 15 and the base region 14 are trenches extending in the depth direction. The gate trench 17 is also connected to... Figure 1 The electrode extends in a strip-like pattern perpendicular to the plane of the paper. Inside the gate trench 17, a polysilicon gate electrode 19 is embedded, separated by a SiO2 gate insulating film 18. A MOSFET with this gate structure is called a trench gate type. Furthermore, the gate electrode 19 is positioned relative to... Figure 1 The two ends of the paper in the vertical direction are exposed on the surface of the semiconductor substrate 40 via gate traces, etc., and are connected to the metal wiring.

[0041] p + Type region 21 and p + n-type region 22 is a diffusion region formed by ion implantation as part of the SiC film constituting n-type region 13. + The n-type region 21 is positioned relatively deep within the n-type region 13, connected to and covering the entire bottom surface of the gate trench 17. + Type region 21 is, for example, a diffusion region formed by ion implantation in a part of the SiC film constituting type region 13. + Type region 22 in p ++ Directly below the n-type contact area 16, so as to pass through the n-type area 13 and p + The n-shaped regions 13 are arranged such that they are separated by n-shaped regions 21 and extend through each other in the depth direction. + Type regions 21 and 12 function to mitigate the electric field near the bottom surface of the gate trench 17.

[0042] The p-type region (also known as a pillar or trap) 23 is located in the p+ The p-type region 23 is located directly below p-type region 22, extending from its upper end to near its lower end within the drift layer 12, and is formed by ion implantation into the drift layer 12. The p-type region 23 is formed sequentially via p-type... ++ Type contact region 16, p-type base region 14 and p + Type region 22 is electrically connected to source electrode 15, which will be described later.

[0043] The interlayer insulating film 24 is configured to cover the upper end of the gate trench 17, insulating the gate from the source electrode 15. The source electrode 25 is a metal film continuously disposed across the surface of the semiconductor substrate 40 where the interlayer insulating film 14 is not located (contact portion) and on the interlayer insulating film 14, and is connected to the n + Type source region 15 and p ++ Type 16 forms an ohmic contact.

[0044] The drain electrode 26 is a metal film formed on the entire back surface of the starting substrate 11 (the back surface of the semiconductor substrate 40).

[0045] In a FET with this structure, as the source-drain voltage increases when the device is turned off, the depletion layer gradually expands from the boundary between the drift layer 12 and the p-type region 23 inwards, until both the drift layer 12 and the p-type region 23 are completely depleted. That is, the drift layer 12 sandwiched between adjacent n-type regions 23 is laterally depleted from both sides, and when the lateral thickness reaches half the spacing of the p-type regions 23, a depletion layer with a thickness corresponding to the depth of the p-type regions 23 is obtained. Therefore, compared to devices with non-superjunction structures, the impurity concentration can be increased to achieve the same breakdown voltage, and the on-resistance can be reduced. The depth of the p-type region 23 is, for example, 3 μm or more, more preferably 10 μm or more.

[0046] (2) Manufacturing method of superjunction MOSFET

[0047] like Figure 2 As shown, firstly, as S1, a drift layer 12 is epitaxially grown on the surface of the starting substrate 11 using a single-wafer CVD (chemical vapor deposition) apparatus or the like. The starting substrate 11 is 4H-SiC, and its surface is tilted at 4 degrees from (0001). The drift layer 12 is n - The film has a thickness of 3 μm to 15 μm. Alternatively, a nitrogen-doped buffer layer of 1 μm to 5 μm thickness can be disposed between the starting substrate 11 and the drift layer 12. The buffer layer converts ground plane dislocations in the starting substrate 11 into harmless penetrating edge dislocations, preventing ground plane dislocations from propagating to the drift layer. It also promotes the recombination of minority carriers.

[0048] Furthermore, the drift layer 12 and the p-type region 23 are sometimes formed through multi-segment epitaxial growth. That is, mask formation and ion implantation are performed each time a thinner epitaxial layer is formed, which is a relatively complicated process. Moreover, ion implantation can roughen the surface, which may introduce new defects and energy levels into the drift layer 12, thus degrading the electrical characteristics of the device. Alternatively, trench backfill epitaxy is known in addition to ion implantation, but its process is equally complicated.

[0049] Secondly, as S2, such as Figure 3A As shown, a polycrystalline silicon layer 31, ranging from 1 μm to 20 μm in thickness, serving as a hard mask, is deposited on the drift layer 12. Furthermore, in this invention, Si represents silicon. The film thickness is determined based on the required implantation inhibition energy, for example, it is approximately 0.5 to 1.5 times the implantation depth, representing the height of the p-type region 23. When forming films using a hot-wall apparatus, compared to SiN and SiO films, Si films offer advantages such as faster deposition speed and lower particle generation. However, thick polycrystalline silicon films are susceptible to substrate warping due to stress within the film. Additionally, the crystallinity of Si films typically varies with deposition temperature; however, if the film is polycrystalline and the grain size is large, there is concern that channeling effects may occur during ion implantation, leading to reduced mask performance. In this example, as described below, an ILIS (Inhibition Layer Inserted Structure) is used for film formation in a single processing furnace, thereby achieving low stress and small particle size. In addition, a SiO2 layer or Si3N4 layer with a thickness of about 20 nm can also be formed between the drift layer 12 and the polysilicon layer 31 as an etch stop layer or buffer layer.

[0050] Secondly, as step S3, the polysilicon layer 31 is annealed (hot-dip) to appropriately alleviate the stress on the substrate where the polysilicon layer 31 is formed. The polysilicon layer 31 retains compressive stress while in its deposited state. Annealing introduces excess Si atoms from the polysilicon layer 31 into the crystallization process, reducing its volume and shifting the residual stress towards the tensile side. If the absolute value of the residual stress is large, the remaining polysilicon layer 31 may tilt during subsequent etching to form the groove 31c, or cause substrate warping, hindering subsequent photolithography and other processes. Conversely, if these adverse effects do not occur, step S3 (annealing) can be omitted.

[0051] Next, as step S4, a patterned resist film 32 is formed on the polysilicon layer 31 by photolithography. Specifically, the resist is coated, cured, exposed, developed, and cleaned. The resist film 32 is formed entirely on the polysilicon layer 31 except directly above the area where the p-type region 23 is to be formed.

[0052] Secondly, as S5, using the resist film 32 as a mask, the polysilicon layer 31 is anisotropically etched using the Bosch process, such as... Figure 3BAs shown, a trench 31c is formed in the polysilicon layer 31. The trench 31c preferably has a width of 0.5 μm to 3 μm and a depth the same as the thickness of the polysilicon layer 31, with an aspect ratio of 10 to 20. Furthermore, the spacing between adjacent trenches 31c is 1 μm to 5 μm. In the Bosch process, a passivation process is performed every few seconds to tens of seconds: exposing the substrate to plasma generated in a C4F8 gas environment for isotropic deposition of a CF-based polymer film; and an etching process is performed preferentially in a direction perpendicular to the substrate surface, exposing the substrate to plasma generated in an SF6 gas environment. The apparatus for this etching includes an etching endpoint detection system, which detects substrate exposure by spectral dispersion of plasma light to identify elements in the environment. Si is easier to etch than SiC, thus significantly reducing the difficulty compared to directly fabricating trenches for embedding p-type regions 23 in the drift layer 12, and even enabling the drilling of depths up to 20 μm in a single operation. Remove any residual resist film after etching.

[0053] Secondly, as S6, the residual polysilicon layer 31 is used as a hard mask, such as Figure 3C As shown, ion implantation is performed on the drift layer 12. Ion implantation involves ionizing aluminum and boron atoms, which act as acceptors (group 3 elements), accelerating them with energies of 1 MeV to 20 MeV, and implanting them approximately perpendicularly into the (1000) plane of the starting substrate 11. During this process, the substrate containing the drift layer 12 is heated and held at 500°C. o Around C. Ions incident on the drift layer 12 induce a channeling effect, penetrating deep into the lattice. On the other hand, ions incident on the polysilicon layer 31 are slowed down and captured within the polysilicon layer 31, and do not actually reach the drift layer 12.

[0054] In this example, very high energy is required to implant ions deep into the drift layer 12. To mitigate damage to the drift layer 12, the substrate is heated to 400°C. o C~650 o Implantation is performed at a C-level. Furthermore, when forming p-type pillars for p-type MOSFETs, nitrogen and phosphorus from group 5 elements can be used.

[0055] Next, as step S7, the unwanted polysilicon layer 31 is completely removed by etching. For example, wet etching using an aqueous solution of fluorinated nitric acid (a mixture of HF and HNO3) or an aqueous solution of tetramethylammonium hydroxide can be used for etching.

[0056] Secondly, as in S8, the substrate containing the drift layer 12 is annealed to activate the implanted impurities, such as... Figure 3D As shown, a p-type region 23 appears where the conductivity reverses from n to p. Annealing is performed using a longitudinal batch furnace at 700°C. o C~1800o The process is carried out for several minutes to tens of hours in an inert gas or Si-containing gas environment. In addition, a capping layer protecting the surface of the drift layer 12 can also be formed before annealing.

[0057] The subsequent processing is the same as the previous method, so the explanation is omitted.

[0058] (3) Polycrystalline silicon layer film deposition apparatus

[0059] Next, the structure of the substrate processing apparatus for forming the polysilicon layer 31 in S2 will be described.

[0060] like Figure 4 As shown, the processing furnace 202 has a heater 207 that functions as a temperature regulator (heating unit). The heater 207 is cylindrical and is vertically mounted by being supported on a retaining plate. The heater 207 also functions as an activation mechanism (activation unit) for activating gases with heat.

[0061] Inside the heater 207, a reaction tube 203 is arranged concentrically with the heater 207. The reaction tube 203 is made of a heat-resistant material such as quartz (SiO2) or silicon carbide (SiC) and is formed into a cylindrical shape with a closed upper end and an open lower end. A manifold 209 is arranged below the reaction tube 203. The manifold 209 is made of a metal material such as stainless steel (SUS) and is formed into a cylindrical shape with open upper and lower ends. The upper end of the manifold 209 is configured to engage with the lower end of the reaction tube 203 to support the reaction tube 203. An O-ring 220a is provided between the manifold 209 and the reaction tube 203 as a sealing component. The reaction tube 203 is installed vertically, just like the heater 207. The reaction tube 203 and the manifold 209 mainly constitute a processing container (reaction container). A processing chamber 201 is formed in the hollow part of the processing container. The processing chamber 201 is configured to hold the wafer 200, which serves as a substrate. The wafer 200 is processed within the processing chamber 201.

[0062] Inside the processing chamber 201, nozzles 249a to 249c, serving as first to third supply units, are respectively installed through the side wall of the manifold 209. Nozzles 249a to 249c are also referred to as the first to third nozzles. Nozzles 249a to 249c are made of, for example, a heat-resistant material such as quartz. Gas supply pipes 232a to 232c are connected to nozzles 249a to 249c respectively. Nozzles 249a to 249c are nozzles of different lengths.

[0063] Nozzle 249a is positioned within the processing chamber 201, extending along the wafer arrangement direction to a position near the top of the wafer arrangement area, which is the region from the lowermost wafer 200 to the uppermost wafer 200. Nozzle 249c is positioned along the wafer arrangement direction to a position near the bottom of the wafer arrangement area. Nozzle 249b is positioned near the center of the wafer arrangement area. Nozzles 249a and 249c are respectively positioned adjacent to nozzle 249b. Gas supply holes 250a and 250c are respectively provided at the front ends of nozzles 249a and 249c.

[0064] In gas supply pipes 232a-232c, mass flow controllers (MFCs) 241a-241c (flow controllers) and valves 243a-243c (on / off valves) are sequentially installed from the upstream side of the airflow. Gas supply pipes 232d and 232e are connected downstream of valve 243a from gas supply pipe 232a. Gas supply pipes 232f and 232h are connected downstream of valve 243b from gas supply pipe 232b. Gas supply pipe 232g is connected downstream of valve 243c from gas supply pipe 232c. In gas supply pipes 232d-232h, MFCs 241d-241h and valves 243d-243h are sequentially installed from the upstream side of the airflow. Gas supply pipes 232a-232h are made of, for example, a metal material such as SUS.

[0065] Raw material gas is supplied to the processing chamber 201 from gas supply pipes 232a-232c via MFCs 241a-241c, valves 243a-243c, and nozzles 249a-249c, respectively. The raw material gas can also be referred to as a gas containing the first element as a raw material.

[0066] Clean gas is supplied into the treatment chamber 201 from the gas supply pipe 232d via MFC 241d, valve 243d, and nozzle 249a.

[0067] Inert gas is supplied to the processing chamber 201 from gas supply pipes 232e to 232g via MFC 241e to 241g, valves 243e to 243g, gas supply pipes 232a to 232c, and nozzles 249a to 249c.

[0068] From gas supply pipe 232h, through MFC 241h, valve 243h, gas supply pipe 232b, and nozzle 249b, a crystal growth inhibitor gas that affects the crystal growth of the raw material gas is supplied into the processing chamber 201.

[0069] The raw material gas supply system (also known as the film-forming gas supply system) is mainly composed of gas supply pipes 232a-232c, MFCs 241a-241c, and valves 243a-243c. The clean gas supply system is mainly composed of gas supply pipe 232d, MFCs 241d, and valves 243d. The inert gas supply system is mainly composed of gas supply pipes 232e-232g, MFCs 241e-241g, and valves 243e-243g. The crystallization growth inhibition gas supply system is mainly composed of gas supply pipe 232h, MFCs 241h, and valves 243h.

[0070] Here, the raw material gas plays the role of film-forming gas and gas containing the first element. Therefore, the raw material gas supply system is also called the film-forming gas supply system or the supply system containing the first element.

[0071] Any or all of the aforementioned supply systems can be configured as an integrated supply system 248 consisting of integrated valves 243a-243h, MFCs 241a-241h, etc. The integrated supply system 248 is configured to be connected to gas supply pipes 232a-232h respectively, and the supply of various gases into the gas supply pipes 232a-232h, i.e., the opening and closing of valves 243a-243h, and the flow adjustment of MFCs 241a-241h, etc., are controlled by the controller 121 described later. The integrated supply system 248 is configured as a single or segmented integrated unit, capable of being installed and removed from the gas supply pipes 232a-232h, etc., on a unit-by-unit basis, and is configured to allow for maintenance, replacement, and addition of the integrated supply system 248 on a unit-by-unit basis.

[0072] An exhaust port 231a is provided below the side wall of the reaction tube 203 to discharge the ambient gas inside the processing chamber 201. The exhaust port 231a can be located opposite the nozzles 249a to 249c (gas supply ports 250a to 250c) across the wafer 200. The exhaust port 231a can be located on the side wall of the manifold 209, or it can be located above the lower part of the side wall of the reaction tube 203, that is, along the wafer arrangement area. An exhaust pipe 231 is connected to the exhaust port 231a. A vacuum pump 246, which serves as an exhaust device, is connected to the exhaust pipe 231 via a pressure sensor 245, which acts as a pressure detector (pressure detection unit) for detecting the pressure inside the processing chamber 201, and an APC (Auto Pressure Controller) valve 244, which acts as a pressure regulator (pressure adjustment unit). The APC valve 244 is configured to allow for vacuum exhaust and cessation of vacuum exhaust within the processing chamber 201 by opening and closing the valve while the vacuum pump 246 is running. Furthermore, by adjusting the valve opening based on pressure information detected by the pressure sensor 245 while the vacuum pump 246 is running, the pressure within the processing chamber 201 can be adjusted. The exhaust system mainly consists of the exhaust pipe 231, the APC valve 244, and the pressure sensor 245. It is also possible to include the vacuum pump 246 within the exhaust system.

[0073] Below the manifold 209, a sealing cover 219 is provided as a furnace opening cover capable of airtightly sealing the lower opening of the manifold 209. The sealing cover 219 is made of a metal material such as SUS and is formed in a disc shape. On the upper surface of the sealing cover 219, an O-ring 220b is provided as a sealing member that abuts against the lower end of the manifold 209. Below the sealing cover 219, a rotation mechanism 267 is provided for rotating the crystal boat 217 (described later). The rotation shaft 255 of the rotation mechanism 267 passes through the sealing cover 219 and is connected to the crystal boat 217. The rotation mechanism 267 is configured to rotate the wafer 200 by rotating the crystal boat 217. The sealing cover 219 is configured to be raised and lowered vertically by a crystal boat lift 115, which is a lifting mechanism provided outside the reaction tube 203. The crystal boat lift 115 is configured as a conveying device (conveying mechanism) to move the wafer 200 into and out of the processing chamber 201 by raising and lowering the sealing cover 219.

[0074] A baffle 219s, serving as a furnace opening cover, is provided below the manifold 209. This baffle closes the lower opening of the manifold 209 while the sealing cover 219 is lowered and the crystal boat 217 is removed from the processing chamber 201. The baffle 219s is formed into a disc shape, for example, from a metal material such as SUS. An O-ring 220c, serving as a sealing component, can be provided on the upper surface of the baffle 219s, abutting against the lower end of the manifold 209. The opening and closing actions (lifting, rotating, etc.) of the baffle 219s are controlled by a baffle opening and closing mechanism 115s.

[0075] The crystal boat 217, serving as a substrate support, is configured to support multiple wafers 200, for example, 25 to 200 wafers, arranged horizontally and with their centers aligned with each other in a vertical direction, in a multi-segment arrangement with intervals between them. The crystal boat 217 is made of heat-resistant materials such as quartz or SiC. Multiple heat insulation plates 218 are supported at the bottom of the crystal boat 217.

[0076] A temperature sensor 263, serving as a temperature detector, is installed inside the reaction tube 203. The energization of the heater 207 is adjusted based on the temperature information detected by the temperature sensor 263, thereby achieving the desired temperature distribution within the processing chamber 201. The temperature sensor 263 is disposed along the inner wall of the reaction tube 203.

[0077] like Figure 5 As shown, the controller 121, serving as the control unit (control mechanism), is configured as a computer equipped with a CPU (Central Processing Unit) 121a, RAM (Random Access Memory) 121b, storage device 121c, and I / O interface 121d. The RAM 121b, storage device 121c, and I / O interface 121d are configured to exchange data with the CPU 121a via an internal bus 121e. An input / output device 122, such as a touch panel, is connected to the controller 121.

[0078] Storage device 121c includes, for example, flash memory, HDD (Hard Disk Drive), SSD (Solid State Drive), etc. Storage device 121c stores in a readable manner a control program for controlling the operation of the substrate processing apparatus, a process recipe describing the steps and conditions of the substrate processing described later, etc. The process recipe functions as a program by combining the steps in the substrate processing described later by the controller 121 to obtain a predetermined result. Hereinafter, the process recipe, control program, etc., will be collectively referred to as a program. Furthermore, the process recipe is also simply referred to as a recipe. In this specification, when the term "program" is used, it may sometimes include only the recipe unit, sometimes only the control program unit, or sometimes both. RAM 121b is configured as a storage area, temporarily storing programs, data, etc., read by CPU 121a.

[0079] I / O interface 121d is connected to the aforementioned MFC241a~241h, valves 243a~243h, pressure sensor 245, APC valve 244, vacuum pump 246, temperature sensor 263, heater 207, rotating mechanism 267, crystal boat elevator 115, baffle opening and closing mechanism 115s, etc.

[0080] CPU 121a is configured to read and execute control programs from storage device 121c, and to read recipes from storage device 121c based on inputs of operation instructions from input / output device 122. CPU 121a is configured to control, according to the read recipe, various gas flow adjustment operations via MFCs 241a to 241h, opening and closing operations of valves 243a to 243h, opening and closing operations of APC valve 244 and pressure adjustment operations of APC valve 244 based on pressure sensor 245, starting and stopping of vacuum pump 246, temperature adjustment operations of heater 207 based on temperature sensor 263, rotation and rotation speed adjustment operations of crystal boat 217 via rotation mechanism 267, lifting and lowering operations of crystal boat 217 via crystal boat elevator 115, and opening and closing operations of baffle 219s via baffle opening and closing mechanism 115s.

[0081] The controller 121 can be configured by installing the aforementioned program stored in the external storage device 123 onto the computer. The external storage device 123 may include, for example, a hard disk such as an HDD, an optical disk such as a CD, an optical disk such as an MO, a USB (Universal Serial Bus) memory, or a semiconductor memory such as an SSD. The storage device 121c and the external storage device 123 constitute a computer-readable storage medium. Hereinafter, these will be collectively referred to as storage media. Furthermore, when providing a program (program product) to a computer, the external storage device 123 may be omitted, and communication methods such as the Internet or dedicated lines may be used instead.

[0082] (4) Polycrystalline silicon layer formation process

[0083] Secondly, refer to Figure 6 , Figure 7A , 7B The substrate processing method for forming a polysilicon layer 31 using the above-described substrate processing apparatus via steps S2 to S3 will be described below. In the following description, the operation of each component constituting the substrate processing apparatus is controlled by the controller 121. In this example, the polysilicon layer 31 is formed by alternately supplying a raw material gas and a crystal growth inhibiting gas. Figure 7A The multilayer film shown.

[0084] That is, the film deposition process includes step C, in which a multilayer film of a predetermined thickness, serving as a polycrystalline silicon layer 31, is formed on the wafer 200 by performing the cycle including steps A and B a predetermined number of times (n times, where n is an integer greater than or equal to 1). In step A, a starting substrate 11 with a pre-formed drift layer 12 is prepared as the wafer 200, and the substrate is exposed to a raw material gas, thereby depositing a polycrystalline film as a primitive film. In step B, the substrate is exposed to a crystal growth-inhibiting gas. Furthermore, step B is performed under conditions where new grains are formed from the polycrystalline film deposited in the subsequent step A.

[0085] (Wafer loading and introduction)

[0086] After multiple wafers 200 are loaded into the crystal boat 217, the baffle 219s is moved by the baffle opening and closing mechanism 115s, opening the lower end of the manifold 209. Subsequently, as... Figure 1 As shown, a crystal boat 217 supporting multiple wafers 200 is lifted by a crystal boat elevator 115 and moved (introduced) into the processing chamber 201. Finally, the processing chamber 201 is hermetically sealed by a sealing cover 219. At this time, inert gas is supplied to the processing chamber 201, and the temperature inside the processing chamber 201 is maintained at the required temperature.

[0087] (Vacuum exhaust and temperature adjustment)

[0088] Subsequently, vacuum exhaust (pressure reduction exhaust) is performed by vacuum pump 246 to bring the pressure (vacuum level) within processing chamber 201, i.e., the space containing wafer 200, to the required level. At this time, pressure sensor 245 measures the pressure within processing chamber 201, and APC valve 244 is controlled based on this measured pressure information. Furthermore, wafer 200 within processing chamber 201 is heated by heater 207 to achieve the required processing temperature. At this time, the energization of heater 207 is controlled based on temperature information detected by temperature sensor 263 to achieve the required temperature distribution within processing chamber 201. Additionally, rotation of wafer 200 begins via rotation mechanism 267. Exhausting from processing chamber 201, heating wafer 200, and rotation continue at least until the processing of wafer 200 is complete.

[0089] Then, steps A and B are executed in sequence. The following is a description of each of these steps.

[0090] [Step A]

[0091] In step A, a raw material gas is supplied to the wafer 200 in the processing chamber 201, exposing the wafer 200 to the raw material gas, thereby depositing a polycrystalline film on the surface of the wafer 200. Then, the supply of raw material gas is stopped, and the remaining raw material gas in the processing chamber 201 is discharged (purified).

[0092] Specifically, valves 243a-243c are opened to supply raw material gas into gas supply pipes 232a-232c. The flow rate of the raw material gas is adjusted by MFCs 241a-241c, and it is supplied into the processing chamber 201 through nozzles 249a-249c and discharged from the exhaust port 231a. At this time, the wafer 200 is supplied with raw material gas, exposing it to the raw material gas. At this time, the pressure in the processing chamber 201 is maintained at a predetermined processing pressure by APC valve 244.

[0093] By supplying a feed gas to wafer 200 under the processing conditions described later, an initial film is deposited on the surface of wafer 200 using thermal CVD to form a polycrystalline film 31a. The polycrystalline film 31a is, for example, a film containing Group 14 elements, such as Si or Ge. In this embodiment, a hot-wall type batch processing chamber is used, thus contrasting with a cold-wall type processing chamber where surface reactions are the primary focus, and CVD is mostly performed in conjunction with a gas-phase reaction. The quality (film quality) of the film obtained through various types of processing chambers may differ. For example, compared to Epi-poly Si (epitaxy polycrystalline silicon) films manufactured using a cold-wall type monolithic apparatus, poly-Si (polycrystalline silicon) films manufactured using a hot-wall type depressurized CVD apparatus tend to have greater stress or a larger absolute value of stress gradient. While the gas-phase reaction provides abundant reaction intermediates, which helps form a high-quality film at low temperatures, it may, as described below, generate excess atoms, leading to increased residual stress.

[0094] As the feed gas, a gas used for depositing polycrystalline films 31a on wafer 200 can be used, such as a gas containing Group 14 elements, or a Si-containing gas, such as a Si-containing gas. For example, a silane (SiH4) gas can be used as the Si-containing gas. When using SiH4 gas as the feed gas, in this step, the SiH4 gas is thermally decomposed to form a polycrystalline silicon film as a polycrystalline film on the surface of wafer 200. In addition to Si-containing gases, the feed gas may also contain reducing gases, carrier gases, or diluting gases such as hydrogen (H2), nitrogen (N2), helium (He), and argon (Ar).

[0095] In step A, the processing conditions for supplying the raw material gas can be exemplified as follows:

[0096] Processing temperature: 400~1000 o C, preferably 500–750 o C, for example, 620 oC; Processing pressure: 1~100000Pa, preferably 10~1000Pa; Raw material gas supply flow rate: 10~5000sccm, preferably 100~1500sccm; Film formation speed: 0.1~30nm / min, preferably 1~20nm / min; Inert gas supply flow rate (per gas supply tube): 0~3000sccm.

[0097] At the end of step A, valves 243a to 243c are closed to stop the supply of raw material gas, and a vacuum is applied to the processing chamber 201 to remove any residual raw material gas from the chamber. At this time, inert gas is supplied to the processing chamber 201 through nozzles 249a to 249c. The inert gas supplied from nozzles 249a to 249c acts as a purifying gas, thereby purifying the processing chamber 201.

[0098] As an inert gas, N2 gas can be used, or other rare gases such as Ar, He, Ne, and Xe can also be used. The same applies to the following steps.

[0099] Examples of treatment conditions for purification in step A include:

[0100] Processing temperature: 400~1000 o C, preferably the same temperature as when the raw material gas is supplied; processing pressure: 1 to 5000 Pa, preferably 5 to 1000 Pa; inert gas supply flow rate (per gas supply pipe): 0.1 to 5000 sccm; inert gas supply time: 1 to 3000 seconds.

[0101] Furthermore, the numerical ranges expressed in this specification, such as "1000~100000Pa", include both the lower and upper limits. Therefore, for example, "1000~100000Pa" means "above 1000Pa and below 100000Pa". The same applies to other numerical ranges. Additionally, the processing temperature in this specification refers to the temperature of the wafer 200 or the temperature inside the processing chamber 201, and the processing pressure refers to the pressure inside the processing chamber 201. Furthermore, the processing time refers to the duration of the processing. These also apply in the following descriptions.

[0102] [Step B]

[0103] After step A is completed, step B is performed. In step B, a growth-inhibiting gas and an inert gas are supplied to the wafer 200 in the processing chamber 201. That is, the wafer 200, after the polycrystalline film 31a is formed on its surface, is exposed to the growth-inhibiting gas. As a result, a growth-inhibiting layer (also called a growth-inhibiting film) 31b is formed on the surface of the wafer 200 with the polycrystalline film. Thereafter, the supply of the growth-inhibiting gas and the inert gas is stopped, and the gas remaining in the processing chamber 201 is discharged.

[0104] Specifically, valve 243h is opened to supply crystal growth inhibiting gas into gas supply pipe 232b. The crystal growth inhibiting gas is supplied to processing chamber 201 via nozzle 249b after flow adjustment via MFC 241h, and discharged from exhaust port 231a. At this time, the wafer 200, on which a polycrystalline film is formed on its surface, is exposed to the crystal growth inhibiting gas by supplying it with the crystal growth inhibiting gas. Meanwhile, with valves 243e to 243g open, inert gas is supplied to processing chamber 201 via each of nozzles 249a to 249c.

[0105] Under the processing conditions described later, a growth-inhibiting gas is supplied to wafer 200, exposing wafer 200 to the growth-inhibiting gas. This forms a growth-inhibiting layer 31b on the surface of the polycrystalline film formed in the previous step A. This growth-inhibiting layer 31b is, for example, a layer containing elements other than those constituting the polycrystalline film. The growth-inhibiting layer 31b stops the continuous growth of the microcrystals (grains) constituting the polycrystalline film.

[0106] Step B is performed under conditions where new grains are formed in the polycrystalline film deposited in the subsequent step A, as described later. That is, by exposing the wafer 200, on which the polycrystalline film is formed, to a growth-inhibiting gas, new grains can be formed in the polycrystalline film deposited in the subsequent step A. In other words, step B serves as a catalyst to terminate the grain boundaries of the polycrystalline film formed on the surface of the wafer 200, providing nuclei at a predetermined density to the polycrystalline film deposited in the subsequent step A, resulting in independent crystallization that is not continuous with the crystallization of the substrate. The growth-inhibiting layer 31b is not limited to being formed during step B and may include amorphous or other less crystalline layers formed in the initial stage of the subsequent step A.

[0107] The thickness of the film or layer formed in step B is thinner than the thickness of the polycrystalline film formed in the previous step A, for example, less than 1 / 10 of the thickness of the polycrystalline film formed in the previous step A. Alternatively, step B may modify or remove a portion of the film formed in the previous step A, or change (reconstruct) its surface state.

[0108] Next, close valves 243h and 243e-243g to stop the supply of crystal growth-inhibiting gases and inert gases. Then, perform vacuum exhaust in the processing chamber 201 to remove any residual gases from the processing chamber 201.

[0109] Examples of treatment conditions for supplying the crystal growth-inhibiting gas in step B include:

[0110] Processing pressure: 1-10000 Pa, preferably 1-1000 Pa; Crystal growth inhibiting gas supply flow rate: 0.1-5000 sccm, preferably 10-500 sccm; Crystal growth inhibiting gas supply time: 0.1 seconds-30 minutes, preferably 1 second-3 minutes; Inert gas supply flow rate (per gas supply pipe): 0-3000 sccm.

[0111] As an example of the processing conditions for venting in step B:

[0112] Processing pressure: 0.1~5000Pa, preferably 10~1000Pa.

[0113] Furthermore, in step B, the output of heater 207 is adjusted to operate at the same processing temperature as in step A. This processing temperature is higher than the substrate temperature during the fabrication of Epi-poly Si films using a cold-wall monolithic apparatus (typically 1000 °C). o (Above C) is low.

[0114] As a crystal growth barrier gas, oxygen (O) gas or nitrogen (N) gas can be used, for example. O gas, for example, oxygen (O2) gas can be used. By using an O gas as a crystal growth barrier gas, at least a portion of the polycrystalline film formed on the surface of wafer 200 in step A can be oxidized, forming a film of a different material from the polycrystalline film on the surface of the polycrystalline film, that is, a layer containing elements other than those constituting the polycrystalline film, i.e., a layer containing O, thus hindering continuous crystal growth. In other words, the oxide layer can be used as a crystal growth barrier layer 31b to hinder the crystal growth of the polycrystalline film.

[0115] Furthermore, step B can be performed under the following conditions: the crystal nuclei formed in step B have the desired areal density, for example, the crystal grain size of the polycrystalline film formed thereon is more than 1 / 5 and less than 1 of the crystal grain size without step B. This condition can be achieved by controlling the oxygen partial pressure, processing temperature, and processing time when supplying O-containing gas in step B.

[0116] [Step C]

[0117] By performing steps A and B asynchronously a predetermined number of times (n times, where n is an integer greater than or equal to 1), a multilayer film of a predetermined thickness, for example, 1 μm to 20 μm, is formed on the surface of the sacrificial layer 300 of wafer 200. If the thickness is 1 μm, it is difficult to form a well of the depth required for the superlattice structure by ion implantation. In addition, if it is greater than 20 μm, it prevents the use of commercially available ion implantation energy (currently around 15 MeV), which is excessive, and the risk of deterioration of the verticality of the mask side faces increases. The above-mentioned cycle is preferably repeated multiple times, and more preferably three times or more. Specifically, whenever the polycrystalline film 31a is formed to a thickness of, for example, 100 to 500 nm, more specifically, 250 nm, a crystal growth barrier layer 31b is formed, thereby forming a multilayer film of a thickness of, for example, 1 μm to 20 μm, more preferably 1 μm to 10 μm, on the surface of the sacrificial layer 300 of wafer 200. In addition, steps A and B can be performed simultaneously.

[0118] Then, after step C, step A is performed to form a polycrystalline film 31a on the crystal growth barrier layer 31b. That is, the polycrystalline film 31a is deposited on the crystal growth barrier layer 31b in a manner that forms new grains. In other words, the polycrystalline film 31a separated by the crystal growth barrier layer on the upper and lower sides does not have crystal continuity or its crystal continuity is restricted. Through EBSD (Electron Back Scatter Diffraction) analysis, it can be confirmed that when the insertion interval of the crystal growth barrier layer 31b is 50 nm, the weighted average grain size of each of the multiple polycrystalline films 31a is substantially equal, which is about 3 times the insertion interval of the crystal growth barrier layer 31b, that is, substantially equal to 160-170 nm.

[0119] Thus, through the crystal growth barrier layer 31b, it will be as follows Figure 7A The grains of the polycrystalline film 31a on the wafer 200 shown are broken down to form a multilayer polycrystalline film 13a, i.e., a multilayer film. The structure of this multilayer film will be referred to as ILIS (inhibition layer inserted structure) below, and the film formation process for this structure will be called the ILIS process. In contrast, conventional single-film structures that do not use ILIS will be referred to as comparative examples (see reference). Figure 7B To obtain a multilayer film of a predetermined thickness, the predetermined number of times (the number of times step B is performed, also known as the number of crystal growth barrier layers) changes the density of amorphous or excess Si atoms in the multilayer film as described later. Therefore, by controlling the predetermined number of times, the residual stress of the multilayer film as a whole can be controlled.

[0120] The predetermined number of times is set so that the absolute value of the residual stress in the multilayer film after the annealing process described later is within an acceptable range. The acceptable value of the residual stress in the film varies depending on the application, for example, -150 to 150 MPa. Here, stress is positive when tensile and negative when compressive. That is, by controlling the number of times step B is performed, the residual stress in the multilayer film after the annealing process can be controlled. Here, residual stress refers to the stress existing in an object in the absence of external force. In this invention, it may include the force acting between the multilayer film and its substrate, i.e., wafer 200, and the stress remaining in the multilayer film after a portion of the multilayer film is removed to release some of the aforementioned residual stress. In addition, residual stress can also be referred to as film stress.

[0121] Here, the number of times step B is performed in the film-forming process is set as follows: the greater the residual stress in the annealed film, the more residual stress is performed; the smaller the residual stress in the film (i.e., the greater the compression side), the fewer residual stress is performed. In other words, by controlling the number of times step B is performed, the residual stress in the multilayer film can be controlled, thereby mitigating the overall residual stress of the multilayer film.

[0122] Furthermore, the grain size of the multilayer film can be controlled by the number of times step B is performed. That is, by confining the grains within each polycrystalline film 31a, at least the size of the grains in the height direction is limited by the spacing of the crystal growth inhibiting layers 31b. In the multilayer film formed in this manner, the thickness of each polycrystalline film is preferably less than one time the weighted average grain size of the film, more preferably less than one-third; in other words, the lateral dimension of the grown crystals is preferably greater than the longitudinal dimension. The smaller the grain size is confined by this method, the smaller the grain size inhomogeneity. From this point of view, the preferred average grain size is in the range of 0 to 0.2 μm. If it exceeds this range, there is a tendency for the grain size inhomogeneity to increase and the surface roughness to deteriorate.

[0123] (Purify and restore atmospheric pressure)

[0124] Next, inert gas is supplied into the processing chamber 201 through nozzles 249a to 249c and discharged through exhaust port 231a. The inert gas supplied through nozzles 249a to 249c acts as a purifying gas, thereby purifying the processing chamber 201 and removing residual gases and reaction byproducts. Afterward, the ambient gas in the processing chamber 201 is replaced with inert gas, restoring the pressure inside the processing chamber 201 to atmospheric pressure.

[0125] (Export and wafer removal)

[0126] Subsequently, the sealing cap 219 is lowered by the crystal boat lift 115, opening the lower end of the manifold 209. Then, the processed wafer 200, supported by the crystal boat 217, is moved (exported) from the lower end of the manifold 209 to the outside of the reaction tube 203. After export, the baffle 219s is moved, and the lower end opening of the manifold 209 is sealed via the O-ring 220c. After the processed wafer 200 is moved to the outside of the reaction tube 203, it is removed from the crystal boat 217.

[0127] Subsequently, in another processing furnace (processing chamber), the crystal boat is introduced, and the pressure and temperature in the processing chamber are adjusted before proceeding to the next annealing process S3.

[0128] Figure 7A This is a cross-sectional TEM (Transmission Electron Microscopy) image of a polycrystalline silicon layer experimentally formed using the method described above. In this experiment, step A, which involves depositing a 250 nm layer on a SiO2 film as a buffer layer, was repeated more than 20 times with step B inserted in between, thereby obtaining a polycrystalline silicon multilayer film with a thickness of more than 5 μm. It was confirmed that independent grains were formed every 250 nm in the depth direction, and the grains were small and uniform in shape. In addition, the surface roughness (Ra) was evaluated to be less than 15 nm. On the other hand, Figure 7B This is a comparative example of a polycrystalline silicon layer deposited continuously without step B. It can be confirmed that in the monolayer polycrystalline silicon layer, the crystals grow in a columnar pattern, resulting in large and uneven grain shapes. This suggests that in-plane inhomogeneities in grain shape and orientation may lead to differences in blocking energy at different locations. Furthermore, the surface roughness is also above 60 nm, which may cause surface scattering during ion implantation.

[0129] Next, the annealing process S3 will be explained. The annealing process S3 is carried out in a different processing furnace than the processing furnace of the film forming process (non-in-situ).

[0130] Here, the wafer 200, after having multiple films formed on its surface, undergoes annealing in a non-plasma N2 environment. At this time, the heater output is adjusted so that the temperature of the wafer 200 is above and 1200°C of the temperature of the wafer 200 in the film deposition process S2. o Below C, 900 is more preferred. o C or above and 1100 oTemperatures below C. Annealing transforms the initial polycrystalline film into films of different materials, often causing film shrinkage. Specifically, during annealing, amorphous Si present near grain boundaries in the growth barrier layer sometimes integrates with adjacent grains, similar to solid-phase epitaxial growth. According to experimental results described later, the more times step C is performed (the more times step B is performed), the higher the proportion of excess Si in the multilayer film, and therefore the greater the shrinkage caused by annealing. That is, the more times the annealing is performed, the greater the shift of residual stress from negative compression to positive tension.

[0131] Adjust the heater output so that the temperature of wafer 200 is above and 1200°C of the temperature of wafer 200 in film deposition process S2. o Below C, 900 is more preferred. o C or above and 1100 o Temperatures below C.

[0132] In the annealing process S3 of this example, the absolute value of the residual stress in the polysilicon layer 31 formed in the film formation process S2, which is performed by appropriately selecting the number of steps B, can be less than that before annealing, for example, becoming about 100 MPa or less. This reduces the stress applied to the drift layer 12, which serves as the substrate, and decreases the risk of stress-induced crystallization defects. Furthermore, it reduces the stress gradient in the polysilicon layer 31, minimizing substrate warping and facilitating subsequent photolithography. On the other hand, if the absolute value of the residual stress exceeds 100 MPa, these risks increase.

[0133] Figure 8 This graph compares the relationship between the number of times the growth inhibition gas is supplied and the residual stress in the film when forming a 1 μm thick polycrystalline silicon multilayer film on a wafer using the aforementioned substrate processing apparatus in the aforementioned ILIS process. It shows the case where no annealing process is performed afterward and the case where an annealing process is performed afterward. Figure 9 The horizontal axis represents the number of times the growth-impeding gas is supplied per 1 μm film thickness, and the vertical axis represents the residual stress in the multilayer film. Regarding the sign of residual stress, a negative sign indicates compressive stress, and a positive sign indicates tensile stress. The internal stress of the multilayer film is assessed using the substrate curvature method, which involves performing film deposition on both sides of the substrate, peeling off one side of the multilayer film, and measuring the substrate warpage. Furthermore, the supply counts of 1, 3, and 9 times refer to the presence of a growth-impeding layer for every 500 nm, 250 nm, and 100 nm increase in depth from the surface of the multilayer film, respectively.

[0134] Without an annealing process, the residual stress in the multilayer film is generally negative (compressive stress). Furthermore, it was confirmed that the more times the crystal growth-inhibiting gas is supplied, the stronger the compressive stress becomes.

[0135] In contrast, with the annealing process, the residual stress in the multilayer film shifts towards the stretching side compared to the case without annealing, and the absolute value decreases. Furthermore, it was confirmed that the more times the crystal growth inhibiting gas is supplied, the greater the shift of residual stress (compressive stress) towards the stretching direction, and the residual stress approaches zero. That is, it was confirmed that the absolute value of residual stress in the multilayer film on the wafer can be reduced by the number of supplying the crystal growth inhibiting gas. In other words, the correlation between residual stress and the number of inhibiting layers is reversed depending on the presence or absence of the annealing process.

[0136] Figure 9 This is a depth graph showing the impurity concentration during ion implantation, using a polysilicon layer with a barrier layer and a comparative polysilicon layer without a barrier layer, experimentally formed by a method according to one aspect of the present invention as masks. Each polysilicon layer is formed on a 20 nm SiO2 film on a Si substrate, according to 620... o C. A 2.0 μm film was formed by CVD at 25 Pa. Barrier layers were inserted every 200 nm. Both samples were implanted with Al at 1280 keV and analyzed by SIMS (Secondary Ion Mass Spectrometry). The samples with barrier layers showed that the Al concentration in the substrate was at background levels, effectively functioning as a mask. On the other hand, in the samples without barrier layers, the concentration curves, especially the shoulder peaks deeper than the peaks, became smoother, and a relatively high Al concentration was detected in the substrate.

[0137] According to this method, one or more of the effects shown below can be obtained.

[0138] (a) By using a uniform multilayer film with small grain size as the implantation mask, the channeling effect within the mask during ion implantation can be prevented. In addition, by improving the in-plane uniformity of the stop energy, the characteristic inhomogeneity of the fabricated device can be suppressed. As a result, thinner masks can be used, and manufacturing costs can be reduced.

[0139] (b) By using a multilayer film with a smaller surface roughness compared to the film thickness as an implantation mask, the effects of surface scattering during ion implantation can be reduced.

[0140] (c) When forming a multilayer film, the residual stress in the multilayer film can be controlled by controlling the number of times it is exposed to the crystal growth barrier gas. By appropriately combining annealing treatments, the collapse of the injection mask and the warping of the substrate can be prevented.

[0141] (d) In addition, since annealing is not inserted or the processing temperature is not changed during the formation of multilayer films, the processing time can be shortened, and the output of the longitudinal processing unit can be increased in particular.

[0142] (4) Variations

[0143] Step B in this method can be modified as shown in the following variation. Unless otherwise specified, the processing steps and conditions in each step of each variation can be the same as the processing steps and conditions in each step of the above substrate processing sequence.

[0144] In this modified example, in step B above, a predetermined gas for forming a film or surface with a different film composition than the polycrystalline film in step A is used instead of the crystal growth-inhibiting gas. That is, the substrate processing apparatus described above is equipped with a predetermined gas supply system that exposes the wafer 200 in the processing chamber 201 to the predetermined gas for forming a film with a different film composition than the polycrystalline film, and performs the processing sequence shown below.

[0145] (raw material gas → predetermined gas) × n

[0146] The predetermined gas is, for example, a gas containing elements of Group 14. That is, the constituent elements of the polycrystalline film in step A and the constituent elements of the film with a different film material in step B can be substantially the same. For example, the film formed by step B can be a film whose composition is substantially the same but whose crystallinity differs from the initial film formed in step A.

[0147] Specifically, for example, in step B, a Si raw material gas other than the aforementioned SiH4 gas, such as silane (Si2H6) gas or chlorosilane gas, can be supplied. In step A, an amorphous silicon film, which is a film of a different material than the polycrystalline film, is formed on the surface of the polycrystalline film formed on the wafer 200. By using a raw material gas different from the raw material gas in step A, the crystallinity can be different without changing the temperature.

[0148] In this modified example, the same effect as described above is also achieved. Furthermore, in this modified example, a gas containing the same elements as the raw material gas in step A is used in step B, thus ensuring that the multilayer film does not contain elements different from those contained in the raw material gas.

[0149] Alternatively, these steps can be performed in parallel without distinguishing them as in steps A and B. In this case, during deposition, a predetermined gas, different from the raw material gas, is supplied along with the raw material gas in a manner that keeps the grain size (cross-sectional area on the plane parallel to the substrate) constant and / or the alignment equal, i.e., the crystallinity fixed. At this time, the partial pressure of the raw material gas, the partial pressure of the predetermined gas exposed along with the raw material gas, or the temperature of the wafer 200 are changed. In this case, the gradient of the residual stress of the polycrystalline film can be maintained within a predetermined range, and the polycrystalline film can be processed into a cantilever while maintaining the stress gradient within the predetermined range. Here, the predetermined gas exposed along with the raw material gas can be, for example, an inert gas such as N2 gas, Ar gas, or H2 gas.

[0150] <Other aspects of the invention>

[0151] The present invention has been specifically described above. However, the present invention is not limited to the above-described manner, and various modifications can be made without departing from its spirit.

[0152] For example, the present invention is not limited to forming a superjunction structure by a single ion implantation, and can also be combined with conventional multi-segment epitaxial methods. For example, a portion of a conventional multilayer epitaxial layer can be formed through the processes S1 to S7 of the present invention. In this case, the effect of reducing the number of processes compared to the past is also achieved.

[0153] Furthermore, for example, the initial film formed in step A of S2 is not limited to a polycrystalline film, but can also be an amorphous film or a monocrystalline film. Additionally, the film formed in step B can be arbitrarily selected from polycrystalline films, amorphous films, etc., that have a different crystallinity than those in step A. When the initial film is an amorphous film, the laminated film easily passes 600... o Annealing polycrystalline at temperatures above C allows step B to facilitate nucleation, grain boundary formation, and grain size control. Furthermore, the film formed in step B only needs to differ from the surface state of the film formed in step A at least in one atomic layer on its surface; it does not necessarily have to be a continuous film. That is, step B is not limited to depositing a new film on top of the initial film deposited in step A; it can also reconstruct the surface of the initial film, allow specific molecules to be (sparsely) adsorbed onto a small portion of the surface, modify it through chemical reactions, break atomic bonds, or excite it. This method achieves the same effects as the methods described above.

[0154] In addition, the starting substrate 11 is not limited to SiC, and can be made of materials such as Si, GaN, Ga2O3, and ZnO.

[0155] Furthermore, the process formula is not limited to newly manufactured cases; for example, it can also be prepared by changing an existing formula already installed in the substrate processing apparatus. In the case of a formula change, the modified formula can be installed in the substrate processing apparatus via an electrical communication line and a storage medium containing the formula. Alternatively, an existing formula already installed in the substrate processing apparatus can be directly changed by operating the input / output device 122 of the existing substrate processing apparatus.

[0156] Furthermore, the above-described method exemplifies the formation of a film using a batch substrate processing apparatus that processes multiple substrates at a time. The present invention is not limited to the above-described method; for example, it can also be preferably applied to the formation of a film using a single-sheet substrate processing apparatus that processes one or more substrates at a time. Additionally, the above-described method exemplifies the formation of a film using a substrate processing apparatus equipped with a hot-wall type furnace. The present invention is not limited to the above-described method; it can also be preferably applied to the formation of a film using a substrate processing apparatus equipped with a cold-wall type furnace.

[0157] When using these substrate processing devices, each process can be performed using the same processing steps and conditions as described above, and the same effect as described above can be obtained.

[0158] Furthermore, the various methods and variations described above can be used in appropriate combinations. In such cases, the processing steps and conditions can be the same as those described in the methods and variations.

[0159] The full disclosure of Japanese Patent Application No. 2024-038963, filed on March 13, 2024, is incorporated herein by reference.

[0160] All documents, patent applications and technical specifications described herein are incorporated herein by reference to the extent that each document, patent application and technical specification is specifically and separately described by reference.

Claims

1. A substrate processing method, characterized in that, have: (a) A process for preparing a substrate, comprising forming a multilayer film of a predetermined thickness with controlled grain size on the substrate by performing a predetermined number of cycles, and patterning the multilayer film, the cycles including a process of exposing the substrate to a raw material gas to deposit a first film, and a process of exposing the substrate to a crystal growth inhibiting gas or a predetermined gas for forming a second film with a different film composition than the first film; and (b) The process of using the patterned multilayer film as a hard mask for ion implantation.

2. The substrate processing method according to claim 1, characterized in that, The predetermined number of times is set such that the average particle size of the crystals of the multilayer film is below a predetermined value.

3. The substrate processing method according to claim 1, characterized in that, The predetermined number of times is set such that the absolute value or gradient of the residual stress of the multilayer film in the state where the multilayer film is exposed on the surface of the substrate is below a predetermined value.

4. The substrate processing method according to claim 1, characterized in that, It also has: (c) The annealing process of the multilayer film prior to (b).

5. The substrate processing method according to claim 1, characterized in that, The first film is a polycrystalline film with silicon and / or germanium as the main constituent elements. The two first membrane grains separated by the exposed process are independent.

6. The substrate processing method according to claim 1, characterized in that, The plurality of first membranes formed according to the predetermined number of times have substantially equal average particle sizes.

7. The substrate processing method according to claim 1, characterized in that, The first film is a polycrystalline or amorphous film with an average particle size of less than 0.2 μm.

8. The substrate processing method according to claim 1, characterized in that, The substrate is a SiC substrate.

9. The substrate processing method according to claim 1, characterized in that, The first film is a polycrystalline or amorphous film with an average particle size of less than 0.2 μm.

10. The substrate processing method according to claim 1, characterized in that, The predetermined thickness is 1 μm to 20 μm, and is set such that the multilayer film has a blocking energy corresponding to the mask for ion implantation of 1 MeV to 20 MeV.

11. The substrate processing method according to claim 1, characterized in that, The absolute value of the residual stress in the multilayer film is less than 100 MPa.

12. The substrate processing method according to claim 1, characterized in that, The surface roughness Ra of the multilayer film is below 15 nm.

13. The substrate processing method according to claim 1, characterized in that, The substrate prepared in (a) has a buffer layer beneath the multilayer film.

14. The substrate processing method according to claim 1, characterized in that, It also has: (d) The process of removing the multilayer film after (b); and (e) An annealing process performed on the substrate after (d) to activate the impurities injected in (c).

15. The substrate processing method according to claim 1, characterized in that, In step (b), the conductivity is reversed by ion implantation, forming a trap with a depth of more than 3 μm in the SiC film.

16. A method for manufacturing a semiconductor device, characterized in that, have: (a) A process for preparing a substrate, comprising forming a multilayer film of a predetermined thickness with controlled grain size on the substrate by performing a predetermined number of cycles, and patterning the multilayer film, the cycles including a process of exposing the substrate to a raw material gas to deposit a first film, and a process of exposing the substrate to a crystal growth inhibiting gas or a predetermined gas for forming a second film with a different film composition than the first film; and (b) The process of using the patterned multilayer film as a hard mask for ion implantation.

17. A hard mask for ion implantation, characterized in that, A multilayer film of a predetermined thickness with controlled grain size formed by performing a predetermined number of cycles is used as a hard mask for ion implantation. The cycle includes a step of depositing a first film by exposing the substrate to a feed gas, and a step of exposing the substrate to a predetermined gas that inhibits crystal growth or forms a second film with a different film composition than the first film.

18. A method for forming a hard mask for ion implantation, characterized in that, have: The process of forming a multilayer film with a thickness of 1 μm to 20 μm on a substrate by performing a predetermined number of cycles includes (a) a process of depositing a polycrystalline or amorphous first film by exposing a SiC or GaN substrate to a raw material gas, and (b) a process of exposing the substrate to a crystal growth inhibiting gas or a predetermined gas for forming a second film with a different film composition than the first film. The two first film grains separated by process (b) are independent.

19. A substrate processing apparatus, characterized in that, have: Processing room; and The control unit is configured to perform the following control: forming a multilayer film with a thickness of 1 μm to 20 μm on a substrate as a hard mask for ion implantation by performing a predetermined number of cycles. The cycle includes (a) a step of depositing a polycrystalline or amorphous first film by exposing a SiC or GaN substrate to a raw material gas in the processing chamber, and (b) a step of exposing the substrate to a predetermined gas that inhibits crystal growth or forms a second film with a different film composition than the first film. The two first film grains separated by process (b) are independent.

20. A program, characterized in that, The substrate processing apparatus is operated by a computer to perform the following steps: within the processing chamber of the substrate processing apparatus, a multilayer film with a thickness of 1 μm to 20 μm is formed on a substrate as a hard mask for ion implantation by performing a predetermined number of cycles. The cycles include (a) depositing a polycrystalline or amorphous first film by exposing a SiC or GaN substrate to a raw material gas within the processing chamber, and (b) exposing the substrate to a predetermined gas that inhibits crystal growth or forms a second film with a different material composition than the first film. The two grains of the first film separated by step (b) are independent.

Images