Low-cost silicon-based heterogeneous integrated lithium niobate and preparation method thereof

Abstract

The invention discloses low-cost silicon-based heterogeneous integrated lithium niobate and a preparation method thereof, a plurality of prefabricated deep holes are formed in certain positions of an oxide layer and a waveguide device module of an initial silicon photonic wafer, the deep holes extend to the lower surface of the oxide layer, a multi-layer metal module is arranged above the initial silicon photonic wafer, and the deep holes extend to the lower surface of the oxide layer. The lower surface of the oxide layer is provided with a lithium niobate module, the lithium niobate module comprises a lithium niobate waveguide layer, a second oxide layer and a radio frequency electrode layer, the second oxide layer near the deep hole is provided with an etching groove, the depth-to-width ratio of the etching groove is smaller than a set threshold value, the radio frequency electrode layer is deposited on the surface of the etching groove, and the radio frequency electrode layer is electrically connected with the deep hole. And the radio frequency electrode layer extends to the surface of the second oxide layer outside the etching groove, so that the radio frequency electrode layer is positioned below the lithium niobate waveguide layer. After the lithium niobate layer is prepared, a metal through hole process in a CMOS (Complementary Metal Oxide Semiconductor) process does not need to be used, and meanwhile, electrical intercommunication of each layer of metal in the chip is ensured, so that the production cost is greatly reduced.

Description

Technical Field

[0001] This invention belongs to the field of silicon-based optoelectronic heterogeneous integration technology. This invention relates to a low-cost silicon-based heterogeneous integrated lithium niobate and its preparation method. Background Technology

[0002] In recent years, silicon photonics chips, with their CMOS-compatible manufacturing processes, have gradually gained favor among mainstream internet companies both domestically and internationally in 800G and 1.6T data communication optical module scenarios. With the continued rise in the popularity of the AI ​​industry, internet companies' demands for computing power are also constantly increasing, and the need for 3.2T and even 6.4T optical modules is gradually emerging. Thin-film lithium niobate modulators, with their ultra-high electro-optic bandwidth characteristics, have become one of the mainstream technical solutions. How to combine the CMOS-compatible manufacturing process of silicon photonics chips with the ultra-high electro-optic bandwidth characteristics of thin-film lithium niobate will be a key challenge in silicon-based heterogeneous integration process fabrication.

[0003] Traditional silicon photonics technology platforms have been developed and accumulated in the industry over many years, forming a complete process flow. High-performance passive optical waveguide devices can be fabricated using heterogeneous silicon nitride, and high-speed, high-intensity photodetectors exceeding 70 GHz can be fabricated using heterogeneous germanium. To realize high-speed, high-performance modulators on silicon photonics platforms, researchers have begun to focus on the process implementation of heterogeneous integrated thin-film lithium niobate.

[0004] Publication number CN116841060A discloses an optical chip, optical module, and communication device, describing a silicon-based heterogeneous integrated thin-film lithium niobate architecture. From bottom to top, the substrate consists of a silicon layer, a silicon nitride layer, a lithium niobate layer, and a metal layer. Because lithium in lithium niobate can contaminate CMOS process lines, it is a CMOS-incompatible material. Furthermore, the metal layer above the lithium niobate layer needs to form an electrical connection with the bottom silicon layer to fabricate a detector, requiring the use of through-hole (TH) technology from CMOS processes. This necessitates the establishment of dedicated lines for fabricating the TH process after the lithium niobate layer, resulting in very high production costs.

[0005] Publication number CN116974097A discloses a lithium niobate modulator and its fabrication method. The substrate consists of a metal layer, a silicon layer, a lithium niobate layer, and a radio frequency (RF) electrode layer, arranged from bottom to top. By flipping the initial silicon photonic wafer, the metal vias required for the silicon photonic device are located below the silicon layer and can be fabricated using CMOS technology on the initial photonic wafer. The RF electrodes of the lithium niobate modulator are located above the lithium niobate layer, separated from the silicon device's metal layer, eliminating the need for CMOS metal via technology. However, the silicon device's metal layer and the lithium niobate RF electrode layer cannot achieve electrical connectivity, hindering complex co-design. Furthermore, the two metal layers are not on the same plane, requiring wire bonding for connection to external circuit boards, rather than more advanced flip-chip bonding. If the silicon device's metal layer and the lithium niobate RF electrode layer need to be placed on the same plane, or if electrical connectivity between them is required, a metal via process from CMOS technology must be used again after the lithium niobate layer is fabricated, resulting in very high production costs. Summary of the Invention

[0006] The purpose of this invention is to provide a low-cost silicon-based heterogeneous integrated lithium niobate and its preparation method. After the lithium niobate layer is prepared, there is no need to use the metal via process in CMOS technology, and at the same time, the electrical interconnection of metal layers in the chip is ensured, which greatly reduces the production cost.

[0007] The technical solution to achieve the purpose of this invention is as follows: A low-cost silicon-based heterogeneous integrated lithium niobate includes an initial silicon photonic wafer. From top to bottom, the initial silicon photonic wafer has a waveguide device module and an oxide layer sequentially disposed. Multiple pre-fabricated deep holes are disposed at certain positions on the oxide layer and the waveguide device module. The deep holes extend to the lower surface of the oxide layer and are filled with metal. A multilayer metal module is disposed above the initial silicon photonic wafer and is electrically connected to the deep holes. A lithium niobate module is disposed on the lower surface of the oxide layer. The lithium niobate module includes a lithium niobate waveguide layer, a second oxide layer, and a radio frequency (RF) electrode layer. An etching trench is disposed on the second oxide layer near the deep holes. The aspect ratio of the etching trench is less than a set threshold. An RF electrode layer is deposited on the surface of the etching trench and is electrically connected to the deep holes. The RF electrode layer extends to the surface of the second oxide layer outside the etching trench, such that the RF electrode layer is located below the lithium niobate waveguide layer.

[0008] In a preferred embodiment, the thickness of the second oxide layer between the lithium niobate waveguide layer and the radio frequency electrode layer is less than the thickness of the radio frequency electrode layer, and the thickness of the radio frequency electrode layer is greater than the depth of the etching trench.

[0009] In a preferred embodiment, the lithium niobate waveguide layer is located below the silicon device layer of the waveguide device module, the radio frequency electrode layer is located below the lithium niobate waveguide layer, the radio frequency electrode layer is provided with traveling wave electrodes, and other positions of the radio frequency electrode layer are provided with wire bonding pads, which are used as electrical interfaces for connecting the chip to external circuits.

[0010] In the preferred technical solution, the etching groove is obtained by using fluorine-based gas and inductively coupled plasma etching.

[0011] In a preferred embodiment, the waveguide device module includes a silicon device layer, a silicon nitride device layer disposed above the silicon device layer, a silicon-germanium device layer disposed above the silicon device layer and in contact with the silicon layer, and a silicon contact hole disposed above the silicon device layer. The silicon contact hole is made of metal and is in contact with the silicon-germanium device layer for leading out detector electrodes.

[0012] In a preferred embodiment, the multilayer metal module includes a first metal layer, a thermoelectric electrode layer, a second metal layer, and inter-metal vias. The first metal layer, the second metal layer, and the thermoelectric electrode layer are all connected to the inter-metal vias and are electrically connected to each other. The first metal layer is electrically connected to silicon contact holes and deep holes.

[0013] This invention also discloses a low-cost method for preparing silicon-based heterostructured lithium niobate, comprising the following steps: S01: Fabrication of an initial silicon photonic wafer, wherein the initial silicon photonic wafer comprises, from top to bottom, a waveguide device module, an oxide layer and an initial substrate; S02: Based on CMOS technology, multiple deep holes are fabricated at certain locations on an initial silicon photonic wafer. The deep holes extend to the lower surface of the oxide layer and are filled with metal. S03: A multilayer metal module is fabricated on top of an initial silicon photonic wafer using CMOS technology, and the multilayer metal module is electrically connected to a deep hole; S04: The upper surface of the multilayer metal module is planarized to form a first bonding interface. A first substrate is bonded to the first bonding interface. Then, the initial substrate of the initial silicon photonic wafer is removed until the deep hole is exposed. The deep hole is then ground to form a second bonding interface. The deep hole is in contact with the second bonding interface. S05: A lithium niobate module is bonded on the second bonding interface, the lithium niobate module comprising a lithium niobate waveguide layer, a second oxide layer and a radio frequency electrode layer; S06: Etch the second oxide layer near the deep hole until it is exposed outside the deep hole to form an etching trench. The aspect ratio of the etching trench is less than a set threshold. Deposit a radio frequency electrode layer on the surface of the etching trench. The radio frequency electrode layer is electrically connected to the deep hole. The radio frequency electrode layer extends to the surface of the second oxide layer outside the etching trench, so that the radio frequency electrode layer is located below the lithium niobate waveguide layer.

[0014] In the preferred embodiment, step S06, etching the second oxide layer near the deep hole until it is exposed outside the deep hole to form an etching trench, includes: A second oxide layer is etched near a deep hole using inductively coupled plasma etching with fluorine-based gas until it is exposed outside the hole. The etching process conditions include an etching chamber pressure of 5-100 mTorr, a wafer substrate temperature of 0-30°C, an upper electrode substrate power of 500-1200 W, and a lower electrode substrate power of 100-500 W.

[0015] In the preferred embodiment, step S06, depositing an RF electrode layer on the surface of the etching trench, includes: The radio frequency electrode layer is constructed using metal physical vapor deposition (MPV). The MPV process conditions include a vacuum level of less than 8 x 10⁻⁶. -5 Pa, temperature 20-200°, electron gun power 5%-40%, deposition rate 0.1~10nm / s, so that the thickness of the RF electrode layer is greater than the depth of the etching trench.

[0016] In the preferred embodiment, step S05, after bonding the lithium niobate module to the second bonding interface, includes: A lithium niobate chip or wafer is bonded at the second bonding interface. The substrate and oxide layer of the lithium niobate chip or wafer are removed until the lithium niobate waveguide layer is exposed. A lithium niobate ridge waveguide is prepared by two etching processes. An oxide layer with a thickness of 500 nm to 1.5 μm is deposited to isolate the lithium niobate waveguide layer and the radio frequency electrode layer, and a traveling wave electrode is fabricated on the radio frequency electrode layer.

[0017] Compared with the prior art, the significant advantages of this invention are: (1) In this invention, deep holes are fabricated on the silicon photonic wafer in the front-end of the lithium niobate module fabrication process. These holes only need to penetrate the waveguide device module and the oxide layer below it. The deep holes are filled with metal material to achieve electrical connection between the silicon photonic device and the back-end lithium niobate RF electrode layer. This allows for complex co-design of front and back devices and brings the electrode layers of the front and back devices to the same plane, supporting flip-chip bonding between the chip and external components. After leaving the CMOS process line, the fabrication of the lithium niobate module avoids the use of metal via technology, greatly reducing the cost of subsequent non-CMOS process manufacturing.

[0018] (2) The standard CMOS process already has a mature through-silicon via (TSV) technology, which is used to realize the circuit connection between the front-side devices and the back-side circuits of the wafer. This via needs to penetrate a silicon substrate of about 100 μm thickness, and the depth-to-width ratio of the via is about 10:1. The process is very difficult and the manufacturing cost is high. The deep via in this invention does not need to penetrate the substrate material, but only needs to penetrate the waveguide device layer and the oxide layer below it of about 3 μm in the silicon photonic wafer. The depth-to-width ratio of the via is less than 4:1, which greatly reduces the process difficulty and reduces the manufacturing cost of silicon photonic wafer CMOS process. Attached Figure Description

[0019] Figure 1 This is a flowchart of the low-cost silicon-based heterointegrated lithium niobate preparation method of this embodiment; Figure 2 This is a cross-sectional view of the initial silicon photonic wafer used to fabricate waveguide device modules; Figure 3 This is a cross-sectional view of the initial silicon photonic wafer fabrication of deep holes; Figure 4 This is a cross-sectional view of the initial silicon photonic wafer fabrication of a multilayer metal module; Figure 5 This is a cross-sectional view of the initial silicon photonic wafer bonded to the first substrate wafer and the initial substrate removed; Figure 6 This is a cross-sectional view of the preparation of the lithium niobate module and the wire bonding pads; Figure 7 This is a cross-sectional view of the preparation of the lithium niobate module and the flip-chip soldered copper pillar; Figure 8 This is a cross-sectional view of the process for fabricating lithium niobate waveguide layers; Figure 9 This is a cross-sectional view of the process for fabricating the radio frequency electrode layer of a lithium niobate module. Detailed Implementation

[0020] The principle of this invention is to propose a novel silicon-based heterogeneous integrated thin-film lithium niobate and its processing method. After the lithium niobate layer is prepared, there is no need to use the metal via process in CMOS, while ensuring the electrical interconnection of metal layers in the chip. This solution can make the most of the existing CMOS process line to prepare silicon-based heterogeneous integrated lithium niobate chips, greatly reducing production costs.

[0021] Example 1: like Figure 6 , 8As shown in Figure 9, a low-cost silicon-based heterogeneous integrated lithium niobate includes an initial silicon photonic wafer. From top to bottom, a waveguide device module 3 and an oxide layer 2 are sequentially disposed on the initial silicon photonic wafer. Multiple pre-fabricated deep holes 4 are disposed at certain positions on the oxide layer 2 and the waveguide device module 3, extending to the lower surface of the oxide layer 2. The deep holes 4 are filled with metal. A multilayer metal module 5 is disposed above the initial silicon photonic wafer, electrically connected to the deep holes 4. Niobium is disposed on the lower surface of the oxide layer 2. The lithium niobate module 7 includes a lithium niobate waveguide layer 71, a second oxide layer 70, and a radio frequency electrode layer 72. The second oxide layer 70 near the deep hole 4 is provided with an etching trench 77. The aspect ratio of the etching trench 77 is less than a set threshold. The radio frequency electrode layer 72 is deposited on the surface of the etching trench 77. The radio frequency electrode layer 72 is electrically connected to the deep hole 4. The radio frequency electrode layer 72 extends to the surface of the second oxide layer 70 outside the etching trench 77, so that the radio frequency electrode layer 72 is located below the lithium niobate waveguide layer 71.

[0022] The radio frequency electrode layer 72 serves as both the traveling wave electrode of the lithium niobate modulator and the metal wiring layer, responsible for forming an electrical connection with the deep via 4, thereby enabling the redistribution (RDL) of the multilayer metal module 5 on the front side of the wafer to the lithium niobate module 7 on the back side of the wafer.

[0023] In a preferred embodiment, the aspect ratio of the deep via is less than 4:1, which is another major factor contributing to the low cost. Compared to the TSV process, the difficulty and cost are significantly reduced. Within the CMOS process, the smaller the aspect ratio of the via, the lower the cost. Outside the CMOS process, avoiding the use of metal vias further reduces costs.

[0024] In a preferred embodiment, the aspect ratio of the etching groove 77 is less than 1:10, and the metal connection between the inside and outside of the etching groove does not require the use of a metal through-hole process.

[0025] In a preferred embodiment, the thickness of the second oxide layer 70 between the lithium niobate waveguide layer 71 and the RF electrode layer 72 is less than the thickness of the RF electrode layer 72. That is, the thickness of the RF electrode layer 72 is greater than the depth of the etching trench 77. This ensures metallic connectivity of the RF electrode layer 72 inside and outside the etching trench.

[0026] In a preferred embodiment, the etched groove 77 is obtained by using a fluorine-based gas and an inductively coupled plasma etching method.

[0027] In a preferred embodiment, the waveguide device module 3 includes a silicon device layer 31, a silicon nitride device layer 33 disposed above the silicon device layer 31, a silicon germanium device layer 32 disposed above the silicon device layer 31 and in contact with the silicon device layer 31, and a silicon contact hole 34 disposed above the silicon device layer 31. The silicon contact hole 34 is metal and in contact with the silicon germanium device layer 32 for leading out detector electrodes.

[0028] In a preferred embodiment, the multilayer metal module 5 includes a first metal layer 51, a thermoelectric layer 52, a second metal layer 53, and an inter-metal via 54. The first metal layer 51, the second metal layer 53, and the thermoelectric layer 52 are all connected to the inter-metal via 54 and are electrically connected to each other. The first metal layer 51 is electrically connected to the silicon contact hole 34 and the deep hole 4.

[0029] In a preferred embodiment, the lithium niobate waveguide layer 71 is located below the silicon device layer 31 of the waveguide device module 3, and the radio frequency electrode layer 72 is located below the lithium niobate waveguide layer 71. The radio frequency electrode layer 72 is provided with traveling wave electrodes, and wire bonding pads are provided at other positions of the radio frequency electrode layer 72. The wire bonding pads are used as electrical interfaces for connecting the chip to external circuits.

[0030] Another embodiment, such as Figure 1 As shown, a low-cost method for preparing silicon-based heterostructured lithium niobate includes the following steps: S01: Fabrication of an initial silicon photonic wafer, which, from top to bottom, comprises a waveguide device module, an oxide layer, and an initial substrate; S02: Based on CMOS technology, multiple deep holes are fabricated at certain locations on the initial silicon photonic wafer. The deep holes extend to the lower surface of the oxide layer and are filled with metal. S03: A multilayer metal module is fabricated on top of an initial silicon photonic wafer using CMOS technology, and the multilayer metal module is electrically connected to a deep hole; S04: The upper surface of the multilayer metal module is planarized to form a first bonding interface. A first substrate is bonded to the first bonding interface. Then, the initial substrate of the initial silicon photonic wafer is removed until the deep hole is exposed. The deep hole is then ground to form a second bonding interface. The deep hole is in contact with the second bonding interface. S05: A lithium niobate module is bonded on the second bonding interface. The lithium niobate module includes a lithium niobate waveguide layer, a second oxide layer, and a radio frequency electrode layer. S06: Etch the second oxide layer near the deep hole until it is exposed outside the deep hole to form an etching trench. The aspect ratio of the etching trench is less than a set threshold. Deposit an RF electrode layer on the surface of the etching trench. The RF electrode layer is electrically connected to the deep hole. The RF electrode layer extends to the surface of the second oxide layer outside the etching trench, so that the RF electrode layer is located below the lithium niobate waveguide layer.

[0031] By bringing out the device electrodes from the initial silicon photonic wafer and placing them at the same plane height as the lithium niobate RF electrode, a copper pillar for flip-chip bonding can be fabricated above the lithium niobate RF electrode layer.

[0032] In a preferred embodiment, the complete steps of a low-cost method for preparing silicon-based heterointegrated lithium niobate include: S1, a waveguide device module fabricated from silicon photonic wafers using CMOS technology, comprising a silicon device layer, a silicon nitride device layer, a silicon-germanium device layer, and silicon contact holes; S2, Deep holes fabricated using CMOS technology; S3, a multilayer metal module fabricated using CMOS technology; S4, the surface of the multi-layer metal module is flattened to form the first bonding interface; S5, the first substrate wafer and the initial silicon photonic wafer are permanently bonded at the first bonding interface; S6, remove the initial substrate until the deep hole is exposed, and finely grind to form the second bonding interface; S7, bonding lithium niobate chips or wafers at the second bonding interface; S8, the lithium niobate chip or wafer removes the substrate and oxide layer to expose the lithium niobate layer; S9, etch the lithium niobate layer to fabricate a ridge-shaped lithium niobate waveguide; S10, deposited oxide coating lithium niobate layer; S11, Etch oxide near deep hole until it is exposed outside the deep hole; S12, fabricate the radio frequency electrode layer to completely cover the deep hole; S13, deposit cladding material and etch to form electrode pads; S14, prepare flip-chip solder copper pillars above electrode pads.

[0033] Figure 2 The diagram shows a cross-sectional view of the initial silicon photonic wafer used to fabricate a waveguide device module, which was completed using a standard CMOS process. Specifically, it includes an initial substrate 1, an oxide layer 2, and a waveguide device module 3.

[0034] The initial substrate 1 is typically made of silicon, with a thickness of 1µm-1mm. The oxide layer 2, made of silicon oxide, is located above the initial substrate 1 and typically has a thickness of 100nm-5µm. The waveguide device module 3 is located above the oxide layer 2 and typically includes a silicon device layer 31, a silicon nitride device layer 33, a silicon-germanium device layer 32, and silicon contact holes 34. The silicon device layer 31 typically has a thickness of 100nm-500nm. Through mature processes such as etching and ion implantation, various optoelectronic devices can be fabricated, such as grating couplers, MMIs, resistors, tunable attenuators, polarization beam combiners / splitters, etc. The silicon nitride device layer 33 is located above the silicon device layer 31, with a thickness of 100nm-800nm. The gap between the silicon device layer 33 and the silicon device layer 31 is typically 10nm-1µm. Through etching, various high-performance passive optical devices can be fabricated. The silicon-germanium device layer 32 is located above and in contact with the silicon device layer 31, with a thickness of 100nm-800nm. It can be fabricated using selective epitaxial growth technology. Combined with the silicon device layer 31 and processes such as ion implantation, it can realize a high-performance photodetector. The silicon contact hole 34 is made of a metallic material, usually tungsten, and is in contact with the silicon-germanium device layer 32 to bring out the detector electrode.

[0035] Figure 3 The diagram shows a cross-sectional view of the deep-hole module fabricated on the initial silicon photonic wafer. Deep hole 4 is fabricated using standard CMOS processes, which can be manufactured using a damascus process or a similar TSV process, including etching the deep hole, depositing an electrical isolation layer on the sidewalls, and filling the deep hole with metal. The standard CMOS process already has a mature TSV process for achieving circuit connectivity between devices on the front and back sides of the wafer. This via needs to penetrate approximately 100µm of silicon substrate, with an aspect ratio of approximately 10:1, making the process very challenging. In this embodiment, deep hole 4 only needs to penetrate the waveguide device module 3 and the oxide layer 2, but not the initial substrate 1. The aspect ratio of deep hole 4 is less than 4:1, significantly reducing the process difficulty.

[0036] Figure 4 The diagram shows a cross-sectional view of the initial silicon photonic wafer fabrication of a multilayer metal module. The multilayer metal module 5 is fabricated using standard CMOS technology and includes a first metal layer 51, a thermoelectric layer 52, a second metal layer 53, and interlayer vias 54. The first metal layer 51, the second metal layer 53, and the interlayer vias 54 are typically made of metals such as Al and Cu, with a thickness typically ranging from 500 nm to 3000 nm. The thermoelectric layer 52 is typically made of metals such as TiN and TaN, with a thickness typically ranging from 50 nm to 300 nm. The first metal layer 51, the second metal layer 53, and the thermoelectric layer 52 are all connected to the interlayer vias 54 and are electrically interconnected. The first metal layer 51 is electrically connected to the silicon contact hole 34 and the deep hole 4.

[0037] Figure 5The diagram shows a cross-sectional view of the initial silicon photonic wafer bonded to the first substrate wafer and then the initial substrate removed. The upper surface of the multilayer metal module 5 is planarized to form the first bonding interface 100. The first substrate 6 is permanently bonded to the initial silicon photonic wafer through the first bonding interface 100. Then, the initial substrate 1 is removed through mechanical grinding and etching until the deep hole 4 is exposed. Fine surface grinding is then performed to form the second bonding interface 200, which is in contact with the deep hole 4. The gap between the second bonding interface 200 and the silicon device layer 31 is typically 10nm-500nm. The first substrate 6 is made of a material with a low dielectric constant, such as quartz.

[0038] Figure 6 The diagram shows a cross-sectional view of the lithium niobate module and wire bonding pads. The lithium niobate module 7 can be fabricated using a low-cost process and includes a lithium niobate waveguide layer 71, an RF electrode layer 72, and wire bonding pads 73. The lithium niobate waveguide layer 71 is located below the silicon device layer 31, and its thickness is typically 200nm-1000nm. The RF electrode layer 72 is located below the lithium niobate waveguide layer 71 and is typically made of gold, but other suitable metals such as copper and aluminum can also be used. Its thickness is typically 600nm-3µm. The RF electrode layer 72 is electrically connected to the deep via 4, eliminating the need for metal vias and significantly reducing process complexity. By etching the oxide 70 surrounding the RF electrode layer 72, grooves 73 are etched to form wire bonding pads, which serve as the electrical interface for connecting the chip to external circuitry.

[0039] Figure 7 The diagram shows a cross-sectional view of the lithium niobate module and flip-chip bonded copper pillars. The lithium niobate module 7 can be fabricated using a low-cost process and includes a lithium niobate waveguide layer 71, an RF electrode layer 72, and flip-chip bonded copper pillars 74. The flip-chip bonded copper pillars 74 are typically fabricated on the RF electrode layer 72 using an electroplating process. Materials include Ni / Cr / Ti / Cu / Sn / Ag, with diameters ranging from 10µm to 100µm and gaps greater than 20µm.

[0040] Figure 8 This is a cross-sectional view of the fabrication process of the lithium niobate module waveguide layer. The lithium niobate chip or wafer is bonded at the second bonding interface 200 via die-to-wafer bonding or wafer-to-wafer bonding. The substrate and oxide layer of the lithium niobate chip or wafer are removed until the lithium niobate waveguide layer 71 is exposed. A lithium niobate ridge waveguide is fabricated through two etching processes. An oxide layer with a thickness of 500 nm to 1.5 μm is deposited to isolate the lithium niobate waveguide layer 71 and the RF electrode layer 72, reducing the metal absorption loss of the lithium niobate waveguide. The oxide near the deep hole 4 is etched until the deep hole 4 is exposed.

[0041] The material of the lithium niobate waveguide layer 71 can also be replaced with other materials with efficient electro-optic effects, such as InP, LiTaO3, BaTiO3, etc.

[0042] The lithium niobate waveguide layer 71 can be bonded by direct bonding or adhesive bonding such as BCB. Direct bonding uses silicon dioxide as the bonding layer, with a thickness of 10-200 nm. In adhesive bonding methods such as BCB, the thickness of the BCB layer ranges from 40-400 nm.

[0043] Figure 9 This is a cross-sectional view of the fabrication process of the radio frequency (RF) electrode layer for the lithium niobate module. The RF electrode layer 72 is fabricated using processes such as lift-off or etching. It serves as both a traveling wave electrode for the lithium niobate modulator and a metal wiring layer, responsible for forming electrical connections with the deep via 4, thus enabling the redistribution (RDL) of the multilayer metal module 5 on the front side of the wafer to the lithium niobate module 7 on the back side. The metal physical vapor deposition process conditions for the RF electrode layer 72 include a vacuum level of less than 8 x 10⁻⁶. -5 At Pa, temperatures of 20-200 degrees Celsius, and electron gun power of 5%-40%, deposition rates of approximately 0.1-10 nm / s can be achieved.

[0044] Since the deep hole 4 is located above the lithium niobate waveguide layer 71, and the RF electrode layer 72 is located below the lithium niobate waveguide layer 71, a metal via process is typically required to achieve the electrical connection between the deep hole 4 and the RF electrode layer 72. To simplify the process and avoid complex metal via fabrication, an inductively coupled plasma etching method using fluorine-based (CHF3, CF4) gas can be used to etch the oxide near the deep hole 4 until the deep hole 4 is exposed. The RF electrode layer 72 is then fabricated based on this interface with etched grooves 77. The etching process conditions include an etching chamber pressure of 5-100 mTorr, a wafer substrate temperature of 0-30 degrees Celsius, an upper electrode substrate power of 500-1200 W, and a lower electrode substrate power of 100-500 W.

[0045] To ensure metallic connectivity between the RF electrode layer 72 inside and outside the etching trench 77, the aspect ratio of the etching trench 77 must be less than 1:10, and the thickness of the RF electrode layer 72 must exceed the depth of the etching trench 77. Furthermore, the thickness of the oxide 70 between the lithium niobate waveguide layer 71 and the RF electrode layer 72 is less than the thickness of the RF electrode layer 72, and the aspect ratio of the oxide etching trench near the deep hole is less than 1:10.

[0046] Etching trenches with an aspect ratio of less than 1:10 will sacrifice the effective device utilization area of ​​the lithium niobate module 7. However, considering that all the high-density devices of the wafer are concentrated in the waveguide device module 3 and the multilayer metal module 5 on the front side of the wafer, the lithium niobate module 7 on the back side of the wafer can simplify the process to the greatest extent, providing favorable conditions for the lithium niobate module 7 to be processed and fabricated outside the CMOS line.

[0047] In a preferred embodiment, the lithium niobate waveguide layer 71 has a thickness of 500 nm, the oxide isolation layer deposited between it and the radio frequency electrode layer 72 has a thickness of 900 nm, the oxide etching trench near the deep hole 4 has a depth of 900 nm and a width of 10 μm, and the radio frequency electrode layer 72 is made of Au material with a thickness of 1.35 μm.

[0048] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A low-cost silicon-based heterogeneous integrated lithium niobate, characterized in that, The system includes an initial silicon photonic wafer, on which a waveguide device module and an oxide layer are sequentially disposed from top to bottom. Multiple pre-fabricated deep holes are disposed at certain positions on the oxide layer and the waveguide device module, extending to the lower surface of the oxide layer. The deep holes are filled with metal. A multilayer metal module is disposed above the initial silicon photonic wafer and is electrically connected to the deep holes. A lithium niobate module is disposed on the lower surface of the oxide layer, comprising a lithium niobate waveguide layer, a second oxide layer, and a radio frequency (RF) electrode layer. An etching trench is disposed on the second oxide layer near the deep holes, with an aspect ratio less than a set threshold. An RF electrode layer is deposited on the surface of the etching trench and is electrically connected to the deep holes. The RF electrode layer extends to the surface of the second oxide layer outside the etching trench, such that the RF electrode layer is located below the lithium niobate waveguide layer.

2. The low-cost silicon-based heterogeneous integrated lithium niobate according to claim 1, characterized in that, The thickness of the second oxide layer between the lithium niobate waveguide layer and the radio frequency electrode layer is less than the thickness of the radio frequency electrode layer, and the thickness of the radio frequency electrode layer is greater than the depth of the etching trench.

3. The low-cost silicon-based heterogeneous integrated lithium niobate according to claim 1, characterized in that, The lithium niobate waveguide layer is located below the silicon device layer of the waveguide device module, and the radio frequency electrode layer is located below the lithium niobate waveguide layer. The radio frequency electrode layer is provided with traveling wave electrodes, and wire bonding pads are provided at other positions on the radio frequency electrode layer. The wire bonding pads are used as electrical interfaces for connecting the chip to external circuits.

4. The low-cost silicon-based heterogeneous integrated lithium niobate according to claim 1, characterized in that, The etching trench was obtained by using fluorine-based gas and inductively coupled plasma etching.

5. The low-cost silicon-based heterogeneous integrated lithium niobate according to claim 1, characterized in that, The waveguide device module includes a silicon device layer, a silicon nitride device layer on top of the silicon device layer, a silicon-germanium device layer on top of the silicon device layer and in contact with the silicon device layer, and a silicon contact hole on top of the silicon device layer. The silicon contact hole is metal and in contact with the silicon-germanium device layer for leading out detector electrodes.

6. The low-cost silicon-based heterogeneous integrated lithium niobate according to claim 5, characterized in that, The multilayer metal module includes a first metal layer, a thermoelectric electrode layer, a second metal layer, and inter-metal vias. The first metal layer, the second metal layer, and the thermoelectric electrode layer are all connected to the inter-metal vias and are electrically connected to each other. The first metal layer is electrically connected to silicon contact holes and deep holes.

7. A low-cost method for preparing silicon-based heterogeneous integrated lithium niobate, characterized in that, Includes the following steps: S01: Fabrication of an initial silicon photonic wafer, wherein the initial silicon photonic wafer comprises, from top to bottom, a waveguide device module, an oxide layer and an initial substrate; S02: Based on CMOS technology, multiple deep holes are fabricated at certain locations on an initial silicon photonic wafer. The deep holes extend to the lower surface of the oxide layer and are filled with metal. S03: A multilayer metal module is fabricated on top of an initial silicon photonic wafer using CMOS technology, and the multilayer metal module is electrically connected to a deep hole; S04: The upper surface of the multilayer metal module is planarized to form a first bonding interface. A first substrate is bonded to the first bonding interface. Then, the initial substrate of the initial silicon photonic wafer is removed until the deep hole is exposed. The deep hole is then ground to form a second bonding interface. The deep hole is in contact with the second bonding interface. S05: A lithium niobate module is bonded on the second bonding interface, the lithium niobate module comprising a lithium niobate waveguide layer, a second oxide layer and a radio frequency electrode layer; S06: Etch the second oxide layer near the deep hole until it is exposed outside the deep hole to form an etching trench. The aspect ratio of the etching trench is less than a set threshold. Deposit a radio frequency electrode layer on the surface of the etching trench. The radio frequency electrode layer is electrically connected to the deep hole. The radio frequency electrode layer extends to the surface of the second oxide layer outside the etching trench, so that the radio frequency electrode layer is located below the lithium niobate waveguide layer.

8. The method for preparing low-cost silicon-based heterogeneous integrated lithium niobate according to claim 7, characterized in that, Step S06, etching the second oxide layer near the deep hole until it is exposed outside the deep hole to form an etching trench, includes: A second oxide layer is etched near a deep hole using inductively coupled plasma etching with fluorine-based gas until it is exposed outside the hole. The etching process conditions include an etching chamber pressure of 5-100 mTorr, a wafer substrate temperature of 0-30°C, an upper electrode substrate power of 500-1200 W, and a lower electrode substrate power of 100-500 W.

9. The method for preparing low-cost silicon-based heterogeneous integrated lithium niobate according to claim 7, characterized in that, Step S06, depositing an RF electrode layer on the surface of the etching trench, includes: The radio frequency electrode layer is constructed using metal physical vapor deposition (MPV). The MPV process conditions include a vacuum level of less than 8 x 10⁻⁶. -5 Pa, temperature 20-200°, electron gun power 5%-40%, deposition rate 0.1~10nm / s, so that the thickness of the RF electrode layer is greater than the depth of the etching trench.

10. The method for preparing low-cost silicon-based heterogeneous integrated lithium niobate according to claim 7, characterized in that, Step S05, after bonding the lithium niobate module on the second bonding interface, includes: A lithium niobate chip or wafer is bonded at the second bonding interface. The substrate and oxide layer of the lithium niobate chip or wafer are removed until the lithium niobate waveguide layer is exposed. A lithium niobate ridge waveguide is prepared by two etching processes. An oxide layer with a thickness of 500 nm to 1.5 μm is deposited to isolate the lithium niobate waveguide layer and the radio frequency electrode layer, and a traveling wave electrode is fabricated on the radio frequency electrode layer.

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