Circuit for detecting plugging and unplugging of host by USB (Universal Serial Bus) 2.0 slave equipment

Abstract

The invention belongs to the technical field of USB (universal serial bus), and relates to a circuit for USB 2.0 slave equipment to detect host plugging, which comprises a level shift circuit, a comparator, a current DAC (digital-to-analog converter) and a calibration control logic circuit, the calibration control logic circuit outputs code words to control the current DAC, the current DAC generates calibration current, the level shift circuit is connected with a dp end or a dm end of the slave equipment, and the level shift circuit is connected with the dp end or the dm end of the slave equipment. The circuit comprises a calibration circuit and a bias current generation circuit, the sum of calibration current and bias current flows into the calibration circuit to generate a voltage detection threshold value, under the action of voltage at the dp end or dm end of slave equipment, a level offset circuit outputs positive end voltage and negative end voltage to a comparator, and the comparator judges whether a host is connected or not according to a comparison result. According to the invention, the slave equipment does not need other auxiliary means and does not need to modify a state machine of the controller, whether the host is plugged or not is detected only through the state of the comparator, detection after entering a suspended state is not needed, and the method has certain compatibility and adaptability.

Description

Technical Field

[0001] This invention relates to Universal Serial Bus (USB) technology, and more specifically to a circuit for detecting host plugging / unplugging of a USB 2.0 slave device. Background Technology

[0002] The USB 2.0 standard only specifies the method for the host to detect whether a device is plugged in or unplugged, but does not specify the method for the slave device to actively detect whether the host is plugged in or unplugged. In some applications, the slave device needs to detect whether the host is connected itself. For example, the slave device needs to enter a low-power mode based on whether the host is connected, or the slave device must maintain its current data and status based on whether the host is connected. In such cases, the slave device needs to initiate host plug-in / unplug detection when necessary.

[0003] CN114860520A discloses a USB slave device unplugging detection circuit, which requires the chip to have a built-in USB suspend circuit and a recovery circuit to detect whether the slave device has been unplugged, requiring a relatively complex circuit design.

[0004] CN112041827A discloses a method for detecting whether a host is connected, and CN106104504A discloses a system and method for detecting disconnection on a dual-mode port of a USB hub. Both methods add a 10uA pull-up current to the DM (full-speed or high-speed device) or DP (low-speed device) and detect the logic state of DP and DM in suspend mode. The connection status of the host is distinguished by the state of DP and DM. This solution requires modification of the USB 2.0 controller state machine for corresponding cooperation.

[0005] Existing technologies have the following drawbacks: Typically, a Vbus (USB bus power, outputting 5V when the host is connected) port detection circuit must be added to the device side to detect whether Vbus has power. However, this requires an additional pin for detection. Determining host insertion / removal by adding a Vbus pin to the device side to detect the presence of 5V power to Vbus is also wasteful of resources. Furthermore, in certain scenarios, this detection method will fail if some hosts do not have Vbus pin power. Alternatively, the state machine of the USB 2.0 controller logic can be modified accordingly, but this only allows detection in suspend mode, and the implementation is relatively complex.

[0006] Therefore, a simpler and more efficient solution is needed for USB slave devices to detect host plugging and unplugging, which does not require complex circuit design and is not limited by the current operating mode of the slave device, and can be detected at any time. Summary of the Invention

[0007] This invention provides a circuit for detecting host insertion / removal of a USB 2.0 slave device. It does not require adding a Vbus pin. Instead, it only requires adding a simple detection circuit to directly detect the insertion / removal of the host from the slave device by detecting the voltage state of the pull-up resistors of the dp (differential data positive line) or dm (differential data negative line).

[0008] A circuit for detecting host insertion / removal of a USB 2.0 slave device includes: a level offset circuit, a comparator, a current DAC, and a calibration control logic circuit. The calibration control logic circuit outputs a codeword to control the current DAC, and the current DAC generates a calibration current Ical. The level offset circuit is connected to the dp or dm terminal of the slave device. The level offset circuit includes a calibration circuit and a bias current generation circuit, and the bias current generation circuit generates a bias current. The calibration current Ical and the bias current The sum of the voltages flows into the calibration circuit, generating a voltage detection threshold Vos. Under the action of the voltage at the dp or dm terminal of the slave device, the level offset circuit outputs positive and negative terminal voltages to the comparator, which determines whether the host is connected based on the comparison result.

[0009] Furthermore, the bias current generation circuit includes an operational amplifier, a bias current setting NMOS transistor, a first bias resistor, and a first current mirror composed of a PMOS transistor. Under the feedback action of the operational amplifier, the bias current setting NMOS transistor, the first bias resistor, and the first current mirror generate a bias current. .

[0010] Furthermore, the calibration circuit includes a second current mirror composed of NMOS transistors, a second bias resistor, a positive terminal level offset NMOS transistor, and a negative terminal level offset NMOS transistor. The sum of the calibration current Ical and the bias current Iref is mirrored to the second offset resistor through the second current mirror, generating a voltage detection threshold Vos on the second offset resistor. Under the action of the voltage at the slave device dp or dm terminal, the branch connecting the positive terminal level offset NMOS transistor and the second bias resistor outputs a positive terminal voltage, and the branch of the negative terminal level offset NMOS transistor outputs a negative terminal voltage. The positive terminal voltage and the negative terminal voltage are provided to the comparator.

[0011] Furthermore, the positive terminal level-offset NMOS transistor and the negative terminal level-offset NMOS transistor are the same size, carry the same current, and have the same voltage; the NMOS transistors in the second current mirror are the same size.

[0012] Furthermore, the calibration current Ical is provided by the current DAC to the level offset circuit to adjust the bias voltage across the second bias resistor. By adjusting the value of Ical, the bias voltage across the second bias resistor is changed, thereby changing the voltage detection threshold.

[0013] Furthermore, the current DAC works in conjunction with the calibration control logic circuit to generate a calibration current Ical. After power-on, the calibration control logic circuit outputs a codeword with the range centered by default to control the magnitude of the Ical output current and adjust the voltage detection threshold. The calibration control logic circuit iterates through the control codeword of the current DAC once to find the most suitable threshold voltage.

[0014] Furthermore, finding the most suitable threshold voltage further includes: when the control code output of the calibration control logic circuit is all 0, the current output of the current DAC is at its minimum; when the control code output of the calibration control logic circuit is all 1, the current output of the current DAC is at its maximum. The calibration control logic circuit gradually increases the control code word, and the voltage detection threshold gradually increases. When the voltage detection threshold is small, the negative terminal voltage output by the level offset circuit is less than the positive terminal voltage, and the comparator output is 1. As the current of the current DAC is continuously increased, the voltage detection threshold gradually increases until the negative terminal voltage output by the level offset circuit is greater than the positive terminal voltage, and the comparator output changes from 1 to 0. At this time, the voltage detection threshold corresponding to the code word is the set maximum value.

[0015] The present invention has the following beneficial effects:

[0016] 1. By adding some detection circuitry, this invention enables the slave device to detect whether the host is plugged in or unplugged simply by querying a simple status, without the need for other auxiliary means or modification of the state machine of the USB 2.0 controller. Moreover, the detection can be performed at any time without entering suspend mode.

[0017] 2. By adding calibration logic, this invention can achieve periodic calibration of the detection threshold, thus achieving more accurate detection. It is not affected by process, voltage and temperature, and can dynamically adapt to various different host devices, with high compatibility and adaptability. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the host's state when the slave device is not connected in the prior art;

[0019] Figure 2 This is a schematic diagram of the host's status when a full-speed or high-speed device is connected.

[0020] Figure 3 This is a schematic diagram of the host's status when a low-speed device is connected;

[0021] Figure 4 This is a schematic diagram of the circuit status of a full-speed or high-speed device when the host is not inserted.

[0022] Figure 5 This is a schematic diagram of the circuit status of the full-speed or high-speed device when the host is inserted.

[0023] Figure 6 This is a schematic diagram of the circuit status of the low-speed device when the host is not inserted;

[0024] Figure 7 This is a schematic diagram of the circuit status of the low-speed device when the host is not inserted;

[0025] Figure 8 This is a schematic diagram illustrating how Vbus is used to detect whether a host is connected in existing technology.

[0026] Figure 9 This is a logic diagram of the device detecting host plugging and unplugging in this invention;

[0027] Figure 10 This is a schematic diagram of the level offset circuit in this invention;

[0028] Figure 11 This is a circuit diagram of the current DAC in this invention. Detailed Implementation

[0029] The USB 2.0 standard specifies the method for the host to detect whether a slave device is plugged in or unplugged. When the slave device is not plugged into the host, the host status is as follows: Figure 1 As shown. At this time, the two 15k pull-down resistors on the host side control the switch to close, and dp and dm are pulled down to 0V by the two pull-down resistors. Since the USB 2.0 protocol specifies that the host side has two Schmitt single-ended receivers to detect the status of dp and dm, when dp and dm are 0, the outputs se_dp and se_dm of the two single-ended receivers are also 0.

[0030] When a full-speed or high-speed device is plugged into the host, the circuit state changes as follows: Figure 2 As shown in the diagram. At this time, the two 15k pull-down resistors on the host side (dp and dm) control the switch to close, and the 1.5k pull-up resistor on the device side (dp) control the switch to close. dm will be pulled down to 0V by the pull-down resistor, but dp will be held at 3.0V by both the pull-up and pull-down resistors. Two Schmitt single-ended receivers detect the states of dp and dm (dp and dm here refer to the host side). The outputs of the two single-ended receivers, se_dp, are 1, while se_dm is 0. When a low-speed device is plugged into the host, the circuit state changes as follows: Figure 3As shown. At this time, the two 15k pull-down resistors on the host side (dp and dm) control the switch to close, and the 1.5k pull-up resistor on the device side (dm) control the switch to close. dp will be pulled down to 0V by the pull-down resistors, but dm will be held at 3.0V by both the pull-up and pull-down resistors. Two Schmitt single-ended receivers detect the states of dp and dm; the outputs of the two single-ended receivers, se_dp, are 0 while se_dm is 1.

[0031] Since the standard USB 2.0 protocol does not mandate that the device needs to detect whether the host is plugged in or out, but some applications require the slave device to also have the ability to detect whether the host is plugged in or out, the circuit state diagram of a full-speed or high-speed device when the host is not plugged in, without adding a Vbus pin, is shown below. Figure 4 As shown in the diagram. At this time, the 1.5k pull-up resistor on the dp terminal of the device controls the switch to close. dp will be pulled up to 3.3V by the pull-up resistor, but dm will have an uncertain voltage due to being in a floating state. Two Schmitt single-ended receivers detect the states of dp and dm. The outputs of the two single-ended receivers, se_dp, are 1, while se_dm is x, indicating an uncertain state. The circuit state diagram of the full-speed or high-speed device when the host is inserted is shown in the diagram. Figure 5 As shown. At this time, the two 15k pull-down resistors on the host side (dp and dm) control the switch to close, and the 1.5k pull-up resistor on the device side (dp) control the switch to close. dm will be pulled down to 0V by the pull-down resistor, but dp will be held at 3.0V by both the pull-up and pull-down resistors. Two Schmitt single-ended receivers detect the states of dp and dm (dp and dm here refer to the device side). The outputs of the two single-ended receivers, se_dp, are 1 while se_dm is 0.

[0032] For low-speed devices, when the host is not plugged in, the circuit status diagram of the low-speed device is as follows: Figure 6 As shown in the diagram. At this time, the 1.5k pull-up resistor on the dm terminal of the device controls the switch to close. dm will be pulled up to 3.3V by the pull-up resistor, but dp is in a floating state, resulting in an uncertain voltage. Two Schmitt single-ended receivers detect the states of dp and dm. The outputs of the two single-ended receivers, se_dp, are x, while se_dm is 1, where x indicates an uncertain state. The circuit state diagram of the low-speed device when the host is plugged in is shown in the diagram. Figure 7 As shown. At this time, the two 15k pull-down resistors on the host side (dp and dm) control the switch to close, and the 1.5k pull-up resistor on the device side (dm) control the switch to close. dp will be pulled down to 0V by the pull-down resistors, but dm will be maintained at 3.0V by both the pull-up and pull-down resistors. Two Schmitt single-ended receivers detect the states of dp and dm (dp and dm here refer to the device side). The outputs of the two single-ended receivers, se_dp, are 0, while se_dm is 1.

[0033] As can be seen from the above, for full-speed or high-speed devices, when the host is not inserted, the two single-ended receivers output se_dp=1 and se_dm=x; when the host is inserted, the two single-ended receivers output se_dp=1 and se_dm=0. These two states are indistinguishable. For low-speed devices, when the host is not inserted, the two single-ended receivers output se_dp=x and se_dm=1; when the host is inserted, the two single-ended receivers output se_dp=0 and se_dm=1. These two states are also indistinguishable. Therefore, regardless of the device's speed, the detection of host insertion / removal by the slave device cannot be performed using conventional methods.

[0034] The common approach in existing technologies to solve the problem of detecting whether the host is plugged in or unplugged by the slave device is to add a Vbus pin to the slave device chip to detect whether there is a 5V power supply on Vbus. If there is a 5V power supply, the detection circuit sets vbus_det=1, indicating that the host is connected; if not, vbus_det=0, which means the host has been unplugged. Figure 8 As shown. If the host insertion / removal is determined by adding a Vbus pin to the device-side chip to detect the presence of 5V power on the Vbus, the drawback is that it requires an extra Vbus pin, resulting in wasted resources. Furthermore, in certain special scenarios, if some hosts do not have a Vbus pin for power, this detection method will fail.

[0035] according to Figures 4-5 As shown, when a full-speed or high-speed device is not connected to the host, the voltage at the dp terminal is 3.3V. However, when the host is connected, due to the pull-down resistor, the voltage at the dp terminal drops to 3.0V. Therefore, by detecting the difference between 3.3V and 3.0V, it is possible to determine whether the host is connected. Similarly, according to... Figures 6-7 As shown, when the host is not connected, the voltage at the dm terminal of the low-speed device is 3.3V. When the host is connected, the voltage at the dm terminal will drop to 3.0V due to the pull-down resistor. Therefore, as long as the difference between the 3.3V and 3.0V voltage is detected, it can be determined whether the host has been connected.

[0036] To achieve the above goals, a threshold voltage of 3.15V can be chosen, and the voltage on dp or dm can be compared with 3.15V. For full-speed or high-speed devices, if the dp voltage is greater than 3.15V, the host is considered disconnected; if the dp voltage is less than 3.15V, the host is considered connected. For low-speed devices, if the dm voltage is greater than 3.15V, the host is considered disconnected; if the dm voltage is less than 3.15V, the host is considered connected. However, in reality, 3.3V will change with the external power supply. Assuming a variation of ±10% in 3.3V, the corresponding threshold level of 3.15V must also vary by ±10%. Furthermore, due to potential variations in the pull-down resistor at the host side and the high common-mode voltage, the design of the comparator and the threshold voltage generation circuit are relatively difficult.

[0037] Taking a full-speed or high-speed device as an example, to simplify the design, this invention uses a level offset circuit to generate the two inputs of the comparator, with the dp voltage shifted downward by one voltage V. GS (V) GS The gate-source voltage of the MOSFET is used to obtain the negative terminal voltage V of the comparator. cmp- Shift the 3.3V power supply down by one voltage (V) GS +150mV) to obtain the positive terminal voltage V of the comparator cmp+ The comparator output indicates whether the host is connected. When the host is not connected, the voltage of dp is 3.3V, therefore the following relationship applies:

[0038]

[0039]

[0040]

[0041]

[0042] Vdp is the voltage at the dp terminal when the device is being tested at full speed or high speed. From the relationship above, we can see that a comparator output of 0 indicates that the host is not connected. When the host is connected, the voltage at dp is 3.0V, therefore the following relationship holds:

[0043]

[0044]

[0045]

[0046]

[0047] As can be seen from the above relationship, a comparator output of 1 indicates that the host is connected. Furthermore, to eliminate the influence of various factors on the threshold voltage, the aforementioned 150mV bias voltage can be calibrated using digitally controlled calibration logic, thus eliminating the effects of uncertainties caused by the power supply and host-side pull-down resistors.

[0048] Figure 9 This is a logic diagram of the device detecting host plugging / unplugging in this invention. Figure 10 This is a schematic diagram of a level offset circuit.

[0049] The detection circuit includes: a level offset circuit, a comparator, a current DAC (Digital-to-Analog Converter, which converts digital signals into corresponding current signals and outputs current signals), and a calibration control logic circuit. Figure 9 DP refers to the testing of full-speed or high-speed equipment, while DM refers to the testing of low-speed equipment.

[0050] This description uses a full-speed device as an example. After the device powers on, the level offset circuit, comparator, and current DAC all start working. At this time, the calibration control logic circuit does not start working. The calibration control logic outputs a default codeword to control the current DAC. The sum of the calibration current Ical and the bias current Iref generated by the current DAC is mirrored to R2, generating a voltage detection threshold Vos. The initial default value of Vos is 0.15V. When the host is not connected, the 1.5k pull-up resistor on the device's dp / dm control switch closes, pulling dp up to 3.3V. At this time, the following relationship is satisfied:

[0051]

[0052]

[0053]

[0054]

[0055]

[0056] At this point, the comparator will output 0, indicating that the host is not connected. Once the host is connected, due to the 15k pull-down effect, dp will be pulled below 3.0V, at which point the following relationship will be satisfied:

[0057]

[0058]

[0059]

[0060]

[0061]

[0062] The comparator will then output 1, indicating that the host has been connected.

[0063] The current DAC circuit is primarily used in conjunction with the calibration control logic to generate a calibration current Ical, which is used to calibrate the connection threshold voltage. Upon power-up, the calibration control logic outputs a centered codeword 1000, controlling the magnitude of the Ical output current. This centered value allows for adjustments to the current, increasing or decreasing it to adjust the threshold voltage. Ical is the current provided by the current DAC circuit to the offset circuit to adjust the bias voltage across R2. By adjusting Ical, the bias voltage across R2 can be changed, thus altering the detection threshold. Initially, Ical has a default value, resulting in a default voltage Vos across R2 of 0.15V. Therefore, when the host pulls dp or dm down to 3.15V, the device can detect the host connection through the comparator's output. As Ical increases, the voltage Vos across R2 also increases. For example, if Vos is now 0.2V, the device can only detect the host connection through the comparator's output when the host pulls dp or dm down to 3.1V via Vbp. Vbp is the bias voltage provided by the level offset circuit to the MOSFET of the current DAC. It ensures that the output current of the current DAC and the current of the offset circuit have consistent PVT variation characteristics, reducing the impact of various condition changes on detection accuracy. PVT is a common abbreviation in chip design, where P stands for process, V for voltage, and T for temperature.

[0064] The level offset circuit includes a calibration circuit and a bias current generation circuit, the bias current generation circuit generating a bias current. Calibration current Ical and bias current The sum of these values ​​flows into the calibration circuit, generating the voltage detection threshold Vos. Under the influence of the voltage at the dp or dm terminal of the slave device, the level offset circuit outputs positive and negative terminal voltages, which are provided to the comparator. The comparator determines whether the host is connected based on the comparison result. More specifically, such as... Figure 10 As shown, the level offset circuit consists of a MOS transistor array (including NMOS transistors M1, M2, M3, M4, M5 and M8, and PMOS transistors M6 and M7), an operational amplifier OP, and a first bias resistor R1 and a second bias resistor R2.

[0065] In the bias current generation circuit, operational amplifier A, bias current setting NMOS transistor M8, and first bias resistor R1 form a negative feedback loop, clamping the source voltage of M8 to the reference voltage Vref. Under the feedback of operational amplifier A, combined with the bias current setting NMOS transistor M8, and the voltage across the first bias resistor R1 being the reference voltage of 1.2V, a bias current is generated. The magnitude of this current is...

[0066]

[0067] In the bias current generation circuit, PMOS transistors M6 and M7 form the first current mirror. With a 16:1 size design, the bias current Iref is 50uA. At the same time, Vbp is pulled to the current DAC terminal to provide bias. The DAC will output a calibration current Ical for calibration. By default, the current of Ical is 50uA. Therefore, the current flowing into M1 is the sum of Ical and Iref, which is 100uA.

[0068] The calibration circuit includes a second current mirror composed of NMOS transistors M1, M2, and M3 of the same size, a second bias resistor, a positive-terminal level-offset NMOS transistor M4, and a negative-terminal level-offset NMOS transistor M5. The sum of the calibration current Ical and the bias current Iref passes through the second current mirror and is mirrored to the second offset resistor R2, generating a voltage detection threshold Vos across the second offset resistor R2. Under the influence of the voltage at the dp or dm terminal of the slave device, the branch connecting the positive-terminal level-offset NMOS transistor M4 and the second bias resistor R2 outputs a positive voltage, and the branch of the negative-terminal level-offset NMOS transistor M5 outputs a negative voltage. The positive and negative voltages are provided to the comparator. The NMOS transistors constituting the second current mirror ensure the following relationship:

[0069]

[0070] in These are the currents flowing through NMOS transistors M1, M2, and M3, respectively.

[0071] Therefore, the current flowing through the second bias resistor R2 is 100uA, and the voltage across it is:

[0072]

[0073] The positive-terminal level-shifted NMOS transistor M4 and the negative-terminal level-shifted NMOS transistor M5 have the same design dimensions and carry the same current, therefore the following relationship can be satisfied:

[0074]

[0075] The positive terminal level offset NMOS transistor M4 is connected to the second bias resistor R2, outputting the positive terminal voltage. The negative terminal level is offset by the NMOS transistor output negative terminal voltage. .

[0076] Therefore, the following relationship can be obtained, where the negative and positive terminal voltages of the comparator are respectively:

[0077]

[0078]

[0079] The above voltage is supplied to the comparator, and the comparator output result determines whether the host is connected. Vdp is the voltage at the dp terminal when detecting full-speed or high-speed devices; for low-speed devices, the voltage at the dm terminal is Vdm.

[0080] The threshold voltage affects the detection results. If the threshold voltage is set too low, temperature changes, comparator offset, and power supply ripple may cause the comparator to mis-trigger, mistaking a non-connected circuit for a connected one. If the threshold voltage is set too high, changes in the host's pull-down resistor may cause detection failure. For example, in the extreme case of the host's pull-down voltage changing from 15kΩ to 30kΩ, the pull-down voltage will change from 3.0V to 3.15V. Therefore, a calibration control logic circuit can be used to dynamically adjust the detection threshold. After the device detects the host connection, it can choose whether to activate the calibration control logic based on actual needs. Due to changes in voltage, temperature, and other factors during use, it may be necessary to dynamically modify the detection threshold voltage. In this case, the calibration control logic circuit can be activated to adjust the threshold voltage to improve detection accuracy. The working principle of the calibration control logic circuit is to traverse the DAC's control code word once to find the most suitable threshold voltage. When the calibration control logic circuit outputs all 0s, the DAC output current is at its minimum; when the calibration control logic circuit outputs all 1s, the DAC output current is at its maximum. The control logic circuit will gradually increase the control code word, and the threshold voltage will gradually increase accordingly. Taking the extreme case above as an example, if the pull-down resistor on the host side is 30k, then dp will be pulled down to 3.15V, with the following relationship:

[0081]

[0082]

[0083]

[0084] Increasing the threshold corresponds to increasing Vos. When Vos is relatively small, Vcmp- is less than Vcmp+, and the comparator output is 1. As the DAC current is continuously increased, Vos increases until Vcmp- is greater than Vcmp+. At this point, the comparator output changes from 1 to 0. The threshold voltage corresponding to the codeword at this point is the highest value set. In practice, half of the highest value should be used to ensure the stability of the circuit.

[0085] The level offset circuit structure is as follows Figure 10 As shown in the diagram, M4 and M5 are the same size, M2 and M3 are the same size, and R1 and R2 are resistors of the same size that are matched to the 1.5k pull-up resistor of the device. Figure 10 It can be seen that M1, M2, and M3 form a matched current mirror, so the currents of M2 and M3 are consistent. Since M4 and M5 have the same dimensions, their gate-source voltages are equal, thus satisfying the following relationship:

[0086]

[0087] A well-designed system can ensure that the voltage Vos across R2 is proportional to the reference voltage Vref, thus guaranteeing...

[0088]

[0089] From the above results, we can deduce that

[0090]

[0091]

[0092] Therefore, by comparing the magnitudes of Vcmp+ and Vcmp-, the host computer can be detected. The calibration control current Ical is generated by the current DAC controlled by the calibration control logic section. Its purpose is to compensate for the effects of temperature and process variations, and also to compensate for the effects of changes in the host computer's pull-down resistors. Specifically, depending on different accuracy requirements, one can choose not to calibrate, perform a one-time calibration, or perform periodic calibration during operation.

[0093] Specific examples of current DACs Figure 11 As shown, M9-M12 are four PMOS transistors forming a current mirror with a specific ratio. Their bias is derived from the level offset circuit Vbp, and the internal current switching is controlled by calibration control logic. The calibration control logic can achieve the following functions:

[0094] (1) If not calibrated, all switches will be open and Ical will not output current.

[0095] (2) During initial connection calibration, the current DAC output current gradually increases. The calibration control logic finds the point where the comparator flips (by continuously adding current), and then adjusts the value of the current DAC according to the calibration result.

[0096] (3) Calibrate regularly during operation, and perform calibration each time the host is connected.

[0097] The comparator's inputs are derived from two voltages, Vcmp+ and Vcmp-, generated by a level offset circuit. An output of 1 indicates that the host is connected, while an output of 0 indicates that the host is disconnected. This output can also be sent to the calibration control logic to calibrate the comparator's comparison threshold, Vos.

[0098] The technical solution designed in this invention adds a detection circuit, enabling USB 2.0 slave devices to detect whether the host is plugged in or unplugged simply by querying a simple status bar, without requiring other auxiliary means or modification of the USB 2.0 controller's state machine. Furthermore, detection can be performed at any time without needing to enter a suspend state. By adding calibration logic, periodic calibration of the detection threshold can be achieved, resulting in more accurate detection. This is unaffected by process technology, voltage, and temperature, and can dynamically adapt to various host devices, exhibiting high compatibility and adaptability.

Claims

1. A circuit for detecting host insertion / removal of a USB 2.0 slave device, comprising: The system includes a level offset circuit, a comparator, a current DAC, and a calibration control logic circuit. The calibration control logic circuit outputs a codeword to control the current DAC, which generates a calibration current Ical. The level offset circuit is connected to the DP or DM terminal of the slave device. The level offset circuit includes a calibration circuit and a bias current generation circuit, which generates a bias current. The calibration current Ical and the bias current The sum of the voltages flows into the calibration circuit, generating a voltage detection threshold Vos. Under the action of the voltage at the dp or dm terminal of the slave device, the level offset circuit outputs positive and negative terminal voltages to the comparator, which determines whether the host is connected based on the comparison result.

2. The circuit for detecting host insertion / removal of a USB 2.0 slave device as described in claim 1, wherein the bias current generation circuit includes an operational amplifier, a bias current setting NMOS transistor, a first bias resistor, and a first current mirror composed of a PMOS transistor; under the feedback action of the operational amplifier, the bias current setting NMOS transistor, the first bias resistor, and the first current mirror generate a bias current. .

3. The circuit for detecting host insertion / removal of a USB 2.0 slave device as described in claim 1, wherein the calibration circuit includes a second current mirror composed of NMOS transistors, a second bias resistor, a positive terminal level offset NMOS transistor, and a negative terminal level offset NMOS transistor. The sum of the calibration current Ical and the bias current Iref is mirrored to the second offset resistor through the second current mirror, generating a voltage detection threshold Vos on the second offset resistor. Under the action of the voltage at the slave device's dp or dm terminal, the branch connecting the positive terminal level offset NMOS transistor and the second bias resistor outputs a positive terminal voltage, and the branch of the negative terminal level offset NMOS transistor outputs a negative terminal voltage. The positive terminal voltage and the negative terminal voltage are provided to a comparator.

4. The circuit for detecting host insertion / removal of a USB 2.0 slave device as described in claim 3, wherein the positive terminal level offset NMOS transistor and the negative terminal level offset NMOS transistor are of the same size, carry the same current, and have the same voltage; the NMOS transistors in the second current mirror are of the same size.

5. The circuit for detecting host insertion / removal of a USB 2.0 slave device as described in claim 3, wherein the calibration current Ical is provided by a current DAC to a level offset circuit for adjusting the bias voltage across the second bias resistor. By adjusting the value of Ical, the bias voltage across the second bias resistor is changed, thereby changing the voltage detection threshold.

6. The circuit for detecting host insertion / removal of a USB 2.0 slave device as described in claim 1, wherein the current DAC cooperates with the calibration control logic circuit to generate a calibration current Ical, and the calibration control logic circuit outputs a codeword with the range centered by default after power-on to control the magnitude of the Ical output current and adjust the voltage detection threshold; the calibration control logic circuit traverses the control codeword of the current DAC once to find the most suitable threshold voltage.

7. The circuit for detecting host insertion / removal of a USB 2.0 slave device as described in claim 6, wherein finding the most suitable threshold voltage further includes: when the control code output of the calibration control logic circuit is all 0, the current output of the current DAC is at its minimum; when the control code output of the calibration control logic circuit is all 1, the current output of the current DAC is at its maximum; the calibration control logic circuit gradually increases the control code word, and the voltage detection threshold gradually increases; when the voltage detection threshold is small, the negative terminal voltage output by the level offset circuit is less than the positive terminal voltage, and the comparator output is 1; as the current of the current DAC is continuously increased, the voltage detection threshold gradually increases until the negative terminal voltage output by the level offset circuit is greater than the positive terminal voltage, and the comparator output changes from 1 to 0. At this time, the voltage detection threshold corresponding to the code word is the set maximum value.

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