Integrated circuit layout optimization method and system based on machine learning

Abstract

The invention relates to the technical field of layout optimization, in particular to an integrated circuit layout optimization method and system based on machine learning. Comprising a weight self-defining module, a candidate layout fusion module and a virtual simulation module. According to the method, a user is allowed to flexibly define the weight of each optimization dimension through a double-window interface or intelligently adjust the weight of each optimization dimension by a system through a dynamic weight self-adaptive mechanism, so that the flexibility of manual intervention is reserved, optimization can be carried out based on historical data and real-time feedback, the problem of over-design or substandard performance caused by the traditional fixed weight is avoided, and the method is suitable for large-scale popularization and application. Model architecture is modularized, each sub-model is independently trained for a specific optimization target, the complexity of the model is reduced, subsequent expansion of new optimization dimensions is facilitated, and through real-time comparison of virtual simulation and a standard threshold value, standard exceeding dimensions are automatically identified and weights are adjusted, and artificial iteration links in a traditional design process are greatly reduced.

Description

Technical Field

[0001] This invention relates to the field of layout optimization technology, and more specifically, to a method and system for integrated circuit layout optimization based on machine learning. Background Technology

[0002] Integrated circuits are a way to miniaturize circuits (mainly including semiconductor devices, but also passive components, etc.). Using certain processes, the transistors, resistors, capacitors, inductors, and other components required for a circuit, along with interconnected wiring, are fabricated on a small piece or several small pieces of semiconductor wafers or dielectric substrates, and then packaged in a package to become a miniature structure with the required circuit function. Integrated circuit layout optimization is a crucial step in physical design. It refers to the process of improving the initial layout through a series of algorithms and strategies after determining the location of each standard cell and macro module on the chip and their interconnections, in order to achieve multiple design goals (such as performance, area, power consumption, etc.). However, when traditional layout methods use a single neural network to learn features, it is difficult to effectively coordinate conflicting optimization objectives such as wiring length (electrical performance), thermal density (reliability), and area utilization (cost). Furthermore, they cannot dynamically adjust based on circuit characteristics (such as high-frequency modules requiring priority heat dissipation) or real-time simulation feedback, resulting in numerous flaws in the final layout scheme. Therefore, this paper provides an integrated circuit layout optimization method and system based on machine learning. Summary of the Invention

[0003] The purpose of this invention is to provide a machine learning-based integrated circuit layout optimization method and system to solve the core problem of traditional integrated circuit layout optimization mentioned in the background art above, namely, that there are strong coupling relationships between multiple key dimensions (such as line performance, heat dissipation efficiency, and space utilization), making it difficult to optimize independently, and manual parameter tuning is inefficient. For example, shortening the wiring length may increase the power supply noise and heat dissipation pressure, while simply reducing the heat density may lead to chip area expansion. Existing methods can usually only compromise on one dimension, resulting in limited overall performance.

[0004] To address the aforementioned technical problems, one objective of this invention is to provide a machine learning-based integrated circuit layout optimization method, comprising the following steps: An optimization weight input window is established to determine the optimization weights for multiple optimization dimensions, including line optimization, heat dissipation optimization, and space optimization. Machine learning algorithms are used to train multi-source optimization dimension integrated circuit layout models, output multiple candidate layout schemes, and then the multiple candidate layout schemes are merged based on optimization weights to form an integrated circuit layout scheme. The virtual simulation of integrated circuit layout schemes generates multi-source virtual optimization data. This virtual optimization data is then compared sequentially with standard data thresholds. If a match is found, a scheme determination signal is output; otherwise, an optimization weight adjustment signal is output. The difference between the virtual optimization data and the standard data thresholds is calculated and updated to determine the optimization weights. Optional input of optimization weights is then entered into the input window. The virtual optimization data consists of simulated values ​​for multiple optimization dimensions, and the standard data threshold is the value of the optimization dimension that meets the safety standard.

[0005] Preferably, the optimization weight input window includes a self-selection window and an update input window. The self-selection window provides users with options to input optimization weights, and the update input window provides options to update optimization weights and historical optimization weights, and pops up a confirmation option, wherein: When it is determined that the option is not checked, the priority of the self-selection window is higher than the priority of updating the input window; When selecting options, the priority of the auto-selection window is lower than that of the update input window.

[0006] Preferably, the updated optimization weight is displayed in the update input window as being superior to the historical optimization weight, wherein the historical optimization weight is the historical record of the previous time node stored in the log record.

[0007] Preferably, the multi-source optimization dimension integrated circuit layout model includes: Collect a large number of circuit layout optimization schemes as training samples; The circuit optimization model is trained with the objective functions of minimizing bus length, reducing via count, and avoiding congestion. A heat dissipation optimization model is trained with the objective functions of minimizing hot spot temperature and temperature distribution uniformity. A space optimization model is trained with the objective functions of maximizing space utilization, minimizing blank fragments, and controlling aspect ratio, where: All models share the same input feature set and output candidate layout schemes represented using two-dimensional continuous coordinates and a connected topology graph. Each model runs inference independently and generates a set of candidate layout schemes.

[0008] Preferably, the circuit optimization model adopts a graph attention network, which models the circuit netlist as a graph, with each node having features and edges representing connection requirements. The GAT is used to extract topological semantic features, outputting a high-dimensional embedding vector for each module to capture its role in the network. A Transformer decoder is introduced to gradually generate module position offsets, and an autoregressive method is used to gradually generate node positions to obtain a new layout. The model is trained to form a circuit optimization model and outputs candidate layout schemes that focus on electrical connections. The heat dissipation optimization model integrates infrared thermal imaging measured data and finite element simulation results as supervision labels, and combines a hybrid deep learning architecture that uses convolutional neural networks to process spatial power distribution features and graph neural networks to model the thermal coupling relationship between modules. In this architecture, CNN and GNN independently encode the spatial and topological information of the input, obtain their respective high-level feature representations, and then concatenate and fuse them before the fully connected layer to form a joint feature vector. The system predicts the steady-state temperature field of complex electronic systems under different power consumption configurations and outputs candidate layout schemes for the temperature distribution of interest. The spatial optimization model uses a variational autoencoder to learn an efficient latent space representation of the layout. The decoder outputs a compact initial layout solution, which is then fine-tuned by a lightweight MLP to meet boundary constraints and train to form a spatial optimization model. The model outputs candidate layout schemes that focus on geometric utilization.

[0009] Preferably, the integrated circuit layout scheme is formed by merging multiple candidate layout schemes based on optimized weights, including the following steps: The objective function score for each candidate solution in each optimization dimension is calculated using a normalization method; We introduce optimization weights to output a weighted comprehensive score matching the objective function score of each candidate solution, and select the top K solutions with the highest comprehensive scores from all candidate solutions as alternatives; Construct a new comprehensive layout, calculate the centroid of the module coordinate set in each candidate scheme, and align the coordinate system by coordinate translation. Calculate the weighted average position by weighting the K schemes, add the global offset, and obtain the final comprehensive layout scheme.

[0010] Preferably, the virtual simulation integrated circuit layout scheme generates multi-source virtual optimization data, and the virtual optimization data is compared with standard data thresholds in sequence, including the following steps: Extract the position, size, type, connection relationship of all modules in the comprehensive layout scheme, as well as the process library information and power consumption model, encapsulate them using script-based integration, and perform batch simulations on the GPU server cluster. Each layout scheme generates a vector, which includes line data, heat dissipation data and space data. Construct a standard threshold matrix, define the target range for each dimension, map multiple dimensions to multiple vectors, calculate the normalized deviation of each dimension, and output an optimization weight adjustment signal if any deviation does not match the deviation index. If all deviations match the deviation index, output a scheme determination signal.

[0011] Preferably, the step of reverse-engineering and comparing the difference between the virtual optimized data and the standard data threshold, and calculating the updated optimization weight, includes the following steps: Determine the optimization direction for each dimension and clarify the upper or lower bound constraints for each dimension; The dimensions corresponding to the deviation index are extracted to determine the degree of deviation. The normalized deviation ratio is used as the deviation measure. The normalized deviation index is used to obtain the correction priority. An exponential smoothing fusion strategy is adopted to control the balance between priority weight and deviation feedback. The weight can decay with the number of iterations until the output scheme determination signal is obtained, thus obtaining the final update weight.

[0012] The second objective of this invention is to provide an integrated circuit layout optimization system based on machine learning, including any one of the machine learning-based integrated circuit layout optimization methods described above, including a weight customization module, a candidate layout fusion module, and a virtual simulation module. The weight customization module is used to establish an optimization weight input window to determine the optimization weights for multiple optimization dimensions, including line optimization, heat dissipation optimization, and space optimization. The candidate layout fusion module is used to train multi-source optimization dimension integrated circuit layout models using machine learning algorithms, output multiple candidate layout schemes, and fuse multiple candidate layout schemes based on optimization weights to form an integrated circuit layout scheme. The virtual simulation module is used to virtually simulate the integrated circuit layout scheme to form multi-source virtual optimization data. It compares the virtual optimization data with the standard data threshold in turn. If they match, it outputs a scheme determination signal. If they do not match, it outputs an optimization weight adjustment signal. It then compares the difference between the virtual optimization data and the standard data threshold to calculate and update the optimization weights. The module can also selectively input the weights into the custom weight module.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: By optimizing the dynamic weight adaptation mechanism of the weight input window, users can flexibly define or have the system intelligently adjust the weights of each optimization dimension through a dual-window interface. This retains the flexibility of manual intervention while enabling optimization based on historical data and real-time feedback, avoiding over-design or performance failures caused by traditional fixed weights. The modular model architecture achieves efficient training and inference through separating circuit, heat dissipation, and space optimization sub-models. Each sub-model is trained independently for a specific optimization objective, which not only reduces model complexity but also facilitates the subsequent expansion of new optimization dimensions. Furthermore, through real-time comparison of virtual simulation with standard thresholds, the system automatically identifies out-of-standard dimensions and adjusts their weights, significantly reducing the manual iteration steps in the traditional design process. This significantly improves the automation level, optimization quality, and iteration efficiency of integrated circuit layout design, solving the technical problems of traditional EDA tools in multi-objective trade-offs, high reliance on manual intervention, and lack of dynamic feedback. Attached Figure Description

[0014] Figure 1 This is the overall flowchart of Example 1; Figure 2 This is a block diagram illustrating the principle of the multi-source optimization dimension integrated circuit layout model in Example 1. Figure 3 This is a block diagram illustrating the principle of the optimized weight input window in Example 1. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] Example 1 like Figures 1-3 As shown, one of the objectives of this invention is to provide a machine learning-based integrated circuit layout optimization method, comprising the following steps: Step 1: Establish an optimization weight input window to determine the optimization weights of multi-source optimization dimensions. The optimization dimensions include line optimization, heat dissipation optimization, and space optimization. This allows users to customize or the system to dynamically set the relative importance of key optimization dimensions such as line, heat dissipation, and space. This is beneficial for customizing the layout optimization direction according to current needs and improving personalized customization requirements. like Figure 3 As shown, the optimization weight input window includes a self-selection window and an update input window. The self-selection window provides users with options to input optimization weights, while the update input window provides options to update optimization weights and historical optimization weights, and then displays a confirmation option. When the selection option is not checked (indicating that human selection is the most important), the priority of the self-selection window is higher than that of the update input window. This helps to ensure that human subjective consciousness is used as the condition for subsequent integrated circuit layout optimization. Even if there are options to update the optimization weight, the human selection is automatically used as the optimization weight output. When the selected option is checked (indicating that the system update result is the most important), the priority of the self-selection window is lower than that of the update input window. This helps ensure that the reasonable optimization weight of the system update is used as the condition for subsequent integrated circuit layout optimization. Even if there are user-input options, the system update selection is automatically used as the optimization weight for output.

[0017] Specifically, the updated optimization weights are displayed in the update input window, prior to the historical optimization weights. The historical optimization weights are historical records stored in the log, representing the previous time point. This is achieved through two windows: a self-selection window and an update input window. Users can easily refer to the optimization weights displayed in the update input window while inputting their own data. Initially, the update input window displays the historical optimization weights. This means that each time integrated circuit layout optimization is performed, a log is generated and stored in the cloud database. Upon initial system startup, the log data from the previous time point—the closest time point to the current time—is actively retrieved, providing users with a basic reference. Furthermore, when optimizing the layout of similar products, users can directly select the "confirm" option and determine the optimization weights with a single click, reducing the time and effort required for inputting optimization weights.

[0018] Step 2: Use machine learning algorithms to train multi-source optimization dimension integrated circuit layout models separately, outputting multiple candidate layout schemes. Each model focuses on a certain set of optimization dimensions, with clear knowledge isolation. On the one hand, it is convenient to retrain the sub-model when it performs poorly in a certain dimension, and it is also convenient to add optimization dimensions later. On the other hand, outputting multiple candidate layout schemes with different optimization dimensions provides a diverse basis for subsequent comprehensive decision-making. Based on the optimization weights, multiple candidate layout schemes are merged to form an integrated circuit layout scheme.

[0019] Specifically, such as Figure 2 As shown, the multi-source optimization dimension integrated circuit layout model includes: Collect a large number of circuit layout optimization schemes as training samples; Firstly, train a circuit optimization model with the objective functions of minimizing bus length, reducing via count, and avoiding congestion (focusing on electrical connections): The circuit optimization model employs a graph attention network, modeling the circuit netlist as a graph. Each node is associated with features, and edges represent connection requirements. A Gaussian Attention (GAT) algorithm is used to extract topological semantic features (automatically learning "which modules are more important" through an attention mechanism). The model outputs a high-dimensional embedding vector for each module, capturing its role in the network. A Transformer decoder is introduced to progressively generate module position offsets, similar to a natural language translation task. The input is a sequence of module features encoded by the GAT algorithm, and the output is the position increment of each module relative to its initial position. An autoregressive approach is used to progressively generate node positions to obtain a new layout (determining the position of one module at a time). This process is then used to train the circuit optimization model. Therefore, by transforming the circuit structure into a graph, extracting semantic features using a deep attention mechanism, and then optimizing the layout using a sequence generation model, the model outputs candidate layout schemes that focus on electrical connections. The model can be run multiple times to generate multiple candidate layout schemes, i.e., multiple new layouts.

[0020] Secondly, a heat dissipation optimization model is trained with the objective function of minimizing hot spot temperature and temperature distribution uniformity (focusing on temperature distribution). The heat dissipation optimization model integrates infrared thermal imaging measured data and finite element simulation results as supervision labels, and combines a hybrid deep learning architecture that uses convolutional neural networks (CNN) to process spatial power distribution features and graph neural networks (GNN) to model the thermal coupling relationship between modules. In this architecture, CNN and GNN independently encode the spatial and topological information of the input, obtain their respective high-level feature representations, and then concatenate and fuse them before the fully connected layer to form a joint feature vector.

[0021] This method predicts the steady-state temperature field of complex electronic systems (such as multi-core chips, high-density PCBs, or server board-level systems) under different power consumption configurations and outputs candidate layout schemes for the temperature distribution of interest. Specifically, in the tag generation stage, ANSYS is used... Icepak establishes a parametric 3D finite element model of heat conduction, covering various typical structural designs (such as radiator size, airflow arrangement, and material thermal conductivity), environmental conditions (natural convection / forced air cooling), and diverse power input modes. Automated scripts generate tens of thousands of simulation samples in batches. Each sample includes the input planar power density distribution map and the corresponding steady-state temperature field output. To improve the model's applicability in real-world scenarios, infrared thermal imaging data from actual hardware platforms under the same operating conditions are simultaneously collected. Image registration technology is used to map the infrared images to a spatial grid coordinate system consistent with the simulation model, followed by denoising, emissivity correction, and non-uniform response compensation. Subsequently, a "simulation-based, experimental-assisted" strategy is adopted to construct composite labels: using Icepak simulation results as the base temperature field, a lightweight bias correction network is introduced to learn the systematic differences between simulation and experimental data, thereby generating training targets that are closer to physical reality. This effectively solves the modeling error problem that may exist in pure simulation, while avoiding the sample scarcity dilemma caused by relying entirely on expensive experimental data.

[0022] Furthermore, the model receives two complementary information sources: the power density distribution in a two-dimensional plane and the topological connections between modules. For the former, the chip or circuit board is divided into a regular N×N grid (e.g., 32×32), with each grid cell encoding the average power density value of its region, forming a single-channel or multi-channel input tensor, which is then fed into a CNN branch for processing. This CNN structure consists of multiple stacked convolutional layers equipped with batch normalization and ReLU activation functions to progressively extract the spatial features of local heat sources, identify potential hotspot clustering patterns and their diffusion trends, and after several downsampling operations, finally output a compact spatial feature vector to characterize the prior thermal behavior caused by the current power distribution. For the latter, namely the thermal influence relationships between modules, an undirected or directed graph G=(V,E) is constructed, where nodes v∈V. Each heat-generating functional module (or grid center point) represents a node with features including module area, packaging type, distance from the heat dissipation interface, and local power consumption. An edge e∈E indicates a significant thermal coupling effect between two modules, usually determined based on geometric proximity (Euclidean distance less than a threshold) or shared thermal resistance path. The edge weight can be set as the inverse of thermal conductivity or an empirical attenuation factor. Based on this graph structure, a graph attention network (GAT) is used as the backbone of the GNN, allowing the model to adaptively learn the intensity of thermal interference between different modules. It is particularly suitable for capturing asymmetric heat transfer phenomena (such as upstream modules causing stronger heating effects on downstream modules). Through a multi-layer message passing mechanism, the GNN can aggregate global topological information and output a set of node embedding vectors rich in contextual semantics. Then, through the readout function, a graph-level representation of the overall system can be obtained, and a heat dissipation optimization model can be trained.

[0023] Thirdly, a spatial optimization model (focusing on geometric utilization) is trained with the objective functions of maximizing space utilization, minimizing blank fragments, and controlling aspect ratio. The spatial optimization model uses a variational autoencoder to learn an efficient latent space representation for the layout. The decoder outputs a compact initial layout solution, which is then fine-tuned using a lightweight MLP to meet boundary constraints, training to form the spatial optimization model. This outputs candidate layout schemes that focus on geometric utilization. Specifically, a large number of high-quality, manually or algorithmically generated reference layout datasets are collected and preprocessed to form layout samples, including chip module placement, PCB component arrangement, data center rack deployment, or urban functional area division, etc. Each sample... The layout is represented in a unified format as a set of rectangular objects with attributes, where each object contains its category label, size, center coordinates, and relative positional relationship with other objects. All samples are normalized to a unit canvas space [0,1]×[0,1] to avoid scale differences interfering with the model learning process. Subsequently, each layout is encoded as a structured input tensor: a grid discretization strategy is used to map it into a multi-channel feature map, where channels represent the existence, area density, edge strength, and other information of different categories. At the same time, a corresponding graph structure representation is constructed, with nodes corresponding to modules and edges connecting spatially adjacent modules to help capture topological dependencies in large-scale layout datasets. The variational autoencoder backbone is pre-trained to stably learn effective latent space distribution and reconstruction capabilities. At this stage, the loss function includes reconstruction error (e.g., L1 distance in coordinate space or IoU loss in image space), KL divergence term, and layout quality regression loss. Subsequently, the encoder and first-stage decoder are frozen, and the MLP fine-tuning network is trained separately, using synthetic perturbation samples (e.g., artificially added overlaps or offsets) as input and the target conflict-free layout as the supervision signal, driving the MLP to master the correction mechanism. Finally, end-to-end fine-tuning can be performed, releasing all parameters and jointly optimizing using the comprehensive objective function J, allowing for flexible balancing of various optimizations according to different application scenarios. The goal is to improve model stability by employing the AdamW optimizer with a learning rate decay strategy and introducing a course learning mechanism during training, gradually transitioning from simple, small-scale layouts to complex, high-density scenarios. During deployment, users can specify the target aspect ratio, module type combination, and quantity, randomly sample or provide a latent vector z, generate an initial layout through the decoder, and then perform 10-20 iterations of fine-tuning by the MLP to finally output a compact and feasible solution that meets engineering requirements. The entire inference process can achieve millisecond-level response on the GPU, supporting real-time interactive design exploration, and providing a brand-new driving solution for fields such as electronic design automation and intelligent manufacturing layout planning.

[0024] Specifically, all models share the same input feature set to ensure that different models can understand the same circuit structure, including basic module information (ID, area, aspect ratio, functional category), connection relationships (which modules need to be connected), power data (average power consumption of each module) and initial coarse location. The output uses two-dimensional continuous coordinates (center point of each module) and a connection topology graph (implicit in the network structure, indicating which modules are connected) to represent candidate layout schemes. Each model runs inference independently to generate a set of candidate layout schemes.

[0025] Furthermore, based on optimized weights, multiple candidate layout schemes are merged to form an integrated circuit layout scheme, including the following steps: The objective function score for each candidate solution in each optimization dimension is calculated using a normalization method; We introduce optimization weights to output a weighted comprehensive score matching the objective function score of each candidate solution, and select the top K solutions with the highest comprehensive scores from all candidate solutions as alternatives; Construct a new comprehensive layout. For the set of module coordinates in each candidate scheme, calculate its centroid and align the coordinate system by coordinate translation (align the centroids and subtract the center coordinates). Calculate the weighted average position by taking a weighted average of K schemes and add the global offset (such as aligning to the lower left corner) to obtain the final comprehensive layout scheme.

[0026] Step 3: The virtual simulation of the integrated circuit layout scheme generates multi-source virtual optimization data. This virtual optimization data is then compared sequentially with standard data thresholds. This facilitates embedding standard threshold verification in the early optimization scheme determination stage, ensuring design compliance and reliability. If a match is found, a scheme determination signal is output; otherwise, an optimization weight adjustment signal is output. The difference between the virtual optimization data and the standard data thresholds is then compared to calculate and update the optimization weights. Optional input of optimization weights into the input window achieves closed-loop feedback and adaptive weight adjustment. Specifically: Virtual optimization data consists of simulated values ​​for multiple optimization dimensions, while standard data thresholds are values ​​for optimization dimensions that meet safety standards.

[0027] Specifically, the virtual simulation integrated circuit layout scheme generates multi-source virtual optimization data, which is then compared with standard data thresholds, including the following steps: Extract the location, size, type, and connection relationship of all modules in the comprehensive layout scheme, as well as process library information (metal layer stacking, minimum linewidth, via resistance, etc.) and power consumption model (average / peak power consumption of each module from RTL). Use scripted integration to encapsulate the data and perform batch simulations on a GPU server cluster. Generate a vector for each layout scheme. The vector includes line data (such as bus length), thermal data (such as maximum junction temperature and temperature standard deviation), and space data (such as area utilization).

[0028] Construct a standard threshold matrix (a key benchmark for judging whether a design scheme is compliant; it is not a fixed value, but a safety boundary dynamically set according to product category, process node, and application scenario), define the target range for each dimension, map multiple dimensions to multiple vectors, calculate the normalized deviation degree of each dimension, if any deviation degree does not match the deviation index, output an optimization weight adjustment signal, if all deviation degrees match the deviation index, output a scheme determination signal (the criteria for judging whether a vector is compliant include no deviation, slight exceedance, and severe exceedance; output a scheme determination signal when there is no deviation or slight exceedance, and output an optimization weight adjustment signal when there is severe exceedance).

[0029] Furthermore, by reverse-engineering and comparing the differences between the virtual optimized data and the standard data thresholds, the updated optimization weights are calculated, including the following steps: Determine the optimization direction for each dimension and clarify the upper or lower limits of the constraints for each dimension. For example, when optimizing wiring: the total wiring length and delay should be as small as possible; when optimizing heat dissipation: the maximum temperature and temperature difference should be as small as possible; when optimizing space: the area utilization rate should be as high as possible. The dimensions corresponding to the deviation index that do not match the degree of deviation are extracted. The normalized deviation ratio is used as the deviation measure. The normalized deviation index is used to obtain the correction priority (indicating the degree to which each dimension should be focused on in the next round). This is beneficial to automatically adjust the focus based on the results of each simulation. An exponential smoothing fusion strategy is adopted to control the balance between priority weights and deviation feedback. It can decay with the number of iterations until the output scheme determination signal is obtained to obtain the final updated weights.

[0030] Its second objective is to provide a machine learning-based integrated circuit layout optimization system, which applies to any of the above-mentioned machine learning-based integrated circuit layout optimization methods, including a weight customization module, a candidate layout fusion module, and a virtual simulation module. The weight customization module is used to establish an optimization weight input window to determine the optimization weights for multiple optimization dimensions, including line optimization, heat dissipation optimization, and space optimization. The candidate layout fusion module is used to train multi-source optimization dimension integrated circuit layout models using machine learning algorithms, output multiple candidate layout schemes, and fuse multiple candidate layout schemes based on optimization weights to form an integrated circuit layout scheme. The virtual simulation module is used to virtually simulate integrated circuit layout schemes to generate multi-source virtual optimization data. It compares the virtual optimization data with standard data thresholds in turn. If they match, it outputs a scheme determination signal; if they do not match, it outputs an optimization weight adjustment signal. It then compares the difference between the virtual optimization data and the standard data thresholds to calculate and update the optimization weights. It also allows for optional input of custom weights into the module.

[0031] In summary, this invention significantly improves the automation level, optimization quality, and iteration efficiency of integrated circuit layout design by constructing an intelligent optimization system based on "human-machine collaboration, multi-model division of labor, closed-loop feedback, and adaptive weighting." It addresses the long-standing pain points of traditional EDA tools, such as multi-objective trade-offs, high reliance on manual intervention, and lack of dynamic feedback. Specifically, this is manifested in the following ways: To enhance the intelligence and automation of design, the system can move from "manual trial and error" to "AI-driven closed-loop optimization". It can automatically identify non-compliant items and reverse-engineer the optimization weights without repeated manual intervention, reducing the reliance on the experience of senior engineers and enabling junior staff to efficiently complete high-quality layout designs. Enhance multi-objective collaborative optimization capabilities by decoupling complex layout problems into independent sub-models such as circuitry, heat dissipation, and space, each with its own function; each sub-model focuses on a specific objective (such as minimizing line length, controlling temperature rise, and improving utilization) to avoid mutual interference; and finally, a comprehensive solution is generated through weighted fusion to balance various indicators. Dynamic adaptive weight adjustment introduces a deviation index mechanism to quantify the gap between virtual simulation results and standard thresholds, automatically calculates the "correction priority" of each dimension, dynamically updates and optimizes weights, takes into account user preferences and system feedback, and prevents oscillations.

[0032] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A machine learning-based integrated circuit layout optimization method, characterized in that, Includes the following steps: An optimization weight input window is established to determine the optimization weights for multiple optimization dimensions, including line optimization, heat dissipation optimization, and space optimization. Machine learning algorithms are used to train multi-source optimization dimension integrated circuit layout models, output multiple candidate layout schemes, and then the multiple candidate layout schemes are merged based on optimization weights to form an integrated circuit layout scheme. The virtual simulation of integrated circuit layout schemes generates multi-source virtual optimization data. This virtual optimization data is then compared sequentially with standard data thresholds. If a match is found, a scheme determination signal is output; otherwise, an optimization weight adjustment signal is output. The difference between the virtual optimization data and the standard data thresholds is calculated and updated to determine the optimization weights. Optional input of optimization weights is then entered into the input window. The virtual optimization data consists of simulated values ​​for multiple optimization dimensions, and the standard data threshold is the value of the optimization dimension that meets the safety standard.

2. The integrated circuit layout optimization method based on machine learning according to claim 1, characterized in that: The optimization weight input window includes a self-selection window and an update input window. The self-selection window provides users with options to input optimization weights, and the update input window provides options to update optimization weights and historical optimization weights, and displays a confirmation option. When it is determined that the option is not checked, the priority of the self-selection window is higher than the priority of updating the input window; When selecting options, the priority of the auto-selection window is lower than that of the update input window.

3. The integrated circuit layout optimization method based on machine learning according to claim 2, characterized in that: The updated optimization weight is superior to the historical optimization weight, which is displayed in the update input window. The historical optimization weight is the historical record of the previous time node stored in the log.

4. The integrated circuit layout optimization method based on machine learning according to claim 1, characterized in that: The multi-source optimization dimension integrated circuit layout model includes: Collect a large number of circuit layout optimization schemes as training samples; The circuit optimization model is trained with the objective functions of minimizing bus length, reducing via count, and avoiding congestion. A heat dissipation optimization model is trained with the objective functions of minimizing hot spot temperature and temperature distribution uniformity. A space optimization model is trained with the objective functions of maximizing space utilization, minimizing blank fragments, and controlling aspect ratio, where: All models share the same input feature set and output candidate layout schemes represented using two-dimensional continuous coordinates and a connected topology graph. Each model runs inference independently and generates a set of candidate layout schemes.

5. The integrated circuit layout optimization method based on machine learning according to claim 4, characterized in that: The circuit optimization model adopts a graph attention network, which models the circuit netlist as a graph. Each node is associated with features, and the edges are connection requirements. The topological semantic features are extracted using GAT, and the high-dimensional embedding vector of each module is output to capture its role in the network. A Transformer decoder is introduced to gradually generate the module position offset. An autoregressive method is used to gradually generate the node positions to obtain a new layout. The model is trained to form a circuit optimization model and outputs candidate layout schemes that focus on electrical connections. The heat dissipation optimization model integrates infrared thermal imaging measured data and finite element simulation results as supervision labels, and combines a hybrid deep learning architecture that uses convolutional neural networks to process spatial power distribution features and graph neural networks to model the thermal coupling relationship between modules. In this architecture, CNN and GNN independently encode the spatial and topological information of the input, obtain their respective high-level feature representations, and then concatenate and fuse them before the fully connected layer to form a joint feature vector. The heat dissipation optimization model predicts the steady-state temperature field of complex electronic systems under different power consumption configurations and outputs candidate layout schemes for the temperature distribution of interest. The spatial optimization model uses a variational autoencoder to learn an efficient latent space representation of the layout. The decoder outputs a compact initial layout solution, which is then fine-tuned by a lightweight MLP to meet boundary constraints and train to form a spatial optimization model. The model outputs candidate layout schemes that focus on geometric utilization.

6. The integrated circuit layout optimization method based on machine learning according to claim 5, characterized in that: Based on optimized weights, multiple candidate layout schemes are merged to form an integrated circuit layout scheme, including the following steps: The objective function score for each candidate solution in each optimization dimension is calculated using a normalization method; We introduce optimization weights to output a weighted comprehensive score matching the objective function score of each candidate solution, and select the top K solutions with the highest comprehensive scores from all candidate solutions as alternatives; Construct a new comprehensive layout, calculate the centroid of the module coordinate set in each candidate scheme, and align the coordinate system by coordinate translation. Calculate the weighted average position by weighting the K schemes, add the global offset, and obtain the final comprehensive layout scheme.

7. The integrated circuit layout optimization method based on machine learning according to claim 6, characterized in that: The virtual simulation integrated circuit layout scheme generates multi-source virtual optimization data, which is then compared with standard data thresholds in sequence, including the following steps: Extract the position, size, type, connection relationship of all modules in the comprehensive layout scheme, as well as the process library information and power consumption model, encapsulate them using script-based integration, and perform batch simulations on the GPU server cluster. Each layout scheme generates a vector, which includes line data, heat dissipation data and space data. Construct a standard threshold matrix, define the target range for each dimension, map multiple dimensions to multiple vectors, calculate the normalized deviation of each dimension, and output an optimization weight adjustment signal if any deviation does not match the deviation index. If all deviations match the deviation index, output a scheme determination signal.

8. The integrated circuit layout optimization method based on machine learning according to claim 7, characterized in that: The process of comparing the difference between the virtual optimized data and the standard data threshold to calculate and update the optimization weights includes the following steps: Determine the optimization direction for each dimension and clarify the upper or lower bound constraints for each dimension; The dimensions corresponding to the deviation index are extracted to determine the degree of deviation. The normalized deviation ratio is used as the deviation measure. The normalized deviation index is used to obtain the correction priority. An exponential smoothing fusion strategy is adopted to control the balance between priority weight and deviation feedback. The weight can decay with the number of iterations until the output scheme determination signal is obtained, thus obtaining the final update weight.

9. A machine learning-based integrated circuit layout optimization system, applied to the machine learning-based integrated circuit layout optimization method according to any one of claims 1-8, characterized in that: It includes a weight customization module, a candidate layout fusion module, and a virtual simulation module; The weight customization module is used to establish an optimization weight input window to determine the optimization weights for multiple optimization dimensions, including line optimization, heat dissipation optimization, and space optimization. The candidate layout fusion module is used to train multi-source optimization dimension integrated circuit layout models using machine learning algorithms, output multiple candidate layout schemes, and fuse multiple candidate layout schemes based on optimization weights to form an integrated circuit layout scheme. The virtual simulation module is used to virtually simulate the integrated circuit layout scheme to form multi-source virtual optimization data. It compares the virtual optimization data with the standard data threshold in turn. If they match, it outputs a scheme determination signal. If they do not match, it outputs an optimization weight adjustment signal. It then compares the difference between the virtual optimization data and the standard data threshold to calculate and update the optimization weights. The module can also selectively input the weights into the custom weight module.

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