Lightweight neural network dynamic energy efficiency management method and system for edge FPGA

Abstract

The invention discloses a lightweight neural network dynamic energy efficiency management method and system for an edge FPGA, and the method specifically comprises the steps: carrying out the real-time monitoring and analysis of the complexity of a neural network task inputted to the FPGA, and building a corresponding relation model between the task complexity and a calculation load; a lightweight power consumption estimation model is embedded in the FPGA, dynamic power consumption is estimated in real time based on the current voltage, frequency and resource occupation state of the FPGA, and lightweight real-time power consumption estimation is achieved; a dynamic voltage and frequency regulation DVFS decision controller is designed, a preset energy efficiency optimization strategy table is inquired, and a voltage and frequency regulation instruction is generated; the power supply voltage and the working frequency are adjusted through a power supply management interface of the FPGA, and energy efficiency management of the FPGA neural network is achieved. According to the invention, while the resource utilization rate of the FPGA neural network is optimized, the voltage frequency switching delay is reduced, and the accuracy and management efficiency of energy efficiency management are improved.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuits and artificial intelligence technology, and in particular to a lightweight neural network dynamic energy efficiency management method and system for edge FPGAs. Background Technology

[0002] With the widespread deployment of artificial intelligence in edge computing scenarios such as the Internet of Things, autonomous driving, and industrial vision, FPGAs have become an important carrier for neural network inference tasks due to their reconfigurability, low latency, and high energy efficiency. However, edge devices typically face strict power budgets, heat dissipation limitations, and real-time requirements.

[0003] Currently, energy efficiency management technologies for FPGAs mainly have the following limitations:

[0004] Energy efficiency regulation is disconnected from task content: Traditional dynamic voltage and frequency regulation (DVFS) technology usually only uses macroscopic indicators such as overall chip temperature and average utilization rate for feedback control. It cannot perceive the inherent semantic complexity of the neural network task being executed, such as the number of targets in the image and signal quality. This causes the system to run at high performance when processing simple scenarios, resulting in energy waste; or when complex tasks suddenly appear, performance bottlenecks are generated due to response delays.

[0005] Insufficient real-time performance and accuracy of power consumption monitoring: Existing solutions mostly rely on off-chip measurements or models based on post-event statistics, which cannot make fast and lightweight real-time estimates of the dynamic power consumption inside the FPGA during the task execution cycle. This makes the dynamic voltage and frequency adjustment (DVFS) decision lack accurate real-time data support and is in a state of blind adjustment.

[0006] Passive response scheduling incurs performance penalties: mainstream methods employ a passive response mode that triggers voltage and frequency increases upon detecting high load. Due to the inherent delays of hundreds of nanoseconds to microseconds in voltage domain switching and phase-locked loop relocking, these delays directly add to the processing time of critical tasks, impacting system real-time performance.

[0007] Therefore, there is an urgent need to invent a new energy efficiency management scheme that can understand the task content, achieve accurate real-time power consumption perception, and proactively adjust the hardware status, so as to fully tap the energy efficiency potential of edge FPGAs in neural network computing. Summary of the Invention

[0008] The purpose of this invention is to provide a lightweight neural network dynamic energy efficiency management method and system for edge FPGAs that features strong real-time performance, high accuracy, low system power consumption, and high management efficiency.

[0009] The technical solution for achieving the objective of this invention is: a lightweight neural network dynamic energy efficiency management method for edge FPGAs, comprising the following steps:

[0010] Step 1: Monitor and analyze the complexity of the neural network task input to the FPGA in real time, quantify and output the computational load, and establish a correspondence model between task complexity and computational load.

[0011] Step 2: Embed a lightweight power consumption estimation model inside the FPGA to estimate dynamic power consumption in real time based on the current voltage, frequency and resource occupancy status of the FPGA, and implement lightweight real-time power consumption estimation in the FPGA logic.

[0012] Step 3: Design a Dynamic Voltage and Frequency Regulation (DVFS) decision controller. Based on the decision input composed of the calculated load, estimated dynamic power consumption, and prediction information of the next task, query the preset energy efficiency optimization strategy table to generate voltage and frequency regulation commands.

[0013] Step 4: According to the voltage and frequency adjustment instructions, adjust the power supply voltage and operating frequency through the FPGA power management interface to realize the energy efficiency management of the FPGA neural network.

[0014] Further, step 1 includes:

[0015] Step 1.1: Determine the first task sample input to the FPGA neural network. Item complexity features ,in, This is the index of the complexity feature. ,and The number of complexity features used;

[0016] Step 1.2: Determine complexity characteristics Weighting coefficients ;

[0017] Step 1.3: Calculate the computational load value of the FPGA. The formula is as follows:

[0018]

[0019] Further, step 1.1 includes:

[0020] Step 1.1.1, Feature Candidate Pool Construction: Initial Selection Task complexity features that affect workload include the number of target objects in the input data. The reciprocal of the signal-to-noise ratio of the input signal and the depth factor of the currently activated neural network model. This constitutes a candidate set of complexity features. ,in, Indicates the first One candidate complexity feature, , An index representing the candidate complexity feature. This represents the total number of candidate complexity features;

[0021] Step 1.1.2, Task Dataset Testing: The task dataset covers scenarios including open areas, congested areas, high-noise signals, and clear signals. The test dataset includes... For each task sample, during testing, record the candidate complexity features of each task sample. , Simultaneously measure and record the actual calculated load value. ;

[0022] Step 1.1.3, Correlation Analysis: Calculate candidate complexity features Compared with the actual calculated load value Pearson correlation coefficient :

[0023]

[0024] In the formula, Indicates the sequence number of the test sample. ; This represents the total number of task samples in the test dataset; For the first In the nth sample The numerical values ​​of each candidate complexity feature. For the first The actual computational load value for each sample; Indicates the first The average of each candidate complexity feature across all task samples. The actual calculated load value is the average value across all samples. ;

[0025] Step 1.1.4, Complexity Feature Filtering: The candidate complexity features are filtered according to... Sort by largest to smallest, select The two largest complexity features As the final determined complexity feature and .

[0026] Furthermore, the determination of complexity features described in step 1.2 Weighting coefficients The details are as follows:

[0027] Use the selected complexity features and the corresponding actual calculated load value The optimal weighting coefficients are fitted using the gradient descent method. .

[0028] Furthermore, the total number of candidate complexity features The number of complexity features used .

[0029] Furthermore, the dynamic power consumption estimation in step 2, based on the current voltage, frequency, and resource occupancy status of the FPGA, is calculated using the following formula:

[0030]

[0031] In the formula, This is the estimated dynamic power consumption value for the FPGA. This is the current operating voltage of the FPGA. This is the current operating frequency of the FPGA. This is the equivalent capacitance of the FPGA chip;

[0032] The comprehensive resource occupancy status factor is calculated based on the proportion of lookup table, register, and memory block resources actually occupied by the current task. The calculation formula is as follows:

[0033]

[0034] In the formula, Logical utilization is the ratio of the number of lookup tables actually used by the current task to the total number of lookup tables. The register activity rate is the proportion of triggers that undergo state transitions within a statistical period. This refers to the memory access rate, which is the proportion of clock cycles required to perform read / write operations on a block of RAM. DSP operating rate, which is the proportion of clock cycles in which the digital signal processing unit is in an effective operational state; , , , They are respectively , , , The weighting coefficients.

[0035] Furthermore, the pre-set energy efficiency optimization strategy table mentioned in step 3 is generated through offline optimization, with the optimization objective being to minimize the total system energy consumption while meeting the real-time deadlines of all tasks; the prediction information for the next task is obtained by parsing the data of the next task to be processed in the task processing queue.

[0036] Furthermore, the generation of voltage and frequency adjustment commands in step 3 is specifically as follows:

[0037] Step 3.1: The DVFS decision controller accesses the task queue descriptor located in the on-chip shared memory, reads the metadata of the next image frame to be processed in the queue, and thus predicts the complexity trend of the next task, forming a predicted load identifier. ;

[0038] Step 3.2: The DVFS decision controller will quantify the current computational load and the overall resource occupancy status factor. and predicted load identifier Together they form a joint query key to access the energy efficiency optimization strategy table;

[0039] Step 3.3: Access the query results of the energy efficiency optimization strategy table and directly output the target voltage. Target frequency The instructions.

[0040] Furthermore, step 4, which involves adjusting the power supply voltage and operating frequency through the FPGA's power management interface, is detailed as follows:

[0041] target voltage With target frequency The instructions are sent to the power management interface module, executed, and at the same time, instructions are issued to adjust the working point required for the next frame.

[0042] A lightweight neural network dynamic energy efficiency management system for edge FPGAs is disclosed. This system implements the aforementioned lightweight neural network dynamic energy efficiency management method for edge FPGAs. The system includes a model building module, a power consumption estimation module, a regulation instruction generation module, and an energy efficiency management module, wherein:

[0043] The model building module monitors and analyzes the complexity of the neural network task input to the FPGA in real time, quantifies and outputs the computational load, and establishes a model of the correspondence between task complexity and computational load.

[0044] The power consumption estimation module embeds a lightweight power consumption estimation model inside the FPGA. It estimates dynamic power consumption in real time based on the FPGA's current voltage, frequency, and resource occupancy status, and implements lightweight real-time power consumption estimation in the FPGA logic.

[0045] The regulation instruction generation module designs a dynamic voltage and frequency regulation (DVFS) decision controller. Based on the decision input composed of the calculated load, estimated dynamic power consumption, and prediction information of the next task, it queries the preset energy efficiency optimization strategy table to generate voltage and frequency regulation instructions.

[0046] The energy efficiency management module adjusts the power supply voltage and operating frequency through the FPGA's power management interface according to the voltage and frequency adjustment commands, thereby realizing the energy efficiency management of the FPGA neural network.

[0047] Compared with the prior art, the present invention has the following significant advantages: (1) It adopts a preset energy efficiency strategy table, adjusts the voltage and frequency operating points according to the complexity of the current task and the next task, and completes the adjustment in advance during the task gap through the power management interface, thereby optimizing resource utilization and reducing voltage and frequency switching delay, ensuring the real-time performance of energy efficiency management, reducing system power consumption, and saving system resources; (2) By combining task complexity perception, fine-grained real-time power consumption monitoring and predictive scheduling, the complexity of neural network tasks is used as the core basis for dynamic voltage and frequency adjustment, which has accurate real-time data support, improves the accuracy of energy efficiency management, and improves the efficiency of system energy efficiency management. Attached Figure Description

[0048] Figure 1 This is a flowchart of the lightweight neural network dynamic energy efficiency management method for edge FPGAs according to the present invention. Detailed Implementation

[0049] like Figure 1 As shown, the present invention provides a lightweight neural network dynamic energy efficiency management method for edge FPGAs, comprising the following steps:

[0050] Step 1: Monitor and analyze the complexity of the neural network task input to the FPGA in real time, quantify and output the computational load, and establish a correspondence model between task complexity and computational load.

[0051] Step 2: Embed a lightweight power consumption estimation model inside the FPGA to estimate dynamic power consumption in real time based on the current voltage, frequency and resource occupancy status of the FPGA, and implement lightweight real-time power consumption estimation in the FPGA logic.

[0052] Step 3: Design a Dynamic Voltage and Frequency Regulation (DVFS) decision controller. Based on the decision input composed of the calculated load, estimated dynamic power consumption, and prediction information of the next task, query the preset energy efficiency optimization strategy table to generate voltage and frequency regulation instructions.

[0053] Step 4: According to the voltage and frequency adjustment instructions, adjust the power supply voltage and operating frequency through the FPGA power management interface to realize the energy efficiency management of the FPGA neural network.

[0054] As a specific example, step 1 includes:

[0055] Step 1.1: Determine the first task sample input to the FPGA neural network. Item complexity features ;

[0056] Step 1.2: Determine complexity characteristics Weighting coefficients ;

[0057] Step 1.3: Calculate the computational load value of the FPGA. The formula is as follows:

[0058]

[0059] In the formula, This is the index of the complexity feature. The number of complexity features used, the The value is 2, meaning it has two complexity features.

[0060] As a specific example, step 1.1 includes:

[0061] Step 1.1.1, Feature Candidate Pool Construction: Initial Selection Task complexity features that affect workload include the number of target objects in the input data. The reciprocal of the signal-to-noise ratio of the input signal and the depth factor of the currently activated neural network model. This constitutes a candidate set of complexity features. ,in, Indicates the first One candidate complexity feature, , An index representing the candidate complexity feature. This represents the total number of candidate complexity features. ;

[0062] Step 1.1.2, Task Dataset Testing: The task dataset covers scenarios including open areas, congested areas, high-noise signals, and clear signals. The test dataset includes... For each task sample, during testing, record the candidate complexity features of each task sample. , Simultaneously measure and record the actual calculated load value. ;

[0063] Step 1.1.3, Correlation Analysis: Calculate candidate complexity features Compared with the actual calculated load value Pearson correlation coefficient :

[0064]

[0065] In the formula, Indicates the sequence number of the test sample. ; This represents the total number of task samples in the test dataset; For the first In the nth sample The numerical values ​​of each candidate complexity feature. For the first The actual computational load value for each sample; Indicates the first The average of each candidate complexity feature across all task samples. The actual calculated load value is the average value across all samples. ;

[0066] Step 1.1.4, Complexity Feature Filtering: The candidate complexity features are filtered according to... Sort by largest to smallest, select The two largest complexity features As the final determined complexity feature and .

[0067] As a specific example, step 1.2 describes determining the complexity features. Weighting coefficients The details are as follows:

[0068] Use the selected complexity features and the corresponding actual calculated load value The optimal weighting coefficients are fitted using the gradient descent method. .

[0069] As a specific example, the real-time estimation of dynamic power consumption based on the current voltage, frequency, and resource occupancy status of the FPGA in step 2 is calculated using the following formula:

[0070]

[0071] In the formula, This is the estimated dynamic power consumption value for the FPGA. This is the current operating voltage of the FPGA. This is the current operating frequency of the FPGA. This is the equivalent capacitance of the FPGA chip;

[0072] The comprehensive resource occupancy status factor is calculated based on the proportion of lookup table, register, and memory block resources actually occupied by the current task. The calculation formula is as follows:

[0073]

[0074] In the formula, Logical utilization is the ratio of the number of lookup tables actually used by the current task to the total number of lookup tables. The register activity rate is the proportion of triggers that undergo state transitions within a statistical period. This refers to the memory access rate, which is the proportion of clock cycles required to perform read / write operations on a block of RAM. DSP operating rate, which is the proportion of clock cycles in which the digital signal processing unit is in an effective operational state; , , , They are respectively , , , The weighting coefficients.

[0075] As a specific example, the preset energy efficiency optimization strategy table mentioned in step 3 is generated through offline optimization, and the optimization goal is to minimize the total energy consumption of the system while meeting the real-time deadlines of all tasks; the prediction information of the next task is obtained by parsing the data of the next task to be processed in the task processing queue.

[0076] As a specific example, the generation of voltage and frequency adjustment commands in step 3 is as follows:

[0077] Step 3.1: The DVFS decision controller accesses the task queue descriptor located in the on-chip shared memory, reads the metadata of the next image frame to be processed in the queue, and thus predicts the complexity trend of the next task, forming a predicted load identifier. ;

[0078] Step 3.2: The DVFS decision controller will quantify the current computational load and the overall resource occupancy status factor. and predicted load identifier Together they form a joint query key to access the energy efficiency optimization strategy table;

[0079] Step 3.3: Access the query results of the energy efficiency optimization strategy table and directly output the target voltage. Target frequency The instructions.

[0080] As a specific example, step 4, which involves adjusting the power supply voltage and operating frequency through the FPGA's power management interface, is detailed as follows:

[0081] target voltage With target frequency The instructions are sent to the power management interface module, executed, and at the same time, instructions are issued to adjust the working point required for the next frame.

[0082] As a concrete example, during task execution, the monitoring circuit continuously collects actual data. and In addition to being used for this estimation, it is also recorded and used for the periodic calibration and optimization of the power consumption estimation model and energy efficiency optimization strategy table in the offline stage, forming a closed loop.

[0083] This invention also provides a lightweight neural network dynamic energy efficiency management system for edge FPGAs. This system implements the aforementioned lightweight neural network dynamic energy efficiency management method for edge FPGAs. The system includes a model building module, a power consumption estimation module, a regulation instruction generation module, and an energy efficiency management module, wherein:

[0084] The model building module monitors and analyzes the complexity of the neural network task input to the FPGA in real time, quantifies and outputs the computational load, and establishes a model of the correspondence between task complexity and computational load.

[0085] The power consumption estimation module embeds a lightweight power consumption estimation model inside the FPGA. It estimates dynamic power consumption in real time based on the FPGA's current voltage, frequency, and resource occupancy status, and implements lightweight real-time power consumption estimation in the FPGA logic.

[0086] The regulation instruction generation module designs a dynamic voltage and frequency regulation (DVFS) decision controller. Based on the decision input composed of the calculated load, estimated dynamic power consumption, and prediction information of the next task, it queries the preset energy efficiency optimization strategy table to generate voltage and frequency regulation instructions.

[0087] The energy efficiency management module adjusts the power supply voltage and operating frequency through the FPGA's power management interface according to the voltage and frequency adjustment commands, thereby realizing the energy efficiency management of the FPGA neural network.

[0088] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0089] Example

[0090] This embodiment provides a lightweight neural network dynamic energy efficiency management method for edge FPGAs. This method is based on the Xilinx Zynq-7020 system-on-a-chip (SoC) platform. Figure 1 As shown, the method specifically includes the following steps:

[0091] Step 1: Monitor and analyze the complexity of the neural network task input to the FPGA in real time, thereby quantifying and outputting its computational load, and establishing a correspondence model between task complexity and computational load, as follows:

[0092] Step 1.1: Determine the complexity characteristics of the neural network task input to the FPGA. The details are as follows:

[0093] Step 1.1.1, Feature Candidate Pool Construction: Initial Selection Task complexity features that affect workload include the number of target objects in the input data. The reciprocal of the signal-to-noise ratio of the input signal and the depth factor of the currently activated neural network model. This constitutes a candidate set of complexity features. ,in An index representing the candidate complexity feature. ;

[0094] Step 1.1.2, Task Dataset Testing: The task dataset covers scenarios including open areas, congested areas, high-noise signals, and clear signals, and includes... For each task sample, during testing, the complexity characteristics of each task sample are recorded. (include , and Simultaneously measure and record the actual calculated load value. .

[0095] Step 1.1.3, Correlation Analysis: Calculate the complexity features for each candidate. Compared with the actual calculated load value Pearson correlation coefficient :

[0096]

[0097] In the formula, For the first Candidate complexity features in each sample , For the first The actual computational load value for each sample , ;

[0098] Step 1.1.4, Complexity Feature Filtering: The candidate complexity features are filtered according to... Sort by largest to smallest, select The two largest complexity features As the final determined complexity feature and .

[0099] Step 1.2: Determine the weighting coefficients The details are as follows:

[0100] Use the selected complexity features and the corresponding measured calculated load value The optimal weighting coefficients are fitted using the gradient descent method. ;

[0101] Step 1.3: Calculate the computational load value of the FPGA. The formula is as follows:

[0102]

[0103] In the formula, To calculate the load value, For the first Complexity features These are the normalized weight coefficients corresponding to the complexity features.

[0104] In this embodiment, the determined task complexity feature is the number of target objects in the input data. and the depth factor of the currently activated neural network model The computational load value obtained from modeling The calculation formula is:

[0105]

[0106] Step 2: Embed a lightweight power estimation model within the FPGA. Based on the FPGA's current voltage, frequency, and resource occupancy status, estimate dynamic power consumption in real time. Implement lightweight real-time power estimation within the FPGA logic. The formula is:

[0107]

[0108] In the formula, For the dynamic power consumption of the FPGA, This is the current operating voltage. The current operating frequency, In this embodiment, the equivalent capacitance of the FPGA is... ; The resource occupancy status factor is calculated based on the proportion of lookup table, register, and memory block resources actually used by the current task. The calculation formula is as follows:

[0109]

[0110] In the formula, Logical utilization is the ratio of the number of lookup tables actually used by the current task to the total number of available lookup tables. The register activity rate is the proportion of triggers that undergo state transitions within a statistical period. This refers to the memory access rate, which is the proportion of clock cycles required to perform read / write operations on a block of RAM. DSP operating rate, which is the proportion of clock cycles in which the digital signal processing unit is in an effective operational state; , , , These are weighting coefficients. In this embodiment, It is divided into three levels: low (0.1-0.4), medium (0.4-0.7), and high (0.7-1.0).

[0111] Step 3: Design a Dynamic Voltage and Frequency Regulation (DVFS) decision controller. Based on the decision input, which is composed of calculated load, estimated dynamic power consumption, and prediction information of the next task, query the preset energy efficiency optimization strategy table to generate voltage and frequency regulation instructions, as follows:

[0112] Step 3.1: The controller accesses the task queue descriptor located in the on-chip shared memory, reads the metadata of the next image frame to be processed in the queue, thereby predicting the complexity trend of the next task and forming a predicted load identifier. ;

[0113] Step 3.2: The controller will quantify the current computing load and resource occupancy status factors. and predicted load identifier Together they form a joint query key to access the preset strategy table;

[0114] Step 3.3: Access the query results of the preset decision table and directly output the target voltage. With target frequency The instructions.

[0115] As a specific example, the preset energy efficiency optimization strategy table is generated through offline optimization, as detailed below:

[0116] (1) Constructing the training task set and discretizing the parameter space: The task set covers various task complexities from low to high. and resource occupancy status factor combination In this embodiment, the task set covers Available in three strengths: 0.7, 1.0, and 1.5. The range is from 0 to 20, with a step size of 2; simultaneously, the operating point space supported by the FPGA is discretized, i.e., a series of feasible voltages are determined. With frequency right ,in, , The frequency range is 50MHz~300MHz with a step size of 10MHz. The external power supply provides the FPGA with an adjustable voltage in the range of 0.85V~1.00V with a step size of 5mV.

[0117] (2) Define the mathematical model of the optimization objective and constraints:

[0118] Optimization objective: Minimize the total system energy consumption. For a given task... and work site In this embodiment, the energy consumption estimation is performed as follows: Task execution time Depend on Decide, These are calibration coefficients;

[0119] Core constraint: Task real-time deadline constraint. A maximum allowed execution time is set for each training task. The required execution time is the estimated time for the selected work point. ;

[0120] Physical constraints: The operating point must meet the following requirements. as well as ,in The minimum voltage required to ensure stable operation of the circuit at this frequency;

[0121] (3) Perform optimization search and strategy table filling: For each task in the training task set Iterate through all discretized working points ,use Estimated energy consumption And use a performance model to estimate the execution time. In all satisfied Among the constrained operating points, select the one that maximizes energy consumption. The smallest working point is denoted as ,Will As a composite index key, The resulting values ​​are populated into the strategy table, as shown in Table 1:

[0122] Table 1 Preset Strategy Table (Fragment)

[0123]

[0124] (4) Strategy verification and smoothing: The generated strategy table is tested on an independent verification task set to evaluate its energy efficiency improvement and real-time performance guarantee; In this embodiment, in order to prevent query jitter, the optimization working points of adjacent indexes in the table are smoothed and filtered to ensure the robustness of the strategy.

[0125] In the initial stage of the system, it runs by default. The baseline model, for the current frame, estimates The controller simultaneously accesses the task queue descriptor located in the on-chip shared memory, reads the metadata of the next image frame to be processed in the queue, and thus predicts the complexity trend of the next task, forming a predicted load identifier. Predicting the next frame It may rise to 12, therefore... Set to "Raise";

[0126] In this embodiment, the controller will quantize the current computational load, i.e. Resource occupancy status factor This refers to the medium level and the predicted load indicator. The terms "increase" and "rise" together form a joint query key, which accesses the preset strategy table, and the query result is directly output as the target voltage. With target frequency The instruction is (0.90V, 200MHz).

[0127] Step 4: According to the voltage and frequency adjustment commands, adjust the power supply voltage and operating frequency of the FPGA through the FPGA's power management interface to realize the energy efficiency management of the FPGA neural network, as follows:

[0128] The target voltage output by the preset decision table With target frequency The instructions are sent to the power management interface module for execution. Simultaneously, the system will issue instructions in advance to adjust the operating point required for the next frame. When the load is indicated to be "increasing," the decision will predictively jump to a higher load strategy, and the controller will simulate queries ( , To predict the state of the next frame, the operating point (0.5V, 250MHz) is obtained, and the operating point is switched to this point in advance to ensure timeliness. When the next frame arrives, the FPGA is already running stably at (0.5V, 250MHz), and the neural network can process the frame at full performance, with an actual processing time of 24.1ms. Simultaneously, the monitoring circuit sends the complete data tuple of this round of execution (...) , , , Actual power consumption and actual latency are written to the buffer for subsequent optimization.

[0129] As a concrete example, during task execution, the monitoring circuit continuously collects actual data. and Besides being used for this estimation, the data is also recorded and used for periodic calibration and optimization of the power consumption model and policy mapping table during offline phases, forming a continuously self-improving closed-loop system. In this embodiment, the system starts a background optimization task at midnight every 24 hours, transferring more than 100,000 data points recorded in the past 24 hours from the buffer to the memory. Using the new dataset, linear regression is rerun to correct the power consumption model parameters. The system identifies combinations that occur frequently but are not perfectly covered by the current policy table, and supplements the policy table for these high-frequency scenarios to improve the policy table.

[0130] This embodiment uses a typical urban road scenario with 24-hour traffic flow changes as an example. Table 2 shows a comparison of the core performance of the method of this invention compared to the traditional fixed high-performance operating point scheme (0.98V, 280MHz). It can be seen that the method of this invention reduces average power consumption by 41.7%, and the task frame processing timeout rate drops from 0.5% in the fixed low-frequency scheme to 0, effectively meeting the reliability requirements of edge applications. During nighttime periods with sparse traffic, the system automatically degrades to [a specific frequency range]. The lightweight model can save up to 31% more energy.

[0131] Table 2 Comparison of core performance of the system described in this invention with traditional fixed high-performance operating point solutions.

[0132]

[0133] This invention combines task complexity awareness, fine-grained real-time power consumption monitoring, and predictive scheduling. It uses the complexity of neural network tasks as the core basis for dynamic voltage and frequency adjustment, forms real-time feedback through embedded lightweight power consumption estimation, and adopts predictive scheduling to effectively reduce voltage and frequency switching delay. Thus, it achieves global energy consumption minimization while ensuring the real-time performance of high-load tasks.

[0134] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A lightweight neural network dynamic energy efficiency management method for edge FPGAs, characterized in that, Includes the following steps: Step 1: Monitor and analyze the complexity of the neural network task input to the FPGA in real time, quantify and output the computational load, and establish a correspondence model between task complexity and computational load. Step 2: Embed a lightweight power consumption estimation model inside the FPGA to estimate dynamic power consumption in real time based on the current voltage, frequency and resource occupancy status of the FPGA, and implement lightweight real-time power consumption estimation in the FPGA logic. Step 3: Design a Dynamic Voltage and Frequency Regulation (DVFS) decision controller. Based on the decision input composed of the calculated load, estimated dynamic power consumption, and prediction information of the next task, query the preset energy efficiency optimization strategy table to generate voltage and frequency regulation commands. Step 4: According to the voltage and frequency adjustment instructions, adjust the power supply voltage and operating frequency through the FPGA power management interface to realize the energy efficiency management of the FPGA neural network.

2. The lightweight neural network dynamic energy efficiency management method for edge FPGA according to claim 1, characterized in that, Step 1 includes: Step 1.1: Determine the first task sample input to the FPGA neural network. Item complexity features ,in, This is the index of the complexity feature. ,and The number of complexity features used; Step 1.2: Determine complexity characteristics Weighting coefficients ; Step 1.3: Calculate the computational load value of the FPGA. The formula is as follows: 。 3. The lightweight neural network dynamic energy efficiency management method for edge FPGA according to claim 2, characterized in that, Step 1.1 includes: Step 1.1.1, Feature Candidate Pool Construction: Initial Selection Task complexity features that affect workload include the number of target objects in the input data. The reciprocal of the signal-to-noise ratio of the input signal and the depth factor of the currently activated neural network model. This constitutes a candidate set of complexity features. ,in, Indicates the first One candidate complexity feature, , An index representing the candidate complexity feature. This represents the total number of candidate complexity features; Step 1.1.2, Task Dataset Testing: The task dataset covers scenarios including open areas, congested areas, high-noise signals, and clear signals. The test dataset includes... For each task sample, during testing, record the candidate complexity features of each task sample. , Simultaneously measure and record the actual calculated load value. ; Step 1.1.3, Correlation Analysis: Calculate candidate complexity features Compared with the actual calculated load value Pearson correlation coefficient : In the formula, Indicates the sequence number of the test sample. ; This represents the total number of task samples in the test dataset; For the first In the nth sample The numerical values ​​of each candidate complexity feature. For the first The actual computational load value for each sample; Indicates the first The average of each candidate complexity feature across all task samples. The actual calculated load value is the average value across all samples. ; Step 1.1.4, Complexity Feature Filtering: The candidate complexity features are filtered according to... Sort by largest to smallest, select The two largest complexity features As the final determined complexity feature and .

4. The lightweight neural network dynamic energy efficiency management method for edge FPGA according to claim 3, characterized in that, Step 1.2 describes determining the complexity features. Weighting coefficients The details are as follows: Use the selected complexity features and the corresponding actual calculated load value The optimal weighting coefficients are fitted using the gradient descent method. .

5. The lightweight neural network dynamic energy efficiency management method for edge FPGA according to claim 4, characterized in that, Total number of candidate complexity features The number of complexity features used .

6. The lightweight neural network dynamic energy efficiency management method for edge FPGA according to claim 5, characterized in that, The dynamic power consumption estimation in real time based on the current voltage, frequency, and resource occupancy status of the FPGA, as described in step 2, is calculated using the following formula: In the formula, This is the estimated dynamic power consumption value for the FPGA. This is the current operating voltage of the FPGA. This is the current operating frequency of the FPGA. This is the equivalent capacitance of the FPGA chip; The comprehensive resource occupancy status factor is calculated based on the proportion of lookup table, register, and memory block resources actually occupied by the current task. The calculation formula is as follows: In the formula, Logical utilization is the ratio of the number of lookup tables actually used by the current task to the total number of lookup tables. The register activity rate is the proportion of triggers that undergo state transitions within a statistical period. Memory access rate, which is the proportion of clock cycles used to perform read / write operations on a block of RAM; DSP operating rate, which is the proportion of clock cycles in which the digital signal processing unit is in an effective operational state; , , , They are respectively , , , The weighting coefficients.

7. The lightweight neural network dynamic energy efficiency management method for edge FPGA according to claim 6, characterized in that, The preset energy efficiency optimization strategy table mentioned in step 3 is generated through offline optimization. The optimization goal is to minimize the total energy consumption of the system while meeting the real-time deadlines of all tasks. The prediction information of the next task is obtained by parsing the data of the next task to be processed in the task processing queue.

8. The lightweight neural network dynamic energy efficiency management method for edge FPGA according to claim 7, characterized in that, The generation of voltage and frequency adjustment commands in step 3 is as follows: Step 3.1: The DVFS decision controller accesses the task queue descriptor located in the on-chip shared memory, reads the metadata of the next image frame to be processed in the queue, and thus predicts the complexity trend of the next task, forming a predicted load identifier. ; Step 3.2: The DVFS decision controller will quantify the current computational load and the overall resource occupancy status factor. and predicted load identifier Together they form a joint query key to access the energy efficiency optimization strategy table; Step 3.3: Access the query results of the energy efficiency optimization strategy table and directly output the target voltage. Target frequency The instructions.

9. The lightweight neural network dynamic energy efficiency management method for edge FPGA according to claim 8, characterized in that, Step 4 involves adjusting the power supply voltage and operating frequency via the FPGA's power management interface, as detailed below: target voltage With target frequency The command is sent to the power management interface module, the command is executed, and at the same time, a command is issued to adjust the working point required for the next frame.

10. A lightweight neural network dynamic energy efficiency management system for edge FPGAs, characterized in that, This system is used to implement the lightweight neural network dynamic energy efficiency management method for edge FPGA as described in any one of claims 1 to 9. The system includes a model building module, a power consumption estimation module, a regulation instruction generation module, and an energy efficiency management module, wherein: The model building module monitors and analyzes the complexity of the neural network task input to the FPGA in real time, quantifies and outputs the computational load, and establishes a model of the correspondence between task complexity and computational load. The power consumption estimation module embeds a lightweight power consumption estimation model inside the FPGA. It estimates dynamic power consumption in real time based on the FPGA's current voltage, frequency, and resource occupancy status, and implements lightweight real-time power consumption estimation in the FPGA logic. The regulation instruction generation module designs a dynamic voltage and frequency regulation (DVFS) decision controller. Based on the decision input composed of the calculated load, estimated dynamic power consumption, and prediction information of the next task, it queries the preset energy efficiency optimization strategy table to generate voltage and frequency regulation instructions. The energy efficiency management module adjusts the power supply voltage and operating frequency through the FPGA's power management interface according to the voltage and frequency adjustment commands, thereby realizing the energy efficiency management of the FPGA neural network.

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