Laser chip

Abstract

The invention provides a laser chip. The laser chip comprises a semiconductor epitaxial structure and a solder preset structure arranged on one side of a positive electrode of the semiconductor epitaxial structure. The solder preset structure comprises an isolation groove, an insulation passivation layer and a metal solder layer. The isolation groove is etched downwards from one side of the positive electrode and at least penetrates through the active region; the insulating passivation layer covers the side wall and the bottom surface of the isolation groove and extends inwards to cover part of the edge of the positive electrode to form an insulating dam, and an electric injection window is reserved in the center; the metal solder layer is arranged in the electric injection window, the edge of the metal solder layer is overlapped on the insulation dam, and the outer edge of the metal solder layer retracts inwards relative to the upper edge of the isolation groove. According to the invention, a triple short circuit prevention mechanism is constructed by using the isolation groove, the insulating medium and the metal solder layer of which the edge is shrunk inwards and lapped, so that the possibility that molten solder overflows and is communicated with the side wall of the active region during reflow soldering is avoided, and high-reliability flip packaging is realized.

Description

Technical Field

[0001] This application relates to the field of laser technology, specifically to a laser chip. Background Technology

[0002] Semiconductor lasers are typically packaged using P-down flip-chip technology to optimize heat dissipation. Traditional flip-chip packaging processes often involve pre-fabricating a large-area solder layer (such as gold-tin solder) of a certain thickness on the surface of the heat sink. This not only wastes expensive metal materials and significantly increases the cost of heat sink preparation and overall packaging, but also makes it difficult to precisely control the uniformity of the solder layer thickness.

[0003] During the high-temperature placement process of reflow soldering, molten solder in its molten state is prone to overflowing towards the chip edge due to its own gravity and the mechanical pressure of the placement process. Since the chip sidewalls (especially near the dicing track) usually have laterally conductive active regions (i.e., PN junctions) and exposed semiconductor layers, once the overflowing solder climbs up and contacts the active region sidewalls, it can easily lead to severe device short-circuit failure. This greatly reduces the yield of wafer-level packaging and the long-term operational reliability of the device. Summary of the Invention

[0004] Therefore, it is necessary to provide a laser chip to solve at least one of the above-mentioned technical problems.

[0005] This application provides a laser chip, including a semiconductor epitaxial structure and a solder pre-placement structure disposed on one side of the positive electrode of the semiconductor epitaxial structure. The solder pre-formed structure includes an isolation trench, an insulating passivation layer, and a metal solder layer; The isolation trench is etched downwards from the positive electrode side along the depth direction, penetrating at least the active region of the semiconductor epitaxial structure; An insulating passivation layer continuously covers the sidewalls and bottom surface of the isolation trench, extends inward and covers part of the edge area of ​​the positive electrode to form an insulating dam, and leaves an uncovered electrical injection window in the central area of ​​the positive electrode. The metal solder layer is located within the electrical injection window, and the edge of the metal solder layer overlaps on the insulating dam. The outer edge of the metal solder layer is recessed inward relative to the upper edge of the isolation trench.

[0006] Thus, by utilizing the isolation trench penetrating the active region, the insulating medium wrapping the trench sidewalls, and the metal solder layer overlapping the insulating dam with its edges recessed, a triple short-circuit protection mechanism combining physical blocking and surface tension current limiting is structurally constructed. During reflow soldering, the molten solder automatically contracts and gathers within the recessed area, physically preventing the solder from overflowing and connecting to the active region sidewalls, thereby achieving highly reliable flip-chip packaging.

[0007] Furthermore, the semiconductor epitaxial structure, from the negative electrode side to the positive electrode side, sequentially includes: a semiconductor substrate, an N-type semiconductor epitaxial layer, an active region, and a P-type semiconductor epitaxial layer; The isolation trench penetrates the P-type semiconductor epitaxial layer, the active region, and the N-type semiconductor epitaxial layer in sequence, and extends downward and terminates inside the semiconductor substrate; the isolation trench physically cuts off the lateral connection of the active region.

[0008] In this way, not only is reliable electrical isolation established at the chip edge, but the lateral transmission of cutting stress to the active area is also effectively blocked during subsequent wafer dicing, providing excellent stress isolation protection for the core light-emitting area.

[0009] Furthermore, the outer edge of the metal solder layer is recessed inward relative to the upper edge of the isolation trench to form an inward distance L, the value of which ranges from 5μm to 50μm; The overall thickness of the metal solder layer is 2μm to 5μm.

[0010] Thus, the lower limit thickness provides the necessary volume buffer for eliminating solder voids and maintaining the eutectic phase; while the upper limit thickness, combined with the set inward distance, effectively prevents excess liquid metal from exceeding the critical value of surface tension bearing capacity, establishing the maximum safe volume basis for preventing solder overflow.

[0011] Furthermore, the surface material of the insulating passivation layer is non-wetting to the molten metal solder layer, so as to physically block the liquid metal from crossing the insulating dam and flowing into the isolation trench during reflow soldering, in conjunction with the inward distance L.

[0012] In this way, even if the liquid solder is subjected to mechanical pressure from the patch, the non-wetting principle can be used to firmly confine the solder to the inside of the insulating dam, further enhancing the effect of preventing overflow short circuits.

[0013] Furthermore, the metal solder layer includes an adhesion layer, a barrier layer, a main solder layer, and an anti-oxidation cap layer stacked from bottom to top.

[0014] Thus, through a multi-layered composite metal system, multiple physical and chemical requirements for interfacial bonding, diffusion prevention, eutectic bonding, and oxidation prevention in flip-chip welding are simultaneously met.

[0015] Furthermore, the adhesion layer is made of Ti or Cr; the barrier layer is made of dense Pt, Ni or W to prevent Sn atoms in the main solder layer from diffusing into the semiconductor during reflow soldering and long-term operation; and the anti-oxidation cap layer is made of pure Au.

[0016] In this way, the problem of bonding between metal and semiconductor is solved, and the dense barrier layer effectively blocks the electromigration and thermal diffusion of Sn atoms, preventing device aging and failure. The pure gold layer ensures soldering wettability under flux-free conditions.

[0017] Furthermore, the composition of the main solder layer is controlled near the Au80 / Sn20 eutectic point; the solder pre-placement structure is configured to allow the laser chip to be directly mounted on the heat sink without pre-placed solder in a flip-chip manner with the P-side down, and the metal solder layer and the heat sink are eutectic bonded by heating and reflow.

[0018] In this way, the heat sink no longer needs to undergo costly thick solder plating, directly reducing the cost of heat sink preparation and overall product packaging. At the same time, the wafer-level deposition process significantly improves the consistency of solder thickness.

[0019] Furthermore, a stress balancing layer is deposited on the side of the laser chip closest to the negative electrode. The stress balancing layer has stresses that are opposite to those of the metal solder layer, and is used to balance the thin film stresses generated by the metal solder layer on the wafer to prevent wafer warping.

[0020] In this way, the physical and mechanical balance mechanism effectively offsets the huge thin film stress generated by the thick metal solder layer on the thinned wafer, preventing severe warping or even microcracks in the wafer and ensuring the smooth progress of subsequent processes.

[0021] Furthermore, isolation trenches are distributed around the perimeter of a single chip, and the center line of the bottom surface of the isolation trenches is configured as the cutting path for mechanical cutting or laser scribing. An insulating passivation layer completely encapsulates the sidewalls of the isolation trench, serving to physically prevent metal extension or burrs generated during the cutting process from contacting the sidewalls of the active area.

[0022] In this way, even if a small amount of metal extension or burrs are generated during the wafer dicing process, they will be physically blocked from the outside by the insulating medium, and the burrs will not be able to contact the active area, thus achieving wafer-level non-destructive dicing with zero short-circuit risk.

[0023] Furthermore, the laser chip includes edge-emitting lasers, vertical-cavity surface-emitting lasers, horizontal-cavity surface-emitting lasers, or photonic crystal surface-emitting lasers.

[0024] Thus, since the core triple short-circuit protection mechanism of this application does not depend on a specific laser resonator structure, it indicates that the wafer-level packaging structure based on deep trench isolation on the positive electrode side and solder shrinkage design has extremely strong versatility and platform attributes, and can widely meet the packaging needs of various semiconductor light-emitting chips that require flip-chip mounting and have high requirements for chip sidewall PN junction protection and short-circuit protection. Attached Figure Description

[0025] The accompanying drawings are for illustrative purposes only and should not be construed as limiting this patent; the same reference numerals are used for components with the same structure and function. Wherein: Figure 1 This is a schematic diagram of a two-dimensional cross-sectional structure of a laser chip provided in one embodiment of this application; Figure 2 This is a three-dimensional partial schematic diagram of the junction (cutting channel area) between adjacent chips during wafer-level manufacturing process provided in one embodiment of this application; Explanation of reference numerals in the attached figures: 10 - Laser chip; Z - Depth direction; 100 - Semiconductor substrate; 101 - N-type semiconductor epitaxial layer; 102 - Active region; 103 - P-type semiconductor epitaxial layer; 104 - Positive electrode; 105 - Negative electrode; 200 - Isolation trench; 201 - Trench sidewall; 202 - Trench bottom surface; 300 - Insulating passivation layer; 301 - Electrical injection window; 302 - Insulating dam; 400 - Metal solder layer; 401 - Adhesion layer; 402 - Barrier layer; 403 - Main solder layer; 404 - Antioxidant cap layer. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; "and / or" in this text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.

[0027] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0028] In the description of this embodiment, unless otherwise stated, "a plurality of" means two or more.

[0029] like Figure 1 , Figure 2As shown, this application provides a laser chip 10, which adopts a P-down flip-chip package design. Structurally, the laser chip 10 mainly includes a semiconductor epitaxial structure as the light-emitting body, and a solder pre-placement structure deeply integrated into the flip-chip mounting surface (i.e., the positive electrode side). For ease of description, the direction from the front side of the chip (i.e., the positive electrode 104 side) to the back side (i.e., the negative electrode 105 side) is defined as the depth direction Z.

[0030] It should be noted that Figure 1 shows in detail the multi-layered fine structure inside the metal solder layer 400 (such as the adhesion layer 401, barrier layer 402, main solder layer 403, and anti-oxidation cap layer 404) and the relative spatial relationships of their overall thickness H and inward distance L. Furthermore, in the figure, to clearly illustrate the topological boundaries and electrical connections of each film layer, the insulating passivation layer 300 (and the insulating dam 302 extending inward to cover the edge of the positive electrode 104 to form it) is simplified as a thicker, darker solid line. However, in actual semiconductor physical structures, it is a solid dielectric thin film layer with a certain physical thickness (e.g., 200 nm to 500 nm) prepared using processes such as vapor deposition.

[0031] like Figure 1 As shown, the semiconductor epitaxial structure of the laser chip 10, stacked sequentially from bottom to top in the reverse depth direction Z, includes: a negative electrode 105, a semiconductor substrate 100, an N-type semiconductor epitaxial layer 101, an active region 102 for generating laser gain, a P-type semiconductor epitaxial layer 103, and a positive electrode 104.

[0032] It is understood that, as a complete light-emitting device, the aforementioned P-type semiconductor epitaxial layer 103 may, in specific implementations, include composite films such as a P-type confinement layer, a P-type waveguide layer, and a P-type ohmic contact layer; correspondingly, the N-type semiconductor epitaxial layer 101 may also include composite films such as an N-type buffer layer, an N-type confinement layer, and an N-type waveguide layer. This application does not impose specific limitations in this regard.

[0033] A solder pre-placement structure is disposed on the positive electrode 104. The structure is divided into three closely fitted sub-units: an isolation trench 200 for physical cutting, an insulating passivation layer 300 for providing insulating protection, and a micro-recessed metal solder layer 400.

[0034] It should be noted that, Figure 2 This is a three-dimensional partial schematic diagram of the junction (dicing area) between adjacent chips during the wafer-level manufacturing process provided in this application embodiment. It highlights the three-dimensional spatial relationship between the isolation trench 200, the insulating passivation layer 300, and the metal solder layer 400. Figure 2The semiconductor epitaxial structure shown below is simplified and abstracted, without detailed differentiation of each semiconductor film layer. The actual layer stacking order and etching depth relationships in this application are presented in [the original text is missing]. Figure 1 The cross-sectional view shown is the standard.

[0035] A. Isolation trenches and insulation passivation structures Combination Figure 1 and Figure 2 It can be seen that the isolation trenches 200 are distributed around the edges of a single chip, and in the wafer manufacturing stage, they actually form the dicing channels between two adjacent chips.

[0036] It should be noted that, Figure 1 The diagram shows a two-dimensional cross-section of a single chip. The isolation trenches 200 on its left and right sides are actually two-dimensional cross-sectional shapes of continuous trenches surrounding the chip, which is consistent with... Figure 2 The deep trench structure shown in the three-dimensional stereoscopic view corresponds perfectly in physical space.

[0037] In terms of in-depth design, such as Figure 1 As shown, the isolation trench 200 is etched downwards along the depth direction Z from the positive electrode 104 side, sequentially penetrating the P-type semiconductor epitaxial layer 103, the active region 102, and the N-type semiconductor epitaxial layer 101, and finally extending downwards and terminating inside the semiconductor substrate 100 (i.e., without penetrating the substrate). Here, "penetration" refers to completely severing all light-emitting epitaxial layer structures along the depth direction Z, rather than penetrating the entire semiconductor substrate 100, thus ensuring that the wafer maintains sufficient mechanical support strength before subsequent mechanical dicing. Figure 2 As shown, this deep Z-groove structure completely severs the lateral connection of the active region 102 in physical space, which not only establishes reliable electrical isolation, but also blocks the transmission of cutting stress to the active region 102 when mechanical scribing or laser cutting is performed along the bottom surface 202 of the groove, thus establishing excellent stress isolation protection.

[0038] The insulating passivation layer 300 uses a dense dielectric material (such as SiN, SiO2, etc.). Figure 1 As shown, the insulating passivation layer 300 continuously covers the sidewalls 201 and bottom surface 202 of the isolation trench 200. Furthermore, the insulating passivation layer 300 extends inward and covers a portion of the edge region of the positive electrode 104, leaving only an electrical injection window 301 uncovered by the insulating medium in the central region of the positive electrode 104. Physically, this ring of solid portion covered by the insulating passivation layer 300 at the edge of the positive electrode 104 forms an insulating dam 302.

[0039] B. Metal solder layer like Figure 1 and Figure 2As shown, the metal solder layer 400 employs an inward-curving edge design. Its outer edge does not cover the entire surface of the positive electrode 104, but rather recedes inward relative to the physical edge of the isolation trench 200. The edge of the metal solder layer 400 overlaps (or is crimped) onto the insulating dam 302.

[0040] The main function of the metal solder layer 400 is to pre-plat the solder directly on the positive electrode side of the wafer, so that no more solder is needed during subsequent packaging. The connection can be achieved by heating and reflowing, which makes the entire soldering process more precise and easier to control.

[0041] The metal solder layer 400 is preferably deposited directly within the electrical injection window 301 using electron beam evaporation or sputtering processes. This deposition process involves depositing multiple layers of metal material (such as an adhesion layer 401, a barrier layer 402, a main solder layer 403, and an anti-oxidation cap layer 404) using electron beam evaporation or sputtering. Alternatively, the material can be partially deposited on the insulating dam 302. This layered structure can be a Ti / Pt / AuSn / Au composite system.

[0042] like Figure 1 As shown, the metal solder layer 400 mainly comprises four physical units: an adhesion layer 401, a barrier layer 402, a main solder layer 403, and an anti-oxidation cap layer 404. These four units are physically stacked, but functionally independent or hierarchically related. In this embodiment, the overall deposition thickness of the metal solder layer 400 is defined as H. Thickness H is a key parameter determined through thermodynamic calculations and process verification, and its value is strictly controlled between 2 μm and 5 μm. This specific thickness range is not arbitrarily chosen, but is the optimal solution determined based on the following deep interface metallurgy and fluid dynamics mechanisms: On one hand, the lower limit of H is set at 2μm based on the physical requirements of eliminating solder voids and maintaining the eutectic phase. Typical flip-chip heat sinks (such as AlN or CuW) inevitably have micro-roughness (Ra is typically on the order of 0.5μm to 1μm). If the overall solder thickness is less than 2μm, the volume of the molten liquid metal will be insufficient to completely fill the micro-valves on the heat sink surface, easily forming closed air voids at the solder interface, leading to fatal abrupt changes in thermal resistance. More importantly, during the high-temperature reflow soldering process, the underlying gold (Au) on the heat sink surface and the chip surface dissolves into the solder layer. If the solder layer is too thin, this dissolution causes a sharp increase in the gold content within the solder, rapidly deviating from the Au80 / Sn20 eutectic point, resulting in a sharp increase in the solder melting point and premature solidification, causing a cold solder joint. The 2μm lower thickness limit provides a necessary volumetric buffer for this metal-to-metal interfusion.

[0043] On the other hand, the upper limit of H is set at 5μm, based on a dual consideration of thin film stress control and overflow critical volume. First, the coefficient of thermal expansion of metal layers such as AuSn alloys differs significantly from that of semiconductor substrates. When a metal layer thicker than 5μm is prepared on a thinned wafer through evaporation or sputtering processes, the enormous thin film stress will cause severe warpage or even microcracks in the entire wafer, making subsequent wafer dicing impossible. Second, this is closely related to the core overflow prevention structure of this application: when the metal solder layer 400 melts, the insulating dam 302 uses non-wetting properties and surface tension to support the liquid metal, but the surface tension has a hydrodynamic upper limit. If the solder thickness exceeds 5μm, the weight of the liquid solder itself and the mechanical extrusion volume during reflow will exceed the critical value of surface tension, causing excess liquid metal to overflow the insulating dam 302 and flow into the isolation trench 200. Therefore, the upper limit thickness of 5μm is the maximum safe volume to ensure the effective operation of the triple short-circuit protection mechanism.

[0044] Among them, the main solder layer 403 (usually Au80 / Sn20) accounts for the largest proportion in thickness H, and plays the main role in connection and filling.

[0045] Adhesion layer 401 (such as Ti or Cr): Its core function is to solve the problem of "bonding force" at the metal-semiconductor interface.

[0046] Barrier layer 402 (such as Pt, Ni or W): It is configured to prevent Sn atoms in the solder from diffusing into the semiconductor during high-temperature reflow soldering and long-term operation, thus preventing device failure.

[0047] Main solder layer 403 (such as AuSn alloy): Its composition is controlled near the Au80 / Sn20 eutectic point, and its thickness is designed to be 2μm to 5μm. This thickness is sufficient to compensate for the micro-roughness of the heat sink surface, while avoiding excessive thickness that could cause wafer warping.

[0048] Anti-oxidation capping layer 404 (such as pure Au): Its function is to prevent Sn oxidation and ensure solder wettability under flux-free conditions.

[0049] The metal solder layer 400 employs an edge-recessed design. Specifically, the outer edge of the solder layer does not cover the entire front side of the chip (mount surface), but rather recedes inward relative to the upper edge of the isolation trench 200 (the chip's physical boundary), forming a recessed distance L. The recessed parameter L is preferably between 5 μm and 50 μm. This microstructure establishes the basis for preventing solder overflow. Within this region, the edge of the metal solder layer 400 directly covers the surface of the insulating dam 302.

[0050] During reflow soldering, the molten solder automatically contracts and gathers within the metal layer. The inwardly recessed area at the edges prevents solder from diffusing outward, thus preventing solder overflow and also blocking solder flow to the outside. Utilizing the non-wetting property of liquid metal on the surface of the insulating passivation layer 300, the possibility of solder flowing to the chip sidewalls is physically eliminated. In addition, even if a small amount of metal extension or burrs are generated during wafer dicing, since the dicing location is at the bottom of the isolation trench 200 and the trench sidewalls are completely covered by the insulating passivation layer 300, the metal burrs cannot contact the sidewalls of the active region 102, thereby achieving wafer-level dicing with zero short-circuit risk.

[0051] It should be noted that, although Figure 1 and Figure 2 While the stress balancing layer is not explicitly shown, in some optional embodiments of this application, to further balance the thin-film stress generated by the thick metal solder layer 400 on the wafer and prevent wafer warping, a stress balancing layer may also be deposited on the side of the laser chip 10 near the negative electrode 105 (e.g., disposed between the semiconductor substrate 100 and the negative electrode 105, or directly deposited on the outer surface of the negative electrode 105). This stress balancing layer can be a specific dielectric film (such as silicon dioxide, silicon nitride, etc.) or a metal film, configured to have internal stresses opposite to the thin-film stress properties of the metal solder layer 400. Those skilled in the art will understand that, as an optional means of chip backside stress compensation, this layer is extremely thin and does not affect front-side light emission and flip-chip bonding. To concisely highlight the core short-circuit protection structure of this application, it is omitted from the drawings, which does not affect the understanding and implementation of the overall technical solution of this application by those skilled in the art.

[0052] C. Manufacturing method This application also provides a method for manufacturing a laser chip, which, by way of example, is implemented through the following steps: S1. An isolation trench penetrating the active region is etched on the positive electrode side of the wafer to physically sever the lateral connection of the PN junction.

[0053] Specifically, a complete wafer with epitaxial growth and front-side processing is provided. On the positive electrode side of the wafer (i.e., the starting point side in the aforementioned Z direction), the pattern position of the isolation trench 200 is defined using photolithography, corresponding to the dicing paths between individual chips. Subsequently, an inductively coupled plasma (ICP) dry etching process is used to etch downwards, strictly controlling the etching depth to penetrate the plane containing the active region 102 and extend to a deeper depth. This step establishes the basis for physical isolation, severing the lateral connections of the PN junction and creating conditions for subsequent non-destructive dicing.

[0054] S2. An insulating passivation layer is deposited on the positive electrode side of the wafer, and an electrical injection window is opened to form an insulating dam.

[0055] Specifically, a plasma-enhanced chemical vapor deposition (PECVD) process is used to deposit an insulating passivation layer 300 on the entire positive electrode side of the wafer. Utilizing the swirling deposition characteristics of vapor deposition, the insulating material completely covers the front surface of the wafer as well as the sidewalls and bottom of the isolation trench 200. Subsequently, through photolithography and etching (RIE) processes, only the insulating layer in the central region of each chip cell is removed to form an electrical injection window 301, while retaining the insulating layer near the trench edge and inside the trench, thereby forming an insulating dam surrounding the chip and achieving electrical isolation protection for the chip edge.

[0056] S3. Deposit a layer of metal solder with recessed edges on the electrical injection window and part of the insulating dam.

[0057] Specifically, using electron beam evaporation or sputtering processes, combined with photolithography lift-off technology, a multilayer metal structure is deposited on the electro-injection window 301 and part of the insulating dam on the positive electrode side of the wafer to form a metal solder layer 400. In this step, through precise design of the photolithographic mask, the edge of the metal layer extends outward relative to the opening of the insulating layer, but is strictly controlled to retract inward relative to the upper edge of the isolation trench 200, thereby forming an inward-recessed region (inward-recessed distance L). This microstructure establishes the basis for preventing solder overflow. During this process, special attention is paid to the dense deposition of the barrier layer 402, ensuring that there are no pinholes to effectively block the diffusion of tin atoms.

[0058] S4. Cut along the center line at the bottom of the isolation trench to obtain an independent chip unit with pre-placed solder.

[0059] Specifically, mechanical cutting or laser scribing is performed along the centerline of the bottom surface 202 of the isolation trench 200. Because the cutting path is located at the bottom of the deep trench, far from the active area 102 and the solder layer 400, the stress generated during cutting is blocked by the trench sidewalls, and the cutting tool does not touch the solder layer, thus completely avoiding short circuits and stress damage caused by cutting burrs. After cutting, an independent chip unit with pre-applied solder is obtained, which can be directly used for subsequent flip-chip packaging.

[0060] S5. The single chip with a pre-applied solder layer is directly soldered and fixed to the heat sink.

[0061] Specifically, the single chip is flip-chip mounted onto the heat sink. The heat sink surface only needs a basic metallization layer (such as titanium / platinum / gold), without the need for a pre-applied solder layer of considerable thickness. During reflow soldering, the chip's built-in solder layer 400 melts and forms a eutectic bond with the heat sink. Due to the presence of the recessed region, the molten solder is firmly confined within the metallization area at the bottom of the chip and does not rise to the chip's sidewalls.

[0062] In this way, by using wafer-level dry etching, vapor deposition and photolithography stripping processes, high-precision, mass production of chips with pre-placed solder and short-circuit protection structures is achieved. Its processing accuracy is far higher than that of traditional heat sink mask processes, which significantly reduces packaging costs while significantly improving device consistency and yield.

[0063] D. Beneficial effects Compared with the prior art, the beneficial effects of this application are: A triple short-circuit protection mechanism is implemented: through "physical isolation + dielectric isolation + distance isolation". The depth of the deep trench is greater than the depth of the active area, completely severing the physical connection of the PN junction; the insulating layer completely wraps the trench sidewalls, so even if solder overflows, a short circuit cannot occur; the solder layer edge is recessed by 5-50μm, away from the cutting track, eliminating the risk of metal extension during mechanical cutting.

[0064] High reliability and yield: By introducing a dense Pt / Ni barrier layer 402, the electromigration and thermal diffusion of Sn atoms are effectively blocked, solving the problem of device aging failure easily caused by wafer-level solder. The pure Au cap layer enables flux-free soldering, avoiding flux contamination of the optical surface, making it particularly suitable for EEL and VCSEL.

[0065] It offers the advantages of both low cost and high precision: by using wafer-level photolithography (accuracy ±1μm) to replace the traditional heat sink-level mask process (accuracy ±50μm), it significantly improves device consistency while reducing costs. Furthermore, the heat sink eliminates the need for costly solder plating, directly reducing heat sink manufacturing costs and ultimately achieving significant cost savings for the entire chip packaging product.

[0066] Furthermore, it is important to emphasize that the triple short-circuit protection wafer-level packaging structure proposed in this application, based on deep trench isolation on the positive electrode side and solder indentation design, possesses extremely strong versatility and platform attributes. Its core short-circuit protection mechanism does not rely on a specific laser resonator structure. Therefore, the laser chip of this application is not only applicable to edge-emitting lasers (EELs) and vertical-cavity surface-emitting lasers (VCSELs), but also widely applicable to various novel semiconductor light-emitting chips such as horizontal-cavity surface-emitting lasers (HCSELs) and photonic crystal surface-emitting lasers (PCSELs). Any semiconductor optoelectronic device requiring flip-chip mounting and with high requirements for chip sidewall PN junction protection and short-circuit protection can adopt the structural scheme described in this application and fall within the protection scope of this application.

[0067] In the description of this embodiment, unless otherwise stated, "a plurality of" means two or more. The above content is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A laser chip, characterized in that, It includes a semiconductor epitaxial structure and a solder pre-placement structure disposed on one side of the positive electrode of the semiconductor epitaxial structure. The solder pre-formed structure includes an isolation trench, an insulating passivation layer, and a metal solder layer; The isolation trench is etched downwards along the depth direction from the positive electrode side, penetrating at least the active region of the semiconductor epitaxial structure; The insulating passivation layer continuously covers the sidewalls and bottom surface of the isolation trench, extends inward and covers part of the edge region of the positive electrode to form an insulating dam, and leaves an uncovered electrical injection window in the central region of the positive electrode. The metal solder layer is disposed within the electrical injection window, and the edge of the metal solder layer overlaps the insulating dam, with the outer edge of the metal solder layer retracting inward relative to the upper edge of the isolation trench.

2. The laser chip according to claim 1, characterized in that, The semiconductor epitaxial structure, from the negative electrode side to the positive electrode side, sequentially includes: a semiconductor substrate, an N-type semiconductor epitaxial layer, an active region, and a P-type semiconductor epitaxial layer; The isolation trench penetrates the P-type semiconductor epitaxial layer, the active region, and the N-type semiconductor epitaxial layer in sequence, and extends downward and terminates inside the semiconductor substrate; the isolation trench physically severs the lateral connection of the active region.

3. The laser chip according to claim 1, characterized in that, The outer edge of the metal solder layer is recessed inward relative to the upper edge of the isolation trench to form an inward distance L, the value of which ranges from 5μm to 50μm; The overall thickness of the metal solder layer is 2 μm to 5 μm.

4. The laser chip according to claim 3, characterized in that, The surface material of the insulating passivation layer is non-wetting to the molten metal solder layer, so that during reflow soldering, it physically prevents the liquid metal from crossing the insulating dam and flowing into the isolation trench in conjunction with the inward distance L.

5. The laser chip according to claim 1, characterized in that, The metal solder layer comprises an adhesion layer, a barrier layer, a main solder layer, and an anti-oxidation cap layer stacked from bottom to top.

6. The laser chip according to claim 5, characterized in that, The adhesion layer is made of Ti or Cr; the barrier layer is made of dense Pt, Ni or W to prevent Sn atoms in the main solder layer from diffusing into the semiconductor during reflow soldering and long-term operation; the anti-oxidation cap layer is made of pure Au.

7. The laser chip according to claim 5, characterized in that, The composition of the main solder layer is controlled near the Au80 / Sn20 eutectic point; the solder pre-placement structure is configured to allow the laser chip to be directly mounted on a heat sink without pre-placed solder in a flip-chip manner with the P-side down, and the metal solder layer and the heat sink are eutectic bonded by heating and reflow.

8. The laser chip according to claim 1, characterized in that, A stress balancing layer is deposited on the side of the laser chip near the negative electrode. The stress balancing layer has stresses that are opposite in nature to those of the metal solder layer, and is used to balance the thin film stresses generated by the metal solder layer on the wafer to prevent wafer warping.

9. The laser chip according to claim 1, characterized in that, The isolation trenches are distributed around the perimeter of the single chip, and the center line of the bottom surface of the isolation trenches is configured as the cutting path of mechanical cutting or laser scribing. The insulating passivation layer that completely covers the sidewall of the isolation trench is used to physically prevent metal extension or burrs generated during the cutting process from contacting the sidewall of the active area.

10. The laser chip according to any one of claims 1 to 9, characterized in that, The laser chip includes an edge-emitting laser, a vertical-cavity surface-emitting laser, a horizontal-cavity surface-emitting laser, or a photonic crystal surface-emitting laser.

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