Power amplifier driving circuit and control method thereof

Abstract

The invention provides a power amplifier driving circuit and a control method thereof, which are used for converting a PWM (Pulse Width Modulation) signal into a driving level and comprise a high-side driving circuit, a low-side driving circuit and a detection control module. The high-side driving circuit comprises a first pre-stage driving circuit and a first post-stage driving circuit; the first pre-stage driving circuit is used for converting the PWM signal into a high-side driving signal; the first post-stage driving circuit comprises a first additional driving module which is used for enhancing a high-side driving signal. The low-side driving circuit comprises a second pre-stage driving circuit and a second post-stage driving circuit, and the second pre-stage driving circuit is used for converting the PWM signal into a low-side driving signal. The second post-stage driving circuit comprises a second additional driving module which is used for enhancing the low-side driving signal. And the detection control module is used for detecting the duty ratio of the PWM signal and controlling the starting and closing of the first additional driving module and the second additional driving module according to a comparison result of the duty ratio and a duty ratio set value.

Description

Technical Field

[0001] This application relates to the field of driver circuits, and more particularly to a power amplifier driver circuit and its control method. Background Technology

[0002] Class D audio amplifiers typically employ a driver circuit including a level shifter and inverters, requiring strong driving capability. The PWM signal is converted to the required drive level for the output transistor (thin-gate transistor) after passing through the level shifter, and then further enhanced by successive inverter stages. Driving the power transistors demands strong driving capability from the driver circuit, usually achieved by adding multiple inverter stages. However, when the signal is small or the circuit needs to operate in a low-power state, the added inverter stages increase power consumption, thus reducing the efficiency of the Class D amplifier. Summary of the Invention

[0003] This application provides a power amplifier driver circuit and its control method, which can determine whether to enhance the circuit's driving capability based on the received PWM signal.

[0004] In a first aspect, this application provides a power amplifier driver circuit for converting a PWM signal into a drive level, including:

[0005] A high-side drive circuit is connected to a first power supply terminal and includes a first pre-stage drive circuit, a first post-stage drive circuit, and a first output terminal. The first pre-stage drive circuit is connected to a PWM signal input terminal and is used to convert the PWM signal into a high-side drive signal. The input terminal of the first post-stage drive circuit is connected to the output terminal of the first pre-stage drive circuit. The first post-stage drive circuit includes a first additional drive module, which is used to enhance the high-side drive signal. The first output terminal is used to output the high-side drive signal.

[0006] A low-side drive circuit is connected to a first ground terminal and includes a second pre-stage drive circuit, a second post-stage drive circuit, and a second output terminal. The second pre-stage drive circuit is connected to the PWM signal input terminal and is used to convert the PWM signal into a low-side drive signal. The input terminal of the second post-stage drive circuit is connected to the output terminal of the second pre-stage drive circuit. The second post-stage drive circuit includes a second additional drive module, which is used to enhance the low-side drive signal. The second output terminal is used to output the low-side drive signal.

[0007] The detection control module is used to detect the duty cycle of the PWM signal and control the activation and deactivation of the first additional drive module and the second additional drive module based on the comparison result between the duty cycle and the duty cycle setting value.

[0008] The first pre-amplifier driver circuit converts the PWM signal into a high-side drive signal and outputs it through the first output terminal. The second pre-amplifier driver circuit converts the PWM signal into a low-side drive signal and outputs it through the second output terminal. A detection and control module detects the duty cycle of the PWM signal. When the duty cycle of the PWM signal is small, the power amplifier driver circuit operates in a small-signal state, at which time the first and second auxiliary drive modules are turned off to reduce the power of the power amplifier driver circuit. When the duty cycle of the PWM signal is large, the power amplifier driver circuit operates in a large-signal state, at which time the first and second auxiliary drive modules are turned on to enhance the circuit's driving capability and achieve high performance and high reliability.

[0009] Optionally, the first post-stage driving circuit further includes a first control driving circuit, which is used to acquire the high-side driving signal output by the first pre-stage driving circuit and control the activation and deactivation of the first additional driving module according to the high-side driving signal output by the first pre-stage driving circuit.

[0010] The second post-stage drive circuit further includes a second control drive circuit, which is used to acquire the low-side drive signal output by the second pre-stage drive circuit and control the activation and deactivation of the second additional drive module according to the low-side drive signal.

[0011] Optionally, the first control drive circuit includes a multi-stage series inverter and a multi-stage parallel NMOS transistor. The input terminal of the multi-stage series inverter is connected to the output terminal of the first pre-stage drive circuit. The sources of the multiple NMOS transistors are all connected to the second ground terminal, the drains are all connected to the output terminal of the first pre-stage drive circuit, and the gates are all connected to the output terminal of the multi-stage series inverter.

[0012] The second control drive circuit includes a multi-stage series inverter and a multi-stage parallel NMOS transistor. The input terminal of the multi-stage series inverter is connected to the output terminal of the second pre-stage drive circuit. The sources of the multiple NMOS transistors are all connected to the second ground terminal, the drains are all connected to the output terminal of the second pre-stage drive circuit, and the gates are connected to the output terminal of the multi-stage series inverter.

[0013] Optionally, the first additional driving module includes a first additional driving circuit and a second additional driving circuit, and the output terminal of the detection control module is connected to the first additional driving circuit and the second additional driving circuit respectively, for controlling the activation and deactivation of the first additional driving circuit and the second additional driving circuit.

[0014] Wherein, when the first additional driving circuit is enabled, the second additional driving circuit is disabled; when the first additional driving circuit is disabled, the second additional driving circuit is enabled.

[0015] The second additional drive module includes a third additional drive circuit and a fourth additional drive circuit. The output terminal of the detection control module is connected to the input terminal of the third additional drive circuit and the input terminal of the fourth additional drive circuit, respectively, for controlling the simultaneous activation and deactivation of the second additional drive circuit and the fourth additional drive circuit.

[0016] Specifically, when the third additional driving circuit is enabled, the fourth additional driving circuit is disabled; when the third additional driving circuit is disabled, the fourth additional driving circuit is enabled.

[0017] Optionally, the first additional driving circuit includes multiple PMOS transistors connected in parallel, with the source of each PMOS transistor connected to the second power supply terminal, the drain connected to the output terminal of the first pre-stage driving circuit, and the gate connected to the output terminal of the detection and control module.

[0018] The third additional driving circuit includes multiple parallel PMOS transistors, with the source of each PMOS transistor connected to the second power supply terminal, the drain connected to the output terminal of the second pre-stage driving circuit, and the gate connected to the output terminal of the detection and control module.

[0019] Optionally, the second additional driving circuit includes multiple NMOS transistors connected in parallel, with the source of each NMOS transistor connected to the second ground terminal, the drain connected to the output terminal of the first pre-stage driving circuit, and the gate connected to the output terminal of the detection and control module.

[0020] The fourth additional driving circuit includes multiple NMOS transistors connected in parallel. The sources of the multiple NMOS transistors are connected to the second ground terminal, the drains are connected to the output terminal of the first pre-stage driving circuit, and the gates are connected to the output terminal of the detection and control module.

[0021] Optionally, the detection and control module is also used to receive at least one of the following protection signals: over-temperature protection signal, over-current protection signal, and short-circuit protection signal;

[0022] When one of the at least one protection signal is an abnormal signal, the detection control module controls the first additional drive module and the second additional drive module to be enabled.

[0023] Optionally, a mode selection circuit is included, wherein the input terminal of the mode selection circuit is used to receive the PWM signal, and the output terminal of the mode selection circuit is connected to the detection and control module;

[0024] The mode selection circuit includes multiple operating modes, each corresponding to a different duty cycle setting value.

[0025] The mode selection circuit is used to select different operating modes based on the duty cycle of the PWM signal and output different duty cycle setting values ​​to the detection and control module.

[0026] Secondly, a control method for a power amplifier drive circuit as described in the first aspect includes:

[0027] Obtain the comparison result between the duty cycle of the PWM signal and the duty cycle setting value;

[0028] When the duty cycle is less than or equal to the duty cycle setting value, the first additional drive module and the second additional drive module are controlled to shut down;

[0029] When the duty cycle is greater than the duty cycle setting value, the first additional drive module and the second additional drive module are enabled.

[0030] When the duty cycle of the PWM signal is small, the power amplifier drive circuit operates in a small-signal state. At this time, the first and second auxiliary drive modules are turned off, reducing the power of the power amplifier drive circuit. When the duty cycle of the PWM signal is large, the power amplifier drive circuit operates in a large-signal state. At this time, the first and second auxiliary drive modules are turned on, enhancing the circuit's driving capability to achieve high performance and high reliability.

[0031] Optionally, the power amplifier drive circuit includes different operating modes, and the control method further includes:

[0032] Different operating modes of the power amplifier drive circuit are selected based on the duty cycle of the PWM signal.

[0033] Different duty cycle settings are determined according to different operating modes of the power amplifier drive circuit.

[0034] Optional, also includes:

[0035] Acquire at least one of the following protection signals: over-temperature protection signal, over-current protection signal, and short-circuit protection signal;

[0036] When one of the at least one protection signal is an abnormal signal, the first additional drive module and the second additional drive module are activated. Attached Figure Description

[0037] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0038] Figure 1 The diagram shown is a schematic diagram of one embodiment of the power amplifier driver circuit of this application.

[0039] Figure 2 The diagram shown is a schematic diagram of another embodiment of the power amplifier driver circuit of this application.

[0040] Figure 3 The diagram shown is a schematic diagram of an embodiment of the first stage driver circuit of the power amplifier driver circuit of this application.

[0041] Figure 4 The diagram shown is a schematic representation of an embodiment of the second stage driver circuit of the power amplifier driver circuit of this application.

[0042] Figure 5 The diagram shown is a schematic representation of an embodiment of the control method for a power amplifier drive circuit according to this application.

[0043] Figure 6 The diagram shown is a schematic diagram of another embodiment of the control method for power amplifier drive circuits according to this application.

[0044] Explanation of reference numerals in the attached figures:

[0045] Power amplifier driver circuit 100; high-side driver circuit 110; first preamplifier driver circuit 111; first power amplifier driver circuit 112; first auxiliary driver module 1121; first output terminal 113; first control driver circuit 114; inverter 1141; NMOS transistor 1142; low-side driver circuit 120; second preamplifier driver circuit 121; second power amplifier driver circuit 122; second auxiliary driver module 1221; second output terminal 123; second control driver circuit 124; inverter 1241; NMOS transistor 12 42; Detection and control module 130; Status detection circuit 131; Control circuit 132; First auxiliary drive circuit 141; PMOS transistor 1411; Second auxiliary drive circuit 142; NMOS transistor 1421; Third auxiliary drive circuit 143; PMOS transistor 1431; Fourth auxiliary drive circuit 144; NMOS transistor 1441; Mode selection circuit 150; Over-temperature protection signal input terminal 161; Over-current protection signal input terminal 162; Short circuit protection signal input terminal 163; PWM signal input terminal 170;

[0046] First power supply terminal PVCC; first ground terminal PGND; second power supply terminal VCC; second ground terminal GND. Detailed Implementation

[0047] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0048] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movements between components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0049] This application provides a power amplifier driver circuit 100, see [link to relevant documentation] Figure 1 As shown, it is used to convert the PWM signal into a drive level. The power amplifier drive circuit 100 includes a high-side drive circuit 110, a low-side drive circuit 120, and a detection and control module 130.

[0050] The high-side drive circuit 110 is connected to the first power supply terminal PVCC and includes a first pre-stage drive circuit 111, a first post-stage drive circuit 112, and a first output terminal 113. The first pre-stage drive circuit 111 is connected to the PWM signal input terminal 170 and is used to convert the PWM signal into a high-side drive signal. The first pre-stage drive circuit 111 includes a level shifting circuit and a multi-stage inverter. The input terminal of the first post-stage drive circuit 112 is connected to the output terminal of the first pre-stage drive circuit 111. The first post-stage drive circuit 112 includes a first auxiliary drive module 1121, which is used to enhance the high-side drive signal. The high-side drive circuit 110 includes an NMOS transistor. The drain of the NMOS transistor is connected to the first power supply terminal PVCC, the gate of the NMOS transistor is connected to the output terminal of the first post-stage drive circuit 112, and the source of the NMOS transistor is the first output terminal 113, which is used to output the high-side drive signal.

[0051] The low-side drive circuit 120 is connected to the first ground terminal PGND and includes a second pre-stage drive circuit 121, a second post-stage drive circuit 122, and a second output terminal 123. The second pre-stage drive circuit 121 is connected to the PWM signal input terminal 170 and is used to convert the PWM signal into a low-side drive signal. The second pre-stage drive circuit 121 includes a level shifting circuit and a multi-stage inverter. The input terminal of the second post-stage drive circuit 122 is connected to the output terminal of the second pre-stage drive circuit 121. The second post-stage drive circuit 122 includes a second additional drive module 1221, which is used to enhance the low-side drive signal. The high-side drive circuit 110 includes an NMOS transistor. The gate of the NMOS transistor is connected to the first ground terminal PGND and the output terminal of the first post-stage drive circuit 112. The drain of the NMOS transistor is the second output terminal 123, which is used to output the low-side drive signal.

[0052] The detection and control module 130 includes a state detection circuit 131 and a control circuit 132. The state detection circuit 131 detects the duty cycle of the PWM signal. The control circuit 132 controls the activation and deactivation of the first auxiliary drive module 1121 and the second auxiliary drive module 1221 based on the comparison result between the duty cycle of the PWM signal detected by the state detection circuit 131 and the duty cycle set value. When the duty cycle of the PWM signal is small, the power amplifier drive circuit 100 operates in a small signal state. At this time, the first auxiliary drive module 1121 and the second auxiliary drive module 1221 are deactivated to reduce the power of the power amplifier drive circuit 100. When the duty cycle of the PWM signal is large, the power amplifier drive circuit 100 operates in a large signal state. At this time, the first auxiliary drive module 1121 and the second auxiliary drive module 1221 are activated to enhance the circuit's driving capability and achieve high performance and high reliability.

[0053] In an optional embodiment, see Figure 2 As shown, the first post-stage drive circuit 112 further includes a first control drive circuit 114. The first control drive circuit 114 is used to acquire the high-side drive signal output by the first pre-stage drive circuit 111, and control the activation and deactivation of the first auxiliary drive module 1121 according to the high-side drive signal output by the first pre-stage drive circuit 111.

[0054] When the high-side drive signal output by the first pre-stage driver circuit 111 is high, the first auxiliary driver module 1121 is turned off. When the high-side drive signal output by the first pre-stage driver circuit 111 is low, the first auxiliary driver module 1121 is turned on to connect the high-side drive signal output by the first pre-stage driver circuit 111 to the second ground terminal GND, so as to quickly pull down the high-side drive signal output by the first output terminal 113.

[0055] See Figure 3As shown, specifically, the first control drive circuit 114 includes a multi-stage series inverter 1141 and a multi-stage parallel NMOS transistor 1142. The input terminal of the multi-stage series inverter 1141 is connected to the output terminal of the first pre-stage drive circuit 111. The sources of the multiple NMOS transistors 1142 are all connected to the second ground terminal GND, the drains are all connected to the output terminal of the first pre-stage drive circuit 111, and the gates are all connected to the output terminal of the multi-stage series inverter.

[0056] When the high-side drive signal output by the first pre-stage driver circuit 111 is high, the high-level high-side drive signal is converted to a low level by the multi-stage series inverter 1141, the multi-stage NMOS transistor 1142 is turned off, and the first auxiliary driver module 1121 is shut down. When the high-side drive signal output by the first pre-stage driver circuit 111 is low, the high-level high-side drive signal is converted to a high level by the multi-stage series inverter, the drain and source of the multi-stage NMOS transistor 1142 are turned on, so as to connect the high-side drive signal output by the first pre-stage driver circuit 111 to the second ground terminal GND, so as to quickly pull down the high-side drive signal output by the first output terminal 113.

[0057] In an optional embodiment, see Figure 2 As shown, the second post-stage drive circuit 122 also includes a second control drive circuit 124. The second control drive circuit 124 is used to acquire the low-side drive signal output by the second pre-stage drive circuit 121, and control the activation and deactivation of the second additional drive module 1221 according to the low-side drive signal.

[0058] When the low-side drive signal output by the second pre-stage driver circuit 121 is high, the second auxiliary driver module 1221 is turned off. When the high-side drive signal output by the second pre-stage driver circuit 121 is low, the second auxiliary driver module 1221 is turned on to connect the low-side drive signal output by the second pre-stage driver circuit 121 to the second ground terminal GND, so as to quickly pull down the low-side drive signal output by the second output terminal 123.

[0059] See Figure 4As shown, specifically, the second control drive circuit 124 includes a multi-stage series inverter 1241 and a multi-stage parallel NMOS transistor 1242. The input terminal of the multi-stage series inverter 1241 is connected to the output terminal of the second pre-stage drive circuit 121. The sources of the multiple NMOS transistors 1242 are all connected to the second ground terminal GND, the drains are all connected to the output terminal of the second pre-stage drive circuit 121, and the gates are connected to the output terminal of the multi-stage series inverter. The number of multi-stage series inverters 1141 in the first control drive circuit 114 is equal to the number of multi-stage series inverters 1241 in the second control drive circuit 124; the number of multi-stage parallel NMOS transistors 1142 in the first control drive circuit 114 is also equal to the number of multi-stage parallel NMOS transistors 1242 in the second control drive circuit 124. This ensures that the duration of the high-side drive signal output from the first output terminal 113 by the first control drive circuit 114 is consistent with the duration of the low-side drive signal output from the second output terminal 123 by the second control drive circuit 124.

[0060] When the low-side drive signal output by the second pre-stage drive circuit 121 is high, the high-level low-side drive signal is converted to a low level by the multi-stage series inverter 1241, the multi-stage NMOS transistor 1242 is turned off, and the second auxiliary drive module 1221 is shut down. When the low-side drive signal output by the second pre-stage drive circuit 121 is low, the high-level low-side drive signal is converted to a high level by the multi-stage series inverter 1241, the drain and source of the multi-stage NMOS transistor 1242 are turned on, so as to connect the low-side drive signal output by the second pre-stage drive circuit 121 to the second ground terminal GND, so as to quickly pull down the low-side drive signal output by the second output terminal 123.

[0061] With the above settings, when the high-side drive signal output by the first preamplifier drive circuit 111 is low, it can quickly pull down the high-side drive signal output by the first output terminal 113; when the low-side drive signal output by the second preamplifier drive circuit 121 is low, it can quickly pull down the low-side drive signal output by the second output terminal 123, thereby avoiding the simultaneous occurrence of high levels at the first output terminal 113 and the second output terminal 123, and reducing the risk of damage to the power amplifier drive circuit 100.

[0062] See Figure 2 As shown, in an optional embodiment, the first additional driving module 1121 includes a first additional driving circuit 141 and a second additional driving circuit 142. The output terminal of the detection control module 130 is connected to the first additional driving circuit 141 and the second additional driving circuit 142 respectively, and is used to control the activation and deactivation of the first additional driving circuit 141 and the second additional driving circuit 142. When the first additional driving circuit 141 is activated, the second additional driving circuit 142 is deactivated; when the second additional driving circuit 142 is activated, the first additional driving circuit 141 is deactivated.

[0063] The detection control module 130 detects the duty cycle of the PWM signal and, based on the comparison between the duty cycle and the set duty cycle value, outputs a control to enable or disable the first auxiliary drive module 1121. When the detection control module 130 enables the first auxiliary drive module 1121, the electrical signal output by the control detection circuit enables the first auxiliary drive circuit 141. The first auxiliary drive circuit 141 enhances the high-side drive signal, thereby enhancing the circuit's driving capability to achieve high performance and high reliability. When the detection control module 130 disables the first auxiliary drive module 1121, the electrical signal output by the control detection circuit enables the second auxiliary drive circuit 142, connecting the high-side drive signal output by the first pre-stage drive circuit 111 to the second ground terminal GND, thereby quickly pulling down the high-side drive signal output by the first output terminal 113.

[0064] See Figure 2 As shown, in an optional embodiment, the second additional driving module 1221 includes a third additional driving circuit 143 and a fourth additional driving circuit 144. The output terminal of the detection control module 130 is connected to the input terminals of the third additional driving circuit 143 and the fourth additional driving circuit 144, respectively, for controlling the activation and deactivation of the second additional driving circuit 142 and the fourth additional driving circuit 144. When the third additional driving circuit 143 is activated, the fourth additional driving circuit 144 is deactivated; when the fourth additional driving circuit 144 is activated, the third additional driving circuit 143 is deactivated.

[0065] The detection control module 130 detects the duty cycle of the PWM signal and controls the activation and deactivation of the second auxiliary drive module 1221 based on the comparison result between the duty cycle and the duty cycle set value. When the detection control module 130 activates the second auxiliary drive module 1221, the electrical signal output by the control detection circuit activates the third auxiliary drive circuit 143. The third auxiliary drive circuit 143 enhances the low-side drive signal, thereby enhancing the circuit's driving capability to achieve high performance and high reliability. When the detection control module 130 deactivates the second auxiliary drive module 1221, the electrical signal output by the control detection circuit activates the fourth auxiliary drive circuit 144, connecting the high-side drive signal output by the second pre-stage drive circuit 121 to the second ground terminal GND to quickly pull down the high-side drive signal output by the second output terminal 123.

[0066] See Figure 3 As shown, in an optional embodiment, the first additional driving circuit 141 includes multiple PMOS transistors 1411 connected in parallel. The sources of the multiple PMOS transistors 1411 are connected to the second power supply terminal VCC, the drains are connected to the output terminal of the first pre-stage driving circuit 111, and the gates are connected to the output terminal of the detection and control module 130.

[0067] The detection control module 130 detects the duty cycle of the PWM signal and, based on the comparison between the duty cycle and the set duty cycle value, controls the activation and deactivation of the first auxiliary drive circuit 141 via a first electrical signal. When the detection control module 130 activates the first auxiliary drive circuit 141, it outputs a low-level first electrical signal to conduct between the drain and source of the PMOS transistor 1411. The high-side drive signal is amplified by multiple parallel PMOS transistors 1411, enhancing the circuit's driving capability to achieve high performance and high reliability. When the detection control module 130 deactivates the first auxiliary drive circuit 141, it outputs a high-level first electrical signal to cut off the PMOS transistor 1411, reducing the power of the power amplifier drive circuit 100.

[0068] See Figure 3 As shown, in an optional embodiment, the second additional driving circuit 142 includes multiple NMOS transistors 1421 connected in parallel. The sources of the multiple NMOS transistors 1421 are connected to the second ground terminal GND, the drains are connected to the output terminal of the first pre-stage driving circuit 111, and the gates are connected to the output terminal of the detection and control module 130.

[0069] The detection control module 130 controls the activation and deactivation of the second auxiliary drive circuit 142 via a second electrical signal. When the detection control module 130 activates the second auxiliary drive circuit 142, it outputs a high-level second electrical signal, turning on the drain and source of the multi-stage parallel NMOS transistors 1421. This connects the high-side drive signal output by the first pre-stage drive circuit 111 to the second ground terminal GND, quickly pulling down the high-side drive signal output by the first output terminal 113. When the detection control module 130 deactivates the second auxiliary drive circuit 142, it outputs a low-level second electrical signal, turning off the multi-stage parallel NMOS transistors.

[0070] See Figure 4 As shown, in an optional embodiment, the third additional driving circuit 143 includes multiple PMOS transistors 1431 connected in parallel. The sources of the multiple PMOS transistors 1431 are connected to the second power supply terminal VCC, the drains are connected to the output terminal of the second pre-stage driving circuit 121, and the gates are connected to the output terminal of the detection and control module 130. The number of multiple PMOS transistors 1411 connected in parallel in the first additional driving circuit 141 is equal to the number of multiple PMOS transistors 1431 connected in parallel in the third additional driving circuit 143.

[0071] The detection control module 130 detects the duty cycle of the PWM signal and, based on the comparison between the duty cycle and the set duty cycle value, controls the activation and deactivation of the first auxiliary drive circuit 141 via a third electrical signal. When the detection control module 130 activates the third auxiliary drive circuit 143, it outputs a low-level third electrical signal to conduct between the drain and source of the PMOS transistor 1431. This multi-stage parallel connection of PMOS transistors 1431 enhances the low-side drive signal, improving the circuit's driving capability and achieving high performance and high reliability. When the detection control module 130 deactivates the third auxiliary drive circuit 143, it outputs a high-level third electrical signal to cut off the PMOS transistors 1431, reducing the power of the power amplifier drive circuit 100.

[0072] See Figure 4 As shown, in an optional embodiment, the fourth additional driving circuit 144 includes multiple NMOS transistors 1441 connected in parallel. The sources of the multiple NMOS transistors 1441 are connected to the second ground terminal GND, the drains are connected to the output terminal of the first pre-stage driving circuit 111, and the gates are connected to the output terminal of the detection and control module 130. The number of NMOS transistors 1421 connected in parallel in the second additional driving circuit 142 is equal to the number of NMOS transistors 1441 connected in parallel in the fourth additional driving circuit 144.

[0073] The detection control module 130 controls the activation and deactivation of the fourth auxiliary drive circuit 144 via a fourth electrical signal. When the detection control module 130 activates the fourth auxiliary drive circuit 144, it outputs a high-level fourth electrical signal, turning on the drain and source of the multi-stage parallel NMOS transistors 1441. This connects the low-side drive signal output by the second pre-stage drive circuit 121 to the second ground terminal GND, quickly pulling down the low-side drive signal output by the second output terminal 123. When the detection control module 130 deactivates the fourth auxiliary drive circuit 144, it outputs a low-level fourth electrical signal, turning off the multi-stage parallel NMOS transistors 1441.

[0074] See Figure 2As shown, in an optional embodiment, the detection control module 130 is further configured to receive at least one of the following protection signals: over-temperature protection signal, over-current protection signal, and short-circuit protection signal. Specifically, the detection control module 130 includes an over-temperature protection signal input terminal 161, an over-current protection signal input terminal 162, and a short-circuit protection signal input terminal 163, and acquires the over-temperature protection signal, over-current protection signal, and short-circuit protection signal respectively through these terminals. When the power amplifier drive circuit 100 experiences over-temperature, over-current, or short-circuit conditions, the corresponding over-temperature protection signal, over-current protection signal, and short-circuit protection signal become abnormal signals. When at least one of the protection signals is an abnormal signal, the detection control module 130 controls the first additional drive module 1121 and the second additional drive module 1221 to be enabled. Specifically, the detection control module 130 controls the second additional drive circuit 142 and the fourth additional drive circuit 144 to be enabled. The drain and source of the multi-stage parallel NMOS transistors in the second auxiliary drive circuit 142 are turned on to connect the high-side drive signal output by the first pre-stage drive circuit 111 to the second ground terminal GND, thereby quickly pulling down the high-side drive signal output by the first output terminal 113. Similarly, the drain and source of the multi-stage parallel NMOS transistors in the fourth auxiliary drive circuit 144 are turned on to connect the low-side drive signal output by the second pre-stage drive circuit 121 to the second ground terminal GND, thereby quickly pulling down the low-side drive signal output by the second output terminal 123. Through this configuration, when the power amplifier drive circuit 100 experiences an abnormal operating state, the first output terminal 113 and the second output terminal 123 can be quickly shut down, which is beneficial for the safe operation of the power amplifier drive circuit 100 and improves its reliability.

[0075] See Figure 2 As shown, in an optional embodiment, the power amplifier drive circuit 100 includes a mode selection circuit 150. The input terminal of the mode selection circuit 150 is used to receive PWM signals, and the output terminal of the mode selection circuit 150 is connected to the detection and control module 130.

[0076] The mode selection circuit 150 includes multiple operating modes, each corresponding to a different duty cycle setting value. The mode selection circuit 150 is used to select different operating modes based on the duty cycle of the PWM signal and outputs different duty cycle setting values ​​to the detection and control module 130.

[0077] In some embodiments, the operating modes include power-saving mode, normal mode, and drive enhancement mode. In power-saving mode, the duty cycle is set to 15%. When the duty cycle of the input PWM signal is less than or equal to 15%, the detection control module 130 controls the first additional drive module 1121 and the second additional drive module 1221 to shut down; when the duty cycle of the input PWM signal is greater than 15%, the detection control module 130 controls the first additional drive module 1121 and the second additional drive module 1221 to enable. In normal mode, the duty cycle is set to 50%. When the duty cycle of the input PWM signal is less than or equal to 50%, the detection control module 130 controls the first additional drive module 1121 and the second additional drive module 1221 to shut down; when the duty cycle of the input PWM signal is greater than 50%, the detection control module 130 controls the first additional drive module 1121 and the second additional drive module 1221 to enable. In drive enhancement mode, the duty cycle is set to 80%. When the duty cycle of the input PWM signal is less than or equal to 80%, the detection control module 130 controls the first auxiliary drive module 1121 and the second auxiliary drive module 1221 to turn off; when the duty cycle of the input PWM signal is greater than 80%, the detection control module 130 controls the first auxiliary drive module 1121 and the second auxiliary drive module 1221 to turn on.

[0078] By selecting different operating modes of the power amplifier driver circuit 100 and adjusting the activation conditions of the first additional driver module 1121 and the second additional driver module 1221 for different usage environments, the power of the power amplifier driver circuit 100 can be adapted to different usage environments, which is beneficial to the applicability of the power amplifier driver circuit 100.

[0079] This embodiment also provides a control method for the power amplifier driver circuit 100, see [link]. Figure 5 As shown, it includes steps S10, S20 and S30.

[0080] In step S10, the comparison result between the duty cycle of the PWM signal and the duty cycle setting value is obtained.

[0081] In step S20, when the duty cycle is less than or equal to the duty cycle setting value, the first additional drive module 1121 and the second additional drive module 1221 are controlled to shut down.

[0082] In step S30, when the duty cycle is greater than the duty cycle setting value, the first additional drive module 1121 and the second additional drive module 1221 are activated.

[0083] When the duty cycle of the PWM signal is small, the power amplifier drive circuit 100 operates in a small-signal state. At this time, the first auxiliary drive module 1121 and the second auxiliary drive module 1221 are turned off, reducing the power of the power amplifier drive circuit 100. When the duty cycle of the PWM signal is large, the power amplifier drive circuit 100 operates in a large-signal state. At this time, the first auxiliary drive module 1121 and the second auxiliary drive module 1221 are turned on, enhancing the circuit's driving capability to achieve high performance and high reliability.

[0084] In optional embodiments, the power amplifier driver circuit 100 includes different operating modes. The control method for the power amplifier driver circuit 100 further includes step S40.

[0085] In step S40, different duty cycle settings are determined according to different operating modes of the power amplifier drive circuit 100.

[0086] In some embodiments, the operating modes include power-saving mode, normal mode, and drive enhancement mode. In power-saving mode, the duty cycle is set to 15%. When the duty cycle of the input PWM signal is less than or equal to 15%, the detection control module 130 controls the first additional drive module 1121 and the second additional drive module 1221 to shut down; when the duty cycle of the input PWM signal is greater than 15%, the detection control module 130 controls the first additional drive module 1121 and the second additional drive module 1221 to enable. In normal mode, the duty cycle is set to 50%. When the duty cycle of the input PWM signal is less than or equal to 50%, the detection control module 130 controls the first additional drive module 1121 and the second additional drive module 1221 to shut down; when the duty cycle of the input PWM signal is greater than 50%, the detection control module 130 controls the first additional drive module 1121 and the second additional drive module 1221 to enable. In drive enhancement mode, the duty cycle is set to 80%. When the duty cycle of the input PWM signal is less than or equal to 80%, the detection control module 130 controls the first auxiliary drive module 1121 and the second auxiliary drive module 1221 to turn off; when the duty cycle of the input PWM signal is greater than 80%, the detection control module 130 controls the first auxiliary drive module 1121 and the second auxiliary drive module 1221 to turn on.

[0087] By selecting different operating modes of the power amplifier driver circuit 100 and adjusting the activation conditions of the first additional driver module 1121 and the second additional driver module 1221 for different usage environments, the power of the power amplifier driver circuit 100 can be adapted to different usage environments, which is beneficial to the applicability of the power amplifier driver circuit 100.

[0088] See Figure 6 As shown, in an optional embodiment, the control method further includes steps S51 and S52.

[0089] In step S51, at least one of the over-temperature protection signal, over-current protection signal, and short-circuit protection signal is acquired.

[0090] In step S52, when at least one of the protection signals is an abnormal signal, the first additional drive module 1121 and the second additional drive module 1221 are activated.

[0091] When the power amplifier driver circuit 100 experiences over-temperature, over-current, or short-circuit conditions, the corresponding over-temperature protection signal, over-current protection signal, and short-circuit protection signal become abnormal signals. When at least one of the protection signals is abnormal, the detection control module 130 controls the first auxiliary drive module 1121 and the second auxiliary drive module 1221 to activate, thereby quickly pulling down the high-side drive signal output from the first output terminal 113 and the low-side drive signal output from the second output terminal 123, and quickly shutting down the first output terminal 113 and the second output terminal 123. This is beneficial for the safe operation of the power amplifier driver circuit 100 and improves its reliability.

[0092] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A power amplifier driver circuit, characterized in that, Used to convert PWM signals to drive levels, including: A high-side drive circuit is connected to a first power supply terminal and includes a first pre-stage drive circuit, a first post-stage drive circuit, and a first output terminal. The first pre-stage drive circuit is connected to a PWM signal input terminal and is used to convert the PWM signal into a high-side drive signal. The input terminal of the first post-stage drive circuit is connected to the output terminal of the first pre-stage drive circuit. The first post-stage drive circuit includes a first additional drive module, which is used to enhance the high-side drive signal. The first output terminal is used to output the high-side drive signal. A low-side drive circuit is connected to a first ground terminal and includes a second pre-stage drive circuit, a second post-stage drive circuit, and a second output terminal. The second pre-stage drive circuit is connected to the PWM signal input terminal and is used to convert the PWM signal into a low-side drive signal. The input terminal of the second post-stage drive circuit is connected to the output terminal of the second pre-stage drive circuit. The second post-stage drive circuit includes a second additional drive module, which is used to enhance the low-side drive signal. The second output terminal is used to output the low-side drive signal. The detection control module is used to detect the duty cycle of the PWM signal and control the activation and deactivation of the first additional drive module and the second additional drive module based on the comparison result between the duty cycle and the duty cycle setting value.

2. The power amplifier driver circuit according to claim 1, characterized in that, The first post-stage driving circuit further includes a first control driving circuit, which is used to acquire the high-side driving signal output by the first pre-stage driving circuit, and control the activation and deactivation of the first additional driving module according to the high-side driving signal output by the first pre-stage driving circuit. The second post-stage drive circuit further includes a second control drive circuit, which is used to acquire the low-side drive signal output by the second pre-stage drive circuit and control the activation and deactivation of the second additional drive module according to the low-side drive signal.

3. The power amplifier driver circuit according to claim 2, characterized in that, The first control drive circuit includes a multi-stage series inverter and a multi-stage parallel NMOS transistor. The input terminal of the multi-stage series inverter is connected to the output terminal of the first pre-stage drive circuit. The sources of the multiple NMOS transistors are all connected to the second ground terminal, the drains are all connected to the output terminal of the first pre-stage drive circuit, and the gates are all connected to the output terminal of the multi-stage series inverter. The second control drive circuit includes a multi-stage series inverter and a multi-stage parallel NMOS transistor. The input terminal of the multi-stage series inverter is connected to the output terminal of the second pre-stage drive circuit. The sources of the multiple NMOS transistors are all connected to the second ground terminal, the drains are all connected to the output terminal of the second pre-stage drive circuit, and the gates are connected to the output terminal of the multi-stage series inverter.

4. The power amplifier driver circuit according to claim 1, characterized in that, The first additional driving module includes a first additional driving circuit and a second additional driving circuit. The output terminal of the detection control module is connected to the first additional driving circuit and the second additional driving circuit respectively, and is used to control the activation and deactivation of the first additional driving circuit and the second additional driving circuit. Specifically, when the first additional driving circuit is enabled, the second additional driving circuit is disabled; when the second additional driving circuit is enabled, the first additional driving circuit is disabled. The second additional drive module includes a third additional drive circuit and a fourth additional drive circuit. The output terminal of the detection control module is connected to the input terminal of the third additional drive circuit and the input terminal of the fourth additional drive circuit, respectively, for controlling the activation and deactivation of the second additional drive circuit and the fourth additional drive circuit. Specifically, when the third additional driving circuit is enabled, the fourth additional driving circuit is disabled; when the fourth additional driving circuit is enabled, the third additional driving circuit is disabled.

5. The power amplifier driver circuit according to claim 4, characterized in that, The first additional driving circuit includes multiple parallel PMOS transistors, with the source of each PMOS transistor connected to the second power supply terminal, the drain connected to the output terminal of the first pre-stage driving circuit, and the gate connected to the output terminal of the detection and control module. The third additional driving circuit includes multiple parallel PMOS transistors, with the source of each PMOS transistor connected to the second power supply terminal, the drain connected to the output terminal of the second pre-stage driving circuit, and the gate connected to the output terminal of the detection and control module. Alternatively, the second additional driving circuit includes multiple NMOS transistors connected in parallel, with the source of each NMOS transistor connected to the second ground terminal, the drain connected to the output terminal of the first pre-stage driving circuit, and the gate connected to the output terminal of the detection and control module. The fourth additional driving circuit includes multiple NMOS transistors connected in parallel. The sources of the multiple NMOS transistors are connected to the second ground terminal, the drains are connected to the output terminal of the first pre-stage driving circuit, and the gates are connected to the output terminal of the detection and control module.

6. The power amplifier driver circuit according to claim 1, characterized in that, The detection and control module is also used to receive at least one of the following protection signals: over-temperature protection signal, over-current protection signal, and short-circuit protection signal; When one of the at least one protection signal is an abnormal signal, the detection control module controls the first additional drive module and the second additional drive module to be enabled.

7. The power amplifier driver circuit according to claim 1, characterized in that, It includes a mode selection circuit, the input of which is used to receive the PWM signal, and the output of which is connected to the detection and control module; The mode selection circuit includes multiple operating modes, each corresponding to a different duty cycle setting value. The mode selection circuit is used to select different operating modes based on the duty cycle of the PWM signal and output different duty cycle setting values ​​to the detection and control module.

8. A control method for a power amplifier drive circuit as described in any one of claims 1-7, characterized in that, include: Obtain the comparison result between the duty cycle of the PWM signal and the duty cycle setting value; When the duty cycle is less than or equal to the duty cycle setting value, the first additional drive module and the second additional drive module are controlled to shut down; When the duty cycle is greater than the duty cycle setting value, the first additional drive module and the second additional drive module are activated.

9. The control method as described in claim 8, characterized in that, The power amplifier drive circuit includes different operating modes, and the control method further includes: Different duty cycle settings are determined according to different operating modes of the power amplifier drive circuit.

10. The control method as described in claim 8, characterized in that, Also includes: Acquire at least one of the following protection signals: over-temperature protection signal, over-current protection signal, and short-circuit protection signal; When one of the at least one protection signal is an abnormal signal, the first additional drive module and the second additional drive module are activated.

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