Phase convergence method, circuit and chip for XGSPON uplink burst data transmission
By performing parity separation and logic processing on the sampled data of XGSPON uplink burst data transmission, the position of the transition edge is quickly determined, and the sampling clock phase is adjusted to the center of the eye diagram. This solves the problem of slow phase convergence speed of SerDes and improves the effective bandwidth of communication.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN PANGO MICROSYST CO LTD
- Filing Date
- 2025-12-23
- Publication Date
- 2026-05-15
AI Technical Summary
SerDes, which does not support BCDR, has a slow phase convergence speed in XGSPON uplink burst data transmission scenarios, resulting in reduced effective bandwidth and difficulty in meeting throughput and real-time requirements.
By acquiring the sampled data of the double-oversampled preamble, separating it into even-bit and odd-bit sequences, performing preset logic processing to determine the position of the transition edge, and adjusting the sampling clock phase to the center region of the eye diagram, an equivalent four-fold oversampling effect is achieved.
It significantly shortens the phase convergence time window and improves the effective bandwidth of XGSPON uplink communication.
Smart Images
Figure CN122053020A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, specifically to a phase convergence method, circuit, and chip for XGSPON uplink burst data transmission. Background Technology
[0002] In the uplink communication of XGSPON (10-Gigabit-capable Symmetric Passive Optical Network), data is transmitted in bursts. This requires the SerDes (Serializer / Deserializer) at the receiving end to quickly complete clock and data recovery (CDR) within a very short time of the preamble of the burst data, thereby locking and converging the sampling clock phase to ensure reliable reception of subsequent valid data.
[0003] To achieve rapid convergence of the aforementioned sampling clock phase, a known solution is to use a dedicated SerDes with Burst-mode Clock and Data Recovery (BCDR) functionality. However, many general-purpose SerDes that do not support BCDR face significant challenges in processing such burst data. Due to the lack of optimization for burst modes, their CDR requires a longer preamble time to complete phase convergence, which directly squeezes the effective data transmission window. Consequently, the effective bandwidth of XGSPON uplink communication is significantly reduced, making it difficult to meet the throughput and real-time requirements of practical applications.
[0004] Improving the phase convergence performance of SerDes, which does not support BCDR, in XGSPON uplink burst data transmission scenarios, reducing its dependence on preamble length, and thus improving the effective bandwidth of XGSPON uplink communication has become a key technical problem that urgently needs to be solved. Summary of the Invention
[0005] In view of the above problems, this application provides a phase convergence method, circuit and chip for XGSPON uplink burst data transmission to solve the above technical problems.
[0006] In a first aspect, this application provides a phase convergence method for XGSPON uplink burst data transmission, comprising: The first sampled data is generated by obtaining the preamble of the burst data oversampled twice, and the even-numbered bits of the first sampled data are recorded as the first even-numbered bit sequence. The sampling clock phase of the burst data is delayed by a first preset angle; Obtain the second sampled data generated by oversampling the preamble by twice the sampling clock phase lagging behind the first preset angle, and record the even-numbered bits of the second sampled data as the second even-numbered bit sequence; The first even-numbered bit sequence, the first odd-numbered bit sequence, the second even-numbered bit sequence, and the second odd-numbered bit sequence are subjected to preset logic processing, and the transition edge position of the preamble is determined based on the result of the preset logic processing. The sampling clock phase of the burst data is adjusted according to the position of the transition edge of the preamble to converge the sampling clock phase of the burst data to the center region of the eye diagram.
[0007] In some embodiments, the preset logic processing includes: Obtain the XOR result of the first even-numbered bit sequence and the second even-numbered bit sequence, and denote it as the first edge detection signal; Obtain the XOR result of the second even-numbered bit sequence and the first odd-numbered bit sequence, and denote it as the second edge detection signal; Obtain the XOR result of the first odd-numbered bit sequence and the second odd-numbered bit sequence, and denote it as the third edge detection signal; Obtain the XOR result of the first part of the second odd-numbered bit sequence and the second part of the first even-numbered bit sequence, and denote it as the fourth edge detection signal; The first part of the second odd-numbered bit sequence is: the second odd-numbered bit sequence after removing the highest bit of the second odd-numbered bit sequence, and the second part of the first even-numbered bit sequence is: the first even-numbered bit sequence after removing the lowest bit of the first even-numbered bit sequence.
[0008] In some embodiments, the step of determining the transition edge position of the preamble based on the result of logical processing includes: Obtain the number of logic 1s in the first edge detection signal, the second edge detection signal, the third edge detection signal, and the fourth edge detection signal; The sampling clock phase interval corresponding to the edge detection signal with the largest number of logic 1s is determined as the transition edge position of the preamble.
[0009] In some embodiments, the step of adjusting the sampling clock phase of the burst data according to the position of the transition edge of the preamble includes: If the position of the transition edge is determined to be within the sampling clock phase interval corresponding to the first edge detection signal or the third edge detection signal, then the sampling clock phase is adjusted to lead by a second preset angle. If the position of the transition edge is determined to be within the sampling clock phase interval corresponding to the second edge detection signal or the fourth edge detection signal, then the sampling clock phase is adjusted to lag by a second preset angle. Wherein, the second preset angle is smaller than the first preset angle.
[0010] In some embodiments, the first preset angle is 45 degrees and the second preset angle is 22.5 degrees.
[0011] In some embodiments, the step of adjusting the sampling clock phase of the burst data according to the position of the transition edge of the preamble further includes: If the position of the transition edge is determined to be within the sampling clock phase interval corresponding to the first edge detection signal or the second edge detection signal, then the second odd-numbered bit sequence is selected as the sampling result of the preamble. If the transition edge position is determined to be within the sampling clock phase interval corresponding to the third edge detection signal or the fourth edge detection signal, then the second even-numbered bit sequence is selected as the sampling result of the preamble.
[0012] In some embodiments, after the step of adjusting the sampling clock phase of the burst data according to the position of the preamble transition edge to converge the sampling clock phase of the burst data to the center region of the eye diagram, the method further includes: After all the burst data has been transmitted, the sampling clock phase is adjusted to 0 degrees.
[0013] Secondly, this application provides a phase convergence circuit for XGSPON uplink burst data transmission, comprising: The parity separation module is used to acquire first sampled data generated by oversampling the preamble of the burst data by twice, and to record the even-numbered bits of the first sampled data as a first even-numbered bit sequence and the odd-numbered bits of the first sampled data as a first odd-numbered bit sequence; and to acquire second sampled data generated by oversampling the preamble by twice the sampling clock phase lagging behind the first preset angle, and to record the even-numbered bits of the second sampled data as a second even-numbered bit sequence and the odd-numbered bits of the second sampled data as a second odd-numbered bit sequence; The phase detection module is used to perform preset logic processing on the first even-numbered bit sequence, the first odd-numbered bit sequence, the second even-numbered bit sequence, and the second odd-numbered bit sequence, and determine the transition edge position of the preamble based on the result of the preset logic processing. The phase adjustment module is used to lag the sampling clock phase of the burst data by a first preset angle, and to adjust the sampling clock phase of the burst data according to the position of the transition edge of the preamble, so as to converge the sampling clock phase of the burst data to the center region of the eye diagram.
[0014] In some embodiments, the phase convergence circuit for XGSPON uplink burst data transmission further includes: A state machine is used to receive the first sampled data, output a first enable signal to control the phase adjustment module to lag the sampling clock phase of the burst data by a first preset angle, and output a second enable signal to control the parity separation module to record the even-numbered bits of the first sampled data as the first even-numbered bit sequence and the odd-numbered bits of the first sampled data as the first odd-numbered bit sequence. The system is configured to receive the second sampled data, output a first enable signal to control the phase adjustment module to adjust the sampling clock phase of the burst data according to the position of the transition edge of the preamble, output a second enable signal to control the parity separation module to record the even-numbered bits of the second sampled data as the second even-numbered bit sequence and the odd-numbered bits of the second sampled data as the second odd-numbered bit sequence, output a third enable signal to control the phase detection module to perform preset logic processing on the first even-numbered bit sequence, the first odd-numbered bit sequence, the second even-numbered bit sequence and the second odd-numbered bit sequence, and determine the position of the transition edge of the preamble according to the result of the preset logic processing.
[0015] Thirdly, this application provides a chip including a phase convergence circuit for XGSPON uplink burst data transmission as described in the second aspect above.
[0016] This application provides a phase convergence method, circuit, and chip for XGSPON uplink burst data transmission. The phase convergence method for XGSPON uplink burst data transmission first acquires the first sampled data generated by a double-oversampled preamble, separating its even-numbered and odd-numbered bits into a first even-numbered bit sequence and a first odd-numbered bit sequence. Then, the sampling clock phase is delayed by a first preset angle to acquire the second sampled data and separate it into a second even-numbered bit sequence and a second odd-numbered bit sequence. Preset logic processing is performed on these four sequences to quickly determine the position of the preamble's transition edge. Then, the sampling clock phase is adjusted to the center region of the eye diagram based on the position of the preamble's transition edge. This application can achieve an equivalent four-fold oversampling effect on hardware devices that only support double-oversampling, solving the problem of slow phase convergence speed and the need for a large number of preambles in XGSPON uplink burst data transmission scenarios for general SerDes that does not support BCDR. It significantly shortens the time window required for phase convergence, thereby significantly improving the effective bandwidth of XGSPON uplink communication.
[0017] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This illustration shows an application scenario of the phase convergence method for XGSPON uplink burst data transmission provided in an embodiment of this application.
[0020] Figure 2 A schematic flowchart of a phase convergence method for XGSPON uplink burst data transmission provided in an embodiment of this application is shown.
[0021] Figure 3 This paper illustrates another schematic flowchart of the phase convergence method for XGSPON uplink burst data transmission provided in an embodiment of this application.
[0022] Figure 4 A schematic diagram of a phase convergence circuit for XGSPON uplink burst data transmission provided in an embodiment of this application is shown.
[0023] Figure 5 Another schematic diagram of a phase convergence circuit for XGSPON uplink burst data transmission provided in an embodiment of this application is shown. Detailed Implementation
[0024] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0025] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.
[0026] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.
[0027] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.
[0028] Figure 1 This illustration shows an application scenario diagram of the phase convergence method for XGSPON uplink burst data transmission provided in an embodiment of this application. For example... Figure 1 As shown, in this application scenario, the Field Programmable Gate Array (FPGA) connects to multiple Optical Network Units (ONU_1 to ONU_N) via its serializer (SerDes) transmitter (SerDes TX) and receiver (SerDes RX) through a 1:N splitter, forming an XGSPON communication link. The SerDes transmitter (SerDes TX) outputs PON downlink data, and the receiver (SerDes TX) receives PON uplink data. The FPGA is configured with a Passive Optical Network Media Access Control (PON MAC) module and a phase convergence circuit. The phase convergence circuit executes the phase convergence method for XGSPON uplink burst data transmission, and its function is implemented by configuring the FPGA's programmable resources. In this application environment, the PON MAC module allocates uplink transmission time slots to each ONU, enabling multiple ONUs to send burst data packets to the FPGA side in different time slots. The SerDes receiver (SerDes RX) receives serial burst data from the splitter and converts it into parallel data. The phase convergence circuit receives parallel sampled data from the SerDes and, during the preamble stage of each burst data packet, executes the phase convergence method described in this application to adjust the sampling clock phase of the SerDes RX to adapt to burst data from different ONUs.
[0029] The ONU can be, but is not limited to, various user terminal devices, such as home gateways and enterprise access devices. The FPGA can be an integrated chip containing a SerDes chip, or a programmable logic device with an external SerDes chip.
[0030] Figure 2 This paper illustrates a flowchart of a phase convergence method for XGSPON uplink burst data transmission provided in an embodiment of this application. Figure 2 As shown, the method includes: S100: Obtain the first sampled data generated from the preamble of the double-oversampled burst data. Record the even-numbered bits of the first sampled data as the first even-numbered bit sequence and the odd-numbered bits as the first odd-numbered bit sequence. Optionally, double oversampling refers to sampling the preamble of the burst data twice within each unit interval (UI) at a rate higher than twice the XGSPON uplink rate. The first sampled data is the sampled data obtained by downsampling the initial sampling clock phase. This embodiment does not limit the initial sampling clock phase; regardless of the angle of the initial sampling clock phase, it can be considered as the 0-sample clock phase. The first sampled data is distinguished by the parity of the bit index, resulting in the first even-numbered bit sequence and the first odd-numbered bit sequence representing the two sampling clock phases, respectively.
[0031] S200: Lag the sampling clock phase of the burst data by a first preset angle. Optionally, the first preset angle is a pre-set phase adjustment amount. By adjusting the phase of the clock signal used for sampling to delay it relative to the current phase by a first preset angle, a different sampling position is provided for the next sampling compared to the previous one.
[0032] S300: Obtain the second sampled data generated by oversampling the preamble with a sampling clock phase that is twice the lag of the first preset angle. Record the even-numbered bits of the second sampled data as the second even-numbered bit sequence and the odd-numbered bits of the second sampled data as the second odd-numbered bit sequence. Optionally, after completing the phase adjustment in step S200, the preamble is oversampled twice again under the new sampling clock phase to obtain the second sampled data. The even-numbered and odd-numbered bits in the second sampled data are extracted and recorded as the second even-numbered bit sequence and the second odd-numbered bit sequence, respectively. By oversampling twice at an interval of twice the first preset angle, and combined with parity separation, data information evenly distributed on four different sampling clock phases is actually obtained. Specifically, the first even-numbered bit sequence and the second even-numbered bit sequence correspond to the sampled data located in the even-numbered bits in the first sampling and the sampling after phase adjustment, respectively. The first odd-numbered bit sequence and the second odd-numbered bit sequence correspond to the sampled data located in the odd-numbered bits in the two samplings, respectively. Since the preamble is a known pattern with a fixed period (e.g., alternating "0" and "1"), even if the two samplings may span adjacent UIs in time, the phase relationship reflected by their sampled values is equivalent to the sampled values sampled within the same UI.
[0033] S400: Perform preset logic processing on the first even-bit sequence, the first odd-bit sequence, the second even-bit sequence, and the second odd-bit sequence, and determine the position of the preamble transition edge based on the result of the preset logic processing. Optionally, the preset logic processing is used to analyze the relationship between the sampled values of different sampling clock phases represented by the above four sequences and distributed within a UI, thereby directly locating the phase interval where the data level transition edge is located. Since the preamble is usually a known fixed pattern (e.g., alternating "0" and "1"), its transition edge position reflects the relationship between the current sampling clock phase and the data eye diagram. By processing and comparing these four sequences through logical operations, it is possible to quickly determine which phase interval is most likely to contain the transition edge.
[0034] S500: Adjust the sampling clock phase of the burst data according to the position of the preamble transition edge to converge the sampling clock phase of the burst data to the center region of the eye diagram. Optionally, after determining the phase interval where the transition edge is located, the approximate phase of the center region of the data eye diagram can be calculated. Then, based on this prediction, the sampling clock phase is adjusted once in a direction away from the transition edge and towards the center of the eye diagram.
[0035] As one implementation, S200: lagging the sampling clock phase of the burst data by a first preset angle, and S500: adjusting the sampling clock phase of the burst data according to the position of the preamble transition edge to converge the sampling clock phase of the burst data to the center region of the eye diagram, both control the operation of the clock adjustment circuit corresponding to the sampling clock by generating a corresponding clock adjustment signal, thereby realizing the adjustment of the sampling clock phase by a corresponding angle.
[0036] It is understood that the phase convergence method for XGSPON uplink burst data transmission provided in this application embodiment is executed during the preamble period at the beginning of burst data transmission. To ensure the execution of this method, it is usually necessary to limit or bypass the operation of the conventional clock data recovery (CDR) function to avoid interference with this method. After this method converges the sampled clock phase to the center region of the eye diagram, the clock data recovery (CDR) function can be re-enabled so that it can perform fine-tuning and continuous tracking of the phase of subsequent transmitted valid burst data. The working principle and implementation method of the clock data recovery (CDR) function for fine-tuning and continuous tracking of the phase of data are within the scope of existing technology in this field, and the purpose of this application embodiment is to shorten the phase convergence time of the burst data transmission process. Therefore, this application embodiment will not provide further explanation of the clock data recovery function.
[0037] The phase convergence method for XGSPON uplink burst data transmission provided in this application embodiment can achieve the effect of equivalent four times oversampling on hardware devices that only support two times oversampling. It solves the problem that the general SerDes, which does not support BCDR, has a slow phase convergence speed and requires a large number of preambles in XGSPON uplink burst data transmission scenarios. It significantly shortens the time window required for phase convergence, thereby significantly improving the effective bandwidth of XGSPON uplink communication.
[0038] Understandably, achieving double oversampling requires that the nominal rate of SerDes be more than twice the uplink rate of XGSPON. Based on this condition, the phase convergence method of this application embodiment can effectively achieve quadruple oversampling in hardware, thereby supporting fast phase convergence.
[0039] In some embodiments, the step of performing preset logic processing on the first even-numbered position sequence, the first odd-numbered position sequence, the second even-numbered position sequence, and the second odd-numbered position sequence in S400 includes: The XOR result of the first even-numbered bit sequence and the second even-numbered bit sequence is obtained and denoted as the first edge detection signal. Optionally, the first edge detection signal is used to detect whether the data transition edge is located between the sampling clock phases corresponding to the first even-numbered bit sequence and the second even-numbered bit sequence. For example, suppose the first sampled data and the second sampled data are both 64-bit parallel data (RDATA[63:0]), and the separated first even-numbered bit sequence Q[31:0] and second even-numbered bit sequence Q_s[31:0] represent even-numbered phase sampled values of 0° (considered as 0°) and lag by a first preset angle (such as 45°), respectively. Performing a bitwise XOR on the two, if each bit of the result is '1', it means that the sampled values of the two phases are different at that data bit, indicating that a transition edge may exist here.
[0040] The XOR result of the second even-numbered bit sequence and the first odd-numbered bit sequence is obtained and denoted as the second edge detection signal. Optionally, the second edge detection signal is used to detect whether the data transition edge is located between the sampling clock phases corresponding to the second even-numbered bit sequence and the first odd-numbered bit sequence. Taking the above 64-bit data as an example, the second even-numbered bit sequence Q_s[31:0] represents the even-numbered phase sampling value that lags behind the first preset angle (such as 45°), and the first odd-numbered bit sequence X[31:0] represents the odd-numbered phase sampling value at 0° (considered as 0°). By performing an XOR operation on the two, it can be determined whether the transition edge exists between the two sampling clock phases based on the XOR result.
[0041] The XOR result of the first odd-numbered bit sequence and the second odd-numbered bit sequence is obtained and denoted as the third edge detection signal. Optionally, the third edge detection signal is used to detect whether the data transition edge is located between the sampling clock phases corresponding to the first odd-numbered bit sequence and the second odd-numbered bit sequence. For example, by XORing the first odd-numbered bit sequence X[31:0] and the second odd-numbered bit sequence X_s[31:0], the existence of the transition edge between the two sampling clock phases can be determined based on the XOR result.
[0042] The XOR result of the first part of the second odd-bit sequence and the second part of the first even-bit sequence is denoted as the fourth edge detection signal. The first part of the second odd-bit sequence is the second odd-bit sequence after removing the most significant bit, and the second part of the first even-bit sequence is the first even-bit sequence after removing the least significant bit. Optionally, the fourth edge detection signal is used to determine whether the data transition edge is located between the sampling clock phases corresponding to the sampling data of the second odd-bit sequence and the first even-bit sequence in the next unit interval (UI). To approximate the phase relationship comparison across UI within a finite bit width, X_s[30:0] obtained by removing the most significant bit of the second odd-bit sequence X_s[31:0] is XORed with Q[31:1] obtained by removing the least significant bit of the first even-bit sequence Q[31:0]. The XOR result can approximately reflect the difference in transition edges between the second odd-bit sequence and the first even-bit sequence in the next unit interval.
[0043] In some embodiments, S400: the step of determining the transition edge position of the preamble based on the result of preset logic processing includes: Obtain the number of logic 1s in the first edge detection signal, the second edge detection signal, the third edge detection signal, and the fourth edge detection signal.
[0044] The sampling clock phase interval corresponding to the edge detection signal with the most logic 1s is determined as the transition edge position of the preamble.
[0045] Optionally, since the preamble has a known fixed pattern (e.g., alternating "0" and "1"), when the sampling clock phase is located in the center region of the stable eye diagram, the number of "1"s in the XOR result is relatively small; while when the sampling clock phase is close to the transition edge, the number of "1"s in the XOR result will increase significantly. By comparing the number of logic 1s in the four edge detection signals, the interval between the two sampling clock phases represented by the edge detection signal with the maximum value is the phase interval where the transition edge is located. For example, if the number of "1"s in the first edge detection signal is the largest, then the transition edge is determined to be located within the phase interval corresponding to the first even-numbered bit sequence and the second even-numbered bit sequence (45° even phase). Compared with judging the transition edge based on only a single bit transition, the embodiments of this application can effectively resist the influence of sampling noise or individual bit errors, thereby more accurately locating the transition edge.
[0046] In some embodiments, S400: the step of adjusting the sampling clock phase of the burst data according to the position of the preamble transition edge specifically includes: If the transition edge position is determined to be within the sampling clock phase range corresponding to the first or third edge detection signal, then the sampling clock phase is adjusted to lead by a second preset angle. Optionally, this indicates that the current sampling clock phase is after the data transition edge, and in order to move the sampling clock phase to the center region of the eye diagram, the sampling clock phase needs to be adjusted in the leading direction. The second preset angle is the step size for phase adjustment.
[0047] If the transition edge position is determined to be within the sampling clock phase range corresponding to the second or fourth edge detection signal, then the sampling clock phase is adjusted to lag by a second preset angle. Optionally, this indicates that the current sampling clock phase is before the data transition edge, and in order to move the sampling clock phase to the center region of the eye diagram, the sampling clock phase needs to be adjusted in the lag direction. The second preset angle is still the step size for phase adjustment.
[0048] Wherein, the second preset angle is smaller than the first preset angle. The first preset angle is used for the first phase adjustment in step S200, which aims to obtain two sampling clock phases with a known interval for subsequent edge detection. The second preset angle is used for the second phase adjustment in step S500, which aims to move the sampling clock phase from the eye diagram center region according to the determined transition edge position within the phase interval determined by the first phase adjustment.
[0049] In some embodiments, the first preset angle in this application is 45 degrees, and the second preset angle is 22.5 degrees. Optionally, configuring the first preset angle to 45 degrees ensures that the four sampled clock phases obtained by double oversampling and parity separation are evenly distributed within a phase range of 0 to 180 degrees (i.e., each sampled clock phase is spaced 45 degrees apart). Based on this, configuring the second preset angle to 22.5 degrees allows the sampled clock phases to converge to the center region of the eye diagram simply by selecting a suitable angle within this range (0 to 45 degrees) after knowing that the transition edge is located within a certain 45-degree interval. This angle is preferably 22.5 degrees. It is understood that the specific value of the second preset angle is not limited to 22.5 degrees; in fact, any value greater than 0 degrees and less than the first preset angle (45 degrees) can achieve the purpose of phase convergence to the center region of the eye diagram.
[0050] In some embodiments, S400: the step of adjusting the sampling clock phase of the burst data according to the position of the preamble transition edge further includes: If the position of the transition edge is determined to be within the sampling clock phase interval corresponding to the first edge detection signal or the second edge detection signal, then the second odd-numbered bit sequence is selected as the sampling result of the preamble.
[0051] If the position of the transition edge is determined to be within the sampling clock phase interval corresponding to the third or fourth edge detection signal, then the second even-numbered bit sequence is selected as the sampling result of the preamble.
[0052] In some embodiments, Figure 3 This paper illustrates another schematic flowchart of the phase convergence method for XGSPON uplink burst data transmission provided in an embodiment of this application, as shown below. Figure 3 As shown, after step S500: adjusting the sampling clock phase of the burst data according to the position of the preamble transition edge to converge the sampling clock phase of the burst data to the center region of the eye diagram, the following is also included: S600: After all burst data has been transmitted, the sampling clock phase is adjusted to 0 degrees. Optionally, after the phase convergence of the burst data is completed in step S500, the valid data in the burst data is transmitted. After the valid data of the burst data has also been transmitted, the sampling clock phase is reset to a certain initial state (i.e., 0 degrees) so that there is a known phase starting point when receiving burst data in the next round, further reducing the locking time of sampling clock phase convergence.
[0053] This application also provides a phase convergence circuit for XGSPON uplink burst data transmission. Figure 4 A schematic diagram of a phase convergence circuit for XGSPON uplink burst data transmission provided in an embodiment of this application is shown, as follows: Figure 4The circuit includes: The parity separation module (ODD / EVEN) is used to acquire the first sampled data generated by the preamble of the twice-oversampled burst data, and to record the even-numbered bits of the first sampled data as the first even-numbered bit sequence and the odd-numbered bits of the first sampled data as the first odd-numbered bit sequence; and to acquire the second sampled data (RDATA2) generated by the preamble of the sampling clock phase lags by a first preset angle by twice the oversampled preamble, and to record the even-numbered bits of the second sampled data as the second even-numbered bit sequence and the odd-numbered bits of the second sampled data as the second odd-numbered bit sequence.
[0054] The phase detection module is used to perform preset logic processing on the first even-numbered bit sequence, the first odd-numbered bit sequence, the second even-numbered bit sequence, and the second odd-numbered bit sequence, and determine the position of the preamble transition edge based on the result of the preset logic processing.
[0055] The phase adjustment module (PI Controller) is used to lag the sampling clock phase of burst data by a first preset angle and to adjust the sampling clock phase of burst data according to the position of the preamble transition edge, so as to converge the sampling clock phase of burst data to the center region of the eye diagram.
[0056] The phase adjustment module (PI Controller) performs the following actions: lags the sampling clock phase of the burst data by a first preset angle, and adjusts the sampling clock phase of the burst data according to the position of the preamble transition edge to converge the sampling clock phase of the burst data to the center region of the eye diagram. In both cases, it generates corresponding clock adjustment signals to control the operation of the corresponding clock adjustment circuit inside SerDes, thereby adjusting the phase of the sampling clock by the corresponding angle.
[0057] It is understood that the phase convergence circuit for XGSPON uplink burst data transmission provided in this application embodiment is applied to the SerDes for transmitting XGSPON uplink burst data. The SerDes receiver converts the input serial burst data (serdes_data) into parallel burst data and performs double oversampling based on its internal sampling clock, outputting first sample data / second sample data. The phase convergence circuit of this application embodiment receives its output first sample data / second sample data and performs subsequent functions such as parity separation, phase detection, and phase adjustment of the SerDes sampling clock.
[0058] For further details regarding the implementation of the above technical solution by each module in the phase convergence circuit for XGSPON uplink burst data transmission, please refer to the description of the phase convergence method for XGSPON uplink burst data transmission provided in the above embodiments of the invention, which will not be repeated here.
[0059] The phase convergence circuit for XGSPON uplink burst data transmission provided in this application embodiment can achieve an equivalent four-fold oversampling effect on hardware SerDes devices that only support two-fold oversampling. This solves the problem of slow phase convergence speed and the need for a large number of preambles in XGSPON uplink burst data transmission scenarios where general SerDes that do not support BCDR are not supported. It significantly shortens the time window required for phase convergence, thereby significantly improving the effective bandwidth of XGSPON uplink communication.
[0060] In some embodiments, Figure 5 Another schematic diagram of the phase convergence circuit for XGSPON uplink burst data transmission provided in this application embodiment is shown, as follows: Figure 5 The circuit also includes: The state machine (OverSample FSM) is used to receive the first sampled data, output the first enable signal en1 to control the phase adjustment module (PI Controller) to lag the sampling clock phase of the burst data by a first preset angle, and output the second enable signal to control the parity separation module (ODD / EVEN) to record the even-numbered bits of the first sampled data as the first even-numbered bit sequence and the odd-numbered bits of the first sampled data as the first odd-numbered bit sequence. The system is used to receive the second sampled data, output a first enable signal en1 to control the phase adjustment module (PIController) to adjust the sampling clock phase of the burst data according to the position of the preamble transition edge, output a second enable signal en2 to control the parity separation module (ODD / EVEN) to record the even-numbered bits of the second sampled data as the second even-numbered bit sequence and the odd-numbered bits of the second sampled data as the second odd-numbered bit sequence, and output a third enable signal en3 to control the phase detection module (Phase Detect) to perform preset logic processing on the first even-numbered bit sequence, the first odd-numbered bit sequence, the second even-numbered bit sequence and the second odd-numbered bit sequence, and determine the position of the preamble transition edge according to the result of the preset logic processing.
[0061] This application embodiment achieves automated timing control of the phase convergence process through a state machine (OverSample FSM). Based on the data sampling completion flag, the state machine generates and outputs corresponding enable signals to control the parity separation module, phase adjustment module, and phase detection module to execute their specific functions sequentially or in parallel. This ensures that the entire phase convergence method can be executed correctly according to the preset steps.
[0062] It is understood that when the embodiments of this application are applied to an FPGA (Field Programmable Gate Array), the parity separation module (ODD / EVEN), phase detection module (Phase Detect), phase adjustment module (PI Controller), and state machine (OverSample FSM) can all be implemented by configuring the programmable resources of the FPGA.
[0063] It is understood that, in specific implementations, the modules / units included in the various devices and products described in the above embodiments may be software modules / units, hardware modules / units, or may be partly software modules / units and partly hardware modules / units.
[0064] For example, for various devices and products applied to or integrated into chips, each module / unit can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into chip modules, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The unit can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, all of their modules / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.
[0065] This application also provides a chip that includes the phase convergence circuit described above for XGSPON uplink burst data transmission. The chip (Integrated Circuit, IC) can be, but is not limited to, a System on Chip (SOC) chip or a System in Package (SIP) chip.
[0066] The above description, in conjunction with specific embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications and substitutions should be considered within the scope of protection of this application.
Claims
1. A phase convergence method for XGSPON uplink burst data transmission, characterized in that, include: The first sampled data is generated by the preamble of the twice oversampled burst data. The even-numbered bits of the first sampled data are recorded as the first even-numbered bit sequence. The odd-numbered bits of the first sampled data are recorded as the first odd-numbered bit sequence. The sampling clock phase of the burst data is delayed by a first preset angle; Obtain the second sampled data generated by oversampling the preamble by twice the sampling clock phase lagging behind the first preset angle, and record the even-numbered bits of the second sampled data as the second even-numbered bit sequence; The first even-numbered bit sequence, the first odd-numbered bit sequence, the second even-numbered bit sequence, and the second odd-numbered bit sequence are subjected to preset logic processing, and the transition edge position of the preamble is determined based on the result of the preset logic processing. The sampling clock phase of the burst data is adjusted according to the position of the transition edge of the preamble to converge the sampling clock phase of the burst data to the center region of the eye diagram.
2. The phase convergence method for XGSPON uplink burst data transmission as described in claim 1, characterized in that, The preset logic processing includes: Obtain the XOR result of the first even-numbered bit sequence and the second even-numbered bit sequence, and denote it as the first edge detection signal; Obtain the XOR result of the second even-numbered bit sequence and the first odd-numbered bit sequence, and denote it as the second edge detection signal; Obtain the XOR result of the first odd-numbered bit sequence and the second odd-numbered bit sequence, and denote it as the third edge detection signal; Obtain the XOR result of the first part of the second odd-numbered bit sequence and the second part of the first even-numbered bit sequence, and denote it as the fourth edge detection signal; The first part of the second odd-numbered bit sequence is: the second odd-numbered bit sequence after removing the highest bit of the second odd-numbered bit sequence, and the second part of the first even-numbered bit sequence is: the first even-numbered bit sequence after removing the lowest bit of the first even-numbered bit sequence.
3. The phase convergence method for XGSPON uplink burst data transmission as described in claim 2, characterized in that, The step of determining the transition edge position of the preamble based on the result of logical processing includes: Obtain the number of logic 1s in the first edge detection signal, the second edge detection signal, the third edge detection signal, and the fourth edge detection signal; The sampling clock phase interval corresponding to the edge detection signal with the largest number of logic 1s is determined as the transition edge position of the preamble.
4. The phase convergence method for XGSPON uplink burst data transmission as described in claim 3, characterized in that, The step of adjusting the sampling clock phase of the burst data according to the position of the transition edge of the preamble includes: If the position of the transition edge is determined to be within the sampling clock phase interval corresponding to the first edge detection signal or the third edge detection signal, then the sampling clock phase is adjusted to lead by a second preset angle. If the position of the transition edge is determined to be within the sampling clock phase interval corresponding to the second edge detection signal or the fourth edge detection signal, then the sampling clock phase is adjusted to lag by a second preset angle. Wherein, the second preset angle is smaller than the first preset angle.
5. The phase convergence method for XGSPON uplink burst data transmission as described in claim 4, characterized in that, The first preset angle is 45 degrees, and the second preset angle is 22.5 degrees.
6. The phase convergence method for XGSPON uplink burst data transmission as described in claim 4, characterized in that, The step of adjusting the sampling clock phase of the burst data according to the position of the transition edge of the preamble further includes: If the position of the transition edge is determined to be within the sampling clock phase interval corresponding to the first edge detection signal or the second edge detection signal, then the second odd-numbered bit sequence is selected as the sampling result of the preamble. If the transition edge position is determined to be within the sampling clock phase interval corresponding to the third edge detection signal or the fourth edge detection signal, then the second even-numbered bit sequence is selected as the sampling result of the preamble.
7. The phase convergence method for XGSPON uplink burst data transmission as described in claim 1, characterized in that, After the step of adjusting the sampling clock phase of the burst data according to the position of the transition edge of the preamble to converge the sampling clock phase of the burst data to the center region of the eye diagram, the method further includes: After all the burst data has been transmitted, the sampling clock phase is adjusted to 0 degrees.
8. A phase convergence circuit for XGSPON uplink burst data transmission, characterized in that, include: The parity separation module is used to acquire first sampled data generated by the preamble of twice the oversampled burst data, record the even-numbered bits of the first sampled data as the first even-numbered bit sequence, and record the odd-numbered bits of the first sampled data as the first odd-numbered bit sequence; and to acquire second sampled data generated by oversampling the preamble by twice the sampling clock phase lagging behind the first preset angle, record the even-numbered bits of the second sampled data as the second even-numbered bit sequence, and record the odd-numbered bits of the second sampled data as the second odd-numbered bit sequence; The phase detection module is used to perform preset logic processing on the first even-numbered bit sequence, the first odd-numbered bit sequence, the second even-numbered bit sequence, and the second odd-numbered bit sequence, and determine the transition edge position of the preamble based on the result of the preset logic processing. The phase adjustment module is used to lag the sampling clock phase of the burst data by a first preset angle, and to adjust the sampling clock phase of the burst data according to the position of the transition edge of the preamble, so as to converge the sampling clock phase of the burst data to the center region of the eye diagram.
9. The phase convergence circuit for XGSPON uplink burst data transmission as described in claim 8, characterized in that, Also includes: A state machine is used to receive the first sampled data, output a first enable signal to control the phase adjustment module to lag the sampling clock phase of the burst data by a first preset angle, and output a second enable signal to control the parity separation module to record the even-numbered bits of the first sampled data as the first even-numbered bit sequence and the odd-numbered bits of the first sampled data as the first odd-numbered bit sequence. The system is configured to receive the second sampled data, output a first enable signal to control the phase adjustment module to adjust the sampling clock phase of the burst data according to the position of the transition edge of the preamble, output a second enable signal to control the parity separation module to record the even-numbered bits of the second sampled data as the second even-numbered bit sequence and the odd-numbered bits of the second sampled data as the second odd-numbered bit sequence, output a third enable signal to control the phase detection module to perform preset logic processing on the first even-numbered bit sequence, the first odd-numbered bit sequence, the second even-numbered bit sequence and the second odd-numbered bit sequence, and determine the position of the transition edge of the preamble according to the result of the preset logic processing.
10. A chip, characterized in that, Includes the phase convergence circuit for XGSPON uplink burst data transmission as described in any one of claims 8 to 9.