Data processing method and device, storage medium, equipment and program product

Abstract

The invention discloses a data processing method and device, a storage medium, equipment and a program product, and the method comprises the steps: at an initialization stage of network equipment, configuring at least one port in the network equipment into an auto-negotiation mode, enabling a hardware automatic speed reduction function, and initializing a plurality of counters, the plurality of counters are configured to be used for recording historical change information of an auto-negotiation state and a link state of the port; the method comprises the following steps: periodically detecting a current link state and a current auto-negotiation state of a port through an upper computer in network equipment; judging whether a preset forced speed reduction condition is met or not according to the current link state, the current auto-negotiation state and the value of each counter; and if the forced speed reduction condition is met, performing speed reduction operation on the highest speed supported by the port through the upper computer, and executing counter reset operation associated with the speed reduction operation to ensure the stability and reliability of the link.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to a data processing method, apparatus, storage medium, device, and program product. Background Technology

[0002] In current Ethernet communication systems, the stability of port status and the reliability of data transmission are crucial. As network bandwidth demands continue to increase, the operating speed of Ethernet ports is also constantly improving. However, under high load or complex network environments, ports may encounter various critical scenarios, such as signal quality degradation and link instability. These problems can lead to data transmission errors or link interruptions, severely impacting device reliability and user experience.

[0003] Traditional Ethernet port management methods often rely on fixed speed settings or manual adjustments, which cannot respond to changes in the network environment in real time. Especially when signal quality fluctuates significantly, fixed speed settings may cause ports to malfunction, while manual adjustments lack timeliness and accuracy, and cannot effectively cope with unexpected situations. Summary of the Invention

[0004] This application provides a data processing method, apparatus, storage medium, device, and program product. By introducing host computer-assisted control and combining real-time monitoring and judgment of port status, intelligent dynamic adjustment of port speed can be achieved. Thus, when the preset forced speed reduction conditions are met, the speed reduction operation is automatically triggered and the associated counter is reset to ensure the stability and reliability of the link.

[0005] On one hand, embodiments of this application provide a data processing method, the method comprising: During the initialization phase of the network device, at least one port in the network device is configured to auto-negotiation mode and the hardware automatic speed reduction function is enabled, and multiple counters are initialized. The multiple counters are configured to record the historical changes in the auto-negotiation state and link state of the port. The host computer in the network device periodically detects the current link status and current auto-negotiation status of the port; Based on the current link state, the current auto-negotiation state, and the values ​​of each counter, determine whether the preset forced speed reduction condition is met; If the forced speed reduction condition is met, the host computer will reduce the maximum speed supported by the port and perform a counter reset operation associated with the speed reduction operation.

[0006] In some embodiments, the plurality of counters includes: The first counter is used to record the number of times the auto-negotiation state of the port changes; The second counter is used to record the number of times the link status of the port is continuously in the link connected state; The third counter is used to record the number of times the link status of the port is continuously in the link disconnected state; The fourth counter is used to record the cumulative number of times the speed reduction operation is performed by the host computer.

[0007] In some embodiments, determining whether a preset forced speed reduction condition is met based on the current link state, the current auto-negotiation state, and the values ​​of each of the counters includes: Compare the current auto-negotiation state with the previously recorded auto-negotiation state of the port; If the current auto-negotiation state is inconsistent with the previously recorded auto-negotiation state of the port, then the value of the first counter is incremented. If the accumulated value of the first counter is greater than or equal to the first preset value, then the forced deceleration condition is determined to be met.

[0008] In some embodiments, performing the counter reset operation associated with the deceleration operation includes: The values ​​of the first counter and the third counter are reset to zero, and the value of the fourth counter is incremented.

[0009] In some embodiments, the method further includes: If the current auto-negotiation state is consistent with the previously recorded auto-negotiation state of the port, then determine whether the value of the first counter is zero; If the value of the first counter is determined to be non-zero, then the value of the third counter is incremented. If the accumulated value of the third counter is greater than the third preset value, then the values ​​of the first counter and the third counter are reset to zero.

[0010] In some embodiments, the method further includes: If the current link status of the port is detected to be a link connected state, then the signal quality index of the link is obtained; If the signal quality index meets the preset quality conditions, the value of the first counter is reset to zero.

[0011] In some embodiments, the method further includes: The value of the second counter is incremented; If the accumulated value of the second counter is greater than or equal to the second preset value, then the values ​​of the first counter and the third counter are reset to zero.

[0012] In some embodiments, the method further includes: After accumulating and judging the value of the second counter, if the value of the fourth counter is greater than zero, the values ​​of the first counter and the third counter are reset to zero, and the port is allowed to try the highest rate before the speed reduction operation in subsequent auto-negotiation.

[0013] In some embodiments, the step of periodically detecting the current link status and current auto-negotiation status of the port via a host computer in the network device includes: The host computer in the network device accesses the registers of the physical layer chip via the control bus at preset time intervals to obtain the current link status and current auto-negotiation status of the port.

[0014] In some embodiments, the step of reducing the maximum speed supported by the port via the host computer includes: The host computer reduces the maximum speed supported by the port by at least one level to guide the port to renegotiate and establish a stable link within the reduced speed range.

[0015] On the other hand, embodiments of this application provide a data processing apparatus, the apparatus comprising: An initialization unit is used to configure at least one port in the network device to auto-negotiation mode and enable hardware automatic speed reduction function during the initialization phase of the network device, and to initialize multiple counters, which are configured to record historical changes in the auto-negotiation state and link state of the port. The detection unit is used to periodically detect the current link status and current auto-negotiation status of the port through the host computer in the network device; The judgment unit is used to determine whether the preset forced speed reduction condition is met based on the current link state, the current auto-negotiation state, and the values ​​of each of the counters. The processing unit is configured to, if the forced speed reduction condition is met, reduce the maximum speed supported by the port via the host computer and execute a counter reset operation associated with the speed reduction operation.

[0016] On the other hand, an embodiment of this application provides a computer-readable storage medium storing a computer program adapted for loading by a processor to perform the data processing method as described in any of the above embodiments.

[0017] On the other hand, an embodiment of this application provides a computer device, which includes a processor and a memory. The memory stores a computer program, and the processor executes the data processing method described in any of the above embodiments by calling the computer program stored in the memory.

[0018] On the other hand, an embodiment of this application provides a computer program product, including computer instructions, which, when executed by a processor, implement the data processing method as described in any of the above embodiments.

[0019] This application embodiment configures at least one port in the network device to auto-negotiation mode and enables hardware automatic speed reduction during the network device initialization phase, and initializes multiple counters configured to record historical changes in the port's auto-negotiation and link states. A host computer in the network device periodically detects the port's current link state and current auto-negotiation state. Based on the current link state, current auto-negotiation state, and the values ​​of each counter, it determines whether a preset forced speed reduction condition is met. If the forced speed reduction condition is met, the host computer performs a speed reduction operation on the port's highest supported rate and executes a counter reset operation associated with the speed reduction operation. This application embodiment configures the port to auto-negotiation mode, enables hardware automatic speed reduction function, and initializes multiple counters for recording port auto-negotiation and historical changes in link status during network device initialization. Combined with the host computer's periodic detection of port status and the judgment of forced speed reduction conditions based on the current status and counter values, it realizes intelligent dynamic adjustment of port speed. Thus, when the preset forced speed reduction conditions (such as link instability) are met, the speed reduction operation can be automatically triggered and the associated counters can be reset, effectively avoiding link interruption problems caused by high-speed transmission. While ensuring the continuity of data transmission, it improves the adaptability of network devices to complex environments, ensures the stability and reliability of the link, and ultimately optimizes the user's network experience. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a first flowchart illustrating the data processing method provided in an embodiment of this application.

[0022] Figure 2 This is a second flowchart illustrating the data processing method provided in an embodiment of this application.

[0023] Figure 3 This is a schematic diagram of the structure of the data processing apparatus provided in the embodiments of this application.

[0024] Figure 4 A schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] Please see Figures 1 to 2 , Figure 1 and Figure 2 These are schematic flowcharts illustrating the data processing method provided in the embodiments of this application. The method may include the following steps: Step 110: During the initialization phase of the network device, at least one port in the network device is configured to auto-negotiation mode and the hardware automatic speed reduction function is enabled. Multiple counters are also initialized, which are configured to record historical changes in the auto-negotiation status and link status of the port.

[0027] The auto-negotiation status includes information such as the port negotiation success rate and duplex mode. The hardware automatic speed reduction function is provided by the physical layer (PHY) chip, while the host computer specifically refers to the central processing unit (CPU) or microcontroller unit (MCU) inside the network device. The port initialization rate is configured to the highest rate supported by the chip (e.g., 1000M), and the initial auto-negotiation status is recorded.

[0028] In some embodiments, the plurality of counters includes: The first counter is used to record the number of times the port's auto-negotiation state changes; The second counter is used to record the number of times the port's link status is in the link connected state consecutively; The third counter is used to record the number of times the port's link status is continuously in the disconnected state; The fourth counter is used to record the cumulative number of times the host computer performs the speed reduction operation.

[0029] Specifically, the multiple counters include a first counter (N1) for recording the number of self-negotiation state changes, a second counter (N2) for recording the number of consecutive link connections (i.e., the number of times the port link state is continuously in the link connected state), a third counter (N3) for recording the number of consecutive link disconnections (i.e., the number of times the port link state is continuously in the link disconnected state), and a fourth counter (N4) for recording the cumulative number of forced speed reductions (i.e., the cumulative number of times the host computer performs speed reduction operations).

[0030] Step 120: The host computer in the network device periodically detects the current link status and current auto-negotiation status of the port.

[0031] In some embodiments, the current link status and current auto-negotiation status of a port are periodically detected by a host computer in the network device, including: accessing the registers of the physical layer chip via the control bus through the host computer in the network device at a preset time interval to obtain the current link status and current auto-negotiation status of the port.

[0032] In this context, the host computer specifically refers to the central processing unit (CPU) or microcontroller unit (MCU) inside the network device. This host computer is relative to the MAC chip and is actually implemented within the switch. If the MAC chip has a built-in CPU or MCU, it can directly control the PHY chip; if the MAC chip does not have a built-in CPU or MCU, an external CPU or MCU is required to control the PHY chip.

[0033] The preset time interval for periodic testing can be set to 500ms. However, for different physical layer (PHY) chips, the preset time interval may need to be adjusted based on the actual test results. For example, the host computer (usually a CPU or MCU) accesses the registers of the physical layer (PHY) chip through control buses such as the Management Data Clock (MDC) or Management Data Input / Output (MDIO) to obtain the port status information. The registers can also be modified via the control bus to adjust the port status information.

[0034] Step 130: Based on the current link status, the current auto-negotiation status, and the values ​​of each counter, determine whether the preset forced speed reduction conditions are met.

[0035] The judgment is a multi-condition state machine decision-making process. The core logic includes: If the port link is connected, the signal quality (e.g., root mean square error, MSE) is first evaluated. If the signal quality is good, the value of the first counter (N1) is reset to zero. Regardless of the signal quality, the value of the second counter (N2) is incremented. When the value of the second counter (N2) reaches a second preset value (e.g., 6), the link is determined to be stable, and the values ​​of the first counter (N1) and the third counter (N3) are reset to zero. If the value of the fourth counter (N4) is greater than 0, the values ​​of the first counter (N1) and the third counter (N3) are reset to zero, and the port is allowed to attempt the highest speed. If the port link is disconnected, the current auto-negotiation state is compared with the previously recorded state. If they are inconsistent, the value of the first counter (N1) is incremented, and when the value of the first counter (N1) reaches a first preset value (e.g., 4), the forced speed reduction condition is determined to be met. If the states are consistent, but the value of the first counter (N1) is not zero, the value of the third counter (N3) is incremented, and when the value of the third counter (N3) reaches the third preset value (e.g., 50), the values ​​of the first counter (N1) and the third counter (N3) are cleared to prevent the counters from failing to reset in cases such as when the network cable is unplugged.

[0036] For example, the first preset value for N1 is 4, the second preset value for N2 is 6, and the third preset value for N3 is 50. The preset values ​​for N1, N2, and N3 affect the speed reduction effect and time. A larger preset value will prolong the speed reduction time, potentially requiring several minutes to achieve port speed reduction; a smaller preset value will result in a worse speed reduction effect, potentially misinterpreting normal network cable plugging and unplugging behavior as poor network cable signal quality. This embodiment aims to avoid link instability caused by repeated negotiations when the signal quality on the network cable is at a critical state under certain extreme conditions. Environmental parameters (temperature, voltage, etc.), cable length, and network cable quality all affect the signal quality on the network cable, and the final decision is based on the signal quality on the network cable; generally, adaptive adjustment of the preset values ​​is unnecessary.

[0037] Step 140: If the forced speed reduction condition is met, the host computer performs a speed reduction operation on the highest speed supported by the port and executes a counter reset operation associated with the speed reduction operation.

[0038] The speed reduction operation refers to the host computer controlling the forced reduction of the maximum speed supported by the port by at least one level (e.g., from 1000M to 100M) to guide the port to renegotiate at a lower speed. The associated counter reset operation includes at least: resetting the values ​​of the first counter (N1) and the third counter (N3) to zero, and accumulating the value of the fourth counter (N4) to record this speed reduction event and update the system status, providing a basis for subsequent possible speed recovery judgment.

[0039] In some embodiments, the host computer performs a speed reduction operation on the highest speed supported by the port, including: The host computer can reduce the maximum speed supported by the port by at least one level to guide the port to renegotiate and establish a stable link within the reduced speed range.

[0040] This operation is achieved by modifying the corresponding control registers of the physical layer (PHY) chip through the host computer, thereby limiting the maximum negotiable rate of the port at the hardware level.

[0041] In some embodiments, the maximum speed supported by the port is reduced from a first speed level to a second speed level via a host computer.

[0042] The first rate tier corresponds to a higher rate than the second rate tier. Rate tiers are typically based on Ethernet standard rates, such as 10Mbps, 100Mbps, and 1000Mbps.

[0043] For example, if the port supports a maximum speed of 1000M, reducing it by one level would limit the port's maximum speed to 100M. Alternatively, the speed could be limited to 10M as needed. This speed-reduction strategy is implemented gradually; if the link remains unstable after reducing the speed to 100M, it can be further reduced to 10M.

[0044] In multi-port devices, the speed reduction decision for each port is independent. The CPU or MCU periodically polls in real time, accessing multiple PHY registers simultaneously via the control bus, and then determines whether speed reduction is necessary based on the returned register values. This design ensures that an anomaly in one port will not affect the normal operation of other ports, while also improving system management efficiency.

[0045] In some embodiments, performing a counter reset operation associated with the deceleration operation includes: Reset the values ​​of the first and third counters to zero, and increment the value of the fourth counter.

[0046] The reset operation ensures that after the speed reduction, N1, which records the number of abnormal negotiations, and N3, which records the number of abnormal disconnections, are cleared to zero, thus preventing historical abnormal states from affecting the establishment of a new link. At the same time, the accumulation of N4 (recording the number of forced speed reductions) provides a basis for judgment on possible subsequent rate recovery mechanisms (such as allowing attempts to restore the original maximum rate after the link stabilizes).

[0047] In some embodiments, based on the current link state, the current auto-negotiation state, and the values ​​of each counter, it is determined whether a preset forced speed reduction condition is met, including: Compare the current auto-negotiation state with the previously recorded port auto-negotiation state; If the current auto-negotiation state is inconsistent with the previously recorded port auto-negotiation state, then the value of the first counter is incremented. If the accumulated value of the first counter is greater than or equal to the first preset value, then the forced speed reduction condition is met.

[0048] The first preset value (e.g., set to 4) is used to define the threshold for "repeated negotiation". Its setting needs to balance the timeliness of deceleration and the avoidance of misjudgment, such as avoiding misjudging normal brief plugging and unplugging as a fault.

[0049] In some embodiments, the method further includes: If the current auto-negotiation state is consistent with the previously recorded port auto-negotiation state, then determine whether the value of the first counter is zero; If the value of the first counter is determined to be non-zero, then the value of the third counter is incremented. If the accumulated value of the third counter is greater than the third preset value, then the values ​​of the first and third counters will be reset to zero.

[0050] The mechanism aims to address the issue of the first counter (N1) failing to be cleared and continuously affecting subsequent logic judgments when the port is in a link-down state for an extended period due to extremely poor network cable quality. The third preset value (e.g., set to 50) corresponds to the threshold for determining "long-term disconnection".

[0051] In some embodiments, the method further includes: if it is determined that the value of the first counter is zero and the current value of the third counter reaches or exceeds a third preset value, then the values ​​of the first counter and the third counter are reset to zero.

[0052] This mechanism is a further improvement on the counter reset logic, ensuring that under any circumstances, as long as the third counter (N3) indicates a prolonged disconnection, the relevant abnormal state counter will be safely reset.

[0053] In some embodiments, the method further includes: If the current link status of the port is detected to be a link connected state, then obtain the signal quality index of the link; If the signal quality indicators meet the preset quality conditions, the value of the first counter will be reset to zero.

[0054] The signal quality metric can be the root mean square error (MSE). The preset quality condition is that the MSE does not exceed the MSE threshold. The MSE threshold is a preset value and needs to be adjusted according to the measured performance of different PHY chips. It is used to distinguish between critical signal degradation and good signal condition.

[0055] This step can be used as a preliminary optimization judgment. If the current link signal quality is good (MSE meets the standard), the first counter (N1) is directly cleared to interrupt the counting process of "repeated negotiation", thereby avoiding unnecessary forced speed reduction triggered by other accidental factors on a stable link with good signal.

[0056] In some embodiments, the method further includes: The value of the second counter is incremented; If the accumulated value of the second counter is greater than or equal to the second preset value, then the values ​​of the first and third counters are reset to zero.

[0057] Specifically, if the current link status of the port is detected to be a link connected state, and the signal quality indicator meets the preset quality conditions and the value of the first counter is reset to zero, or the signal quality indicator does not meet the preset quality conditions, the value of the second counter is incremented.

[0058] The second counter (N2) is used to confirm that the link has been stably connected for a period of time (e.g., 6 consecutive detection cycles LinkUp). Its accumulation can be independent of the judgment of signal quality. Once the second preset value (e.g., 6) is met, the link is considered to have entered a stable state. At this time, the abnormal state counters (N1, N3) are cleared to prepare for possible rate recovery judgment or a new round of monitoring.

[0059] In some embodiments, the method further includes: if the value of the fourth counter is greater than zero, resetting the values ​​of the first counter and the third counter to zero, and allowing the port to attempt the highest rate before the rate-down operation in subsequent auto-negotiation.

[0060] Specifically, when the value of the second counter after accumulation is greater than or equal to the second preset value, and the values ​​of the first counter and the third counter are reset to zero, or when the value of the second counter after accumulation is less than the second preset value, it is determined whether the value of the fourth counter is greater than zero.

[0061] This step constitutes a complete "slow-down-stabilize-recover" control loop: a positive fourth counter (N4) indicates that the port was forcibly slowed down due to instability; once the link is determined to have stabilized again (whether confirmed by N2 meeting the standard or other reasons), the system resets the fault counter and "allows" the port to attempt its original maximum rate in the next round of negotiation. This is not a forced speed increase, but rather the removal of the software-imposed rate limit, allowing the hardware auto-negotiation function to retry the optimal rate, thereby automatically restoring a high-performance connection when physical link conditions may improve.

[0062] To better illustrate the data processing method provided in the embodiments of this application, please refer to... Figure 2 The data processing method provided in this application embodiment can be summarized into the following steps S1 to S18: In this process, the microcontroller unit (MCU) or central processing unit (CPU) inside the network device is executed periodically as the host computer, and the control logic of each port is independent.

[0063] Step S1, Network Device Initialization. Specifically, during the network device initialization phase, at least one port in the network device is configured to auto-negotiation mode and the hardware automatic speed reduction function is enabled. Multiple counters are also initialized, configured to record historical changes in the port's auto-negotiation and link states.

[0064] For example, during the power-on initialization phase of the network device, the port mode is configured to Auto-Negotiation State (AN) mode, the port speed is configured to the highest supported speed, the hardware automatic speed reduction function is enabled, and the current Auto-Negotiation State (AN) status is recorded. Simultaneously, the values ​​of four counters (counter N1, counter N2, counter N3, and counter N4) are initialized to 0. N1 records the number of times the AN status changes, N2 records the number of times the link is continuously in a link-up state, N3 records the number of times the link is continuously in a link-down state, and N4 records the number of times forced speed reduction occurs.

[0065] Step S2: The host computer in the network device periodically checks the current link status and current auto-negotiation status of the port. If the current link status of the port is detected as link up, then step S3 is executed; if the current link status of the port is detected as link down, then step S10 is executed (the value of the second counter (N2) is reset to zero), and then step S11 is executed. The time interval for periodic detection is, for example, 500 milliseconds. The host computer accesses the PHY chip registers through control buses such as MDC / MDIO to obtain the port status information.

[0066] Step S3: Obtain the signal quality indicators of the link and determine whether the signal quality indicators meet the preset quality conditions. If yes, proceed to step S4; otherwise, proceed directly to step S5.

[0067] The signal quality metric can be the root mean square error (MSE). The preset quality condition is that the MSE does not exceed the MSE threshold. The MSE threshold is a preset value and needs to be adjusted according to the measured performance of different PHY chips. It is used to distinguish between critical signal degradation and good signal condition.

[0068] For example, the current MSE is judged. If the MSE does not exceed the root mean square error threshold, the link signal quality is considered to be good, and steps S4-S8 are executed; if the MSE exceeds the root mean square error threshold, the link signal quality is considered to be poor, and step S5 is executed directly.

[0069] Step S4: Reset the value of the first counter (N1) to zero. This operation is based on the logic of "interrupting abnormal negotiation counting if the signal quality is good" to avoid triggering speed reduction due to accidental disturbances on a stable link.

[0070] Step S5: Accumulate the value of the second counter (N2).

[0071] Specifically, if the current link status of the port is detected as a connected state, and the signal quality indicator meets the preset quality conditions and the value of the first counter (N1) is reset to zero, or if the signal quality indicator does not meet the preset quality conditions, the value of the second counter (N2) is incremented. The increment of N2 is independent of the signal quality and is intended to count consecutive Link Up events to confirm link stability.

[0072] Step S6: Determine whether the accumulated value of the second counter (N2) is greater than or equal to the second preset value. If yes, proceed to step S7; otherwise, proceed to step S8.

[0073] For example, if the accumulated value of the second counter (N2) is greater than or equal to the second preset value, it indicates that the link state is stable at this time, and steps S7-S8 are executed; if the accumulated value of the second counter (N2) is less than the second preset value, it is still impossible to determine whether the link state is stable, and step S8 is executed directly. The second preset value (e.g., 6) needs to be set properly. Too small a value may lead to a misjudgment of temporary stability, while too large a value will make the confirmation of stability after the speed reduction too slow.

[0074] Step S7: Reset the values ​​of the first counter (N1) and the third counter (N3) to zero. Once the link is confirmed to be stable (N2 meets the standard), clear all abnormal status records (N1, N3) to prepare for subsequent monitoring or rate recovery.

[0075] Step S8: Determine if the value of the fourth counter (N4) is greater than zero. If yes, proceed to step S9; otherwise, proceed to step S18.

[0076] Specifically, after the value of the accumulated second counter (N2) is greater than or equal to the second preset value, and the values ​​of the first counter (N1) and the third counter (N3) are reset to zero, or when the value of the accumulated second counter (N2) is less than the second preset value, it is determined whether the value of the fourth counter is greater than zero.

[0077] For example, the value of the fourth counter (N4) is checked. If the value of the fourth counter (N4) is greater than 0, it means that the host computer has previously forced a reduction in the port rate, thereby bringing the link to its current stable state. In this case, the values ​​of the first counter (N1) and the third counter (N3) are reset to 0, and the port is allowed to link to the highest rate before the rate reduction operation, ensuring that the next port auto-negotiation starts from the highest rate, and then the current loop is exited (step S18). If the value of the fourth counter (N4) is equal to 0, it means that the link is not yet stable or the link has already stabilized at the highest rate, and the current loop is exited directly (step S18).

[0078] Step S9 resets the values ​​of the first counter (N1) and the third counter (N3) to zero, allowing the port to attempt the highest rate before the rate reduction operation in subsequent auto-negotiation. This operation is executed after the judgment in step S8 is true, and essentially removes the rate limiting flag in the software layer.

[0079] Steps S8-S9 are key to the "slowdown-recovery" closed loop: when a slowdown record is detected (N4>0) and the current link is stable or in the judgment process, the system will reset the counter and remove the software limit on the highest rate, allowing the hardware to retry the original high rate during the next negotiation.

[0080] Step S10: Reset the value of the second counter (N2) to zero.

[0081] For example, if the current link status of the port is detected as link down in step S2, the value of the second counter (N2) is reset to zero, and step S11 continues. Because N2 is used to count continuous Link Up, once the link is broken, the continuity is interrupted, so it needs to be cleared to zero.

[0082] Step S11: Compare the current auto-negotiation state with the previously recorded port auto-negotiation state. If the current auto-negotiation state is inconsistent with the previously recorded port auto-negotiation state, proceed to step S12; if the current auto-negotiation state is consistent with the previously recorded port auto-negotiation state, proceed to step S15.

[0083] For example, the currently recorded AN state is compared with the previously recorded AN state. If the two states are inconsistent, it indicates that the link cannot stabilize at the current rate and renegotiation has occurred. In this case, the value of the first counter (N1) is incremented by 1 (step 12), and then step S13 is executed. If the two states are consistent, step 15 is executed. Changes in the AN state are the most direct indicator for identifying the "repeated negotiation" phenomenon.

[0084] Step S12: Accumulate the value of the first counter (N1).

[0085] Specifically, if the current self-negotiation state is inconsistent with the previously recorded port self-negotiation state, the value of the first counter (N1) is incremented, and step S13 is executed again. The increment of N1 is the core of quantifying the degree of "repeated negotiation".

[0086] Step S13: Determine whether the accumulated value of the first counter (N1) is greater than or equal to the first preset value. If yes, the forced speed reduction condition is met, and step S14 continues. If no, step S15 is executed.

[0087] For example, the value of the first counter (N1) is checked. If the value of the first counter (N1) is greater than or equal to the first preset value, it indicates that the current link has entered a state of repeated negotiation and cannot stabilize the link at the currently set maximum speed. The host computer needs to force a speed reduction. In this case, step S14 can continue to be executed. For example, the host computer can control the maximum speed supported by the port to be forcibly reduced by one level, reset the values ​​of the first counter (N1) and the third counter (N3) to 0, increment the value of the fourth counter (N4) by 1, and then execute step S15. If the value of the first counter (N1) is less than the preset value, it is still impossible to determine whether the link can stabilize at the currently set maximum speed, and step S15 is executed directly. The first preset value (e.g., 4) is the threshold for triggering forced speed reduction, and its setting should avoid overreacting to short-term, occasional negotiation fluctuations.

[0088] Step S14: Reduce the maximum speed supported by the port by at least one level through the host computer, reset the values ​​of the first counter (N1) and the third counter (N3) to zero, and accumulate the value of the fourth counter (N4).

[0089] The speed reduction operation is implemented by writing to the PHY chip registers, for example, reducing the maximum speed from 1000M to 100M. The counter operation ensures that the state machine restarts after the speed reduction (N1 and N3 are cleared) and records the intervention event (N4 is incremented by 1).

[0090] Step S15: Record the current auto-negotiation state; and determine whether the value of the first counter (N1) is zero; if the value of the first counter (N1) is not zero, then increment the value of the third counter and continue to step S16; if the value of the first counter (N1) is zero, then directly execute step S16. This logic is designed to handle the "long-term Link Down" scenario: when the port is in the Link Down state and an abnormal negotiation has occurred (N1>0), the disconnection duration is quantified by incrementing N3.

[0091] For example, record the current AN state and judge the value of the first counter (N1). If the value of the first counter (N1) is not equal to 0, increment the value of the third counter (N3) by 1 and then execute step S16; if the value of the first counter (N1) is equal to 0, directly execute step S16.

[0092] Step S16: Determine whether the value of the third counter (N3) is greater than the third preset value. If yes, proceed to step S17; otherwise, proceed to step S18.

[0093] For example, the value of the third counter (N3) is checked. If the value of the third counter (N3) is greater than the third preset value, it means that the port has been without a link for a long time, and the counters need to be reset. That is, step S17 is executed to reset the values ​​of the first counter (N1) and the third counter (N3) to 0, and then the current loop is exited (step S18); if the value of the third counter (N3) is not greater than the third preset value, the current loop is exited directly (step S18). The third preset value (e.g., 50) corresponds to the "long-term disconnection" judgment, and is used to prevent counters such as N1 from permanently maintaining a non-zero value and "locking" the logic in extreme cases such as the network cable being unplugged or completely damaged.

[0094] Step S17: Reset the values ​​of the first counter (N1) and the third counter (N3) to zero. This is a protective reset operation for prolonged disconnection.

[0095] Step S18: Exit this cycle. After completing this periodic detection and processing, wait for the next detection cycle to begin, and then start executing again from step S2.

[0096] All of the above technical solutions can be combined in any way to form optional embodiments of this application, and will not be described in detail here.

[0097] This application embodiment configures at least one port in the network device to auto-negotiation mode and enables hardware automatic speed reduction during the network device initialization phase, and initializes multiple counters configured to record historical changes in the port's auto-negotiation and link states. A host computer in the network device periodically detects the port's current link state and current auto-negotiation state. Based on the current link state, current auto-negotiation state, and the values ​​of each counter, it determines whether a preset forced speed reduction condition is met. If the forced speed reduction condition is met, the host computer performs a speed reduction operation on the port's highest supported rate and executes a counter reset operation associated with the speed reduction operation. This application embodiment configures the port to auto-negotiation mode, enables hardware automatic speed reduction function, and initializes multiple counters for recording port auto-negotiation and historical changes in link status during network device initialization. Combined with the host computer's periodic detection of port status and the judgment of forced speed reduction conditions based on the current status and counter values, it realizes intelligent dynamic adjustment of port speed. Thus, when the preset forced speed reduction conditions (such as link instability) are met, the speed reduction operation can be automatically triggered and the associated counters can be reset, effectively avoiding link interruption problems caused by high-speed transmission. While ensuring the continuity of data transmission, it improves the adaptability of network devices to complex environments, ensures the stability and reliability of the link, and ultimately optimizes the user's network experience.

[0098] To facilitate better implementation of the data processing method of this application embodiment, this application embodiment also provides a data processing apparatus. Please refer to... Figure 3 , Figure 3 A schematic diagram of the structure of a data processing apparatus provided in an embodiment of this application. The data processing apparatus 200 may include: The initialization unit 210 is used to configure at least one port in the network device to auto-negotiation mode and enable hardware automatic speed reduction function during the initialization phase of the network device, and to initialize multiple counters, which are configured to record the historical changes in the auto-negotiation status and link status of the port. The detection unit 220 is used to periodically detect the current link status and current auto-negotiation status of the port through the host computer in the network device; The judgment unit 230 is used to determine whether the preset forced speed reduction condition is met based on the current link status, the current auto-negotiation status, and the values ​​of each counter. The processing unit 240 is used to perform a speed reduction operation on the highest speed supported by the port through the host computer if the forced speed reduction condition is met, and to perform a counter reset operation associated with the speed reduction operation.

[0099] In some embodiments, the plurality of counters includes: The first counter is used to record the number of times the port's auto-negotiation state changes; The second counter is used to record the number of times the port's link status is in the link connected state consecutively; The third counter is used to record the number of times the port's link status is continuously in the disconnected state; The fourth counter is used to record the cumulative number of times the host computer performs the speed reduction operation.

[0100] In some embodiments, the determination unit 230 is configured to: compare the current auto-negotiation state with the previously recorded auto-negotiation state of the port; if the current auto-negotiation state is inconsistent with the previously recorded auto-negotiation state of the port, then increment the value of the first counter; if the incremented value of the first counter is greater than or equal to a first preset value, then determine that the forced speed reduction condition is met.

[0101] In some embodiments, the processing unit 240 is configured to perform a counter reset operation associated with the deceleration operation, including: resetting the values ​​of the first counter and the third counter to zero, and accumulating the value of the fourth counter.

[0102] In some embodiments, the determining unit 230 is further configured to determine whether the value of the first counter is zero if the current auto-negotiation state is consistent with the auto-negotiation state of the port recorded last time. The processing unit 240 is further configured to, if the value of the first counter is determined to be non-zero, increment the value of the third counter; if the value of the incremented third counter is greater than a third preset value, reset the values ​​of the first counter and the third counter to zero.

[0103] In some embodiments, the processing unit 240 is further configured to: if the current link state of the port is detected to be a link connected state, then obtain the signal quality index of the link; if the signal quality index meets the preset quality conditions, then reset the value of the first counter to zero.

[0104] In some embodiments, the processing unit 240 is further configured to: if the value of the second counter is accumulated; if the value of the accumulated second counter is greater than or equal to a second preset value, then reset the values ​​of the first counter and the third counter to zero.

[0105] In some embodiments, the processing unit 240 is further configured to: if the value of the fourth counter is greater than zero, reset the values ​​of the first counter and the third counter to zero, and allow the port to attempt the highest rate before the rate-down operation in subsequent auto-negotiation.

[0106] In some embodiments, the detection unit 220 is configured to access the registers of the physical layer chip via a control bus through a host computer in the network device based on a preset time interval, in order to obtain the current link status and current auto-negotiation status of the port.

[0107] In some embodiments, the processing unit 240 is configured to perform a speed reduction operation on the maximum speed supported by the port via a host computer, including: reducing the maximum speed supported by the port by at least one level via the host computer, so as to guide the port to renegotiate and establish a stable link within the reduced speed range.

[0108] It should be noted that the functions of each module in the data processing device 200 in this application embodiment can be referred to the specific implementation of any embodiment in the above method embodiments, and will not be repeated here.

[0109] Each unit in the above-described device can be implemented entirely or partially through software, hardware, or a combination thereof. Each unit can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each unit.

[0110] For example, the data processing device 200 may be integrated into a terminal or server that has storage and a processor and thus computing power, or the data processing device 200 may be the terminal or server.

[0111] In some embodiments, this application also provides a computer device including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0112] Figure 4 A schematic diagram of the structure of the computer device provided in the embodiments of this application, such as... Figure 4 As shown, the computer device 300 may include: a communication interface 301, a memory 302, a processor 303, and a communication bus 304. The communication interface 301, memory 302, and processor 303 communicate with each other via the communication bus 304. The communication interface 301 is used for data communication between the device 300 and external devices. The memory 302 can be used to store software programs and modules, and the processor 303 runs the software programs and modules stored in the memory 302, such as the software programs for the corresponding operations in the aforementioned method embodiments.

[0113] In some embodiments, the processor 303 may invoke software programs and modules stored in the memory 302 to perform the following operations: during the initialization phase of the network device, configuring at least one port in the network device to auto-negotiation mode and enabling hardware automatic speed reduction function, and initializing multiple counters, which are configured to record historical changes in the port's auto-negotiation state and link state; periodically detecting the current link state and current auto-negotiation state of the port through the host computer in the network device; determining whether a preset forced speed reduction condition is met based on the current link state, current auto-negotiation state, and the values ​​of each counter; if the forced speed reduction condition is met, performing a speed reduction operation on the highest speed supported by the port through the host computer, and executing a counter reset operation associated with the speed reduction operation.

[0114] In some embodiments, the computer device 300 may be integrated into a terminal or server that has storage and a processor and thus computing power, or the computer device 300 may be the terminal or server.

[0115] This application also provides a computer-readable storage medium for storing a computer program. This computer-readable storage medium can be applied to a computer device, and the computer program causes the computer device to execute the corresponding processes in the methods described above in the embodiments of this application; for brevity, further details are omitted here.

[0116] This application also provides a computer program product including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the corresponding processes in the methods described above in the embodiments of this application. For brevity, these details will not be elaborated further here.

[0117] This application also provides a computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the corresponding processes in the methods described above in the embodiments of this application. For brevity, these details will not be elaborated further here.

[0118] It should be understood that the processor in the embodiments of this application may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor described above can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0119] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0120] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0121] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0122] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data processing method, characterized in that, The method includes: During the initialization phase of the network device, at least one port in the network device is configured to auto-negotiation mode and the hardware automatic speed reduction function is enabled, and multiple counters are initialized. The multiple counters are configured to record the historical changes in the auto-negotiation state and link state of the port. The host computer in the network device periodically detects the current link status and current auto-negotiation status of the port; Based on the current link state, the current auto-negotiation state, and the values ​​of each counter, determine whether the preset forced speed reduction condition is met; If the forced speed reduction condition is met, the host computer will reduce the maximum speed supported by the port and perform a counter reset operation associated with the speed reduction operation.

2. The data processing method as described in claim 1, characterized in that, The plurality of counters includes: The first counter is used to record the number of times the auto-negotiation state of the port changes; The second counter is used to record the number of times the link status of the port is continuously in the link connected state; The third counter is used to record the number of times the link status of the port is continuously in the link disconnected state; The fourth counter is used to record the cumulative number of times the speed reduction operation is performed by the host computer.

3. The data processing method as described in claim 2, characterized in that, The step of determining whether a preset forced speed reduction condition is met based on the current link state, the current auto-negotiation state, and the values ​​of each of the counters includes: Compare the current auto-negotiation state with the previously recorded auto-negotiation state of the port; If the current auto-negotiation state is inconsistent with the previously recorded auto-negotiation state of the port, then the value of the first counter is incremented. If the accumulated value of the first counter is greater than or equal to the first preset value, then the forced deceleration condition is determined to be met.

4. The data processing method as described in claim 3, characterized in that, The execution of the counter reset operation associated with the deceleration operation includes: The values ​​of the first counter and the third counter are reset to zero, and the value of the fourth counter is incremented.

5. The data processing method as described in claim 3, characterized in that, The method further includes: If the current auto-negotiation state is consistent with the previously recorded auto-negotiation state of the port, then determine whether the value of the first counter is zero; If the value of the first counter is determined to be non-zero, then the value of the third counter is incremented. If the accumulated value of the third counter is greater than the third preset value, then the values ​​of the first counter and the third counter are reset to zero.

6. The data processing method as described in claim 2, characterized in that, The method further includes: If the current link status of the port is detected to be a link connected state, then the signal quality index of the link is obtained; If the signal quality index meets the preset quality conditions, the value of the first counter is reset to zero.

7. The data processing method as described in claim 6, characterized in that, The method further includes: The value of the second counter is incremented; If the accumulated value of the second counter is greater than or equal to the second preset value, then the values ​​of the first counter and the third counter are reset to zero.

8. The data processing method as described in claim 7, characterized in that, The method further includes: If the value of the fourth counter is greater than zero, the values ​​of the first counter and the third counter are reset to zero, and the port is allowed to attempt the highest rate before the rate reduction operation in subsequent auto-negotiation.

9. The data processing method as described in claim 1, characterized in that, The step of periodically detecting the current link status and current auto-negotiation status of the port through the host computer in the network device includes: The host computer in the network device accesses the registers of the physical layer chip via the control bus at preset time intervals to obtain the current link status and current auto-negotiation status of the port.

10. The data processing method as described in claim 1, characterized in that, The step of reducing the maximum supported speed of the port via the host computer includes: The host computer reduces the maximum speed supported by the port by at least one level to guide the port to renegotiate and establish a stable link within the reduced speed range.

11. A data processing apparatus, characterized in that, The device includes: An initialization unit is used to configure at least one port in the network device to auto-negotiation mode and enable hardware automatic speed reduction function during the initialization phase of the network device, and to initialize multiple counters, which are configured to record historical changes in the auto-negotiation state and link state of the port. The detection unit is used to periodically detect the current link status and current auto-negotiation status of the port through the host computer in the network device; The judgment unit is used to determine whether the preset forced speed reduction condition is met based on the current link state, the current auto-negotiation state, and the values ​​of each of the counters. The processing unit is configured to, if the forced speed reduction condition is met, reduce the maximum speed supported by the port via the host computer and execute a counter reset operation associated with the speed reduction operation.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program adapted for loading by a processor to perform the data processing method as described in any one of claims 1-10.

13. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing a computer program, and the processor executing the data processing method as described in any one of claims 1-10 by calling the computer program stored in the memory.

14. A computer program product comprising computer instructions, characterized in that, When the computer instructions are executed by the processor, they implement the data processing method according to any one of claims 1-10.

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