PCB wire method gold plating process

Abstract

The invention discloses a PCB wire method gold plating process. The process comprises the following steps of cutting, primary external light imaging, copper and tin plating, primary film stripping, secondary external light imaging, primary alkaline etching, primary outer layer AOI, third external light imaging, gold plating, secondary film stripping, fourth external light imaging, secondary alkaline etching, secondary outer layer AOI and subsequent procedures. Only circuit pattern manufacturing is carried out in the primary external light imaging step and the copper and tin plating step, then corrosion resistance is carried out on a dry film at the position where a wire is manufactured in the secondary external light imaging step, the etching degree of a circuit and the etching degree of the pattern can be kept consistent in the primary alkaline etching process, and the etching degree of the circuit and the etching degree of the pattern can be kept consistent in the manner of respectively carrying out external light imaging and dry film compensation. The copper thickness of the subsequent wire position is ensured to be uniform, and the yield of the product is greatly improved through two times of outer layer AOI etching inspection.

Description

Technical Field

[0001] This invention relates to the field of PCB conductor technology, and in particular to a gold plating process for PCB conductors. Background Technology

[0002] The wire plating process is a common process in PCB manufacturing. In consumer PCBs, it is mainly used for gold finger / button gold plating. Since the circuit pattern is relatively regular, the wires are also relatively regular and neat, with very few wire residue issues.

[0003] Many military / aerospace products require localized gold plating (mainly for bonding), and many pads on the entire board need to be traced with conductive traces. The trace patterns are complex, and the copper plating process suffers from uneven copper plating because the patterns affect the distribution of electric field lines. During the etching of the traces, the uneven copper thickness results in incomplete copper etching (as shown below). Figure 1 This has led to frequent issues with residual wires, which has been a persistent problem for our company. The defect rate has been around 20% for a long time. The residual wires require repair or rework etching, which has a significant impact on quality and schedule. Summary of the Invention

[0004] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a PCB conductor gold plating process that can achieve uniform copper thickness in conductors and improve the cleanliness of the etching at the conductor locations.

[0005] According to an embodiment of the present invention, a PCB wire gold plating process includes the following steps: material cutting: cutting a large copper-clad board into a size suitable for subsequent processing according to engineering design requirements; Initial external light imaging: transferring the circuit pattern onto the circuit board; Copper-tin plating: Plating copper and tin onto the circuit pattern. Initial film removal: Removal of the dry film formed in non-circuit pattern areas during the initial external light imaging; Secondary external light imaging: Dry film is used to cover the board surface, and then a pattern (negative film) of the conductor position is made. Initial alkaline etching: Etching circuit patterns and wires, followed by film removal and tin removal; Initial outer layer AOI: Inspects the outer circuit pattern and conductors; Three-stage external light imaging: A dry film is applied to the conductor location; Gold plating: Applying gold plating to the circuit pattern; Secondary film removal: Removing the dry film that covered the conductor position during the three external light imaging steps; Four external light imaging: Cover the surface of the circuit pattern with a dry film; Secondary alkaline etching: Etching the conductor location to remove the conductor; Secondary outer layer AOI: Detects residual wires; Subsequent processes: Proceed with the normal subsequent process flow.

[0006] It has at least the following beneficial effects: by only creating the circuit pattern in the initial external light imaging step and the copper-tin plating step, and then creating a dry film at the conductor position for etching resistance in the secondary external light imaging, the etching degree of the circuit and pattern can be kept consistent during the initial alkaline etching. By performing external light imaging and dry film compensation separately, the copper thickness at the conductor position is ensured to be uniform. Then, by inspecting the outer layer AOI etching twice, the product yield is greatly improved.

[0007] According to some embodiments of the present invention, in the secondary external light imaging, tertiary external light imaging and quaternary external light imaging steps, a dry film is applied to the plate surface using a vacuum lamination method.

[0008] According to some embodiments of the present invention, in the initial alkaline etching step, the dry film serves as the resist layer for the conductors, while simultaneously etching the circuit pattern and the conductor pattern, followed by film removal and tin removal.

[0009] According to some embodiments of the present invention, in the initial outer layer AOI step, the detection data used for comparison is formed by superimposing the outer layer circuit pattern and the conductor pattern.

[0010] According to some embodiments of the present invention, in the secondary alkaline etching step, the copper thickness of the etched wire is uniform before etching, and is only the sum of the thickness of the base copper and the first copper plating.

[0011] According to some embodiments of the present invention, in the gold plating step, nickel-gold plating or thick gold plating is selectively performed.

[0012] According to some embodiments of the present invention, the pretreatment in the secondary and quaternary external light imaging steps includes only water washing and drying, and does not include acid washing and grinding.

[0013] According to some embodiments of the present invention, this process is used to manufacture military or aerospace printed circuit boards with partially gold-plated pads and complex circuit patterns.

[0014] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0015] The present invention will be further described below with reference to the accompanying drawings and embodiments, wherein: Figure 1 This is a process flow diagram of an embodiment of the present invention. Detailed Implementation

[0016] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0017] In the description of this invention, the use of "first" and "second" is for the purpose of distinguishing technical features only, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or the order of the technical features indicated.

[0018] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0019] Reference Figure 1 This invention discloses a PCB wire gold plating process, comprising the following steps: Material cutting: Cutting large-sized copper-clad laminates into sizes suitable for subsequent processing according to engineering design requirements; Initial external light imaging: transferring the circuit pattern onto the circuit board; Copper-tin plating: Plating copper and tin onto the circuit pattern. Initial film removal: Removal of the dry film formed in non-circuit pattern areas during the initial external light imaging; Secondary external light imaging: Dry film is used to cover the board surface, and then a pattern (negative film) of the conductor position is made. Initial alkaline etching: Etching circuit patterns and wires, followed by film removal and tin removal; Initial outer layer AOI: Inspects the outer circuit pattern and conductors; Three-stage external light imaging: A dry film is applied to the conductor location; Gold plating: Applying gold plating to the circuit pattern; Secondary film removal: Removing the dry film that covered the conductor position during the three external light imaging steps; Four external light imaging: Cover the surface of the circuit pattern with a dry film; Secondary alkaline etching: Etching the conductor location to remove the conductor; Secondary outer layer AOI: Detects residual wires; Subsequent processes: Proceed with the normal subsequent process flow.

[0020] Understandably, by only creating the circuit pattern during the initial external light imaging and copper-tin plating steps, and then creating a dry film at the conductor location for etching resistance during the second external light imaging, the etching degree of the circuit and pattern can be kept consistent during the initial alkaline etching. By performing external light imaging and dry film compensation separately, the copper thickness at the subsequent conductor location is ensured to be uniform. Then, by conducting two external AOI etching inspections, the product yield is greatly improved.

[0021] Furthermore, in the secondary, tertiary, and quaternary external light imaging steps, a vacuum film application method is used to cover the plate surface with a dry film.

[0022] Understandably, on complex circuit boards, traditional film lamination is prone to air bubbles or poor adhesion, leading to uneven distribution of the dry film resist. This unevenness distorts the distribution of electric field lines during electroplating, exacerbating uneven copper plating. Vacuum lamination ensures a tight, all-around adhesion between the dry film and the uneven surface of the complex circuit board, forming a uniform and consistent resist layer. This provides a more regular current distribution interface for the electroplating process, effectively improving the distortion of electric field lines caused by complex patterns during copper plating. It promotes uniform plating thickness from the source, laying the foundation for subsequent uniform etching and preventing incomplete etching due to excessive local copper thickness.

[0023] Furthermore, in the initial alkaline etching step, the dry film serves as the resist layer for the conductors, while simultaneously etching out the circuit pattern and conductor pattern, followed by film removal and tin removal.

[0024] Understandably, by using dry film as a resist layer for the conductors, the lack of tin plating in the conductor area is compensated for, making the etching degree of the conductor pattern and the circuit pattern more similar during etching, thus reducing the unevenness of conductor etching.

[0025] Furthermore, in the initial outer layer AOI step, the detection data used for comparison is composed of the outer layer circuit pattern and the conductor pattern superimposed.

[0026] Understandably, this step utilizes specialized inspection data generated by overlaying the outer layer circuit pattern and the conductor pattern for initial outer layer AOI, achieving a targeted and comprehensive screening of the conductor forming quality after the initial etching. It can accurately detect potential defects such as conductor width, gaps, or connection abnormalities caused by uneven copper plating. Identifying and intercepting problematic boards before they enter the expensive gold plating and subsequent cleaning processes, preventing poorly formed conductors from flowing into subsequent processes, and avoiding ineffective processing and final product failure, is a crucial step in controlling process quality and reducing rework rates.

[0027] Furthermore, in the secondary alkaline etching step, the copper thickness of the etched wires is uniform before etching, and is only the sum of the thickness of the base copper and the first copper plating.

[0028] Understandably, the removed conductor's structure consists only of the sum of the base copper and the thickness of the first copper plating layer, and this thickness is uniform thanks to the aforementioned process optimization. For this thin and uniform structure, a secondary alkaline etching process allows the etching solution to penetrate and remove the entire copper layer of the conductor more quickly and thoroughly, with a high degree of controllability. Even if micron-level thickness unevenness remains after the initial etching, this proprietary etching step can completely dissolve it, ensuring the conductor is thoroughly removed.

[0029] Furthermore, in the gold plating step, selective nickel-gold plating or thick gold plating is performed.

[0030] Understandably, this process framework is designed to accommodate solutions for diverse product needs. Whether it's a nickel-gold layer requiring excellent solderability and bonding performance, or a thick gold layer demanding high wear resistance and reliability, this framework is compatible. This flexibility ensures that the core quality issue of wire residue is addressed without sacrificing the final functionality and reliability requirements of the product, making the process widely applicable.

[0031] Furthermore, the pretreatment in the secondary and quaternary external light imaging steps only includes water washing and drying, excluding acid washing and grinding.

[0032] Understandably, for boards with pre-formed precision circuits and conductors, acid pickling can corrode the fine lines or alter the metal surface condition, while grinding can mechanically damage the formed conductors or cause surface unevenness. This damage can further distort the electric field distribution during subsequent electroplating, exacerbating uneven copper plating. The simplified pretreatment avoids these risks, protects the integrity of the formed structure, and removes interfering factors for obtaining a uniform plating layer and achieving thorough etching.

[0033] Furthermore, this process is used to manufacture military or aerospace printed circuit boards with complex circuit patterns that include partially gold-plated pads.

[0034] It is worth noting that this process is applied to military or aerospace printed circuit boards with locally gold-plated pads and complex circuit patterns. By implementing this process, circuit boards that meet the stringent quality requirements of such high-end fields can be produced stably and reliably, transforming the long-standing problem of high defect rates in production into a controllable and high-quality manufacturing process.

[0035] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0036] Of course, the present invention is not limited to the above-described embodiments. Those skilled in the art can make equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A PCB conductor gold plating process, characterized in that, Includes the following steps: Material cutting: Cutting large-sized copper-clad laminates into sizes suitable for subsequent processing according to engineering design requirements; Initial external light imaging: transferring the circuit pattern onto the circuit board; Copper-tin plating: Plating copper and tin onto the circuit pattern. Initial film removal: Removal of the dry film formed in non-circuit pattern areas during the initial external light imaging; Secondary external light imaging: Dry film is used to cover the board surface, and then a pattern (negative film) of the conductor position is made. Initial alkaline etching: Etching circuit patterns and wires, followed by film removal and tin removal; Initial outer layer AOI: Inspects the outer circuit pattern and conductors; Three-stage external light imaging: A dry film is applied to the conductor location; Gold plating: Applying gold plating to the circuit pattern; Secondary film removal: Removing the dry film that covered the conductor position during the three external light imaging steps; Four external light imaging: Cover the surface of the circuit pattern with a dry film; Secondary alkaline etching: Etching the conductor location to remove the conductor; Secondary outer layer AOI: Detects residual wires; Subsequent processes: Proceed with the normal subsequent process flow.

2. The PCB wire gold plating process according to claim 1, characterized in that, In the secondary, tertiary, and quaternary external light imaging steps, a dry film is applied to the board surface using a vacuum lamination method.

3. The PCB wire gold plating process according to claim 1, characterized in that, In the initial alkaline etching step, the dry film serves as the resist layer for the conductors, while simultaneously etching out the circuit pattern and conductor pattern. Subsequently, the film is removed and the tin is removed.

4. The PCB wire gold plating process according to claim 1, characterized in that, In the initial outer layer AOI step, the detection data used for comparison is composed of the outer layer circuit pattern and the conductor pattern superimposed.

5. The PCB wire gold plating process according to claim 1, characterized in that, In the secondary alkaline etching step, the copper thickness of the etched wires is uniform before etching, and is only the sum of the thickness of the base copper and the first copper plating.

6. The PCB wire gold plating process according to claim 1, characterized in that, In the gold plating process, selective nickel-gold plating or thick gold plating is used.

7. The PCB wire gold plating process according to claim 1, characterized in that, The pretreatment in the secondary and quaternary external light imaging steps only includes water washing and drying, excluding acid washing and grinding.

8. The PCB wire gold plating process according to claim 1, characterized in that, This process is used to manufacture military or aerospace printed circuit boards with complex circuit patterns that include partially gold-plated pads.

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