Back contact battery, battery assembly and photovoltaic system

Abstract

The invention is applicable to the field of photovoltaic technology, and provides a back contact battery, a battery assembly and a photovoltaic system, the back contact battery comprises a silicon substrate, the silicon substrate comprises a back surface and a front surface, and the back surface is provided with first areas and second areas which are alternately arranged at intervals along a first direction; at least one bulge is formed on the silicon substrate between the first region and the second region which are adjacent to each other; the first doped polycrystalline silicon layer is arranged in the first region; the second doped polycrystalline silicon layer is arranged in the second region; the isolation layer is located between the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer, and the doping concentration of the isolation layer is smaller than or equal to 1E18 / cm < 3 >; the first metal electrode is electrically connected with the first doped polycrystalline silicon layer; and the second metal electrode is electrically connected with the second doped polycrystalline silicon layer. According to the back contact battery, the electrical isolation effect between the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer can be improved, and the risk of short-circuit electric leakage is reduced.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and in particular to a back-contact battery, battery module and photovoltaic system. Background Technology

[0002] A solar cell is a semiconductor device that converts solar energy into electrical energy. Under sunlight, a solar cell generates a photocurrent, which is then output as electrical energy through electrodes. In recent years, solar cell manufacturing technology has continuously advanced, production costs have decreased, and conversion efficiency has increased. Solar cell power generation has become increasingly widespread and is an important energy source for electricity supply. In particular, because the metal electrodes of the back-contact cell are all located on the back side, the metal electrodes can avoid blocking the front of the cell. Compared to bifacial cells with metal electrodes on both the front and back, this improves cell efficiency.

[0003] In related technologies, the back side of a back contact cell is usually provided with a first doped polysilicon layer and a second doped polysilicon layer with opposite doping types. The silicon substrate of the back contact cell is usually provided with a trench between the first doped polysilicon layer and the second doped polysilicon layer to isolate the first doped polysilicon layer and the second doped polysilicon layer. However, there is still a problem that the electrical isolation effect between the first doped polysilicon layer and the second doped polysilicon layer is poor. Summary of the Invention

[0004] This invention provides a back contact battery, which aims to solve the problem of poor electrical isolation between the first doped polysilicon layer and the second doped polysilicon layer in the prior art back contact batteries.

[0005] This invention is implemented by providing a back contact battery, comprising: A silicon substrate includes a back side and a front side disposed opposite to each other. The back side has a first region and a second region disposed alternately along a first direction. The first region and the second region extend along a second direction, which intersects the first direction. The silicon substrate has at least one protrusion formed between adjacent first regions and second regions. A first doped polysilicon layer is disposed in the first region; A second doped polysilicon layer is disposed in the second region; An isolation layer is disposed on the back side and between the first doped polysilicon layer and the second doped polysilicon layer. The doping concentration of the isolation layer is less than that of the first doped polysilicon layer and the second doped polysilicon layer, and the doping concentration of the isolation layer is less than or equal to 1E18 / cm. 3 ; A first metal electrode is electrically connected to the first doped polycrystalline silicon layer; and The second metal electrode is electrically connected to the second doped polycrystalline silicon layer.

[0006] Preferably, the isolation layer is at least partially disposed on the protrusion.

[0007] Preferably, the isolation layer has trenches that partially or completely penetrate the isolation layer along the thickness direction of the silicon substrate.

[0008] Preferably, the trench partially penetrates the isolation layer along the thickness direction of the silicon substrate, and the ratio of the depth of the trench to the thickness of the isolation layer is 0.5 to 0.9.

[0009] Preferably, the trench completely penetrates the isolation layer along the thickness direction of the silicon substrate, with the center plane along the thickness direction of the silicon substrate as the reference plane, and the distance from the bottom surface of the trench to the center plane is greater than the distance from the plane containing the first region to the center plane and the distance from the plane containing the second region to the center plane.

[0010] Preferably, at least a portion of the trench penetrates the isolation layer along the second direction.

[0011] Preferably, the trench completely penetrates the isolation layer along the thickness direction of the silicon substrate, and the protrusion has a textured surface corresponding to the trench.

[0012] Preferably, the velvety structure includes at least one of a regular pyramid, an inverted pyramid, a nanopillar, and a nanopore.

[0013] Preferably, the width of the groove along the first direction is 10 to 200 micrometers.

[0014] Preferably, the height of the protrusion is 2 to 15 micrometers.

[0015] Preferably, the width of the protrusion along the first direction is 20 to 350 micrometers.

[0016] Preferably, the difference between the width of the protrusion along the first direction and the width of the groove along the first direction is greater than 20 micrometers.

[0017] Preferably, the trench is filled with a polymer insulating material.

[0018] Preferably, the height of the first metal electrode and the height of the second metal electrode are both greater than the height of the protrusion.

[0019] Preferred options also include: A first dielectric layer is disposed in the first region, located between the silicon substrate and the first doped polysilicon layer; and The second dielectric layer is disposed in the second region and is located between the silicon substrate and the second doped polysilicon layer.

[0020] Preferably, the first dielectric layer and the second dielectric layer each comprise one or a combination of at least two of the following: a silicon oxide layer, an aluminum oxide layer, a silicon carbide layer, a silicon nitride layer, a silicon oxynitride layer, and an intrinsic amorphous silicon layer.

[0021] Preferred options also include: A third dielectric layer is disposed between the isolation layer and the raised surface, and the trench penetrates the third dielectric layer along the thickness direction of the silicon substrate.

[0022] Preferably, the thickness of the third dielectric layer is greater than the thickness of at least one of the first dielectric layer and the second dielectric layer.

[0023] Preferably, the insulating layer is doped with at least one of oxygen, nitrogen, and carbon. The oxygen concentration in the isolation layer is 1×10⁻⁶. 16 ~2×10 22 atoms / cm 3 And / or, the nitrogen concentration in the isolation layer is 1×10⁻⁶. 16 ~2×10 22 atoms / cm 3 And / or, the concentration of carbon in the isolation layer is 1×10⁻⁶. 16 ~2×10 22 atoms / cm 3 .

[0024] Preferably, the number of protrusions between adjacent first and second regions is 1 to 3.

[0025] Preferably, the isolation layer further includes: A first extension extending to the first region, the first extension covering a portion of the first region, the first extension being connected to the first doped polysilicon layer along the first direction; A second extension extending into the second region, the second extension covering a portion of the second region, the second extension being connected to the second doped polysilicon layer along the first direction.

[0026] Preferably, the protrusion includes a top surface disposed away from the front side along the thickness direction of the silicon substrate, a first side surface and a second side surface disposed opposite to each other along the first direction, the first side surface and the second side surface being respectively connected to the top surface, and the isolation layer covering at least one of the top surface, the first side surface and the second side surface.

[0027] Preferably, along the thickness direction of the silicon substrate, the protrusion includes a first end portion away from the front surface and a second end portion close to the front surface, wherein the width of the first end portion along the first direction is greater than the width of the second end portion along the first direction.

[0028] Preferred options also include: A passivation layer, wherein the passivation layer at least covers the first doped polysilicon layer, the second doped polysilicon layer, and the isolation layer.

[0029] Preferably, the isolation layer is an intrinsic semiconductor layer or a doped semiconductor layer.

[0030] Preferably, the intrinsic semiconductor layer is at least one of an intrinsic polycrystalline silicon layer, an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, and an intrinsic nanocrystalline silicon layer.

[0031] Preferably, the doped semiconductor layer is at least one of a doped polycrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer.

[0032] Preferably, the doping concentration of the isolation layer is less than 2E17 / cm. 3 .

[0033] Preferably, the doping concentration of the isolation layer is less than 1E17 / cm. 3 .

[0034] Preferably, the doping concentration of both the second doped polysilicon layer and the first doped polysilicon layer is greater than 1E19 / cm. 3 .

[0035] The present invention also provides a battery assembly including the aforementioned back contact battery.

[0036] The present invention also provides a photovoltaic system including the above-described battery module.

[0037] The present invention provides a back-contact battery by forming a first region and a second region alternately spaced along a first direction on the back side of a silicon substrate. A first doped polysilicon layer is formed in the first region, and a second doped polysilicon layer is formed in the second region. At least one protrusion is formed between adjacent first and second regions on the silicon substrate, and the first and second doped polysilicon layers are separated by the at least one protrusion, thus achieving electrical isolation between the first and second doped polysilicon layers. Simultaneously, an isolation layer is formed on the back side in the region between the first and second doped polysilicon layers. The doping concentration of the isolation layer is lower than the doping concentrations of the first and second doped polysilicon layers, and the doping concentration of the isolation layer is less than or equal to 1E18 / cm². 3This controls the doping concentration of the isolation layer to be less than or equal to 1E18 / cm. 3 By utilizing a low-doping concentration isolation layer, the current transmission capability of the isolation layer is relatively weak. Under this doping concentration, the isolation layer can prevent conduction between the first and second doped polysilicon layers. The back contact battery of the present invention uses a combination of isolation layer and bumps to jointly achieve isolation between the first and second doped polysilicon layers, which can improve the electrical isolation effect between the first and second doped polysilicon layers, greatly reduce the risk of short circuit leakage between the first and second doped polysilicon layers, and improve the performance of the back contact battery. Attached Figure Description

[0038] Figure 1 A cross-sectional schematic diagram of the back contact battery of the first embodiment provided in this invention; Figure 2 This is a schematic diagram of the back contact battery portion structure of the first embodiment of the present invention; Figure 3 for Figure 1 A magnified view of part A in the middle; Figure 4 A cross-sectional schematic diagram of the back contact battery according to a second embodiment of the present invention; Figure 5 A cross-sectional schematic diagram of the back contact battery according to a third embodiment of the present invention; Figure 6 A cross-sectional schematic diagram of the back contact battery according to the fourth embodiment of the present invention; Figure 7 for Figure 6 A magnified view of part B in the middle; Figure 8 This is a schematic diagram of the back contact battery portion structure of the fourth embodiment provided in this invention. Figure 9 A partial cross-sectional schematic diagram of the back contact battery of the fifth embodiment of the present invention; Figure 10 A cross-sectional schematic diagram of the back contact battery according to the sixth embodiment of the present invention; Figure 11 This is a cross-sectional schematic diagram of the back contact battery according to the seventh embodiment of the present invention.

[0039] Explanation of key symbols: Back contact battery 100, silicon substrate 1, back side 11, front side 12, first direction X, second direction Y, first region 111, second region 112, protrusion 13, first doped polycrystalline silicon layer 2, second doped polycrystalline silicon layer 3, isolation layer 4, trench 40, textured structure 1311, first metal electrode 5, second metal electrode 6, polymer insulating material 7, first dielectric layer 8, second dielectric layer 9, third dielectric layer 10, first extension 41, second extension 42, passivation layer 15, top surface 130, first side surface 131, second side surface 132. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. Examples of embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the invention, and should not be construed as limiting the invention. Furthermore, it should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0041] In the description of this invention, it should be understood that the terms "upper", "lower", "back", "front", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0042] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0043] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0044] Please refer to Figures 1-4 This invention provides a back contact battery 100, comprising: The silicon substrate 1 includes a back side 11 and a front side 12 disposed opposite to each other. The back side 11 has a first region 111 and a second region 112 disposed alternately along a first direction X. The first region 111 and the second region 112 extend along a second direction Y, which intersects with the first direction X. The silicon substrate 1 has at least one protrusion 13 formed between adjacent first regions 111 and second regions 112. A first doped polysilicon layer 2 is disposed in the first region 111; A second doped polysilicon layer 3 is disposed in the second region 112; An isolation layer 4 is provided on the back side 11 and located between the first doped polysilicon layer 2 and the second doped polysilicon layer 3. The doping concentration of the isolation layer 4 is less than the doping concentration of the first doped polysilicon layer 2 and the second doped polysilicon layer 3, and the doping concentration of the isolation layer 4 is less than or equal to 1E18 / cm. 3 ; The first metal electrode 5 is electrically connected to the first doped polycrystalline silicon layer 2; and The second metal electrode 6 is electrically connected to the second doped polycrystalline silicon layer 3.

[0045] An embodiment of the present invention provides a back-contact battery 100 by forming a first region 111 and a second region 112 alternately spaced along a first direction X on the back side 11 of a silicon substrate 1. A first doped polysilicon layer 2 is formed in the first region 111, and a second doped polysilicon layer 3 is formed in the second region 112. At least one protrusion 13 is formed between adjacent first regions 111 and second regions 112 on the silicon substrate 1. Thus, the first doped polysilicon layer 2 and the second doped polysilicon layer 3 are separated by at least one protrusion 13, which can achieve electrical isolation between the first doped polysilicon layer 2 and the second doped polysilicon layer 3. At the same time, an isolation layer 4 is formed on the back side 11, located between the first doped polysilicon layer 2 and the second doped polysilicon layer 3. The doping concentration of the isolation layer 4 is less than the doping concentration of the first doped polysilicon layer 2 and the second doped polysilicon layer 3, and the doping concentration of the isolation layer 4 is less than or equal to 1E18 / cm. 3 Thus, the doping concentration of isolation layer 4 is controlled to be less than or equal to 1E18 / cm. 3 By utilizing the low doping concentration of the isolation layer 4, the current transmission capability of the isolation layer 4 is relatively weak. Under this doping concentration, the isolation layer 4 can further prevent the conduction between the first doped polysilicon layer 2 and the second doped polysilicon layer 3. The back contact battery 100 of the present invention utilizes the combination of the isolation layer 4 and the protrusion 13, which can greatly improve the electrical isolation effect between the first doped polysilicon layer 2 and the second doped polysilicon layer 3, greatly reduce the risk of short circuit leakage between the first doped polysilicon layer 2 and the second doped polysilicon layer 3, thereby improving the performance of the back contact battery 100.

[0046] In this embodiment of the invention, the silicon substrate 1 includes a back side 11 and a front side 12 disposed opposite to each other along the thickness direction Z of the silicon substrate 1. The front side 12 of the silicon substrate 1 is the side of the silicon substrate 1 that mainly receives sunlight when the back contact battery 100 is working normally, and the back side 11 of the silicon substrate 1 is the surface opposite to the front side 12 of the silicon substrate 1.

[0047] In this embodiment of the invention, the first region 111 and the second region 112 extend along the second direction Y, that is, the length direction of both the first region 111 and the second region 112 is along the second direction Y. There are multiple first doped polysilicon layers 2 and second doped polysilicon layers 3, which are alternately arranged along the first direction X, and both extend along the second direction Y. In this embodiment of the invention, the protrusion 13 and the isolation layer 4 also extend along the second direction Y, that is, the length direction of the first doped polysilicon layer 2, the second doped polysilicon layer 3, the protrusion 13, and the isolation layer 4 is all along the second direction Y. Preferably, the size of the protrusion 13 along the second direction Y is equal to the size of the isolation layer 4 along the second direction Y, and the size of the protrusion 13 along the second direction Y is equal to the size of either the first doped polysilicon layer 2 or the second doped polysilicon layer 3 along the second direction Y. The first direction X and the second direction Y can be perpendicular or not perpendicular. Preferably, the first direction X and the second direction Y are perpendicular.

[0048] In this embodiment of the invention, one of the first doped polysilicon layer 2 and the second doped polysilicon layer 3 is a P-type doped polysilicon layer, and the other is an N-type doped polysilicon layer. The specific doping type of the first doped polysilicon layer 2 and the second doped polysilicon layer 3 is not limited. Specifically, the first doped polysilicon layer 2 can be a P-type doped polysilicon layer, and the second doped polysilicon layer 3 can be an N-type doped polysilicon layer; or, the first doped polysilicon layer 2 can be an N-type doped polysilicon layer, and the second doped polysilicon layer 3 can be a P-type doped polysilicon layer. The P-type doped polysilicon layer is doped with a P-type dopant element, that is, it is doped with P-type dopant atoms; the N-type doped polysilicon layer is doped with an N-type dopant element, that is, it is doped with N-type dopant atoms. The P-type dopant element is a Group IIIA element in the periodic table, and the N-type dopant element is a Group VA element in the periodic table. For example, the P-type dopant element can be boron, and the N-type dopant element can be phosphorus.

[0049] In this embodiment of the invention, the isolation layer 4 may or may not be disposed on the surface of the protrusion 13. That is, the surface of the protrusion 13 may be covered by the isolation layer 4, or the surface of the protrusion 13 may not be covered by the isolation layer 4. When the isolation layer 4 is disposed on the surface of the protrusion 13, the isolation layer 4 covers at least a portion of the surface of the protrusion 13, that is, the isolation layer 4 may cover a portion of the surface of the protrusion 13 or cover the entire surface of the protrusion 13. In this case, a portion or all of the surface of the protrusion 13 is covered by the isolation layer 4.

[0050] like Figure 1 As shown, in one embodiment of the present invention, the isolation layer 4 is at least partially disposed on the protrusion 13.

[0051] In this embodiment, the isolation layer 4 is at least partially disposed on the protrusion 13. This can be understood as the isolation layer 4 covering at least a portion of the surface of the protrusion 13, with some or all of the surface of the protrusion 13 covered by the isolation layer 4. In practical applications, the back contact battery 100 may have the isolation layer 4 disposed on a portion of the surface of the protrusion 13, or it may have the isolation layer 4 disposed on all the surface of the protrusion 13. Since the isolation layer 4 is at least partially disposed on the protrusion 13, that is, by adding the isolation layer 4 to the protrusion 13, the superimposed isolation layer 4 on the surface of the protrusion 13 can improve the electrical isolation effect between the protrusion 13 and the first doped polysilicon layer 2 and the second doped polysilicon layer 3. Moreover, due to the presence of the protrusion 13, the isolation layer 4 is disposed on the surface of the protrusion 13, which helps to increase the height of the protrusion 13. Furthermore, the isolation layer 4 can extend along the surface of the protrusion 13 from the first region 111 to the second region 112, which helps to increase the height of the isolation layer 4 along the protrusion 13. The increased surface size, which increases the creepage distance between the first doped polysilicon layer 2 and the second doped polysilicon layer 3, greatly improves the electrical isolation effect of the isolation layer 4 between the first doped polysilicon layer 2 and the second doped polysilicon layer 3. Therefore, the isolation layer 4 is at least partially disposed on the protrusion 13, which can further increase the electrical isolation effect between the first doped polysilicon layer 2 and the second doped polysilicon layer 3, further reduce the risk of short circuit leakage between the first doped polysilicon layer 2 and the second doped polysilicon layer 3, and better improve the performance of the back contact battery 100.

[0052] like Figure 4 As shown, in another embodiment of the present invention, the isolation layer 4 may not be provided on the protrusion 13.

[0053] In this embodiment, the isolation layer 4 is not disposed on the protrusion 13, that is, the surface of the protrusion 13 is not covered by the isolation layer 4. The isolation layer 4 can be disposed in the region between the first doped polysilicon layer 2 and the second doped polysilicon layer 3 where the protrusion 13 is not disposed. For example, the isolation layer 4 is disposed in the region of the first region 111 near the protrusion 13, and / or, the isolation layer 4 is disposed in the region of the second region 112 near the protrusion 13. Electrical isolation between the first doped polysilicon layer 2 and the second doped polysilicon layer 3 can also be achieved using the protrusion 13 and the isolation layer 4. In addition, in some embodiments, when multiple protrusions 13 are disposed between adjacent first doped polysilicon layers 2 and second doped polysilicon layers 3, the isolation layer 4 can only cover the region between adjacent protrusions 13 on the back surface 11, or the isolation layer 4 can only cover the surface of the protrusion 13, or the isolation layer 4 can cover both the surface of the protrusion 13 and the region between adjacent protrusions 13 on the back surface 11.

[0054] In this embodiment of the invention, at least one protrusion 13 is provided between adjacent first doped polysilicon layer 2 and second doped polysilicon layer 3. The first doped polysilicon layer 2 and the second doped polysilicon layer 3 are isolated by the protrusion 13 and the isolation layer 4 to achieve good electrical isolation between the second doped polysilicon layer 3 and the first doped polysilicon layer 2.

[0055] In this embodiment of the invention, the protrusion 13 protrudes towards the back surface 11 away from the silicon substrate 1, relative to the plane of the first region 111 and the plane of the second region 112. This causes the first doped polysilicon layer 2 and the second doped polysilicon layer 3 to be located on opposite sides of the protrusion 13 along the first direction X. In this way, the protrusion 13 physically isolates the first doped polysilicon layer 2 and the second doped polysilicon layer 3, achieving electrical isolation between the first doped polysilicon layer 2 and the second doped polysilicon layer 3. The number of protrusions 13 formed on the silicon substrate 1 between adjacent first regions 111 and second regions 112 is unlimited.

[0056] For example, such as Figure 1 As shown, a protrusion 13 is formed between adjacent first regions 111 and second regions 112 in the silicon substrate 1. An isolation layer 4 is disposed on the protrusion 13. The first doped polysilicon layer 2 and the second doped polysilicon layer 3 are isolated by the protrusion 13 and the isolation layer 4. For example, as... Figure 5 As shown, the silicon substrate 1 forms two protrusions 13 between adjacent first regions 111 and second regions 112. The two protrusions 13 are spaced apart in the first direction X. An isolation layer 4 is disposed on both protrusions 13. The first doped polysilicon layer 2 and the second doped polysilicon layer 3 are isolated by the two protrusions 13 and the isolation layer 4, which can further improve the electrical isolation effect between the first doped polysilicon layer 2 and the second doped polysilicon layer 3.

[0057] For example, the silicon substrate 1 can form three protrusions 13 between adjacent first regions 111 and second regions 112. The three protrusions 13 are spaced apart in the first direction X. The first doped polysilicon layer 2 and the second doped polysilicon layer 3 are isolated by the three protrusions 13. An isolation layer 4 is simultaneously disposed on the three protrusions 13, which can further improve the isolation effect between the first doped polysilicon layer 2 and the second doped polysilicon layer 3. Of course, the number of protrusions 13 formed on the silicon substrate 1 between adjacent first regions 111 and second regions 112 can be greater than three, which can further improve the electrical isolation effect between the first doped polysilicon layer 2 and the second doped polysilicon layer 3.

[0058] In a preferred embodiment of the present invention, the number of protrusions 13 between adjacent first regions 111 and second regions 112 is 1 to 3.

[0059] In this embodiment, the number of protrusions 13 between adjacent first regions 111 and second regions 112 is controlled to be 1 to 3. This can achieve good electrical isolation between the first doped polysilicon layer 2 and the second doped polysilicon layer 3, and avoid the excessive number of protrusions 13 between the first regions 111 and second regions 112, which would result in an excessively large area ratio of the protrusions 13. This ensures sufficient area for the first regions 111 and second regions 112, thereby guaranteeing good power generation efficiency of the battery.

[0060] In this embodiment of the invention, when the isolation layer 4 is at least partially disposed on the protrusion 13, the isolation layer 4 may cover only a portion of the protrusion 13, or it may cover the entire protrusion 13. Specifically, when there is one protrusion 13 between adjacent first regions 111 and second regions 112, the isolation layer 4 covers at least a portion of the protrusion 13. This can be understood as the isolation layer 4 covering a portion or all of the protrusion 13; when there are two or more protrusions 13 between adjacent first regions 111 and second regions 112, that is, when there are two or more protrusions 13, the isolation layer 4 covers a portion or all of at least one protrusion 13.

[0061] In this embodiment of the invention, the specific shape of the protrusion 13 is not limited, and the protrusion 13 can specifically be a boss. The cross-sectional shape of the protrusion 13 can be at least one of square, semi-circular, and trapezoidal.

[0062] Please refer to this again. Figure 3 As an embodiment of the present invention, the protrusion 13 includes a top surface 130 disposed away from the front surface 12 along the thickness direction Z of the silicon substrate 1, a first side surface 131 and a second side surface 132 disposed opposite to each other along the first direction X, the first side surface 131 and the second side surface 132 being connected to the top surface 130 respectively, and the isolation layer 4 covering at least one of the top surface 130, the first side surface 131 and the second side surface 132.

[0063] In this embodiment, the isolation layer 4 covers at least one of the top surface 130, the first side surface 131, and the second side surface 132. This can be understood as the isolation layer 4 covering only a portion of at least one of the top surface 130, the first side surface 131, and the second side surface 132, or covering the entire area of ​​at least one of the top surface 130, the first side surface 131, and the second side surface 132. Preferably, the isolation layer 4 simultaneously covers the top surface 130, the first side surface 131, and the second side surface 132, which can greatly increase the spread length of the isolation layer 4 along the surface of the protrusion 13, and is more conducive to improving the isolation effect of the isolation layer 4 on the first doped polysilicon layer 2 and the second doped polysilicon layer 3.

[0064] In this embodiment of the invention, the isolation layer 4 may be doped with p-type or n-type doped atoms, or it may not be doped with p-type or n-type doped atoms. When the isolation layer 4 is not doped with p-type or n-type doped atoms, the doping concentration of the isolation layer 4 is 0 / cm. 3 When the isolation layer 4 is doped with P-type or N-type dopant atoms, the doping type of the isolation layer 4 is the same as that of the first doped polysilicon layer 2 or the second doped polysilicon layer 3. That is, the doping type of the isolation layer 4 is the same as that of the first doped polysilicon layer 2, or the doping type of the isolation layer 4 is the same as that of the second doped polysilicon layer 3. Specifically, both the isolation layer 4 and the first doped polysilicon layer 2 are doped with P-type dopant atoms, and the second doped polysilicon layer 3 is doped with N-type dopant atoms; or, both the isolation layer 4 and the first doped polysilicon layer 2 are doped with N-type dopant atoms, and the second doped polysilicon layer 3 is doped with P-type dopant atoms.

[0065] In this embodiment of the invention, the doping concentration of the isolation layer 4 is the concentration of doped atoms in the active state in the isolation layer 4, the doping concentration of the first doped polysilicon layer 2 is the concentration of doped atoms in the active state in the first doped polysilicon layer 2, and the doping concentration of the second doped polysilicon layer 3 is the concentration of doped atoms in the active state in the second doped polysilicon layer 3.

[0066] Specifically, when the doping type of the isolation layer 4 is P-type, the doping concentration of the isolation layer 4 is the concentration of the active P-type doped atoms in the isolation layer 4; conversely, when the doping type of the isolation layer 4 is N-type, the doping concentration of the isolation layer 4 is the concentration of the active N-type doped atoms in the isolation layer 4.

[0067] When the doping type of the first doped polysilicon layer 2 is P-type, the doping concentration of the first doped polysilicon layer 2 is the concentration of P-type doped atoms in the active state in the first doped polysilicon layer 2; when the doping type of the first doped polysilicon layer 2 is N-type, the doping concentration of the first doped polysilicon layer 2 is the concentration of N-type doped atoms in the active state in the first doped polysilicon layer 2.

[0068] When the doping type of the second doped polysilicon layer 3 is P-type, the doping concentration of the second doped polysilicon layer 3 is the concentration of P-type doped atoms in the active state in the second doped polysilicon layer 3; when the doping type of the second doped polysilicon layer 3 is N-type, the doping concentration of the second doped polysilicon layer 3 is the concentration of N-type doped atoms in the active state in the second doped polysilicon layer 3.

[0069] In this embodiment of the invention, the doping concentration of the isolation layer 4 is less than the doping concentration of the first doped polysilicon layer 2 and the second doped polysilicon layer 3. This can be understood as the concentration of active doped atoms in the isolation layer 4 being less than the concentration of active doped atoms in the first doped polysilicon layer 2, and the concentration of active doped atoms in the isolation layer 4 being less than the concentration of active doped atoms in the second doped polysilicon layer 3.

[0070] The doping concentration of the isolation layer 4 is less than or equal to 1E18 / cm³. 3 This can be understood as the concentration of doped atoms in the active state in isolation layer 4 being less than or equal to 1E18 / cm³. 3 For example, if the doped atom in isolation layer 4 is a phosphorus atom, then the concentration of activated phosphorus atoms in isolation layer 4 is less than or equal to 1E18 / cm³. 3 If the doped atom in isolation layer 4 is boron atom, then the concentration of active boron atom in isolation layer 4 is less than or equal to 1E18 / cm³. 3 .

[0071] In this embodiment of the invention, the doping concentration of the isolation layer 4 can be less than or equal to 1E18 / cm². 3 Any value in the range. For example, the doping concentration of the isolation layer 4 can be 0 / cm. 3 1E3 / cm 3 1E4 / cm 3 1E5 / cm 3 1E6 / cm 3 1E8 / cm 3 1E9 / cm 3 1E10 / cm 3 1E11 / cm 3 1E12 / cm 3 1E13 / cm 3 1E14 / cm 3 1E15 / cm 3 1E16 / cm 3 1E17 / cm 3 2E17 / cm 3 3E17 / cm 3 4E17 / cm 3 5E17 / cm 3 1E18 / cm 3 Any value in the range.

[0072] As an embodiment of the present invention, the isolation layer 4 is an intrinsic semiconductor layer or a doped semiconductor layer.

[0073] In this embodiment of the invention, the isolation layer 4 may be made of the same material as the first doped polysilicon layer 2 and the second doped polysilicon layer 3, or it may be made of a different material. The isolation layer 4 is an intrinsic semiconductor layer or a doped semiconductor layer, and the doping concentration of the isolation layer 4 is less than or equal to 1E18 / cm². 3 Within this doping concentration range, the current transport capability of the isolation layer 4 is relatively weak, thus achieving isolation between the first doped polysilicon layer 2 and the second doped polysilicon layer 3. Of course, in some embodiments, the isolation layer 4 can also be an insulating material. For example, the isolation layer 4 can be a stack of one or more of silicon oxide, silicon nitride, and silicon oxynitride layers, and the doping concentration of the isolation layer 4 is less than or equal to 1E18 / cm³. 3 .

[0074] As an embodiment of the present invention, the intrinsic semiconductor layer is at least one of an intrinsic polycrystalline silicon layer, an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, and an intrinsic nanocrystalline silicon layer. It can be understood that the isolation layer 4 can be one or a stack of at least two of the intrinsic polycrystalline silicon layer, intrinsic amorphous silicon layer, intrinsic microcrystalline silicon layer, and intrinsic nanocrystalline silicon layer. Preferably, the isolation layer 4 is an intrinsic amorphous silicon layer or an intrinsic polycrystalline silicon layer, which can better achieve electrical isolation between the first doped polycrystalline silicon layer 2 and the second doped polycrystalline silicon layer 3.

[0075] In one embodiment of the present invention, the doped semiconductor layer is at least one of a doped polycrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer. Preferably, the isolation layer 4 and the first doped polycrystalline silicon layer 2 are integrally formed, which facilitates the integral molding and fabrication of the isolation layer 4 and the first doped polycrystalline silicon layer 2. Specifically, the first doped polycrystalline silicon layer 2, the second doped polycrystalline silicon layer 3, and the isolation layer 4 are all doped polycrystalline silicon layers, and the doping type of the isolation layer 4 is the same as the doping type of the first doped polycrystalline silicon layer 2 or the second doped polycrystalline silicon layer 3.

[0076] In one embodiment of the present invention, the doping concentration of the isolation layer 4 is less than 2E17 / cm. 3 .

[0077] In this embodiment, the doping concentration of the isolation layer 4 is controlled to be less than 2E17 / cm. 3 This further reduces the doping concentration of isolation layer 4, which helps to ensure the good electrical isolation effect of isolation layer 4.

[0078] As an embodiment of the present invention, the doping concentration of the isolation layer 4 is less than 1E17 / cm. 3 .

[0079] In this embodiment, the doping concentration of the isolation layer 4 is controlled to be less than 1E17 / cm. 3 This further reduces the doping concentration of isolation layer 4, which helps to ensure the good isolation effect of isolation layer 4.

[0080] In one embodiment of the present invention, both the first doped polysilicon layer 2 and the isolation layer 4 are doped with group VA elements, the second doped polysilicon layer 3 is doped with group IIIA elements, and the doping concentration of the isolation layer 4 is less than 3E17 / cm³. 3 .

[0081] In this embodiment, both the first doped polysilicon layer 2 and the isolation layer 4 are doped with elements from Group VA of the periodic table, and the second doped polysilicon layer 3 is doped with elements from Group IIIA of the periodic table. The doping concentration of the isolation layer 4 is controlled to be less than 3E17 / cm³. 3 This ensures good isolation effect of isolation layer 4, while also facilitating the control of doping concentration and processing.

[0082] In one embodiment of the present invention, both the first doped polysilicon layer 2 and the isolation layer 4 are doped with group IIIA elements, the second doped polysilicon layer 3 is doped with group VA elements, and the doping concentration of the isolation layer 4 is less than 1E17 / cm³. 3 .

[0083] In this embodiment, both the first doped polysilicon layer 2 and the isolation layer 4 are doped with Group IIIA elements from the periodic table, and the second doped polysilicon layer 3 is doped with Group VA elements from the periodic table. The doping concentration of the isolation layer 4 is controlled to be less than 1E17 / cm³. 3 This ensures good isolation effect of isolation layer 4, while also facilitating the control of doping concentration and processing.

[0084] In one embodiment of the present invention, the doping concentrations of both the second doped polysilicon layer 3 and the first doped polysilicon layer 2 are greater than 1E19 / cm². 3 .

[0085] In this embodiment, the doping concentrations of both the second doped polysilicon layer 3 and the first doped polysilicon layer 2 are controlled to be greater than 1E19 / cm. 3 This ensures lower contact resistance between the first doped polysilicon layer 2 and the first metal electrode 5, and between the second doped polysilicon layer 3 and the second metal electrode 6, which is more conducive to improving battery efficiency.

[0086] Please refer to the reference. Figures 5-8 As an embodiment of the present invention, the isolation layer 4 has a trench 40, which partially or completely penetrates the isolation layer 4 along the thickness direction Z of the silicon substrate 1.

[0087] In this embodiment, the isolation layer 4 has trenches 40. This can be understood as all isolation layers 4 of the back contact battery 100 having trenches 40, or only a portion of the isolation layers 4 of the back contact battery 100 having trenches 40. The trenches 40 are located at the top surface 130 of the protrusion 13, and the depth direction of the trenches 40 is the same as the thickness direction Z of the silicon substrate 1, which facilitates the processing of the trenches 40.

[0088] In this embodiment, trenches 40 are formed in the isolation layer 4. The trenches 40 can completely penetrate the isolation layer 4 or partially penetrate it along the thickness direction Z of the silicon substrate 1. By forming trenches 40 in the isolation layer 4, the conductivity of the isolation layer 4 can be reduced, thereby improving the electrical isolation effect of the isolation layer 4 on the second doped polysilicon layer 3 and the first doped polysilicon layer 2.

[0089] Please refer to Figures 6-7 As an embodiment of the present invention, the trench 40 completely penetrates the isolation layer 4 along the thickness direction Z of the silicon substrate 1. Taking the center plane P on the thickness direction Z of the silicon substrate 1 as the reference plane, the distance H3 from the bottom surface of the trench 40 to the center plane P is greater than the distance H1 from the plane where the first region 111 is located to the center plane P and the distance H2 from the plane where the second region 112 is located to the center plane P.

[0090] In this embodiment, the trench 40 completely penetrates the isolation layer 4 along the thickness direction Z of the silicon substrate 1. That is, the depth of the trench 40 is greater than the thickness of the isolation layer 4. The trench 40 exposes the silicon substrate 1, so that the isolation layer 4 is at least partially blocked, which can further improve the electrical isolation effect of the isolation layer 4 on the second doped polysilicon layer 3 and the first doped polysilicon layer 2.

[0091] Wherein, the central plane P in the thickness direction Z of the silicon substrate 1 is parallel to the plane containing the front surface 12 and the first region 111, and the central plane P in the thickness direction Z of the silicon substrate 1 is located between the plane containing the front surface 12 and the first region 111, and the central plane P in the thickness direction Z of the silicon substrate 1 can be located at the center position or a non-center position between the plane containing the front surface 12 and the first region 111; or, the central plane P in the thickness direction Z of the silicon substrate 1 is parallel to the plane containing the front surface 12 and the second region 112, and the central plane P in the thickness direction Z of the silicon substrate 1 is located between the plane containing the front surface 12 and the second region 112, and the central plane P in the thickness direction Z of the silicon substrate 1 can be located at the center position or a non-center position between the plane containing the front surface 12 and the second region 112.

[0092] In this embodiment, the distance H3 from the bottom surface of the trench 40 to the center plane P in the thickness direction Z of the silicon substrate 1 is greater than the distance H1 from the plane where the first region 111 is located to the center plane P and the distance H2 from the plane where the second region 112 is located to the center plane P. This avoids the trench 40 from being too deep and exceeding the plane where the first region 111 is located and the plane where the second region 112 is located, thereby reducing the risk of the cell bending or cracking due to the trench 40 being too deep, and also avoiding large recombination losses caused by the trench 40 being too deep.

[0093] Please refer to the reference. Figure 8 As an embodiment of the present invention, at least a portion of the trench 40 penetrates the isolation layer 4 along the second direction Y.

[0094] In this embodiment, at least a portion of the trenches 40 penetrate the isolation layer 4 along the second direction Y, such that the isolation layer 4 is divided into two completely isolated parts by the trenches 40. These two isolated parts are not connected to each other, thereby achieving good insulation between the two parts. This further reduces the conductivity of the isolation layer 4 and greatly improves the electrical isolation effect of the isolation layer 4 on the second doped polysilicon layer 3 and the first doped polysilicon layer 2. Preferably, each trench 40 penetrates the corresponding isolation layer 4 along the second direction Y.

[0095] In some embodiments, at least some of the trenches 40 may not completely penetrate the isolation layer 4 along the second direction Y, that is, at least a portion of the trenches 40 may have dimensions along the second direction Y that are smaller than the dimensions of the isolation layer 4 along the second direction Y.

[0096] For example, the ratio of the dimension of the trench 40 along the first direction X to the dimension of the separator 4 along the first direction X can be 10% to 70%, and the ratio of the dimension of the trench 40 along the second direction Y to the dimension of the separator 4 along the second direction Y can be 0.05% to 5%. In this case, during the metal electrode printing process, the trench 40 can be used as a mark point, and the position of the trench 40 can be identified by a vision system to adjust the position of the battery or screen, ensuring battery alignment accuracy and improving the printing accuracy of the metal electrode. In some embodiments, some of the trenches 40 penetrate the separator 4 along the second direction Y, while some of the trenches 40 do not completely penetrate the separator 4 along the second direction Y. This can better improve the isolation effect of a portion of the separator 4, and the trenches 40 on a portion of the separator 4 can be used as mark points to facilitate battery positioning and improve the printing accuracy of the metal electrode.

[0097] Please refer to the reference. Figure 7 As an embodiment of the present invention, the width W4 of the groove 40 along the first direction X is 10~200 micrometers.

[0098] In this embodiment, the width W4 of the trench 40 along the first direction X is controlled to be 10~200 micrometers. This ensures the good isolation effect of the isolation layer 4 while avoiding excessive composite loss due to an excessively large width of the trench 40 along the first direction X. For example, the width W4 of the trench 40 along the first direction X can be any value among 10 micrometers, 15 micrometers, 20 micrometers, 25 micrometers, 32 micrometers, 35 micrometers, 40 micrometers, 45 micrometers, 50 micrometers, 60 micrometers, 70 micrometers, 80 micrometers, 90 micrometers, 95 micrometers, 100 micrometers, 120 micrometers, 125 micrometers, 130 micrometers, 140 micrometers, 150 micrometers, 160 micrometers, 170 micrometers, 180 micrometers, 190 micrometers, and 200 micrometers.

[0099] As an embodiment of the present invention, the trench 40 completely penetrates the isolation layer 4 along the thickness direction Z of the silicon substrate 1, and the protrusion 13 is provided with a textured structure 1311 on the surface of the trench 40.

[0100] In this embodiment, the groove 40 is disposed at the position of the protrusion 13, and the protrusion 13 has a textured surface 1311 on the surface corresponding to the groove 40. Due to the presence of the textured surface 1311, the absorption of incident sunlight on the back side 11 can be increased, which is beneficial to improving the utilization rate of sunlight and thus improving the battery efficiency. The textured surface 1311 can be disposed on both the bottom surface and the inner wall surface of the groove 40.

[0101] As an embodiment of the present invention, the velvet structure 1311 includes at least one of a regular pyramid, an inverted pyramid, a nanopillar, and a nanopore.

[0102] In this embodiment, the specific structure of the textured structure 1311 is not limited. The textured structure 1311 can be one of a regular pyramid, an inverted pyramid, a nanopillar, or a nanopore. The textured structure 1311 can also be a combination of at least two of the following: a regular pyramid, an inverted pyramid, a nanopillar, or a nanopore. By configuring the textured structure 1311 to include at least one of the following: a regular pyramid, an inverted pyramid, a nanopillar, or a nanopore, a good light-trapping effect can be achieved, which is beneficial for improving the absorption of incident sunlight on the back side 11 and improving the power generation efficiency of the battery's back side 11.

[0103] For example, when the textured structure 1311 is a right-side-up pyramid, the height of the textured structure 1311 can be greater than or equal to 0.1 μm and less than or equal to 4 μm. For example, the height of the textured structure 1311 can be 0.1 μm, 0.5 μm, 0.9 μm, 1 μm, 1.2 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.8 μm, 2 μm, 2.2 μm, 2.5 μm, 3 μm, 3.5 μm, or 4 μm, etc. In this case, the height of the textured structure 1311 is within the above range, which helps to prevent the specific surface area of ​​the textured morphology region from being too small due to the height of the textured structure 1311 being too small. This further makes the textured structure 1311 have a higher light-trapping effect and reduces the deposition quality difference of the passivation layer 15 in different regions of the textured structure 1311, thereby improving the passivation effect of the surface passivation layer 15. In addition, in order to reduce the reflection of sunlight by the front side 12, the front side 12 is also provided with a velvety surface, which is not shown in the attached figure.

[0104] Please refer to the reference. Figure 9 In another embodiment of the present invention, the trench 40 extends through the isolation layer 4 along the thickness direction Z of the silicon substrate 1, and the ratio of the depth H5 of the trench 40 to the thickness D6 of the isolation layer 4 is 0.5 to 0.9.

[0105] In this embodiment, the trench 40 partially penetrates the isolation layer 4 along the thickness direction Z of the silicon substrate 1. This can be understood as at least a portion of the trenches 40 penetrating the isolation layer 4 along the thickness direction Z of the silicon substrate 1. The depth H5 of the trench 40 is less than the thickness D6 of the isolation layer 4, meaning the isolation layer 4 is thinned at the trench 40 location. Due to the presence of the trench 40, the conductivity of the isolation layer 4 is reduced, thereby improving the electrical isolation effect of the isolation layer 4 on the second doped polysilicon layer 3 and the first doped polysilicon layer 2. Furthermore, since the trench 40 penetrates at least a portion of the thickness of the isolation layer 4, it does not completely penetrate the isolation layer 4 along the thickness direction Z of the silicon substrate 1. This avoids damage to the interior of the silicon substrate 1 during laser trenching, preventing the formation of recombination centers and avoiding significant recombination losses in the battery. Preferably, the trench 40 is located at the top surface 130 of the protrusion 13.

[0106] In this embodiment, when the trench 40 penetrates the isolation layer 4 along the thickness direction Z of the silicon substrate 1, the ratio of the depth H5 of the trench 40 to the thickness D6 of the isolation layer 4 is controlled to be 0.5~0.9. This can improve the electrical isolation effect of the isolation layer 4 on the second doped polysilicon layer 3 and the first doped polysilicon layer 2, and avoid the trench 40 from being too deep. This prevents excessive recombination damage to the isolation layer 4 caused by the laser trenching 40, ensuring low battery recombination loss and thus ensuring battery efficiency.

[0107] Please refer to the reference. Figure 10As an embodiment of the present invention, the trench 40 is filled with polymer insulating material 7.

[0108] In this embodiment, the polymer insulating material 7 can be one or a combination of at least two of the following: parylene, fluorinated polymer, epoxy resin, acrylate, polyimide, and phenolic resin. Using these materials ensures good insulation performance, improves the insulation effect at the trench 40 location, and provides good stress relief at the trench 40 location, reducing the risk of microcracks or warping in the back contact battery 100. Of course, the specific material of the polymer insulating material 7 is not limited to these; it can also be other polymer insulating materials.

[0109] Please refer to this again. Figure 1 and Figure 3 As an embodiment of the present invention, the height H0 of the protrusion 13 is 2 to 15 micrometers.

[0110] In this embodiment, the height H0 of the protrusion 13 is the greater of the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing the first region 111, and the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing the second region 112. Specifically, if the plane containing the first region 111 and the plane containing the second region 112 are coplanar, that is, the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing the first region 111 and the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing the second region 112 are the same, then the height H0 of the protrusion 13 is the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing either the first region 111 or the second region 112; if the plane containing the first region 111 and the plane containing the second region 112 are not coplanar, the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing either the first region 111 or the second region 112 is the same. If the distance to the plane containing the first region 111 is greater than the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing the second region 112, then the height H0 of the protrusion 13 is the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing the first region 111; conversely, if the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing the second region 112 is greater than the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing the first region 111, then the height H0 of the protrusion 13 is the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing the second region 112.

[0111] In this embodiment, the height of the protrusion 13 is controlled to be 2~15 micrometers, which can achieve good electrical isolation between the second doped polysilicon layer 3 and the first doped polysilicon layer 2, and facilitate the processing of the protrusion 13. At the same time, it avoids the protrusion 13 being too high and excessively affecting the thickness of the silicon substrate 1 in the first region 111 and the second region 112, ensuring good structural strength of the battery and reducing the risk of cell cracking or bending.

[0112] For example, the height H0 of protrusion 13 can be any value among 2 micrometers, 2.2 micrometers, 2.5 micrometers, 2.8 micrometers, 3 micrometers, 3.5 micrometers, 4 micrometers, 4.5 micrometers, 5 micrometers, 5.6 micrometers, 6 micrometers, 6.5 micrometers, 7 micrometers, 7.5 micrometers, 8 micrometers, 8.6 micrometers, 9 micrometers, 9.5 micrometers, 10 micrometers, 10.5 micrometers, 11 micrometers, 11.5 micrometers, 12 micrometers, 12.5 micrometers, 13 micrometers, 13.5 micrometers, 14 micrometers, 14.5 micrometers, and 15 micrometers.

[0113] Please refer to the reference. Figure 7 As an embodiment of the present invention, the width W0 of the protrusion 13 along the first direction X is 20~350 micrometers.

[0114] In this embodiment, the width W0 of the protrusion 13 along the first direction X is the width of a single protrusion 13 along the first direction X. Controlling the width W0 of the protrusion 13 along the first direction X to be 20-350 micrometers allows for lower precision requirements in laser etching within this width range, making it easier to achieve through modifications to existing process equipment. Simultaneously, the protrusion 13 achieves good insulation. If the width of the protrusion 13 is too small, it will be difficult to form the trench 40; if the width of the protrusion 13 is too large, it will result in excessive sacrifice of laser productivity, and the area ratio of the first region 111 and the second region 112 will decrease, reducing the separation capability of photogenerated carriers. Therefore, setting the width of the protrusion 13 along the first direction X to 20-350 micrometers is beneficial for the processing of the protrusion 13 while maintaining good battery efficiency.

[0115] For example, the width W0 of the protrusion 13 along the first direction X can be any value among 20 micrometers, 22 micrometers, 25 micrometers, 30 micrometers, 32 micrometers, 35 micrometers, 40 micrometers, 45 micrometers, 50 micrometers, 60 micrometers, 70 micrometers, 80 micrometers, 90 micrometers, 100 micrometers, 110 micrometers, 120 micrometers, 130 micrometers, 140 micrometers, 160 micrometers, 185 micrometers, 190 micrometers, 200 micrometers, 210 micrometers, 230 micrometers, 240 micrometers, 250 micrometers, 270 micrometers, 280 micrometers, 300 micrometers, 320 micrometers, 340 micrometers, and 350 micrometers.

[0116] As an embodiment of the present invention, the difference between the width W0 of the protrusion 13 along the first direction X and the width W4 of the groove 40 along the first direction X is greater than 20 micrometers.

[0117] In this embodiment, the width W0 of the protrusion 13 along the first direction X is the width of a single protrusion 13 along the first direction X, and the width W4 of the groove 40 along the first direction X is the width of a single groove 40 along the first direction X. The width W0 of the protrusion 13 along the first direction X is greater than the width W4 of the groove 40 along the first direction X, and the difference between the two is greater than 20 micrometers. This avoids the difference between the width of the protrusion 13 and the width of the groove 40 being too small, which facilitates the processing and formation of the groove 40 and ensures a good isolation effect of the protrusion 13.

[0118] As one embodiment of the present invention, it also includes: The first dielectric layer 8 is disposed in the first region 111, located between the silicon substrate 1 and the first doped polysilicon layer 2; and The second dielectric layer 9, located in the second region 112, is situated between the silicon substrate 1 and the second doped polysilicon layer 3.

[0119] In this embodiment, the first dielectric layer 8 is disposed between the first doped polysilicon layer 2 and the silicon substrate 1, and the second dielectric layer 9 is disposed between the second doped polysilicon layer 3 and the silicon substrate 1. The first dielectric layer 8 and the second dielectric layer 9 passivate the surface of the silicon substrate 1 and allow carriers to pass through efficiently. The materials of the first dielectric layer 8 and the second dielectric layer 9 can be the same or different.

[0120] As an embodiment of the present invention, the first dielectric layer 8 and the second dielectric layer 9 respectively include one or a combination of at least two of the following: silicon oxide layer, aluminum oxide layer, silicon carbide layer, silicon nitride layer, silicon oxynitride layer, and intrinsic amorphous silicon layer.

[0121] In this embodiment, the first dielectric layer 8 and the second dielectric layer 9 are each one of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, and an intrinsic amorphous silicon layer, or they can be a stacked structure of at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, and intrinsic amorphous silicon layer. Preferably, the first dielectric layer 8 and the second dielectric layer 9 are both silicon oxide layers.

[0122] As one embodiment of the present invention, it also includes: A third dielectric layer 10 is disposed between the surface of the isolation layer 4 and the protrusion 13, and a trench 40 penetrates the third dielectric layer 10 along the thickness direction Z of the silicon substrate 1.

[0123] In this embodiment, the isolation layer 4 is disposed on the protrusion 13, and a third dielectric layer 10 is disposed between the isolation layer 4 and the surface of the protrusion 13. The third dielectric layer 10 can passivate the surface of the protrusion 13, which can further improve the battery efficiency.

[0124] As an embodiment of the present invention, the thickness of the third dielectric layer 10 is greater than the thickness of at least one of the first dielectric layer 8 and the second dielectric layer 9.

[0125] In this embodiment, the thickness of the third dielectric layer 10 is greater than the thickness of at least one of the first dielectric layer 8 and the second dielectric layer 9, which is beneficial to improving the passivation effect of the third dielectric layer 10. The third dielectric layer 10 can be one or a combination of at least two of the following: a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a silicon carbide layer. Of course, the thicknesses of the third dielectric layer 10, the first dielectric layer 8, and the second dielectric layer 9 can also be the same.

[0126] As an embodiment of the present invention, the isolation layer 4 is doped with at least one of oxygen, nitrogen and carbon elements; The oxygen concentration in isolation layer 4 is 1×10⁻⁶. 16 ~2×10 22 atoms / cm 3 And / or, the nitrogen concentration in isolation layer 4 is 1×10 16 ~2×10 22 atoms / cm 3 And / or, the carbon concentration in isolation layer 4 is 1×10 16 ~2×10 22 atoms / cm 3 .

[0127] In this embodiment, at least one of oxygen, nitrogen, and carbon is doped into the isolation layer 4. Specifically, one of oxygen, nitrogen, and carbon can be doped into the isolation layer 4, or at least two of oxygen, nitrogen, and carbon can be doped simultaneously; moreover, the concentration of oxygen in the isolation layer 4 is controlled to be 1×10⁻⁶. 16 ~2×10 22 atoms / cm 3 The nitrogen concentration in isolation layer 4 is 1×10⁻⁶. 16 ~2×10 22 atoms / cm 3 The carbon concentration in isolation layer 4 is 1×10⁻⁶. 16 ~2×10 22 atoms / cm 3 This can increase the resistivity of the isolation layer 4, thereby further enhancing the electrical isolation effect of the isolation layer 4.

[0128] Please refer to the reference. Figure 1 and Figure 3 As an embodiment of the present invention, the isolation layer 4 further includes: A first extension 41 extends to the first region 111, the first extension 41 covers a portion of the first region 111, and the first extension 41 is connected to the first doped polysilicon layer 2 along the first direction X. The second extension 42 extends to the second region 112, and the second extension 42 covers a portion of the second region 112. The second extension 42 is connected to the second doped polysilicon layer 3 along the first direction X.

[0129] In this embodiment, the isolation layer 4 is disposed on the protrusion 13, and the isolation layer 4 forms a first extension 41 and a second extension 42. The first extension 41 extends to the first region 111, and the second extension 42 extends to the second region 112. This can further increase the unfolded length of the isolation layer 4, increase the distance between the first doped polysilicon layer 2 and the second doped polysilicon layer 3 along the surface of the silicon substrate 1, thereby increasing the creepage distance between the first doped polysilicon layer 2 and the second doped polysilicon layer 3, and further improving the electrical isolation effect between the first doped polysilicon layer 2 and the second doped polysilicon layer 3.

[0130] Please refer to Figure 11 As another embodiment of the present invention, along the thickness direction Z of the silicon substrate 1, the protrusion 13 includes a first end far from the front surface 12 and a second end close to the front surface 12, wherein the width W1 of the first end along the first direction X is greater than the width W2 of the second end along the first direction X.

[0131] In this embodiment, under the premise that the protrusion 13 achieves electrical isolation between the first doped polysilicon layer 2 and the second doped polysilicon layer 3, since the width W1 of the first end of the protrusion 13 along the first direction X is greater than the width W2 of the second end of the protrusion 13 along the first direction X, the second end of the protrusion 13 has a "brim structure", which is conducive to the protrusion 13 achieving the light trapping effect. The sunlight incident on the front side 12 is emitted from the back side 11 to the side of the protrusion 13. The sunlight emitted from the back side 11 can be better reflected back into the silicon substrate 1 by the side of the protrusion 13, thereby increasing the secondary absorption of sunlight and improving the utilization rate of sunlight. Moreover, since the width W1 of the first end of the protrusion 13 along the first direction X is greater than the width W2 of the second end of the protrusion 13 along the first direction X, the side of the isolation layer 4 is inclined, which is conducive to increasing the length design of the isolation layer 4 on the protrusion 13, and can further improve the electrical isolation effect of the isolation layer 4.

[0132] As an embodiment of the present invention, at least one of the top surface 130, the first side surface 131, and the second side surface 132 is provided with a textured structure (not shown).

[0133] In this embodiment, the texture structure can be a plurality of strip-shaped convex structures or a porous structure. At least one of the top surface 130, the first side surface 131, and the second side surface 132 is provided with a texture structure. The texture structure can further enhance the light-trapping effect of the protrusion 13 and further improve the absorption rate of sunlight on the back surface 11, thereby improving battery efficiency.

[0134] As one embodiment of the present invention, it also includes: Passivation layer 15 covers at least the first doped polysilicon layer 2, the second doped polysilicon layer 3, and the isolation layer 4.

[0135] In this embodiment, the passivation layer 15 can specifically be one or a stack of at least two of the following: an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The passivation layer 15 covers the second doped polysilicon layer 3, the first doped polysilicon layer 2, and the isolation layer 4. The passivation layer 15 also covers the bottom surface and inner wall surface of the trench 40. By providing the passivation layer 15, the passivation effect of the back surface 11 can be improved. The first metal electrode 5 passes through the passivation layer 15 and is electrically connected to the first doped polysilicon layer 2, and the second metal electrode 6 passes through the passivation layer 15 and is electrically connected to the second doped polysilicon layer 3.

[0136] In this embodiment of the invention, the first metal electrode 5 and the second metal electrode 6 have opposite polarities, and the first metal electrode 5 and the second metal electrode 6 are alternately arranged along a first direction X. Both the first metal electrode 5 and the second metal electrode 6 can be silver electrodes or aluminum electrodes. The first metal electrode 5 is in direct contact with the first doped polysilicon layer 2 to form an electrical connection, and the second metal electrode 6 is in direct contact with the second doped polysilicon layer 3 to form an electrical connection. Alternatively, the first metal electrode 5 and the first doped polysilicon layer 2 can also be indirectly contacted to form an electrical connection, and the second metal electrode 6 and the second doped polysilicon layer 3 can also be indirectly contacted to form an electrical connection.

[0137] Please refer to the reference. Figure 6 As an embodiment of the present invention, the height D1 of the first metal electrode 5 and the height D2 of the second metal electrode 6 are both greater than the height H0 of the protrusion 13.

[0138] In this embodiment, the height D1 of the first metal electrode 5 is the vertical distance from the side of the first metal electrode 5 facing away from the silicon substrate 1 to the side of the first metal electrode 5 close to the silicon substrate 1; the height D2 of the second metal electrode 6 is the vertical distance from the side of the second metal electrode 6 facing away from the silicon substrate 1 to the side of the second metal electrode 6 close to the silicon substrate 1. The height H0 of the protrusion 13 has been described above and will not be repeated here. Controlling the heights D1 of the first metal electrode 5 and D2 of the second metal electrode 6 to be greater than the height H0 of the protrusion 13 facilitates the first metal electrode 5 and the second metal electrode 6 to protrude from the protrusion 13 on the back surface 11, which is convenient for welding the first metal electrode 5 and the second metal electrode 6 to the solder ribbon.

[0139] This invention also provides a battery assembly, which includes the back contact battery 100 described in the above embodiments. It should be noted that this battery assembly has the same or similar beneficial effects as the back contact battery 100, and the related aspects between the two can be referred to each other; to avoid repetition, they will not be repeated here.

[0140] In this embodiment, multiple back-contact batteries 100 in the battery assembly are connected in series by solder strips to form a battery string, thereby achieving series current collection and output.

[0141] It is understood that in such embodiments, the battery assembly may also include a metal frame, a backsheet, photovoltaic glass, and an encapsulating film. The encapsulating film may be filled between the front and back sides of the back contact battery 100, the photovoltaic glass, adjacent battery cells, etc. As a filler, it may be a transparent colloid with good light transmittance and aging resistance. For example, the encapsulating film may be an EVA film or a POE film, and the specific choice can be made according to the actual situation, without limitation.

[0142] Photovoltaic glass can be applied to the encapsulating film on the front side of the back contact cell 100. The photovoltaic glass can be ultra-clear glass, which has high light transmittance, high transparency, and superior physical, mechanical, and optical properties. For example, ultra-clear glass can achieve a light transmittance of over 92%. It can protect the back contact cell 100 while minimizing impact on its efficiency. Simultaneously, the encapsulating film bonds the photovoltaic glass and the back contact cell 100 together, providing sealing, insulation, and waterproofing / moisture protection for the back contact cell 100.

[0143] The backsheet can be attached to the adhesive film on the back side of the back contact cell 100. The backsheet provides protection and support for the back contact cell 100, and offers reliable insulation, water resistance, and aging resistance. Multiple options are available for the backsheet, typically tempered glass, acrylic glass, or aluminum alloy TPT composite adhesive film, etc., and the specific choice is determined based on the specific circumstances and is not limited here. The backsheet, back contact cell 100, adhesive film, and photovoltaic glass can be mounted on a metal frame. The metal frame serves as the main external support structure for the entire battery module, providing stable support and installation. For example, the battery module can be installed at the desired location using the metal frame.

[0144] This invention also provides a photovoltaic system, which includes the battery module described in the above embodiments. It should be noted that this photovoltaic system has the same or similar beneficial effects as the back-contact battery 100 described above, and the related aspects between the two can be referred to each other; to avoid repetition, they will not be repeated here.

[0145] In this embodiment, the photovoltaic system can be applied in photovoltaic power plants, such as ground-mounted power plants, rooftop power plants, and floating power plants. It can also be applied to equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it is understood that the application scenarios of the photovoltaic system are not limited to these; that is, the photovoltaic system can be applied in all fields that require solar energy to generate electricity. Taking a photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a combiner box, and an inverter. The photovoltaic array may be an array combination of multiple battery modules; for example, multiple battery modules can form multiple photovoltaic arrays. The photovoltaic array is connected to the combiner box, which can collect the current generated by the photovoltaic array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to achieve solar power supply.

[0146] In the description of this specification, references to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0147] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A back-contact battery, characterized in that, include: A silicon substrate, the silicon substrate including a back side and a front side disposed opposite to each other, the back side having a first region and a second region disposed alternately at intervals along a first direction, the first region and the second region respectively extending along a second direction, the second direction intersecting the first direction; The silicon substrate has at least one protrusion formed between adjacent first and second regions; A first doped polysilicon layer is disposed in the first region; A second doped polysilicon layer is disposed in the second region; An isolation layer is disposed on the back side and located between the first doped polysilicon layer and the second doped polysilicon layer. The doping concentration of the isolation layer is less than the doping concentrations of the first doped polysilicon layer and the second doped polysilicon layer, and the doping concentration of the isolation layer is less than or equal to 1E18 / cm. 3 ; The first metal electrode is electrically connected to the first doped polysilicon layer. and The second metal electrode is electrically connected to the second doped polycrystalline silicon layer.

2. The back contact battery according to claim 1, characterized in that, The isolation layer is at least partially disposed on the protrusion.

3. The back contact battery according to claim 2, characterized in that, The isolation layer has trenches that partially or completely penetrate the isolation layer along the thickness direction of the silicon substrate.

4. The back contact battery according to claim 3, characterized in that, The trench extends through the isolation layer along the thickness direction of the silicon substrate, and the ratio of the depth of the trench to the thickness of the isolation layer is 0.5 to 0.

9.

5. The back contact battery according to claim 3, characterized in that, The trench completely penetrates the isolation layer along the thickness direction of the silicon substrate. With the center plane along the thickness direction of the silicon substrate as the reference plane, the distance from the bottom surface of the trench to the center plane is greater than the distance from the plane containing the first region to the center plane and the distance from the plane containing the second region to the center plane.

6. The back contact battery according to any one of claims 3 to 5, characterized in that, At least a portion of the trench penetrates the isolation layer along the second direction.

7. The back contact battery according to claim 3, characterized in that, The trench completely penetrates the isolation layer along the thickness direction of the silicon substrate, and the protrusion has a textured surface corresponding to the trench.

8. The back contact battery according to claim 7, characterized in that, The textured structure includes at least one of the following: upright pyramid, inverted pyramid, nanopillar, and nanopore.

9. The back contact battery according to claim 3, characterized in that, The width of the groove along the first direction is 10 to 200 micrometers.

10. The back contact battery according to claim 1, characterized in that, The height of the protrusion is 2 to 15 micrometers.

11. The back contact battery according to claim 1, characterized in that, The width of the protrusion along the first direction is 20 to 350 micrometers.

12. The back contact battery according to claim 3, characterized in that, The difference between the width of the protrusion along the first direction and the width of the groove along the first direction is greater than 20 micrometers.

13. The back contact battery according to claim 3, characterized in that, The trench is filled with a polymer insulating material.

14. The back contact battery according to claim 1, characterized in that, The height of the first metal electrode and the height of the second metal electrode are both greater than the height of the protrusion.

15. The back contact battery according to claim 3, characterized in that, Also includes: A first dielectric layer is disposed in the first region and is located between the silicon substrate and the first doped polysilicon layer; and The second dielectric layer is disposed in the second region and is located between the silicon substrate and the second doped polysilicon layer.

16. The back contact battery according to claim 15, characterized in that, The first dielectric layer and the second dielectric layer respectively include one or a combination of at least two of the following: silicon oxide layer, aluminum oxide layer, silicon carbide layer, silicon nitride layer, silicon oxynitride layer, and intrinsic amorphous silicon layer.

17. The back contact battery according to claim 15, characterized in that, Also includes: A third dielectric layer is disposed between the isolation layer and the raised surface, and the trench penetrates the third dielectric layer along the thickness direction of the silicon substrate.

18. The back contact battery according to claim 17, characterized in that, The thickness of the third dielectric layer is greater than the thickness of at least one of the first dielectric layer and the second dielectric layer.

19. The back contact battery according to claim 1, characterized in that, The isolation layer is doped with at least one of oxygen, nitrogen and carbon elements; The oxygen concentration in the isolation layer is 1×10⁻⁶. 16 ~2×10 22 atoms / cm 3 And / or, the nitrogen concentration in the isolation layer is 1×10⁻⁶. 16 ~2×10 22 atoms / cm 3 And / or, the concentration of carbon in the isolation layer is 1×10⁻⁶. 16 ~2×10 22 atoms / cm 3 .

20. The back contact battery according to claim 1, characterized in that, The number of protrusions between adjacent first and second regions is 1 to 3.

21. The back contact battery according to claim 2, characterized in that, The isolation layer also includes: A first extension extending to the first region, the first extension covering a portion of the first region, the first extension being connected to the first doped polysilicon layer along the first direction; A second extension extending into the second region, the second extension covering a portion of the second region, the second extension being connected to the second doped polysilicon layer along the first direction.

22. The back contact battery according to claim 2, characterized in that, The protrusion includes a top surface disposed away from the front side along the thickness direction of the silicon substrate, a first side surface and a second side surface disposed opposite to each other along the first direction, the first side surface and the second side surface being respectively connected to the top surface, and the isolation layer covering at least one of the top surface, the first side surface and the second side surface.

23. The back contact battery according to claim 1, characterized in that, Along the thickness direction of the silicon substrate, the protrusion includes a first end portion away from the front surface and a second end portion near the front surface, wherein the width of the first end portion along the first direction is greater than the width of the second end portion along the first direction.

24. The back contact battery according to claim 1, characterized in that, Also includes: A passivation layer, wherein the passivation layer at least covers the first doped polysilicon layer, the second doped polysilicon layer, and the isolation layer.

25. The back contact battery according to claim 1, characterized in that, The isolation layer is an intrinsic semiconductor layer or a doped semiconductor layer.

26. The back contact battery according to claim 25, characterized in that, The intrinsic semiconductor layer is at least one of intrinsic polycrystalline silicon layer, intrinsic amorphous silicon layer, intrinsic microcrystalline silicon layer, and intrinsic nanocrystalline silicon layer.

27. The back contact battery according to claim 26, characterized in that, The doped semiconductor layer is at least one of the following: a doped polycrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer.

28. The back contact battery according to claim 1, characterized in that, The doping concentration of the isolation layer is less than 2E17 / cm. 3 .

29. The back contact battery according to claim 1, characterized in that, The doping concentration of the isolation layer is less than 1E17 / cm. 3 .

30. The back contact battery according to claim 1, characterized in that, The doping concentrations of both the second doped polysilicon layer and the first doped polysilicon layer are greater than 1E19 / cm. 3 .

31. A battery assembly, characterized in that, Includes the back contact battery as described in any one of claims 1 to 30.

32. A photovoltaic system, characterized in that, Includes the battery assembly as described in claim 31.

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