Solar cell, manufacturing method thereof and photovoltaic module

Abstract

The embodiment of the invention relates to the photovoltaic field, and provides a solar cell piece and a manufacturing method thereof, and a photovoltaic module, the solar cell piece comprises a substrate, the substrate is provided with metal regions arranged at intervals, and the metal regions are provided with tunneling layers and doped conductive layers; the passivation layer is located on the surface of the doped conductive layer; the orthographic projection of the first grid line on the surface of the substrate is located in the metal area, the first grid line penetrates through the passivation layer and is in contact connection with the doped conductive layer, the first grid line is made of one or more of silver, nickel, aluminum, manganese or copper, and the efficiency of the solar cell can be improved.

Description

Cross-reference to related applications

[0001] This application is a divisional application of Chinese invention patent application filed on August 23, 2024, with application number 2024111701742 and invention title "Solar Cell and Method of Manufacturing Thereof, Photovoltaic Module". Technical Field

[0002] This disclosure relates to the photovoltaic field, and in particular to a solar cell and its manufacturing method, and a photovoltaic module. Background Technology

[0003] Fossil fuels cause air pollution and have limited reserves, while solar energy has advantages such as being clean, pollution-free, and abundant. Therefore, solar energy is gradually becoming the core clean energy source to replace fossil fuels. Due to the excellent photoelectric conversion efficiency of solar cells, solar cells have become the focus of development for clean energy utilization.

[0004] For solar cells, the higher the photoelectric conversion efficiency, the better. Therefore, it is necessary to propose a solar cell with higher photoelectric conversion efficiency. Summary of the Invention

[0005] This disclosure provides a solar cell and its manufacturing method, as well as a photovoltaic module, which can at least improve the photoelectric conversion efficiency of the solar cell.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a solar cell, comprising: a substrate having spaced-apart metal regions, a tunneling layer and a doped conductive layer on the metal regions; a passivation layer located on the surface of the doped conductive layer; and a first grid line whose orthogonal projection on the surface of the substrate is located in the metal regions, and the first grid line penetrates the passivation layer and is in contact with the doped conductive layer, wherein the material of the first grid line is one or more of silver, nickel, aluminum, manganese or copper.

[0007] In some embodiments, the system further includes: a second gate line, the second gate line extending in a direction different from that of the first gate line, and the second gate line being electrically connected to a plurality of the first gate lines; a gate-like line, the gate-like line being located in a metal region, the gate-like line extending in the same direction as that of the second gate line, and the gate-like line and the second gate line being arranged at intervals, the gate-like line being electrically connected to a plurality of the first gate lines, the gate-like line being located between adjacent second gate lines, and the material of the gate-like line being different from that of the second gate lines.

[0008] In some embodiments, the tunneling layer is located only in the metal region, and the doped conductive layer is located only on the surface of the tunneling layer.

[0009] In some embodiments, the doped conductive layer includes a first doped portion corresponding to the metal region and a second doped portion corresponding to a region between adjacent metal regions, and further includes a groove located between adjacent metal regions, wherein the groove at least penetrates a portion of the second doped portion.

[0010] In some embodiments, a non-metallic region is further included, the non-metallic region being located between adjacent metallic regions, and the doped conductive layer is also located in the non-metallic region, wherein the thickness of the doped conductive layer located in the metallic region is at least greater than the thickness of the doped conductive layer partially located in the non-metallic region.

[0011] In some embodiments, the thickness of the doped conductive layer located at any point in the metal region is greater than or equal to the thickness of the doped conductive layer located at any point in the non-metal region.

[0012] In some embodiments, the material of the first gate line is a material in which a first metal encapsulates a second metal, wherein the conductivity of the first metal is greater than or equal to the conductivity of the second metal.

[0013] In some embodiments, the system further includes: a gate-like line located in the metal region, the gate-like line extending in a different direction than the first gate line.

[0014] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a solar cell, comprising: providing a substrate having spaced-apart metal regions; forming a tunneling layer and a doped conductive layer, the tunneling layer and the doped conductive layer being located in the metal regions; forming a passivation layer, the passivation layer being located on the surface of the doped conductive layer; forming a first grid line, the orthographic projection of the first grid line on the surface of the substrate being located in the metal regions, and the first grid line penetrating the passivation layer and contacting the doped conductive layer, wherein the material of the first grid line is one or more of silver, nickel, aluminum, manganese or copper.

[0015] In some embodiments, the step of forming a doped conductive layer includes: forming an initial doped conductive layer located on the surface of the tunneling layer away from the substrate; performing a laser process, wherein the laser process irradiates at least a portion of the initial doped conductive layer located between adjacent metal regions; and performing an etching process, wherein the etching process removes at least a portion of the initial doped conductive layer irradiated by the laser process, and the remaining initial doped conductive layer serves as the doped conductive layer.

[0016] In some embodiments, the ratio of the area of ​​the initial doped conductive layer irradiated by the laser process to the area of ​​the initial doped conductive layer is 40% to 90%.

[0017] In some embodiments, the etching process further etches the initial doped conductive layer located in the metal region to improve the surface roughness of the initial doped conductive layer located in the metal region.

[0018] In some embodiments, before forming the first gate line, the method further includes: forming an initial second gate line in a metal region, the extension direction of the initial second gate line being different from the extension direction of the first gate line; and performing a first sintering process, the first sintering process converting the initial second gate line into a second gate line.

[0019] In some embodiments, the step of forming the first gate line includes: forming an initial first gate line, wherein the orthographic projection of the initial first gate line onto the substrate surface is located in a metal region; and performing a second sintering process, wherein the second sintering process converts the initial first gate line into a first gate line, and the temperature of the second sintering process is lower than the temperature of the first sintering process.

[0020] In some embodiments, the second sintering process includes: a curing step for curing the initial first gate line; and a laser-assisted sintering step for converting the cured initial first gate line into the first gate line.

[0021] In some embodiments, the laser-assisted sintering step further applies a reverse bias voltage, wherein the voltage value of the reverse bias voltage applied to the first gate line is 1.1 to 1.3 times the voltage value of the reverse bias voltage applied to the second gate line.

[0022] In some embodiments, the larger the ratio of the reverse bias voltage applied to the first gate line to the reverse bias voltage applied to the second gate line, the smaller the ratio of the laser power applied to the first gate line to the laser power applied to the second gate line.

[0023] According to some embodiments of this disclosure, another aspect of this disclosure also provides a photovoltaic module, including: a battery string, which is formed by connecting multiple solar cells as described above, or by connecting multiple solar cells formed by the manufacturing method described above; an encapsulating film for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulating film away from the battery string.

[0024] The technical solution provided in this disclosure has at least the following advantages: the tunneling layer and the doped conductive layer together constitute the passivation contact structure of the solar cell. The passivation contact structure can form band bending on the back side of the substrate, realizing selective transport of charge carriers. At the same time, by setting the material of the first grid line to one or more of silver, nickel, aluminum, manganese or copper, the impact of the process of forming the first grid line on the doped conductive layer and the substrate is reduced, further improving the photoelectric conversion efficiency of the solar cell. Attached Figure Description

[0025] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A cross-sectional view of a solar cell provided in an embodiment of this disclosure; Figure 2 Another cross-sectional view of a solar cell provided in an embodiment of this disclosure; Figure 3 A top view of a solar cell provided in an embodiment of this disclosure; Figure 4 Another top view of a solar cell provided according to an embodiment of this disclosure; Figure 5 Another cross-sectional view of a solar cell provided in an embodiment of this disclosure; Figure 6 Another cross-sectional view of a solar cell provided in an embodiment of this disclosure; Figure 7 Another top view of a solar cell provided in an embodiment of this disclosure; Figure 8 Another top view of a solar cell provided in an embodiment of this disclosure; Figures 9 to 18 This is a schematic diagram of the structure corresponding to each step of a method for manufacturing a solar cell according to an embodiment of the present disclosure; Figure 19 A perspective view of a photovoltaic module provided in an embodiment of this disclosure; Figure 20 This is a cross-sectional view of a photovoltaic module provided in an embodiment of the present disclosure. Detailed Implementation

[0027] As is known from the background technology, in current solar cells, the doped conductive layer on the back is relatively thick. Excessive thickness of the doped conductive layer can cause parasitic absorption problems, affecting the current density and limiting the photoelectric conversion efficiency of the solar cell.

[0028] This disclosure provides a solar cell with a passivated contact structure formed by a tunneling layer and a doped conductive layer. The passivated contact structure can form band bending on the back side of the substrate, enabling selective carrier transport. Furthermore, by setting the thickness of the doped conductive layer in the metal region to be at least greater than the thickness of the doped conductive layer in a portion of the non-metal region, in other words, by reducing the thickness of the doped conductive layer in at least a portion of the non-metal region, the parasitic absorption problem of the doped conductive layer is improved. It is understood that thinning the thickness of the doped conductive layer in the non-metal region will affect the doped conductive layer in the metal region. In particular, when the material of the first grid line is a burn-through material, the burn-through material will pass through the doped conductive layer into the substrate during the formation of the first grid line, resulting in reduced efficiency. Therefore, this disclosure further improves the photoelectric conversion efficiency of the solar cell by setting the first grid line to a non-burn-through material, thereby cooperating with the thinning of the doped conductive layer.

[0029] In the description of the embodiments of this disclosure, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary or secondary relationship of the indicated technical features. In the description of the embodiments of this disclosure, "a plurality of" means two or more, unless otherwise explicitly defined.

[0030] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0031] In the description of the embodiments of this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0032] In the description of embodiments of this disclosure, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0033] In the description of the embodiments of this disclosure, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this disclosure.

[0034] In the description of the embodiments of this disclosure, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0035] In the accompanying drawings corresponding to the embodiments of this disclosure, the thickness and area of ​​the layers are enlarged for better understanding and ease of description. When describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be a third component between the two components. Conversely, when describing a component on the surface of another component, or when another component is formed or disposed on the surface of a component, it indicates that there is no third component between the two components. Furthermore, when describing a component as being "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0036] In the description of embodiments of this disclosure, when a component "includes" another component, other components are not excluded unless otherwise stated, and may be further included. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "on / located" on another component, it can be "directly" on the other component (i.e., located on the surface of the other component with no other components between them), or another component may be present therein. Additionally, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located therein.

[0037] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "component" is also intended to include the plural form unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0038] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0039] refer to Figure 1 and Figure 2 , Figure 1 This is a cross-sectional view of a solar cell provided in an embodiment of the present disclosure. Figure 2 This is another cross-sectional view of a solar cell provided in an embodiment of the present disclosure. It should be noted that, for Figure 1 and Figure 2 In other words, Figure 1 and Figure 2 The structure of the front of the solar cell is not shown in the diagram. Figure 1 and Figure 2 These are all schematic diagrams of partial structures.

[0040] In some embodiments, a solar cell may include a substrate 100, which includes a metal region 110 and a non-metal region 120, and has a front side 130 and a back side 140 opposite to each other.

[0041] The solar cell may also include a tunneling layer 101 located on the back side 140.

[0042] The solar cell may further include: a doped conductive layer 102 located on the surface of the tunneling layer 101 away from the substrate 100, wherein the thickness of the doped conductive layer 102 located in the metal region 110 is at least greater than the thickness of the doped conductive layer 102 located in the non-metal region 120.

[0043] The solar cell may also include a passivation layer 103, which is located on the surface of the doped conductive layer 102.

[0044] The solar cell may further include: a first grid line 104, the first grid line 104 having its orthographic projection on the back side of the substrate 100 located in the metal region 110, and the first grid line 104 penetrating the passivation layer 103 and contacting the doped conductive layer 102, the first grid line 104 being made of a non-burn-through material.

[0045] This disclosure provides a solar cell in which a tunneling layer 101 and a doped conductive layer 102 together constitute a passivation contact structure. The passivation contact structure can form band bending on the back side of the substrate 100, enabling selective carrier transport. Furthermore, by ensuring that the thickness of the doped conductive layer 102 located in the metal region 110 is at least greater than the thickness of the doped conductive layer 102 in a portion of the non-metal region 120—in other words, by reducing the thickness of the doped conductive layer 102 at least a portion of the non-metal region 120—the parasitic absorption of the doped conductive layer 102 is improved. The problem is understandable: when the thickness of the doped conductive layer 102 at the non-metallic region 120 is reduced, it will affect the doped conductive layer 102 in the metallic region 110. In particular, when the material of the first gate line 104 is a burn-through material, the burn-through material will pass through the doped conductive layer 102 and enter the substrate during the formation of the first gate line 104, resulting in a decrease in efficiency. Therefore, in this embodiment, the first gate line 104 is set to a non-burn-through material, thereby cooperating with the thinning of the doped conductive layer 102 to further improve the photoelectric conversion efficiency of the solar cell.

[0046] Regarding the metal region 110 and non-metal region 120 of the substrate 100, the metal region 110 is the part of the substrate 100 directly opposite the grid lines. For example, the grid lines include the main grid and the sub-grid. The metal region 110 is the part of the substrate 100 directly opposite the main grid and the sub-grid. In some embodiments, the solar cell is a gridless cell. The metal region 110 is the part of the substrate 100 directly opposite the sub-grid. The non-metal region 120 is the part excluding the metal region 110.

[0047] Regarding the front side 130 and back side 140 of the substrate 100, the front side 130 can serve as a light-receiving surface for receiving incident light, while the back side 140 serves as a backlighting surface. In some embodiments, the solar cell is a bifacial cell, in which case both the front and back sides of the substrate can serve as light-receiving surfaces and can be used to receive incident light. It is understood that the backlighting surface referred to in the embodiments of this disclosure can also receive incident light, but the degree of reception of incident light is weaker than that of the light-receiving surface, and therefore it is defined as a backlighting surface.

[0048] In some embodiments, the material of the tunneling layer 101 may be one or more combinations of silicon oxide, silicon oxynitride, aluminum oxide, and silicon oxide.

[0049] For the doped conductive layer 102, the thickness of the doped conductive layer 102 located in the metal region 110 is at least greater than the thickness of the doped conductive layer 102 in a portion of the non-metal region 120. In other words, the average thickness of the doped conductive layer 102 located in the non-metal region 120 is less than the thickness of the doped conductive layer 102 located in the metal region.

[0050] In some embodiments, the thickness of the doped conductive layer 102 located at any location in the metal region 110 is greater than or equal to the thickness of the doped conductive layer 102 located at any location in the non-metal region 120. In other words, the bottom surface of the doped conductive layer 102 located in the non-metal region 120 away from the substrate 100 is not lower than the bottom surface of the doped conductive layer 102 located in the metal region 110 away from the substrate 100. This avoids the sidewall of the first grid line 104 from contacting the doped conductive layer 102 in the non-metal region 110, thereby preventing metal contact recombination at the contact surface between the first grid line 104 and the doped conductive layer 102 in the non-metal region 110, thereby improving the performance of the solar cell.

[0051] refer to Figure 2 In some embodiments, the doped conductive layer 102 includes a first doped portion 132 corresponding to the metal region 110 and a second doped portion 142 corresponding to the non-metal region 120. The solar cell further includes a groove 112 located in the non-metal region 120, and the groove 112 at least penetrates a portion of the second doped portion 142. In other words, the groove 112 is formed at the portion of the doped conductive layer 102 corresponding to the non-metal region 120. By forming the groove 112, the parasitic absorption problem of the doped conductive layer 102 can also be improved, thereby improving the performance of the solar cell.

[0052] In some embodiments, the groove may also extend through the tunneling layer.

[0053] In some embodiments, the thickness of the first doped portion 132 is greater than the thickness of the second doped portion 142. In other words, the thickness of the second doped portion 142 is reduced, thereby further reducing the parasitic absorption problem of the doped conductive layer 102.

[0054] In some embodiments, the thickness of the doped conductive layer 102 located in the metal region 110 being at least greater than the thickness of the doped conductive layer 102 in a portion of the non-metal region 120 can also mean: the metal region 110 has a doped conductive layer 102, while all the doped conductive layer 102 in the non-metal region 120 is etched away; it can also mean: the doped conductive layer 102 in the metal region 110 is thinned, while all the doped conductive layer 102 in the non-metal region 120 is etched away; or it can mean: the doped conductive layer 102 in the metal region 110 is not processed, while the non-metal region 120 is thinned. The doped conductive layer 102 in region 120 can also refer to: both the doped conductive layer 102 in metal region 110 and the doped conductive layer 102 in non-metal region 120 are thinned, but the thickness of the thinned non-metal region 120 is greater than the thickness of the thinned metal region 110; or it can refer to: the doped conductive layer 102 in metal region 110 is not processed, and the doped conductive layer 102 in non-metal region 120 has two morphologies, part of which is the groove 112 formed after complete etching, and part of which is the thinned doped conductive layer 102 in non-metal region 120.

[0055] It is understandable that, for the above solution, by thinning the thickness of at least part of the doped conductive layer 102 of the non-metallic region 120, the parasitic light absorption capacity of the non-metallic region 120 is reduced. For the metallic region 110, the doped conductive layer 102 and the tunneling layer 101 need to form a passivation contact structure to reduce the recombination of charge carriers in the metallic region 110 and to achieve selective transport of charge carriers. Therefore, for the metallic region 110, the doped conductive layer 102 can only be thinned and cannot be removed.

[0056] In some embodiments, when thinning the thickness of at least the doped conductive layer 102 in the non-metallic region 120, a wet etching process is typically performed. During the wet etching process, when thinning the doped conductive layer 102 in the non-metallic region 120, due to insufficient alkali-blocking ability of the mask on the surface of the metal region 110, etching holes are formed in the metal region 110. These etching holes will cause some paste to enter the substrate 100 through the etching holes during the subsequent formation of the first grid line due to the burn-through process, resulting in a decrease in the photoelectric conversion efficiency of the entire solar cell. Therefore, the first grid line in this embodiment uses a non-burn-through material to avoid the paste entering the substrate 100 during the burn-through process, thereby reducing the negative impact of thinning the doped conductive layer 102 and ensuring the reliability of the solar cell while improving the photoelectric conversion efficiency.

[0057] In some embodiments, the doped conductive layer 102 may be a polycrystalline silicon layer doped with N-type or P-type elements, wherein the doping type and doping concentration of the doped conductive layer 102 may be selected according to the actual situation.

[0058] In some embodiments, the non-burn-through material can be a metallic material, which can be a material in which a first metal encapsulates a second metal, wherein the electrical conductivity of the first metal is greater than or equal to the electrical conductivity of the second metal, the first metal can be silver, nickel or aluminum, and the second metal can be nickel, aluminum, manganese or copper, for example, silver-coated copper material.

[0059] In some embodiments, the tunneling layer 101 is located only in the metal region 110 of the back side 140, the doped conductive layer 102 is located only on the surface of the tunneling layer 101, and the passivation layer 103 also covers the surface of the non-metallic region 120 of the back side 140. In other words, removing all tunneling layers 101 and doped conductive layers corresponding to the non-metallic region 110 can, on the one hand, ensure that the doped conductive layer 102 is completely removed and minimize the parasitic absorption of the doped conductive layer 102, and on the other hand, remove the tunneling layer 101 damaged during the removal of the doped conductive layer 102, thereby further improving the reliability of the solar cell.

[0060] In some embodiments, the passivation layer 103 covers a portion of the surface of the non-metallic region 120 of the substrate 100. It is understood that in some embodiments, only a portion of the doped conductive layer 102 and a portion of the tunneling layer 101 are removed during the thinning of the doped conductive layer 102. Therefore, during the formation of the passivation layer 103, it will partially cover the surface of the non-metallic region 140 of the substrate 100.

[0061] In some embodiments, small particles of first metal powder may be added to the first gate line 104. The shape of the powder may be spherical or flake-shaped, thereby increasing the contact area between the first metal and the doped conductive layer 102 and improving the contact resistance between the first gate line 104 and the doped conductive layer 102.

[0062] The following example uses silver as the first metal. By setting silver as the first metal, silver-silicon alloy microcrystalline particles can be formed at the contact surface between the first gate line 104 and the doped conductive layer 102, thereby forming more contact sites. Moreover, the silver-silicon alloy microcrystalline particles can reduce the potential barrier between silver and silicon, thereby reducing the contact resistance and forming an ohmic contact. Furthermore, silver powder can be added to the first gate line 104 to improve the total amount of silver-silicon alloy formed and improve the contact resistance.

[0063] In some embodiments, the morphology of the silver-silicon alloy microcrystalline particles can be controlled to be spherical or dendritic. The bonding force and contact characteristics of the dendritic silver-silicon alloy microcrystalline particles are better than those of the spherical silver-silicon alloy microcrystalline particles. The spherical silver-silicon alloy microcrystalline particles have better metal recombination loss than those of the dendritic silver-silicon alloy microcrystalline particles, thereby further improving the performance of the solar cell.

[0064] refer to Figure 3 , Figure 3 This is a top view of a solar cell provided in an embodiment of the present disclosure. In order to more clearly illustrate the metal area and the non-metal area, the metal area is filled with dots, and the remaining unfilled parts of the substrate surface are the non-metal area.

[0065] In some embodiments, the solar cell may further include: a second grid line 105, the extension direction of the second grid line 105 being different from the extension direction of the first grid line 104, the second grid line 105 being electrically connected to multiple first grid lines 104, and the sum of the areas of all second grid lines 105 projected onto the back side of the substrate 100 being less than the sum of the areas of the first grid lines 104 projected onto the surface of the substrate 100. It is understood that for each second grid line 105, the metal region 110 corresponding to the second grid line 105 will necessarily have a doped conductive layer 102. The larger the sum of the areas of the second grid lines 105 projected onto the back side of the substrate, the more severe the parasitic absorption problem of the doped conductive layer 102 becomes. Therefore, setting the sum of the areas of all second grid lines 105 projected onto the back side of the substrate 100 to be less than the sum of the areas of the first grid lines 104 projected onto the surface of the substrate 100 can control the area of ​​the doped conductive layer 102, thereby controlling the parasitic absorption problem of the doped conductive layer 102.

[0066] On the other hand, for the second grid line 105, the second grid line usually uses burn-through paste, and the use of burn-through paste will increase the cost of the entire solar cell. By setting the area of ​​all the second grid lines 105 projected onto the back of the substrate 100 to be smaller than the area of ​​the first grid line 104 projected onto the surface of the substrate 100, the material of the burn-through paste can be controlled, thereby controlling the cost of the solar cell.

[0067] In some embodiments, the material of the second grid line 105 can also be a non-burn-through material. It is understood that by setting the material of the second grid line 105 to be a non-burn-through material, the paste can also be prevented from entering the substrate 100 during the burn-through process, thereby improving the reliability of the solar cell.

[0068] In some embodiments, a solder joint structure 106 may also be provided on the top surface of the second grid line 105. The material of the solder joint structure 106 may be set as a burn-through material. By setting the material of the solder joint structure 106 as a burn-through material, the reliability of the welding can be improved.

[0069] In some embodiments, the material of the second gate line 105 can also be a burn-through material. The conductivity of the burn-through material is greater than that of the non-burn-through material. Therefore, setting the material of the second gate line 105 to a burn-through material can improve the carrier transport rate.

[0070] refer to Figures 4 to 6 , Figure 4 This is another top view of a solar cell provided according to an embodiment of the present disclosure. Figure 5 A solar cell provided in one embodiment of this disclosure is along Figure 4 Cross-sectional view along the aa1 direction. Figure 6 A solar cell provided in one embodiment of this disclosure is along Figure 4The cross-section along the bb1 direction is shown. To clearly illustrate the metallic and non-metallic regions, the metallic region is filled with dots, while the remaining unfilled portion of the substrate surface represents the non-metallic region.

[0071] In some embodiments, the solar cell may further include: a grid-like line 107, located in the metal region 110, extending in the same direction as the second grid line 105, and spaced apart from the second grid line 105. The grid-like line 107 is in contact with multiple first grid lines 104, and is located between adjacent second grid lines 105. The material of the grid-like line 107 is different from that of the second grid line 105. By providing the grid-like line 107, the lateral transmission capacity can be balanced, thereby further improving the performance of the solar cell.

[0072] In some embodiments, the material of the gate-like line 107 may be polycrystalline silicon.

[0073] In some embodiments, the gate-like line 107 is made of polysilicon, while the second gate line 105 is made of a non-burn-through material, and a solder joint structure 106 is provided on the top surface of the second gate line 105, the solder joint structure 106 being made of a burn-through material; in some embodiments, the gate-like line 107 is made of polysilicon, while the second gate line 105 is made of a burn-through material, and a solder joint structure 106 is provided on the top surface of the second gate line 105, the solder joint structure 106 being made of a burn-through material.

[0074] In some embodiments, the gate-like line 107 may be formed based on a partially doped conductive layer 102. In other words, the gate-like line 107 may be a portion that is not etched from the partially doped conductive layer 102 and is retained, with this retained portion of the doped conductive layer 102 serving as the region corresponding to the metal region 110 and as the gate-like line 107. In other embodiments, the gate-like line 107 may also be additionally formed for contact connection with the first gate line, thereby balancing the lateral transmission capability.

[0075] refer to Figure 7 , Figure 7 This is another top view of a solar cell provided in an embodiment of the present disclosure, wherein, in order to more clearly illustrate the metal region and the non-metal region, the metal region is filled with dots, and the remaining unfilled portion of the substrate surface is the non-metal region.

[0076] In some embodiments, the solar cell is a gridless cell, and the solar cell may include a first grid line 104 and a grid-like line 107, wherein the extension direction of the grid-like line 107 is at an angle to the extension direction of the first grid line 104.

[0077] The solar cell also includes a solder joint structure 106, which is disposed on the top surface of the first grid line 104 and contacts and connects with the first grid line 104. The solder joint structure 106 serves as the contact structure between the subsequent solder strip and the first grid line 104. The material of the solder joint structure 106 can be a burn-through material.

[0078] refer to Figure 8 , Figure 8 This is another top view of a solar cell provided in an embodiment of the present disclosure, wherein, in order to more clearly illustrate the metal region and the non-metal region, the metal region is filled with dots, and the remaining unfilled portion of the substrate surface is the non-metal region.

[0079] In some embodiments, the solar cell is a gridless cell, and the solar cell includes only the first grid line 104.

[0080] The solar cell also includes a solder joint structure 106, which is disposed on the top surface of the first grid line 104 and contacts and connects with the first grid line 104. The solder joint structure 106 serves as the contact structure between the subsequent solder strip and the first grid line 104. The material of the solder joint structure 106 can be a burn-through material.

[0081] This disclosure provides a solar cell in which a tunneling layer 101 and a doped conductive layer 102 together constitute a passivation contact structure. The passivation contact structure can form band bending on the back side of the substrate 100, enabling selective carrier transport. Furthermore, by ensuring that the thickness of the doped conductive layer 102 located in the metal region 110 is at least greater than the thickness of the doped conductive layer 102 in a portion of the non-metal region 120—in other words, by reducing the thickness of the doped conductive layer 102 at least a portion of the non-metal region 120—the parasitic absorption of the doped conductive layer 102 is improved. The problem is understandable: when the thickness of the doped conductive layer 102 at the non-metallic region 120 is reduced, it will affect the doped conductive layer 102 in the metallic region 110. In particular, when the material of the first gate line 104 is a burn-through material, the burn-through material will pass through the doped conductive layer 102 and enter the substrate during the formation of the first gate line 104, resulting in a decrease in efficiency. Therefore, in this embodiment, the first gate line 104 is set to a non-burn-through material, thereby cooperating with the thinning of the doped conductive layer 102 to further improve the photoelectric conversion efficiency of the solar cell.

[0082] Another embodiment of this disclosure also provides a method for manufacturing a solar cell. This method can be used to form the aforementioned solar cell. The method for manufacturing a solar cell provided in another embodiment of this disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as those in the foregoing embodiments can be referred to the corresponding descriptions in the foregoing embodiments, and will not be repeated below.

[0083] refer to Figures 9 to 17 , Figures 9 to 17 This is a schematic diagram showing the structural steps corresponding to each step of a method for manufacturing a solar cell according to an embodiment of the present disclosure, wherein... Figure 9 To provide a base; Figure 10 exist Figure 9 A tunnel layer was formed on this basis; Figure 11 exist Figure 10 An initial doped conductive layer was formed on this basis; Figure 12 exist Figure 11 A doped conductive layer was formed on this basis; Figure 13 exist Figure 12 A passivation layer was formed on this basis. Figure 14 This is a top view of the back of a solar cell. Figure 13 The initial second grid line was formed based on this; Figure 15 This is a top view of the back of a solar cell. Figure 14 Based on this, the initial second gate line is converted into a second gate line; Figure 16 This is a top view of the back of a solar cell. Figure 15 The initial first gate line is formed based on this; Figure 17 for Figure 16 Cross-sectional view in the AA1 direction; Figure 18 exist Figure 17 Based on this, the initial first gate line is converted into the first gate line.

[0084] In some embodiments, a method of manufacturing a solar cell may include providing a substrate 100, the substrate 100 including a metal region 110 and a non-metal region 120, and the substrate 100 having opposing front side 130 and back side 140.

[0085] The method of manufacturing a solar cell may also include: forming a tunneling layer 101, the tunneling layer 101 being located on the back side 140.

[0086] The method of fabricating a solar cell may further include: forming a doped conductive layer 102, the doped conductive layer 102 being located on the surface of the tunneling layer 101 away from the substrate 100, wherein the thickness of the doped conductive layer 102 located in the metal region 110 is at least greater than the thickness of the doped conductive layer 102 partially located in the non-metal region 120.

[0087] The method of manufacturing a solar cell may also include: forming a passivation layer 103, wherein the passivation layer 103 is located on the surface of the doped conductive layer 102.

[0088] The method for manufacturing a solar cell may further include: forming a first grid line 104, the orthogonal projection of the first grid line 104 on the back side of the substrate 100 being located in the metal region 110, and the first grid line 104 penetrating the passivation layer 103 and contacting the doped conductive layer 102, wherein the material of the first grid line 104 is a non-burn-through material.

[0089] In some embodiments, before forming the tunneling layer 101, the process may further include: texturing the front surface 130 of the substrate 100 to form a pyramid shape on the front surface 130 of the substrate 100.

[0090] In some embodiments, the step of forming the doped conductive layer 102 includes: forming an initial doped conductive layer 122, the initial doped conductive layer 122 being located on the surface of the tunneling layer 101 away from the substrate 100; performing a laser process, the laser process irradiating at least a portion of the initial doped conductive layer 122 located in the non-metallic region 120; and performing an etching process, the etching process removing at least a portion of the initial doped conductive layer 122 irradiated by the laser process, the remaining initial doped conductive layer 122 serving as the doped conductive layer 102. By employing both laser and etching processes to remove the initial doped conductive layer 122, damage to the initial doped conductive layer 122 can be reduced while obtaining a thinner doped conductive layer 102. In other words, the formed doped conductive layer 102 has higher reliability, thereby increasing the reliability of the formed solar cell.

[0091] In some embodiments, during the formation of the doped conductive layer 102, the initial doped conductive layer 122 of the metal region 110 is also etched. In the etching process, the etching process increases the surface roughness of the initial doped conductive layer 122 of the metal region 110, so that when the first grid line 104 is formed later, the contact area between the first grid line and the doped conductive layer 102 can be increased, thereby improving the contact resistance between the first grid line 104 and the doped conductive layer 102 and increasing the fill factor of the formed solar cell. On the other hand, since the thickness of the doped conductive layer 102 of the metal region 110 is also reduced, the parasitic absorption of the doped conductive layer 102 will be further reduced, thereby increasing the short-circuit current of the formed solar cell.

[0092] In some embodiments, the process parameters of the laser process may include: the laser type is a green laser or an ultraviolet laser, the pulse width is 0.1-100 ns, and the laser-treated area accounts for 30-95% of the total back surface area, such as 40%, 50%, 63%, 78%, or 90%. It is understood that the laser-treated portion of the initial doped conductive layer 122 is easier to etch in subsequent etching processes compared to the untreated initial doped conductive layer 122. In other words, the laser-treated portion of the initial doped conductive layer 122 will be etched to a greater thickness in subsequent etching processes. Therefore, controlling the laser-treated area to account for 30-95% of the total back surface area can further reduce the parasitic absorption of the doped conductive layer 102.

[0093] In some embodiments, the laser-processed area accounts for 40-90% of the total back surface area. In this way, while ensuring the reduction of parasitic absorption of the doped conductive layer 102, the passivation contact capability can be guaranteed, thereby improving the photoelectric conversion efficiency of the solar cell.

[0094] In some embodiments, controlling the thickness of the doped conductive layer 102 located in the metal region 110 to be at least greater than the thickness of the doped conductive layer 102 in a portion of the non-metal region 120 can mean that the initial doped conductive layer 122 in the metal region 110 is not thinned, and all the initial doped conductive layers 122 in the non-metal region 120 are removed. In this case, the laser process can be to irradiate a continuous pattern, irradiate all the initial doped conductive layers 122 in the non-metal region 120, and the etching process can simultaneously etch all the initial doped conductive layers 122 in the non-metal region 120, and the etching time is greater than or equal to 80 seconds.

[0095] Controlling the thickness of the doped conductive layer 102 in the metal region 110 to be at least greater than the thickness of the doped conductive layer 102 in the non-metal region 120 can also mean thinning the initial doped conductive layer 122 in the metal region 110 and removing all the initial doped conductive layers 122 in the non-metal region 120. In this case, the laser process can irradiate the initial doped conductive layers 122 in both the metal region 110 and the non-metal region 120. The laser power irradiating the metal region 110 is less than the laser power irradiating the non-metal region 120, and the etching process simultaneously etches the entire surface of the initial doped conductive layer 122, with an etching time of 10~70s. On the one hand, controlling the laser power irradiating the metal region 110 and the non-metal region 120 to be different makes the metal region 110 more difficult to etch than the non-metal region 120. On the other hand, controlling the etching time of the etching process avoids etching through the initial doped conductive layer 122 in the metal region 110, thus avoiding affecting the reliability of the solar cell.

[0096] Controlling the thickness of the doped conductive layer 102 located in the metal region 110 to be at least greater than the thickness of the doped conductive layer 102 in a portion of the non-metal region 120 can also mean: not thinning the initial doped conductive layer 122 in the metal region 110, but thinning all the initial doped conductive layers 122 in the non-metal region 120. In this case, the laser process can be to irradiate a continuous pattern, irradiate all the initial doped conductive layers 122 in the non-metal region 120, and the etching process can simultaneously etch all the initial doped conductive layers 122 in the non-metal region 120, with an etching time of 10~70s.

[0097] Controlling the thickness of the doped conductive layer 102 located in the metal region 110 to be at least greater than the thickness of the doped conductive layer 102 in a portion of the non-metal region 120 can also mean: thinning the initial doped conductive layer 122 in the metal region 110 and simultaneously thinning the initial doped conductive layer 122 in the non-metal region 120, wherein the thickness of the thinned initial doped conductive layer 122 in the non-metal region 120 is greater than the thickness of the thinned initial doped conductive layer 122 in the metal region 110. In this case, the laser process can irradiate the initial doped conductive layer 122 in both the metal region 110 and the non-metal region 120, wherein the laser power irradiating the metal region 110 is less than the laser power in the non-metal region 120, and the etching process simultaneously etches the entire surface of the initial doped conductive layer 122, with an etching time of 10~70s.

[0098] Controlling the thickness of the doped conductive layer 102 located in the metal region 110 to be at least greater than the thickness of the doped conductive layer 102 in the non-metal region 120 can also mean: not thinning the initial doped conductive layer 122 in the metal region 110, and removing part of the initial doped conductive layer 122 in the non-metal region 120, that is, forming a groove 112 in the non-metal region 120 (see reference). Figure 2 In this case, the laser process produces a discontinuous pattern, and the etching process etches the initial doped conductive layer 122 that has been treated by the laser, with an etching time greater than or equal to 80 seconds.

[0099] Controlling the thickness of the doped conductive layer 102 located in the metal region 110 to be at least greater than the thickness of the doped conductive layer 102 in the non-metal region 120 can also mean: not thinning the initial doped conductive layer 122 in the metal region 110, removing part of the initial doped conductive layer 122 in the non-metal region 120, thinning part of the initial doped conductive layer 122 in the non-metal region 120, that is, there are two morphologies on the non-metal region 120, one is the thinned initial doped conductive layer 122, and the other is the formation of a groove 112 on the non-metal region 120. In this case, the laser process is a discontinuous pattern, and the etching time in the etching process is 10~70s.

[0100] It is understood that in the above embodiments, the result is that the thickness of the doped conductive layer 102 located at any location in the metal region 110 is greater than or equal to the thickness of the doped conductive layer 102 located at any location in the non-metal region 120. Alternatively, the thickness of the doped conductive layer 102 in some non-metal regions 120 may be greater than the thickness of the doped conductive layer 102 in the metal region 110. For example, if the initial doped conductive layer 122 in the metal region 110 is thinned and some of the initial doped conductive layer 122 in the non-metal region 120 is removed, then since some of the initial doped conductive layer 122 in the non-metal region 120 is not processed, the thickness of the doped conductive layer 102 in some non-metal regions 120 may be greater than the thickness of the doped conductive layer 102 in the metal region 110.

[0101] It is understood that, for the above embodiments, the greater the thickness of the doped conductive layer 102 to be removed, the greater the laser power in the laser process can be, and the longer the etching time in the etching process can be. The laser power and etching time can be adjusted according to the actual required morphology.

[0102] In some embodiments, a portion of the tunneling layer 101 is etched at the same time as the initial doped conductive layer 122. In another embodiment, the tunneling layer is not affected while the initial doped conductive layer is etched. Therefore, in some other embodiments, the tunneling layer also covers the entire back side.

[0103] In some embodiments, before forming the first gate line, the process may further include: forming an initial second gate line 115 in the metal region 110, the extension direction of the initial second gate line 115 being different from the extension direction of the first gate line; and performing a first sintering process, the first sintering process converting the initial second gate line 115 into a second gate line 105. Forming the second gate line 105 can also collect the charge carriers on the first gate line, facilitating the collection and output of charge carriers.

[0104] It is understandable that by sintering the second grid line 105 before forming the first grid line, the temperature during the formation of the first grid line can be avoided to prevent the oxidation of materials that are not burned through the slurry, thereby preventing the conductivity of the formed first grid line from decreasing and the line resistance of the first grid line from increasing, which would lead to a loss of battery efficiency.

[0105] In some embodiments, before forming the first gate line, the method further includes forming a front main gate and a front sub-gate, wherein the front main gate and the front sub-gate may be made of the same material as the second gate line 105, for example, a sintered material may be used.

[0106] In some embodiments, the second gate line 105, the front main gate, and the front sub-gate can be simultaneously sintered using a first sintering process. The process parameters of the first sintering process may include: a sintering temperature of 400~700℃, a photo-annealing temperature of 200~400℃, and a light intensity of 1~30 solar irradiance.

[0107] In some embodiments, the step of forming the first gate line 104 includes: forming an initial first gate line 114, the orthographic projection of the initial first gate line 114 onto the surface of the substrate 100 being located in the metal region 110; and performing a second sintering process, the second sintering process converting the initial first gate line 114 into the first gate line 104, wherein the temperature of the second sintering process is lower than the temperature of the first sintering process. For the first gate line 104, the material of the first gate line 104 is a non-burn-through material; therefore, the temperature of the second sintering process can be reduced, thereby preventing metal ions from penetrating the doped conductive layer 102 and entering the substrate 100, thus avoiding impact on the performance of the solar cell.

[0108] In some embodiments, the second sintering process may include: a curing step, which is used to cure the initial first gate line 114 to prevent the initial first gate line 114 from shifting in subsequent process steps; and a laser-assisted sintering step, which is used to convert the cured initial first gate line 114 into a first gate line 104.

[0109] In some embodiments, the process parameters for the curing step may include: curing temperature 100~400℃, optimal curing temperature 150~350℃, and curing time 3-30min. The process parameters for the laser-assisted sintering step may include: the light source may be infrared light, red light, green light, or a combination of multiple light sources, and a reverse bias voltage of 10~20V may be applied.

[0110] Understandably, for the second sintering process, the solidification step and the laser-assisted sintering step can achieve precise control of the electrode depth, avoid metal ions burning through the doped conductive layer 102 into the substrate 100, and avoid battery efficiency loss caused by excessive metal composite.

[0111] In some embodiments, the laser-assisted sintering step also simultaneously assists in the sintering of the second gate line 105, and the reverse bias voltage applied to the first gate line 104 is 1.1 to 1.5 times the reverse bias voltage applied to the second gate line 105, and the laser power applied to the first gate line 104 is 1.1 to 1.3 times the laser power applied to the second gate line 105. By increasing the reverse bias voltage and laser power applied to the first gate line 104, alloy formation is ensured at the contact surface between the first gate line 104 and the doped conductive layer 102, thereby reducing the potential barrier between the first gate line 104 and the doped conductive layer 102.

[0112] Taking the material of the first gate line 104 as silver-clad copper as an example, the laser-assisted sintering step will generate a transient large current. The heat generated by the transient large current can locally melt the silver and silicon to form a silver-silicon alloy. The formation of the silver-silicon alloy can significantly reduce the potential barrier between silver and silicon, thereby reducing the contact resistance and forming an ohmic contact.

[0113] In some embodiments, the laser-assisted sintering step can employ either full-surface scanning or grid line scanning. Full-surface scanning means irradiating the entire back side of the solar cell with laser, while grid line scanning means irradiating only the first grid line 104 and the second grid line 105 of the solar cell with laser. Full-surface scanning is preferred over grid line scanning.

[0114] The larger the ratio of the reverse bias voltage applied to the first gate line 104 to the reverse bias voltage applied to the second gate line 105, the smaller the ratio of the laser power applied to the first gate line 104 to the laser power applied to the second gate line 105. In other words, the greater the increase in the reverse bias voltage applied to the first gate line 104, the smaller the increase in the laser power applied to the first gate line 104. By setting the reverse bias voltage and laser power to be complementary, the contact resistance between the first gate line 104 and the doped conductive layer 102 can be reduced, and the contact resistance can be less than 2 mΩ. 2 .

[0115] In other embodiments, during the formation of the first gate line and the second gate line, the initial first gate line and the initial second gate line can be printed first, and the first gate line and the second gate line can be formed by high-temperature sintering and photo-annealing in the same process step. Then, the contact resistance between the first gate line and the doped conductive layer 102 can be improved by laser-assisted sintering.

[0116] It is understandable that, compared to the above embodiment where the second grid line is formed first and then formed through the same process steps, the present disclosure embodiment can improve the production efficiency of solar cells. However, for the first grid line, the material of the first grid line is a non-burn-through material. Taking silver-coated copper as an example, the high-temperature sintering process will expose the copper powder, which will cause the copper powder to oxidize, resulting in a decrease in the performance of the first grid line. Therefore, antioxidants can be added to the material of the first grid line to prevent the exposed copper powder from being oxidized. Alternatively, the thickness of the silver coating on the surface of the copper powder can be increased to isolate oxygen. Or, the high-temperature sintering step can be carried out in a nitrogen or inert gas atmosphere.

[0117] Another embodiment of this disclosure also provides a photovoltaic module, which may include the solar cell in the above embodiments, or include a solar cell formed by the manufacturing method of the solar cell in the above embodiments. The manufacturing method of the solar cell provided in another embodiment of this disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts of the foregoing embodiments can be referred to the corresponding descriptions of the foregoing embodiments, and will not be repeated below.

[0118] refer to Figure 19 and Figure 20 ,in Figure 19 This is a three-dimensional structural diagram of a photovoltaic module provided in an embodiment of this disclosure. Figure 20 for Figure 19 Cross-sectional view along the M1M2 direction.

[0119] A photovoltaic module may include: a battery string 20, which is formed by connecting multiple solar cells as described in some or all of the above embodiments or solar cells prepared by some or all of the above embodiments; an encapsulating film 21 for covering the surface of the battery string; and a cover plate 22 for covering the surface of the encapsulating film 21 facing away from the battery string.

[0120] In some embodiments, the solar cell includes, but is not limited to, one or any combination of TOPCon cells (Tunnel Oxide Passivated Contact cells), tandem cells, etc. Tandem cells include, but are not limited to, perovskite cells stacked with TOPCon cells.

[0121] In some embodiments, there is no spacing between the solar cells, meaning that the solar cells overlap each other.

[0122] In some embodiments, the encapsulating film 21 includes a first encapsulating layer and a second encapsulating layer. The first encapsulating layer covers one of the front or back sides of the solar cell, and the second encapsulating layer covers the other of the front or back sides of the solar cell. Specifically, at least one of the first encapsulating layer or the second encapsulating layer can be an organic encapsulating film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene coelastomer (POE) film, or polyethylene terephthalate (PET) film.

[0123] It is worth noting that the first encapsulation layer and the second encapsulation layer still have a dividing line before lamination. After lamination, the photovoltaic module will no longer have the concept of a first encapsulation layer and a second encapsulation layer. That is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 21.

[0124] In some embodiments, the cover plate 22 can be a glass cover plate, a plastic cover plate, or other cover plate with light-transmitting function. Specifically, the surface of the cover plate 22 facing the encapsulating film 21 can be an uneven surface, thereby increasing the utilization rate of incident light. The cover plate 22 includes a first cover plate and a second cover plate, the first cover plate being opposite to the first encapsulation layer and the second cover plate being opposite to the second encapsulation layer; or the first cover plate being opposite to one side of the solar cell and the second cover plate being opposite to the other side of the solar cell.

[0125] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A solar cell, characterized in that, include: A substrate having spaced-apart metal regions on which a tunneling layer and a doped conductive layer are disposed; A passivation layer, wherein the passivation layer is located on the surface of the doped conductive layer; A first gate line, the orthographic projection of the first gate line on the substrate surface is located in the metal region, and the first gate line is connected to the doped conductive layer, wherein the material of the first gate line is one or more of silver, nickel, aluminum, manganese or copper.

2. The solar cell according to claim 1, characterized in that, Also includes: The second gate line extends in a different direction than the first gate line, and the second gate line is electrically connected to multiple first gate lines. A gate-like line is located in the metal region. The extension direction of the gate-like line is the same as that of the second gate line, and the gate-like line and the second gate line are arranged at intervals. One gate-like line is electrically connected to multiple first gate lines. The material of the gate-like line is different from that of the second gate line.

3. The solar cell according to claim 1, characterized in that, The tunneling layer is located only in the metal region, and the doped conductive layer is located only on the surface of the tunneling layer.

4. The solar cell according to claim 1, characterized in that, The doped conductive layer includes a first doped portion corresponding to the metal region and a second doped portion corresponding to the region between adjacent metal regions. It also includes: a groove located between adjacent metal regions, and the groove at least penetrates a portion of the second doped portion.

5. The solar cell according to claim 1 or 4, characterized in that, It also includes a non-metallic region located between adjacent metallic regions, and the doped conductive layer is also located in the non-metallic region. The thickness of the doped conductive layer located in the metallic region is at least greater than the thickness of the doped conductive layer partially located in the non-metallic region.

6. The solar cell according to claim 5, characterized in that, The thickness of the doped conductive layer located at any point in the metal region is greater than or equal to the thickness of the doped conductive layer located at any point in the non-metal region.

7. The solar cell according to claim 1, characterized in that, The first grid line is made of a material in which a first metal encapsulates a second metal, and the conductivity of the first metal is greater than or equal to the conductivity of the second metal.

8. The solar cell according to claim 1, characterized in that, Also includes: A gate-like line, located in the metal region, extends in a direction different from that of the first gate line.

9. A method for manufacturing a solar cell, characterized in that, include: A substrate is provided, the substrate having spaced-apart metal regions; A tunneling layer and a doped conductive layer are formed, wherein the tunneling layer and the doped conductive layer are located in the metal region; A passivation layer is formed on the surface of the doped conductive layer; A first gate line is formed, the orthographic projection of the first gate line on the substrate surface is located in the metal region, and the first gate line is connected to the doped conductive layer. The material of the first gate line is one or more of silver, nickel, aluminum, manganese or copper.

10. The method for manufacturing a solar cell according to claim 9, characterized in that, The steps for forming the doped conductive layer include: An initial doped conductive layer is formed, the initial doped conductive layer being located on the surface of the tunneling layer away from the substrate; A laser process is performed, wherein the laser process irradiates at least a portion of the initial doped conductive layer located between adjacent metal regions; An etching process is performed, wherein at least a portion of the initial doped conductive layer irradiated by the laser process is removed, and the remaining initial doped conductive layer serves as the doped conductive layer.

11. The method for manufacturing a solar cell according to claim 10, characterized in that, The ratio of the area of ​​the initial doped conductive layer irradiated by the laser process to the area of ​​the initial doped conductive layer is 40% to 90%.

12. The method for manufacturing a solar cell according to claim 10, characterized in that, The etching process also etches the initial doped conductive layer located in the metal region to improve the surface roughness of the initial doped conductive layer located in the metal region.

13. The method for manufacturing a solar cell according to claim 9, characterized in that, Before forming the first gate line, the process also includes: An initial second gate line is formed in the metal region, and the extension direction of the initial second gate line is different from the extension direction of the first gate line. A first sintering process is performed, in which the initial second gate line is converted into a second gate line.

14. The method for manufacturing a solar cell according to claim 13, characterized in that, The steps for forming the first gate line include: An initial first gate line is formed, wherein the orthographic projection of the initial first gate line on the substrate surface is located in the metal region; A second sintering process is performed, in which the initial first gate line is converted into the first gate line, and the temperature of the second sintering process is lower than the temperature of the first sintering process.

15. The method for manufacturing a solar cell according to claim 14, characterized in that, The second sintering process includes: A curing step, wherein the curing step is used to cure the initial first gate line; A laser-assisted sintering step, wherein the laser-assisted sintering step is used to convert the solidified initial first grid line into the first grid line.

16. The method for manufacturing a solar cell according to claim 15, characterized in that, The laser-assisted sintering step further applies a reverse bias voltage, wherein the voltage value of the reverse bias voltage applied to the first gate line is 1.1 to 1.3 times the voltage value of the reverse bias voltage applied to the second gate line.

17. The method for manufacturing a solar cell according to claim 16, characterized in that, The larger the ratio of the reverse bias voltage applied to the first gate line to the reverse bias voltage applied to the second gate line, the smaller the ratio of the laser power applied to the first gate line to the laser power applied to the second gate line.

18. A photovoltaic module, characterized in that, include: A battery string is formed by connecting multiple solar cells as described in any one of claims 1 to 8, or by connecting multiple solar cells formed by the manufacturing method as described in any one of claims 9 to 17; An encapsulating film is used to cover the surface of the battery string; A cover plate is used to cover the surface of the encapsulating film that faces away from the battery string.

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