Vertical LED chip and preparation method thereof

Abstract

The invention discloses a vertical LED chip and a preparation method thereof, and relates to the field of semiconductor photoelectric devices. The preparation method of the vertical LED chip comprises the following steps: providing an epitaxial wafer; forming an imprint glue layer on the P-type contact layer; forming an imprint pattern on the imprint glue layer; transferring the imprinting pattern to the P-type contact layer to form a plurality of bulges in the first preset area; forming a dielectric layer and a second reflecting layer on the bulge to obtain a first intermediate; forming a transparent conductive layer on one side of the P-type contact layer of the first intermediate; forming a first electrode on the transparent conductive layer to obtain a second intermediate; the orthographic projection of the first electrode on the P-type contact layer coincides with the first preset area. Or the orthographic projection of the first electrode on the P-type contact layer is located in the first preset area; and forming a second electrode on the substrate side of the second intermediate. According to the invention, the light extraction efficiency and reliability of the vertical LED chip can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronic devices, and more particularly to a vertical LED chip and its fabrication method. Background Technology

[0002] In existing GaAs-based vertical LED chips, the main electrode is located on a P-type GaP window layer. Because an ohmic contact is formed between the main electrode and the P-type GaP window layer, it acts as a good current channel, allowing current to be injected directly downwards. This results in light emission being concentrated primarily below the main electrode, with a large amount of light being blocked and absorbed by the main electrode, leading to low brightness in this LED chip structure. Furthermore, the P-type GaP window layer also exhibits extremely high light absorption, further reducing the light extraction efficiency of the vertical LED chip.

[0003] To address the aforementioned technical issues, a novel structure introduces a transparent conductive layer between the P-type GaP window layer and the main electrode. This reduces the thickness of the P-type GaP window layer by more than 50%, lowering epitaxial wafer growth costs and resulting in higher LED chip brightness due to more uniform current distribution. However, the transparent conductive layer in this structure is often deposited onto the surface of the P-type GaP window layer via electron beam evaporation or magnetron sputtering, rather than through epitaxial growth. Therefore, during wire bonding, when the main electrode is subjected to significant pressure or ultrasonic vibration power, the bonding electrode may detach along with the underlying ITO layer, resulting in lower reliability. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a vertical LED chip and its preparation method, which has high light extraction efficiency and high reliability.

[0005] To address the aforementioned technical problems, this invention provides a method for fabricating a vertical LED chip, comprising the following steps: S1. Provide an epitaxial wafer, the epitaxial wafer comprising a substrate and a first reflective layer, an N-type semiconductor layer, an MQW layer, a P-type semiconductor layer and a P-type contact layer sequentially disposed on the substrate; S2. An imprinted adhesive layer is formed on the P-type contact layer; S3. An embossed pattern is formed on the embossing adhesive layer; S4. Transfer the embossed pattern onto the P-type contact layer to form multiple protrusions in the first preset area; S5. A dielectric layer and a second reflective layer are formed on the protrusion to obtain a first intermediate. S6. A transparent conductive layer is formed on one side of the P-type contact layer of the first intermediate; S7. A first electrode is formed on the transparent conductive layer to obtain a second intermediate; wherein the orthographic projection of the first electrode on the P-type contact layer coincides with the first preset region; or the orthographic projection of the first electrode on the P-type contact layer is located inside the first preset region. S8. A second electrode is formed on one side of the substrate of the second intermediate.

[0006] As an improvement to the above technical solution, step S2 includes: S21: Spin-coating the imprinting adhesive onto the P-type contact layer; wherein the spin-coating speed is 2000rpm~3000rpm, the spin-coating time is 30s~50s, the spin-coating thickness is 200nm~1000nm, and the viscosity of the imprinting adhesive is 5mPa·s~50mPa·s. S22: The imprinting adhesive is baked and cured to obtain an imprinting adhesive layer; wherein the baking temperature is 80℃~120℃ and the baking time is 1min~5min.

[0007] As an improvement to the above technical solution, in step S3, an ultraviolet light curing nanoimprinting process is used to form the imprinted pattern; wherein the wavelength of the ultraviolet light source is 365nm and the exposure dose range is 50mJ / cm. 2 ~800mJ / cm 2 The imprinting pressure is 0.5MPa~2MPa, and the imprinting time is 1min~3min.

[0008] As an improvement to the above technical solution, the dielectric layer is a stacked structure formed by one or more of SiO2, MgF2, TiO2, and Ti2O5 layers; the thickness of the dielectric layer is 0.3 μm to 3 μm; and / or The second reflective layer is one or more of Au, Ag, and Al layers, and the thickness of the second reflective layer is 100 nm to 1000 nm; and / or The protrusion is pyramidal, hemispherical, or ellipsoidal, and its height is 1.5μm to 4μm.

[0009] As an improvement to the above technical solution, in step S6, the thickness of the transparent conductive layer conforms to the following relationship:

[0010] Where δ is the thickness of the transparent conductive layer, n is the refractive index of the transparent conductive layer, λ is the dominant wavelength of the vertical LED chip, and k is a natural number with a value range of 1 to 3; The transparent conductive layer is one or more of ITO, IZO, and IGZO layers.

[0011] As an improvement to the above technical solution, the P-type contact layer is a P-type GaP window layer with a thickness of 1μm~5μm and a doping concentration of 1×10⁻⁶. 18 cm -3 ~1×10 19 cm -3 .

[0012] As an improvement to the above technical solution, the first reflective layer is Al. x Ga 1-x As / Al y Ga 1-y As-type DBR layer or Ga α In 1-α P / Al β Ga 1-β As-type DBR layer; the thickness of the first reflective layer is 0.5μm~8μm.

[0013] As an improvement to the above technical solution, the substrate is a GaAs substrate; The N-type semiconductor layer is an N-type AlGaInP confinement layer; The P-type semiconductor layer is a P-type AlGaInP confinement layer.

[0014] As an improvement to the above technical solution, step S8 includes: S81. The substrate is thinned by grinding; S82. A second electrode is formed on the thinned substrate to obtain an LED wafer; S83. Cut the LED wafer to obtain a vertical LED chip.

[0015] Accordingly, the present invention also discloses a vertical LED chip, which is prepared by the above-described preparation method.

[0016] Implementing this invention has the following beneficial effects: In one embodiment of the present invention, a method for fabricating a vertical LED chip involves forming multiple protrusions on a first predetermined region of a P-type contact layer using a nanoimprinting process. A dielectric layer and a second reflective layer are then formed on these protrusions. A transparent conductive layer is formed on the second reflective layer and the P-type contact layer not covered by the second reflective layer, and a first electrode is formed on the transparent conductive layer. Based on this structure, firstly, the interfacial bonding strength between the transparent conductive layer, the first electrode, and the P-type contact layer is improved, reducing the probability of electrode and transparent conductive layer detachment and enhancing the reliability of the vertical LED chip. Secondly, the high-resistivity dielectric layer allows for more uniform lateral current distribution within the P-type contact layer, suppressing current congestion and improving luminous brightness. Thirdly, the synergistic effect of the dielectric layer and the reflective layer effectively reflects light incident on the first electrode, which then escapes after reflection through the first reflective layer, improving light extraction efficiency. Fourthly, the protrusions increase the reflective area, further enhancing light extraction efficiency. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of an epitaxial wafer in one embodiment of the present invention; Figure 2 This is a schematic diagram of the epitaxial wafer structure after step S2 in one embodiment of the present invention; Figure 3 This is a schematic diagram of the epitaxial wafer structure after step S3 in one embodiment of the present invention; Figure 4 This is a schematic diagram of the epitaxial wafer structure after step S4 in one embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the first intermediate obtained in step S5 of an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of the first intermediate body after step S6 in one embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of the second intermediate obtained in step S7 of one embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of a vertical LED chip in one embodiment of the present invention; In the figure, 110 is the substrate, 120 is the N-type GaAs buffer layer, 130 is the first reflective layer, 140 is the N-type semiconductor layer, 150 is the MQW layer, 160 is the P-type semiconductor layer, 170 is the P-type contact layer, 171 is the protrusion, 200 is the imprinting adhesive layer, 210 is the imprinted pattern, 300 is the dielectric layer, 400 is the second reflective layer, 500 is the transparent conductive layer, 600 is the first electrode, and 700 is the second electrode. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application.

[0019] In the description of this application, it should be understood that the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0021] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0022] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0023] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0024] This invention provides a method for fabricating a vertical LED chip, which includes the following steps: S1. Provide epitaxial wafers; Please see Figure 1 The epitaxial wafer includes a substrate 110, and a first reflective layer 130, an N-type semiconductor layer 140, an MQW layer 150, a P-type semiconductor layer 160, and a P-type contact layer 170 sequentially disposed on the substrate 110. Specifically, the vertical LED chip of the present invention can be a blue, red, green, yellow, or violet LED chip, and different types of semiconductor layers can be selected based on the control of the emission wavelength. Exemplarily, in one embodiment, when the vertical LED chip is a blue LED chip, the N-type semiconductor layer 140 is an N-type GaN layer, the MQW layer 150 is an InGaN-GaN type multiple quantum well layer, the P-type semiconductor layer 160 can be a P-type GaN layer, and the P-type contact layer 170 can be a P-type InGaN layer or a heavily doped P-type GaN layer, but is not limited thereto. In another embodiment, when the vertical LED chip is a violet LED chip, the N-type semiconductor layer 140 can be an N-type AlGaN layer, the MQW layer 150 can be an AlGaN-AlGaN type multiple quantum well layer, the P-type semiconductor layer 160 can be a P-type AlGaN layer, and the P-type contact layer 170 can be a P-type GaN layer, but is not limited thereto.

[0025] Preferably, in one embodiment, the vertical LED chip is a red LED chip, and the epitaxial wafer includes an N-type GaAs buffer layer 120, a first reflective layer 130, an N-type semiconductor layer 140 (N-type AlGaInP confinement layer), an MQW layer 150, a P-type semiconductor layer 160 (P-type AlGaInP confinement layer), and a P-type contact layer 170 (P-type GaP window layer) sequentially disposed on a substrate 110. The following steps are described using a red LED chip, but the technical solution of the present invention is not limited to the red LED chip described herein.

[0026] Specifically, in some embodiments, the P-type contact layer 170 is a P-type GaP window layer with a thickness of 1 μm to 5 μm and a doping concentration of 1 × 10⁻⁶.18 cm -3 ~1×10 19 cm -3 The present invention effectively enhances the current spreading effect by setting a transparent conductive layer 500 on the P-type contact layer 170. Therefore, the thickness of the P-type contact layer 170 can be appropriately reduced, thereby reducing light absorption and improving light extraction efficiency.

[0027] Specifically, the first reflective layer 130 may be a DBR reflective layer, but is not limited thereto. For example, the first reflective layer 130 may be an Al... x Ga 1-x As (x = 0.05~0.2) / Al y Ga 1-y As (y=0.7~0.95) type DBR layer or Ga α In 1-α P(α=0.35~0.55) / Al β Ga 1-β The first reflective layer 130 has an As (β=0.5~0.8) type DBR layer and a thickness of 0.5μm~8μm, but is not limited thereto. Preferably, in some embodiments, the first reflective layer 130 comprises alternating layers of Al. x Ga 1-x As layer and Al y Ga 1-y The As layer has a period number of 5 to 40. The thickness of the first reflective layer 130 is 0.5 μm to 10 μm, exemplarily 1.5 μm, 2.5 μm, 3.5 μm, 4.5 μm, 5.5 μm, 6.5 μm, 7.5 μm or 8.5 μm, but is not limited thereto. Preferably, it is 0.5 μm to 8 μm.

[0028] S2. An imprinting adhesive layer 200 is formed on the P-type contact layer 170; Specifically, please refer to Figure 2 The imprinting layer 200 can be formed using a thermosetting nanoimprinting adhesive or a UV-curable imprinting adhesive, but is not limited thereto. Preferably, in some embodiments, step S2 includes: S21: Spin-coat the imprinting adhesive onto the P-type contact layer 170; The imprinting adhesive is a UV-curable nanoimprinting adhesive with a viscosity of 5 mPa·s to 50 mPa·s (25℃). The UV-curable nanoimprinting adhesive has excellent thermal stability, high resolution, and resistance to high-temperature etching and chemical corrosion, which facilitates the maintenance of the structure in subsequent high-temperature processes of vertical LED chips.

[0029] Specifically, the spin coating speed is 2000rpm~3000rpm, the spin coating time is 30s~50s, and the spin coating thickness is 200nm~1000nm.

[0030] S22: Bake and cure the imprinting adhesive to obtain imprinting adhesive layer 200; Specifically, the baking temperature is 80℃~120℃, and the baking time is 1min~5min. Baking removes solvents and improves the uniformity and adhesion of the imprinting adhesive layer 200, optimizing the transfer accuracy of the pattern.

[0031] S3: Form an embossed pattern on the embossing adhesive layer; Specifically, a nanoimprint template is used to apply pressure to the adhesive layer surface and then cured by ultraviolet light or heat to accurately transfer the pattern. Preferably, in some embodiments, an ultraviolet light curing nanoimprinting process is used to form the imprinted pattern 210. Here, a 365nm wavelength ultraviolet light source is used, and the exposure dose range is 50mJ / cm². 2 ~800mJ / cm 2 The imprinting pressure is 0.5MPa~2MPa, and the imprinting time is 1min~3min. The UV curing process not only ensures the stability of the pattern morphology, but also forms a strong chemical bond between the imprinting adhesive and the P-type contact layer 170 interface, significantly improving the etching resistance in subsequent etching processes. The synergistic control of UV light and pressure precisely balances the flow and cross-linking rate of the adhesive, avoiding edge collapse or insufficient filling, ensuring the high fidelity and structural integrity of the imprinted pattern 210, and providing a reliable mask basis for subsequent dry etching.

[0032] Specifically, please refer to Figure 3 The embossed pattern 210 includes multiple raised shapes, which may be cones, pyramids, prisms or hemispheres.

[0033] S4: Transfer the embossed pattern 210 onto the P-type contact layer 170 to form a plurality of protrusions 171 in the first preset area; Specifically, using the imprinted adhesive pattern as a mask, the corresponding structure is precisely etched into the P-type contact layer 170 using ICP or RIE dry etching technology, thus obtaining the protrusion 171. Preferably, ICP etching is used, with the etching gas being a Cl2 / BCl3 mixture at a total flow rate of 20 sccm to 50 sccm, a Cl2 to BCl3 flow ratio of 3:1 to 5:1, an ICP power of 800W to 1500W, and an RF power of 20W to 100W. Based on this etching process, damage to the P-type contact layer 170 can be effectively reduced while forming the protrusion 171.

[0034] Specifically, please refer to Figure 4The protrusion 171 is pyramidal, hemispherical, or ellipsoidal, and its height is greater than the sum of the thickness of the dielectric layer 300 and the thickness of the second reflective layer 400. This ensures that the protrusion 171 is not filled in after the formation of the dielectric layer 300 and the second reflective layer 400, thereby maintaining and increasing the reflective area and enhancing the adhesion between the protrusion and the transparent conductive layer 500. Specifically, the height of the protrusion 171 is 1μm to 5μm, exemplarily 1.2μm, 1.7μm, 2.2μm, 3.5μm, or 4.8μm, but is not limited thereto. Preferably, it is 1.5μm to 4μm.

[0035] Specifically, the protrusions 171 can be arranged closely together, meaning their bottom surfaces at least partially overlap; the protrusions 171 can also be arranged at a certain interval. Preferably, in some embodiments, the protrusions 171 are arranged in a periodic array with a spacing of 0.5μm to 3μm to ensure synergistic optimization of light extraction efficiency and current spreading performance.

[0036] S5: A dielectric layer and a second reflective layer are formed on the protrusion to obtain the first intermediate; Specifically, the dielectric layer 300 is a high-resistivity layer, which may be one or more of SiO2, MgF2, TiO2, and Ti2O5 layers, but is not limited thereto. Preferably, it is a SiO2 or MgF2 layer. The thickness of the dielectric layer 300 is 0.3 μm to 3 μm, exemplary values ​​are 0.5 μm, 1.2 μm, 1.9 μm, 2.4 μm, or 2.8 μm, but is not limited thereto. Preferably, it is 0.5 μm to 1 μm.

[0037] Specifically, the second reflective layer 400 is a metallic reflective layer, exemplarily one or more of Au, Ag, and Al layers, but not limited thereto. Preferably, it is an Ag layer. The thickness of the second reflective layer 400 is 100nm to 3000nm, exemplarily 150nm, 300nm, 800nm, 1200nm, or 2500nm, but not limited thereto. Preferably, it is 100nm to 1000nm.

[0038] Specifically, please refer to Figure 5 The dielectric layer 300 and the second reflective layer 400 only cover the surface of the protrusion 171, and do not cover the P-type contact layer 170 other than the protrusion 171.

[0039] Based on the aforementioned protrusion 171 and the dielectric layer 300 and second reflective layer 400 covering its surface, firstly, the interfacial bonding strength between the transparent conductive layer 500, the first electrode 600, and the P-type contact layer 170 is improved, reducing the probability of electrode and transparent conductive layer 500 detachment and improving the reliability of the vertical LED chip. Secondly, the high-resistivity dielectric layer 300 allows for more uniform lateral current distribution in the P-type contact layer 170, suppressing current congestion and improving luminous brightness. Thirdly, through the synergistic effect of the dielectric layer 300 and the reflective layer, light incident on the first electrode 600 is effectively reflected and then escapes after reflection by the first reflective layer 130, improving light extraction efficiency. Fourthly, the protrusion 171 increases the reflective area, further improving light extraction efficiency.

[0040] S6: A transparent conductive layer is formed on one side of the P-type contact layer of the first intermediate; Please refer to Figure 6 A transparent conductive layer 500 covers the second reflective layer 400 and the surface of the P-type contact layer 170 that is not obstructed by the protrusion 171. The transparent conductive layer 500 can improve the uniformity of lateral current spread and reduce contact resistance. Specifically, the transparent conductive layer 500 can be one or more of ITO, IZO, IGZO, and IGO layers, but is not limited thereto. Preferably, the transparent conductive layer 500 is an ITO layer.

[0041] Preferably, in some embodiments, the thickness of the transparent conductive layer 500 conforms to the following relationship:

[0042] Where δ is the thickness of the transparent conductive layer 500, n is the refractive index of the transparent conductive layer 500, λ is the dominant wavelength perpendicular to the LED chip, and k is a natural number ranging from 1 to 3. Based on the above thickness control, the transparent conductive layer 500 can possess both excellent electrical properties and optical transmittance, further improving light extraction efficiency.

[0043] S7: A first electrode is formed on the transparent conductive layer to obtain a second intermediate; The first electrode 600 can be formed using processes such as vapor deposition and sputtering, but is not limited to these methods. The first electrode 600 can be formed using one or more of the commonly used Cr layer, Al layer, Pt layer, Au layer, etc., but is not limited to these methods.

[0044] Specifically, please refer to Figure 7The orthographic projection of the first electrode 600 on the P-type contact layer 170 coincides with the first preset region; or the orthographic projection of the first electrode 600 on the P-type contact layer 170 is located inside the first preset region. Based on this, one can ensure that the current is efficiently injected into the P-type contact layer 170 and spreads evenly laterally, avoiding local overheating; the other can effectively prevent the first electrode 600 from absorbing light and improve the light extraction efficiency.

[0045] S8. A second electrode is formed on one side of the substrate of the second intermediate.

[0046] The second electrode 700 can be formed using processes such as vapor deposition and sputtering, but is not limited to these methods. The second electrode 700 can be formed using one or more of the commonly used Cr layer, Al layer, Pt layer, Au layer, etc., but is not limited to these methods.

[0047] Preferably, in some embodiments, step S8 includes: S81. Thin the substrate by grinding; S82. A second electrode is formed on the thinned substrate to obtain an LED wafer; S83. Cut the LED wafer to obtain vertical LED chips.

[0048] Specifically, through tangenting, back-cutting, and dicing processes, the LED wafer is cut into separate vertical LED chips, the structure of which is as follows: Figure 8 As shown.

[0049] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with the described embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0050] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for fabricating a vertical LED chip, characterized in that, Includes the following steps: S1. Provide an epitaxial wafer, the epitaxial wafer comprising a substrate and a first reflective layer, an N-type semiconductor layer, an MQW layer, a P-type semiconductor layer and a P-type contact layer sequentially disposed on the substrate; S2. An imprinted adhesive layer is formed on the P-type contact layer; S3. An embossed pattern is formed on the embossing adhesive layer; S4. Transfer the embossed pattern onto the P-type contact layer to form multiple protrusions in the first preset area; S5. A dielectric layer and a second reflective layer are formed on the protrusion to obtain a first intermediate. S6. A transparent conductive layer is formed on one side of the P-type contact layer of the first intermediate; S7. A first electrode is formed on the transparent conductive layer to obtain a second intermediate; wherein the orthographic projection of the first electrode on the P-type contact layer coincides with the first preset region; or the orthographic projection of the first electrode on the P-type contact layer is located inside the first preset region. S8. A second electrode is formed on one side of the substrate of the second intermediate.

2. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, Step S2 includes: S21: Spin-coating the imprinting adhesive onto the P-type contact layer; wherein the spin-coating speed is 2000rpm~3000rpm, the spin-coating time is 30s~50s, the spin-coating thickness is 200nm~1000nm, and the viscosity of the imprinting adhesive is 5mPa·s~50mPa·s. S22: The imprinting adhesive is baked and cured to obtain an imprinting adhesive layer; wherein the baking temperature is 80℃~120℃ and the baking time is 1min~5min.

3. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, In step S3, an imprinted pattern is formed using ultraviolet light curing nanoimprinting technology; wherein the wavelength of the ultraviolet light source is 365nm and the exposure dose range is 50mJ / cm. 2 ~800mJ / cm 2 The imprinting pressure is 0.5MPa~2MPa, and the imprinting time is 1min~3min.

4. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, The dielectric layer is a stacked structure formed by one or more of SiO2, MgF2, TiO2, and Ti2O5 layers; the thickness of the dielectric layer is 0.3 μm to 3 μm; and / or The second reflective layer is one or more of Au, Ag, and Al layers, and the thickness of the second reflective layer is 100 nm to 1000 nm; and / or The protrusion is pyramidal, hemispherical, or ellipsoidal, and its height is 1.5μm to 4μm.

5. The method for fabricating a vertical LED chip as described in any one of claims 1 to 4, characterized in that, In step S6, the thickness of the transparent conductive layer conforms to the following relationship: Where δ is the thickness of the transparent conductive layer, n is the refractive index of the transparent conductive layer, λ is the dominant wavelength of the vertical LED chip, and k is a natural number with a value range of 1 to 3; The transparent conductive layer is one or more of ITO, IZO, and IGZO layers.

6. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, The P-type contact layer is a P-type GaP window layer with a thickness of 1 μm to 5 μm and a doping concentration of 1 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3 .

7. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, The first reflective layer is Al x Ga 1-x As / Al y Ga 1-y As-type DBR layer or Ga α In 1-α P / Al β Ga 1-β As-type DBR layer; the thickness of the first reflective layer is 0.5μm~8μm.

8. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, The substrate is a GaAs substrate; The N-type semiconductor layer is an N-type AlGaInP confinement layer; The P-type semiconductor layer is a P-type AlGaInP confinement layer.

9. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, Step S8 includes: S81. The substrate is thinned by grinding; S82. A second electrode is formed on the thinned substrate to obtain an LED wafer; S83. Cut the LED wafer to obtain a vertical LED chip.

10. A vertical LED chip, characterized in that, It is prepared by the preparation method according to any one of claims 1 to 9.

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