Miniature LED chip and manufacturing method thereof

Abstract

The invention provides a miniature LED chip and a manufacturing method thereof.According to the miniature LED chip and the manufacturing method thereof, a composite reflection structure is arranged, light emitted by an active area is subjected to full-angle reflection, the composite reflection structure comprises a first DBR insulating layer, a first metal reflector and a second DBR insulating layer, the first DBR insulating layer reflects light with the small angle, and the second DBR insulating layer reflects light with the small angle; a first opening of the first DBR insulating layer is used for weakening reflection of light rays with small geometric center angles of the LED chip, normal light of the geometric center area of the LED chip is reduced, and light rays with large angles are reflected through the first metal reflecting mirror and are reflected to a light emitting surface; after penetrating through the first metal reflector, a part of light with a large angle is reflected back by the second DBR insulating layer, penetrates through the first metal reflector again and generates constructive interference with first-time reflected light of the first metal reflector, lateral light emitting is increased, the reflectivity of the composite reflection structure is remarkably improved, and then the overall brightness and the light emitting angle of the LED chip are improved. The process is simple and convenient, and is convenient for production.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device manufacturing technology, and more specifically, relates to a micro LED chip and its manufacturing method. Background Technology

[0002] Mini-LED refers to LED chips with dimensions on the order of 100 micrometers, primarily used in backlighting and direct-view displays. In terms of size, a single Mini-LED chip ranges from 50 to 200 μm, with a pixel pitch of approximately 0.5 to 1 mm. Compared to traditional LED chip backlighting products, this smaller pixel pitch allows for the integration of more LED backlight beads onto a single display screen. This divides the screen into more finely divided backlight zones, facilitating more precise localized light emission adjustment and achieving contrast levels approaching those of OLED screens. Furthermore, compared to OLED screens, Mini-LED backlit screens offer advantages such as longer lifespan and reduced burn-in resistance.

[0003] However, the current luminous efficiency of Mini-LED is relatively low. In order to achieve a better display effect, more backlight chips and backlight design need to be integrated, making it difficult to make the thickness thinner. The accumulation of multiple backlight chips can also generate more heat, which puts higher demands on the heat dissipation of the equipment. This greatly limits the application of Mini-LED chips. Summary of the Invention

[0004] In view of this, the present invention provides a micro LED chip and its manufacturing method to solve the problems in the prior art where the low luminous efficiency of Mini-LEDs leads to the integration of more backlight beads and backlight design to achieve better display effects, making it difficult to make the chip thinner, and the accumulation of multiple backlight beads easily generates more heat, which puts higher demands on the heat dissipation of the equipment and greatly limits the application of Mini-LED chips.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A micro LED chip, comprising:

[0007] An epitaxial stack, wherein the epitaxial stack comprises at least a first type semiconductor layer, an active region, and a second type semiconductor layer stacked sequentially;

[0008] A composite reflection structure is disposed on the side surface of the epitaxial stack opposite to the light-emitting surface, and reflects the light emitted from the active region at all angles. The composite reflection structure includes a first DBR insulating layer, a first metal mirror, and a second DBR insulating layer stacked sequentially along the direction opposite to the epitaxial stack. The first DBR insulating layer is used to reflect light at a first incident angle, and the second DBR insulating layer is used to reflect light at a second incident angle. The first incident angle is θ1, and the second incident angle is θ2, then θ1 < θ2, and the first DBR insulating layer and the second DBR insulating layer extend at least to the sidewall of the epitaxial stack.

[0009] Wherein, the first DBR insulating layer has at least one first opening exposing the surface of the epitaxial stack portion and at least one first protrusion structure corresponding to it; the first metal mirror covers the first opening and the first protrusion structure; the second DBR insulating layer covers the exposed surfaces of the first DBR insulating layer and the first metal mirror.

[0010] The first electrode is electrically connected to the first type of semiconductor layer, and the second electrode is electrically connected to the second type of semiconductor layer, with the first electrode and the second electrode disposed far apart from each other.

[0011] Preferably, a substrate is disposed on one side of the light-emitting surface of the epitaxial stack, the micro LED chip has a dicing channel that exposes a portion of the surface of the substrate facing the epitaxial stack, and the composite reflective structure covers the exposed surface of the epitaxial stack;

[0012] The epitaxial stack has a first mesa exposing a portion of the first type semiconductor layer and a second mesa exposing a portion of the second type semiconductor layer on the side opposite to the substrate. The first opening exposes a portion of the surface of the second mesa. The second DBR insulating layer has a first electrode via exposing a portion of the surface of the first mesa and a second electrode via exposing a portion of the surface of the first metal mirror.

[0013] Both the first electrode and the second electrode are located on the side of the composite reflective structure away from the epitaxial stack. The first electrode fills the first electrode via and forms an electrical connection with the first type semiconductor layer, and the second electrode fills the second electrode via and forms an electrical connection with the second type semiconductor layer.

[0014] Preferably, θ1 includes 0°-50°, including the endpoint value; θ2 includes 45°-90°, including the endpoint value; the reflection bandwidth range of the first DBR insulating layer and the second DBR insulating layer is 400nm-800nm, including the endpoint value.

[0015] Preferably, when θ1 is 0°, the single-layer optical thickness of the first DBR insulating layer is 1 / 4λ1; when θ1 is not equal to 0°, the single-layer optical thickness of the first DBR insulating layer is 1 / 4λ1*sinθ1, where λ1 represents the center reflection wavelength of the first DBR insulating layer.

[0016] The single-layer optical thickness of the second DBR insulating layer is 1 / 4λ2*sinθ2, where λ2 represents the center reflection wavelength of the second DBR insulating layer.

[0017] Preferably, both the first DBR insulating layer and the second DBR insulating layer are periodic structures consisting of alternating stacks of two materials with different refractive indices. The refractive index difference between the high-refractive-index material and the low-refractive-index material in the first DBR insulating layer is y, and the refractive index difference between the high-refractive-index material and the low-refractive-index material in the second DBR insulating layer is z. Therefore, y > z. Furthermore, the single-layer optical thickness of the first DBR insulating layer is smaller than that of the second DBR insulating layer.

[0018] Preferably, the percentage of the first opening in the first DBR insulating layer refers to the percentage of the total area of ​​the vertical projection of the first opening on the plane where the active region is located to the light-emitting area of ​​the epitaxial stack. If the percentage of the first opening in the first DBR insulating layer is S, then the value of S ranges from 15% to 40%, including the endpoint value.

[0019] Preferably, the contact interface between the first DBR insulating layer and the first metal reflector, and the contact interface between the first metal reflector and the second DBR insulating layer are both provided in a concave-convex interlocking configuration.

[0020] Preferably, the second DBR insulating layer has a first uneven structure on the side surface opposite to the first metal reflector, and the second electrode extends to a portion of the surface of the first uneven structure.

[0021] Preferably, a second metal reflector is provided on the first platform, and the first electrode is electrically connected to the first type of semiconductor layer through the second metal reflector.

[0022] Preferably, the epitaxial stack further includes a transparent conductive layer located on the second mesa, and each of the first openings exposes a portion of the surface of the transparent conductive layer.

[0023] Preferably, the first DBR insulating layer further has at least one second opening exposing a portion of the sidewall surface of the epitaxial stack and at least one second protrusion structure corresponding to it, and the second DBR insulating layer covers the second opening and the second protrusion structure.

[0024] Preferably, the second DBR insulating layer has a second uneven structure on the side surface opposite to the sidewall of the epitaxial stack, and the first electrode covers a portion of the surface of the second uneven structure.

[0025] This invention also provides a method for manufacturing a micro LED chip, comprising the following steps:

[0026] Step 1: Prepare an epitaxial stack, wherein the epitaxial stack comprises at least a first type semiconductor layer, an active region, and a second type semiconductor layer stacked sequentially;

[0027] Step 2: A composite reflection structure is formed on the surface of the epitaxial stack away from the light-emitting surface. The composite reflection structure reflects the light emitted from the active region at all angles. The composite reflection structure includes a first DBR insulating layer, a first metal mirror, and a second DBR insulating layer stacked sequentially along the direction away from the epitaxial stack. The first DBR insulating layer is used to reflect light at a first incident angle, and the second DBR insulating layer is used to reflect light at a second incident angle. The first incident angle is θ1, and the second incident angle is θ2, then θ1 < θ2, and the first DBR insulating layer and the second DBR insulating layer extend at least to the sidewall of the epitaxial stack.

[0028] Wherein, the first DBR insulating layer has at least one first opening exposing the surface of the epitaxial stack portion and at least one first protrusion structure corresponding to it; the first metal mirror covers the first opening and the first protrusion structure; the second DBR insulating layer covers the exposed surfaces of the first DBR insulating layer and the first metal mirror.

[0029] Step 3: Prepare the first electrode and the second electrode;

[0030] The first electrode is electrically connected to the first type of semiconductor layer; the second electrode is electrically connected to the second type of semiconductor layer, and the first electrode and the second electrode are disposed far apart from each other.

[0031] Preferably, the preparation of the epitaxial stack includes providing a substrate and growing the epitaxial stack on the substrate;

[0032] After step one and before step two: firstly, by etching the epitaxial stack, a cleavage is formed to expose the surface of the substrate portion, a first mesa is formed to expose a portion of the first type semiconductor layer, and a second mesa is formed to expose the second type semiconductor layer;

[0033] The composite reflective structure formed in step two covers the exposed surface of the epitaxial stack; the first opening exposes a portion of the surface of the second platform.

[0034] Before fabricating the first electrode and the second electrode, the second DBR insulating layer is first made to have a first electrode through hole that exposes the surface of the first mesa portion and a second electrode through hole that exposes the surface of the first metal mirror portion.

[0035] Both the first electrode and the second electrode are located on the side of the composite reflective structure away from the epitaxial stack. The first electrode fills the first electrode via and forms an electrical connection with the first type semiconductor layer, and the second electrode fills the second electrode via and forms an electrical connection with the second type semiconductor layer.

[0036] Preferably, forming the composite reflective structure specifically includes the following steps:

[0037] Step A01: Form a patterned first photoresist on the first and second mesa surfaces;

[0038] Step A02: Deposit a first DBR insulating layer on an epitaxial stack with a patterned first photoresist;

[0039] Step A03: Remove the first photoresist to form at least one first opening and at least one first protrusion structure corresponding to the first mesa portion surface, and expose the first mesa portion surface.

[0040] Step A04: Deposit a first metal reflector onto the first opening and the first protrusion structure;

[0041] Step A05: Form a patterned second photoresist on the exposed portion of the first platform and on a portion of the first metal mirror;

[0042] Step A06: Deposit a second DBR insulating layer on the exposed surfaces of the first DBR insulating layer, the first metal mirror, and the first platform.

[0043] Step A07: Remove the second photoresist to expose the surface of the first mesa portion to form a first electrode via, and expose the surface of the first metal mirror portion to form a second electrode via.

[0044] Preferably, step A01 further includes step B01, forming a patterned first photoresist on the sidewall of the epitaxial stack;

[0045] Step A03 further includes step B01, removing the first photoresist to form a second opening and a second protrusion structure;

[0046] The first DBR insulating layer has at least one second opening that exposes a portion of the sidewall surface of the epitaxial stack and at least one corresponding second protrusion structure, and the second DBR insulating layer covers the second opening and the second protrusion structure.

[0047] By employing the above technical solution, this application provides a micro LED chip and its fabrication method. A composite reflection structure is set on the surface of the epitaxial laminate facing away from the light-emitting surface, and reflects light emitted from the active region at all angles. The composite reflection structure includes a first DBR insulating layer, a first metal mirror, and a second DBR insulating layer. The first DBR insulating layer reflects light at a first incident angle, and the second DBR insulating layer reflects light at a second incident angle. The first incident angle is θ1, and the second incident angle is θ2, where θ1 < θ2, and the first DBR insulating layer and the second DBR insulating layer are in parallel. The layer extends at least to the sidewall of the epitaxial stack; wherein, the first DBR insulating layer has at least one first opening exposing a portion of the surface of the epitaxial stack and at least one corresponding first protrusion structure; a first metal mirror covers the first opening and the first protrusion structure; a second DBR insulating layer covers the exposed surfaces of the first DBR insulating layer and the first metal mirror; so that the first DBR insulating layer of the composite reflective structure can directly and efficiently reflect light rays (including normal and near-normal rays) emitted from the active region at a small first incident angle, and the first opening of the first DBR insulating layer is designed to reduce the angle of the first metal mirror. The reflection of light rays with smaller first incident angles is achieved by using the first opening in the first DBR insulating layer to reduce the reflection of light rays with smaller first incident angles at the geometric center of the LED chip, thereby reducing the normal light in the geometric center region of the LED chip. Meanwhile, the first metal reflector efficiently captures light rays with larger second incident angles that are directed towards the composite reflective structure (these rays penetrate the first DBR insulating layer) and reflects them to the light-emitting surface, thereby improving lateral light emission, increasing the emission angle, and preventing them from being absorbed by the semiconductor during long-path propagation. Because the first metal reflector has certain... With low transmittance, some light rays with a larger second incident angle are reflected back by the second DBR insulating layer after passing through the first metal reflector, and then pass through the first metal reflector again. This reflected light undergoes constructive interference with the first reflected light from the first metal reflector, increasing lateral light emission and achieving a large emission angle light pattern design. This significantly improves the reflectivity of the entire composite reflective structure. Lateral light that would normally be absorbed and lost is effectively captured and reflected by the composite reflective structure, and after directional optimization, is finally extracted from the light-emitting surface, increasing the lateral light intensity and thus improving the overall brightness and emission angle of the LED chip. The process is simple and convenient to manufacture, facilitating mass production. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0049] Figure 1 This is a schematic diagram of the structure of a micro LED chip provided in an embodiment of the present invention;

[0050] Figure 2 An optical transmission schematic diagram provided for an embodiment of the present invention;

[0051] Figure 3 The light distribution curve of the micro LED chip corresponding to the unopened first DBR insulating layer;

[0052] Figure 4 The light distribution curve of the micro LED chip corresponding to the first opening ratio S < 15% of the first DBR insulating layer;

[0053] Figure 5 The first opening ratio S of the first DBR insulating layer provided in the embodiments of the present invention is 15%-40%, including the light distribution curve of the micro LED chip corresponding to the endpoint value;

[0054] Figure 6 This is a schematic diagram of another micro LED chip provided in an embodiment of the present invention;

[0055] Figure 7 This is a schematic diagram of the structure of another micro LED chip provided in an embodiment of the present invention;

[0056] Figure 8 A flowchart illustrating a method for fabricating a micro LED chip according to an embodiment of the present invention;

[0057] Figures 9 to 12 for Figure 8 The process cross-sectional diagrams corresponding to each step of the manufacturing method shown;

[0058] Figure 13 A flowchart illustrating a method for fabricating a composite reflective structure according to an embodiment of the present invention;

[0059] Figures 14 to 19 for Figure 13 The process cross-sectional diagrams corresponding to each step of the manufacturing method shown are as follows.

[0060] Explanation of symbols in the diagram:

[0061] a1, First protruding structure; a2, Second protruding structure; b1, First concave-convex structure; b2, Second concave-convex structure; K1, First opening; K2, Second opening; L1, First reflected ray; L2, Second reflected ray; Q, Cutting path; R1, First incident ray; R2, Second incident ray; S, Percentage of the first opening in the first DBR insulating layer; T1, First mesa; T2, Second mesa; X, Normal; y, Refractive index difference between the high-refractive-index material and the low-refractive-index material in the first DBR insulating layer; z, Refractive index difference between the high-refractive-index material and the low-refractive-index material in the second DBR insulating layer; θ1, First incident angle; θ2, Second incident angle;

[0062] 1. Substrate; 2. First type semiconductor layer; 3. Second type semiconductor layer; 4. Active region; 5. Transparent conductive layer; 6. Composite reflective structure; 61. First DBR insulating layer; 62. Second DBR insulating layer; 81. First metal mirror; 82. Second metal mirror; 91. First electrode; 92. Second electrode; 031. First photoresist; 032. Second photoresist; 911. First electrode via; 921. Second electrode via. Detailed Implementation

[0063] To make the content of this invention clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0064] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0065] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0066] In view of this, the present application provides a micro LED chip, such as Figure 1 As shown, it includes:

[0067] The epitaxial stack includes at least a first type semiconductor layer 2, an active region 4 and a second type semiconductor layer 3 stacked sequentially.

[0068] The composite reflective structure 6 is disposed on the side surface of the epitaxial stack away from the light-emitting surface and reflects the light emitted from the active region 4 at all angles. The composite reflective structure 6 includes a first DBR insulating layer 61, a first metal mirror 81 and a second DBR insulating layer 62 stacked sequentially along the direction away from the epitaxial stack. The first DBR insulating layer 61 is used to reflect light at a first incident angle and the second DBR insulating layer 62 is used to reflect light at a second incident angle. The first incident angle is θ1 and the second incident angle is θ2, then θ1 < θ2, and the first DBR insulating layer 61 and the second DBR insulating layer 62 extend at least to the sidewall of the epitaxial stack.

[0069] The first DBR insulating layer 61 has at least one first opening K1 that exposes the surface of the epitaxial stack and at least one first protrusion a1 that is correspondingly provided thereto; the first metal mirror 81 covers the first opening K1 and the first protrusion a1; the second DBR insulating layer 62 covers the exposed surfaces of the first DBR insulating layer 61 and the first metal mirror 81.

[0070] The first electrode 91 is electrically connected to the first type semiconductor layer 2, and the second electrode 92 is electrically connected to the second type semiconductor layer 3, with the first electrode 91 and the second electrode 92 disposed far apart from each other.

[0071] It should be noted that in LEDs, the angle at which light is emitted from the active region in all directions is 0°-90°. The composite reflection structure 6 provided in this embodiment is disposed on the surface of the epitaxial stack facing away from the light-emitting surface, and reflects the light emitted from the active region 4 at all angles (0°-90°). The composite reflection structure 6 includes a first DBR insulating layer 61, a first metal reflector 81, and a second DBR insulating layer 62, forming a Fabry-Perot microcavity structure similar to "DBR-metal-DBR". The first DBR insulating layer 61 is used to reflect light at a first incident angle, and the second DBR insulating layer 62 is used to reflect light at a second incident angle. The first incident angle is θ1, and the second incident angle is θ2, then θ1 < θ2. That is, the first DBR insulating layer 61 reflects the light emitted from the active region 4 at a smaller first incident angle θ1, and the second DBR insulating layer 62 reflects the light emitted from the active region 4 at a larger second incident angle θ2. Figure 2As shown, the first incident angle θ1 refers to the angle between the first incident ray R1 emitted from the active region 4 and the normal X on the first DBR insulating layer 61; the first incident ray R1 undergoes high reflection on the first DBR insulating layer 61 to emit the first reflected ray L1; the second incident angle θ2 refers to the angle between the second incident ray R2 emitted from the active region 4 and the normal X on the first metal reflector 81 or the second DBR insulating layer 62; the second incident ray R2 undergoes high reflection on the first metal reflector 81 or the second DBR insulating layer 62 to emit the second reflected ray L2. Wherein, Figure 1 Taking multiple first openings K1 as an example, the first protrusion structure a1 of the first DBR insulating layer 61 is formed by the unopened area around the first opening K1, and the first opening K1 is arranged around the first protrusion structure a1.

[0072] Combination Figures 1 to 2 As shown, the first DBR insulating layer 61 of the composite reflective structure 6 can directly and efficiently reflect light rays (including normal and near-normal rays) emitted from the active region 4 at a small first incident angle θ1. The design of the first opening K1 in the first DBR insulating layer 61 reduces the reflection of the light rays at the small first incident angle θ1 by the first metal reflector 81. Specifically, the first opening K1 of the first DBR insulating layer 61 reduces the reflection of the light rays at the geometric center of the LED chip at a small first incident angle θ1, thus reducing the normal light in the geometric center region of the LED chip. Furthermore, the first metal reflector 81 efficiently captures light rays at a larger second incident angle θ2 that are directed towards the composite reflective structure 6 (these rays will penetrate the first DBR insulating layer 61), and reflects the larger second incident angle θ2 light rays to the light-emitting surface (epipolar stack). The side surface facing away from the composite reflective structure 6 is used to enhance lateral light emission and increase the emission angle, preventing absorption by the semiconductor during long-path propagation. Because the first metal reflector 81 has a certain low transmittance, some light rays with a larger second incident angle θ2 are reflected back by the second DBR insulating layer 62 after passing through the first metal reflector 81, and then pass through the first metal reflector 81 again. This reflected light undergoes constructive interference with the first reflected light from the first metal reflector 81, increasing lateral light emission and achieving a large emission angle light pattern design. This significantly improves the reflectivity of the entire composite reflective structure 6. Lateral light that would otherwise be absorbed and lost is effectively captured and reflected by the composite reflective structure 6, and after direction optimization, is finally extracted from the light-emitting surface, increasing the lateral light intensity and thus improving the overall brightness and emission angle of the LED chip. Here, normal light refers to incident light parallel to the normal X, i.e., light rays incident perpendicularly to the interface at an angle of 0°; the geometric center of the LED chip refers to the geometric symmetry center of the LED chip (light-emitting core area) in its physical structure.

[0073] It should also be noted that this embodiment does not limit the specific doping type of the first type semiconductor layer 2 and the second type semiconductor layer 3. The doping types of the first type semiconductor layer 2 and the second type semiconductor layer 3 are opposite. The first type semiconductor layer 2 can be a P-type semiconductor layer or an N-type semiconductor layer. The materials of the N-type semiconductor layer and the P-type semiconductor layer can be GaN.

[0074] In addition, in this embodiment Figure 1 The micro LED chip shown is a flip-chip structure. The composite reflective structure 6 can also be applied to other structures of micro LED chips, such as a conventional structure.

[0075] In an optional embodiment of this application, the reflectivity of the first metal mirror 81 is lower than that of the first DBR insulating layer 61.

[0076] In an optional embodiment of this application, the reflectivity of the first metal mirror 81 is lower than that of the second DBR insulating layer 62.

[0077] Continue to refer to Figure 1 As shown, a substrate 1 is disposed on one side of the light-emitting surface of the epitaxial stack, and the micro LED chip has a dicing Q that exposes a portion of the substrate surface facing the epitaxial stack. The composite reflective structure 6 covers the exposed surface of the epitaxial stack.

[0078] The epitaxial stack has a first mesa T1 exposing a portion of the first type semiconductor layer 2 and a second mesa T2 exposing a portion of the second type semiconductor layer 3 on the side opposite to the substrate 1. A first opening K1 exposes a portion of the surface of the second mesa T2. The second DBR insulating layer 62 has a first electrode via 911 (not shown in the figure) exposing a portion of the surface of the first mesa T1 and a second electrode via 921 (not shown in the figure) exposing a portion of the surface of the first metal mirror 81. Those skilled in the art will understand that the first DBR insulating layer also exposes a portion of the surface of the first mesa T1.

[0079] The first electrode 91 and the second electrode 92 are both located on the side of the composite reflective structure 6 away from the epitaxial stack. The first electrode 91 fills the first electrode through-hole 911 and forms an electrical connection with the first type semiconductor layer 2. The second electrode 92 fills the second electrode through-hole 921 and forms an electrical connection with the second type semiconductor layer 3. The first electrode 91 and the second electrode 92 are disposed far apart.

[0080] It should be noted that the growth substrate 1 provided in this embodiment can be a substrate made of materials such as sapphire, and this embodiment of the present invention does not impose specific limitations on it.

[0081] In addition, in this embodiment, the second electrode 92 can be electrically connected to the second type semiconductor layer 3 through the first metal reflector 81, and the LED chip device can be separated through the cutting channel Q. This can avoid the problem of incomplete coverage when the epitaxial stack is subsequently isolated and insulated, thus avoiding the impact on the reliability of the LED chip.

[0082] In this embodiment, the size and shape of the first opening K1 and the first protrusion structure a1 are not limited and can be determined according to specific circumstances. In an optional embodiment of this application, the first opening K1 can be a periodically arranged through-hole structure, through which the first metal reflector 81 can form an electrical connection with the second type semiconductor layer 3, thereby achieving uniform current diffusion. In an optional embodiment of this application, the cross-sectional area of ​​the first protrusion structure a1 gradually decreases along the direction away from the epitaxial stack; optionally, the first protrusion structure a1 can be a trapezoidal structure.

[0083] In an optional embodiment of this application, the angle between the sidewall of the dicing track Q and the substrate 1 is 30°-88°.

[0084] In an optional embodiment of this application, the first electrode 91 is insulated from the sidewalls of the epitaxial stack through the first DBR insulating layer 61 and the second DBR insulating layer 62.

[0085] In an optional embodiment of this application, θ1 includes 0°-50°, including the endpoint value; θ2 includes 45°-90°, including the endpoint value; the reflection bandwidth range of the first DBR insulating layer 61 and the second DBR insulating layer 62 is 400nm-800nm, including the endpoint value.

[0086] It should be noted that by setting θ1 to include 0°-50°, including the endpoint values; and θ2 to include 45°-90°, including the endpoint values, the first incident angle θ1 reflected by the first DBR insulating layer 61 covers 0°-50°, and the second incident angle θ2 reflected by the second DBR insulating layer 62 covers 45°-90°, so as to achieve high reflectivity across the entire angle from 0°-90°, and with an overlap angle of 45°-50°. When the reflectivity of the first DBR insulating layer 61 decreases near 50°, the second DBR insulating layer 62 starts to cover from 45°, so the boundary area can still be effectively handled.

[0087] It should also be noted that in this embodiment, the reflection bandwidth range of the first DBR insulating layer 61 and the second DBR insulating layer 62 is 400nm-800nm, that is, the first DBR insulating layer 61 and the second DBR insulating layer 62 may include wavelengths of 400nm-800nm ​​suitable for reflecting the wavelengths generated in the active region 4.

[0088] In an optional embodiment of this application, when θ1 is 0°, the single-layer optical thickness of the first DBR insulating layer 61 is 1 / 4λ1; when θ1 is not equal to 0°, the single-layer optical thickness of the first DBR insulating layer 61 is 1 / 4λ1*sinθ1, where λ1 represents the center reflection wavelength of the first DBR insulating layer 61.

[0089] The single-layer optical thickness of the second DBR insulating layer 62 is 1 / 4λ2*sinθ2, where λ2 represents the center reflection wavelength of the second DBR insulating layer 62.

[0090] In an optional embodiment of this application, both the first DBR insulating layer 61 and the second DBR insulating layer 62 are periodic structures of alternating stacks of two materials with different refractive indices. The refractive index difference between the high refractive index material and the low refractive index material of the first DBR insulating layer is y, and the refractive index difference between the high refractive index material and the low refractive index material of the second DBR insulating layer is z. Therefore, y > z. Furthermore, the single-layer optical thickness of the first DBR insulating layer 61 is smaller than the single-layer optical thickness of the second DBR insulating layer 62.

[0091] It should be noted that the refractive index difference between high-refractive-index materials and low-refractive-index materials refers to the comparison of the refractive indices of the materials. The first DBR insulating layer 61 requires a material combination with higher contrast. In this embodiment, the second DBR insulating layer 62 can use a material combination with lower contrast. In combination with setting the single-layer optical thickness of the first DBR insulating layer 61 to be smaller than the single-layer optical thickness of the second DBR insulating layer 62, the first DBR insulating layer 61 reflects light at the first incident angle θ1, and the second DBR insulating layer 62 reflects light at the second incident angle θ2.

[0092] It should also be noted that, in this embodiment, the number of cycles in which the first DBR insulating layer 61 and the second DBR insulating layer 62 are alternately stacked is not specifically limited, and can be set according to actual needs.

[0093] In one optional embodiment of this application, the high refractive index layer includes, but is not limited to, a Ti3O5 layer or a Ta2O5 layer, and the low refractive index layer includes, but is not limited to, a SiO2 layer or a MgF2 layer.

[0094] In an optional embodiment of this application, the first opening percentage of the first DBR insulating layer refers to the percentage of the total area of ​​the vertical projection of the first opening K1 onto the plane of the active region 4 to the total area of ​​the epitaxial stacked light-emitting layer. The first opening percentage of the first DBR insulating layer is S, and the value of S ranges from 15% to 40%, including endpoint values. This is to avoid the first metal reflector 81 being too small to reduce the reflection of the first incident angle θ1 light rays (including normal and near-normal rays), which would prevent the first metal reflector 81 from efficiently capturing the second incident angle θ2 light rays. Simultaneously, it avoids the first opening K1 being too large, which would prevent the first DBR insulating layer 61 from reflecting the first incident angle θ1 light rays emitted from the active region 4.

[0095] It should be noted that during the LED chip emission angle test, the inventors discovered that the absence of an opening in the first DBR insulating layer or an excessively small opening ratio (S) in the first DBR insulating layer resulted in a low emission angle, failing to meet the requirements of applications such as backlighting or direct-view displays that demand a large emission angle. The emission angle test is a controlled process using a goniometer and photometric probe to measure the luminous intensity of the light source at different spatial angles, plotting a luminous intensity distribution curve, and determining the full angle corresponding to when the luminous intensity drops to 50% of the maximum central luminous intensity.

[0096] like Figure 3 The image shows the light distribution curve of the micro-LED chip corresponding to the unopened first DBR insulating layer, with a emission angle not exceeding 135°; Figure 4 The image shows the light distribution curve of a micro-LED chip corresponding to a first opening ratio S < 15% in the first DBR insulating layer, with a light emission angle of 135°-145°; Figure 5 As shown, the first opening ratio S of the first DBR insulating layer provided in this embodiment of the invention is 15%-40%, including the light distribution curve of the micro-LED chip corresponding to the endpoint value, and its emission angle can be extended to 140°-170°. Combined with... Figures 3-5 As shown, as the brightness of the normal light at 0° decreases, the light distribution angle (light emission angle) corresponding to the position of the luminous intensity of the 1 / 2 micro LED chip gradually expands.

[0097] In an optional embodiment of this application, the contact interfaces between the first DBR insulating layer 61 and the first metal reflector 81, and between the first metal reflector 81 and the second DBR insulating layer 62, are both provided with an interlocking, textured surface. This increases the contact area, thereby improving the adhesion between the first DBR insulating layer 61 and the first metal reflector 81, and between the first metal reflector 81 and the second DBR insulating layer 62. This effectively resists displacement in the parallel direction between layers, enhances the interfacial bonding and stability of the composite reflective structure 6, prevents delamination of the composite reflective structure 6, and ultimately improves the reliability of the LED chip.

[0098] In an optional embodiment of this application, the surface of the second DBR insulating layer 62 facing away from the first metal reflector 81 has a first uneven structure b1, and the second electrode 92 extends to a portion of the surface of the first uneven structure b1. This can effectively increase the contact area between the second DBR insulating layer 62 and the second electrode 92, improve the thrust reliability of both, and avoid the risk of electrode detachment.

[0099] In an optional embodiment of this application, the first DBR insulating layer 61 and the second DBR insulating layer 62 further extend to the dicing channel Q to isolate and insulate the epitaxial stack, thereby ensuring the reliability of the LED chip.

[0100] In an optional embodiment of this application, the first metal reflector 81 includes, but is not limited to, one or more of the following: Cr layer, Ni layer, Al layer, Ag layer, Cu layer, TiW layer, Ti layer, Pt layer, and Au layer.

[0101] Preferably, in this embodiment, the first metal reflector 81 is an Al layer or an Ag layer.

[0102] In an optional embodiment of this application, the thickness of the first metal reflector 81 ranges from 1000A to 20000A, including the endpoint values.

[0103] In an optional embodiment of this application, the first electrode 91 and the second electrode 92 are both, but are not limited to, one or more of the following: Cr layer, Ni layer, Al layer, Ti layer, Pt layer, and Au layer.

[0104] Optionally, in this embodiment, both the first electrode 91 and the second electrode 92 are pad electrodes.

[0105] In an optional embodiment of this application, such as Figure 6 As shown, a second metal reflector 82 is provided on the first platform T1, and the first electrode 91 is electrically connected to the first type semiconductor layer 2 through the second metal reflector 82. The second metal reflector 82 can be used to reflect the light emitted from the active region 4 to the first electrode 91, and can also prevent the first electrode 91 from absorbing light.

[0106] In an optional embodiment of this application, reference continues to be made to... Figure 6 As shown, to enhance the current spreading effect, the epitaxial stack also includes a transparent conductive layer 5 located on the second mesa T2, and the first opening K1 exposes part of the surface of the transparent conductive layer 5. The second electrode 92 can form an electrical connection with the second type semiconductor layer 3 through the first metal reflector 81, the transparent conductive layer 5, and the second type semiconductor layer 3.

[0107] Optionally, in this embodiment, the thickness of the transparent conductive layer 5 ranges from 300A to 2000A, including the endpoint values.

[0108] In an optional embodiment of this application, such as Figure 7 As shown, the first DBR insulating layer 61 also has at least one second opening K2 that exposes a portion of the sidewall surface of the epitaxial stack and at least one second protrusion a2 corresponding to it, and the second DBR insulating layer 62 covers the second opening K2 and the second protrusion a2.

[0109] It should be noted that, in this embodiment, the first DBR insulating layer 61 further has at least one second opening K2 exposing a portion of the sidewall surface of the epitaxial stack and at least one corresponding second protrusion a2, and the second DBR insulating layer 62 covers the second opening K2 and the second protrusion a2, wherein, Figure 7 Taking multiple examples of second openings K2, the second protrusion structure a2 of the first DBR insulating layer 61 is formed by the unopened area surrounding the second opening K2, and the second opening K2 is arranged around the second protrusion structure a2. Specifically, the first DBR insulating layer 61 in the epitaxial stack sidewall region can directly and efficiently reflect light emitted from the active region 4 at a small first incident angle θ1 (including normal and near-normal light), while the second DBR insulating layer 62 in the epitaxial stack sidewall region can efficiently reflect light emitted from the active region 4 at a larger second incident angle θ2. The design of the second opening K2 and the second protrusion structure a2 scatters light, converting some of the vertical light into larger angle light, making it easier for the light confined within the cavity to refract out of the cavity, further improving the brightness and emission angle of the LED chip.

[0110] It should also be noted that the size and shape of the second opening K2 and the second protrusion structure a2 are not limited in this embodiment and can be determined according to specific circumstances. In an optional embodiment of this application, the second opening K2 can be a periodically arranged through-hole structure. In an optional embodiment of this application, the cross-sectional area of ​​the second protrusion structure a2 gradually decreases along the direction away from the epitaxial stack.

[0111] Optionally, in this embodiment, the second DBR insulating layer 62 has a second uneven structure b2 on the side surface facing away from the sidewall of the epitaxial stack, and the first electrode 91 covers a portion of the surface of the second uneven structure b2. This can effectively increase the contact area between the second DBR insulating layer 62 and the first electrode 91, improve the thrust reliability of both, and avoid the risk of electrode detachment.

[0112] In an optional embodiment of this application, the contact interface between the first DBR insulating layer 61 and the second DBR insulating layer 62 in the sidewall region of the epitaxial stack is provided in a recessed and convex interlocking manner. This increases the contact area, thereby improving the adhesion between the first DBR insulating layer 61 and the second DBR insulating layer 62 in the sidewall region of the epitaxial stack, enhancing the interfacial bonding and stability between the two, preventing delamination, and further improving the reliability of the LED chip.

[0113] This application provides a method for fabricating a micro LED chip, such as... Figure 8 As shown, the manufacturing method includes:

[0114] Step 1, such as Figure 9 As shown, an epitaxial stack is prepared, which includes at least a first type semiconductor layer 2, an active region 4 and a second type semiconductor layer 3 stacked sequentially.

[0115] Step Two, as follows Figure 11 As shown, a composite reflection structure 6 is formed on the surface of the epitaxial stack away from the light-emitting surface. The composite reflection structure 6 reflects the light emitted from the active region 4 at all angles. The composite reflection structure 6 includes a first DBR insulating layer 61, a first metal mirror 81 and a second DBR insulating layer 62 stacked sequentially along the direction away from the epitaxial stack. The first DBR insulating layer 61 is used to reflect light at a first incident angle and the second DBR insulating layer 62 is used to reflect light at a second incident angle. The first incident angle is θ1 and the second incident angle is θ2, then θ1 < θ2, and the first DBR insulating layer 61 and the second DBR insulating layer 62 extend at least to the sidewall of the epitaxial stack.

[0116] The first DBR insulating layer 61 has at least one first opening K1 that exposes the surface of the epitaxial stack and at least one first protrusion a1 that is correspondingly provided thereto; the first metal mirror 81 covers the first opening K1 and the first protrusion a1; the second DBR insulating layer 62 covers the exposed surfaces of the first DBR insulating layer 61 and the first metal mirror 81.

[0117] Step 3, Reference Figure 1 As shown, the first electrode 91 and the second electrode 92 are fabricated.

[0118] The first electrode 91 is electrically connected to the first type semiconductor layer 2, and the second electrode is electrically connected to the second type semiconductor layer 3, with the first electrode 91 and the second electrode 92 disposed far apart from each other.

[0119] It should be noted that the microLED chip fabricated using the method described in this embodiment is based on... Figures 1 to 2As shown, the first DBR insulating layer 61 of the composite reflective structure 6 can directly and efficiently reflect light rays (including normal and near-normal rays) emitted from the active region 4 at a small first incident angle θ1. The design of the first opening K1 in the first DBR insulating layer 61 reduces the reflection of the light rays at the small first incident angle θ1 by the first metal reflector 81. Specifically, the first opening K1 in the first DBR insulating layer 61 reduces the reflection of the light rays at the geometric center of the LED chip at a small first incident angle θ1, thus reducing the normal ray in the geometric center region of the LED chip. The first metal reflector 81 efficiently captures light rays at a larger second incident angle θ2 that are directed towards the composite reflective structure 6 (these rays penetrate the first DBR insulating layer 61) and reflects them to the light-emitting surface (the epitaxial layer is away from the composite reflective structure). The first metal reflector 81 has a certain low transmittance. Some light rays with a larger second incident angle θ2 will be reflected back by the second DBR insulating layer 62 after passing through the first metal reflector 81 and will pass through the first metal reflector 81 again. This part of the reflected light will have constructive interference with the first reflected light of the first metal reflector 81, increasing the side light emission and realizing a large light emission angle light pattern design. This will significantly improve the reflectivity of the entire composite reflective structure 6. The side light that would have been absorbed and lost will be effectively captured and reflected by the composite reflective structure 6 and finally extracted from the light emission surface after direction optimization, so as to increase the side light intensity and thus improve the overall brightness and light emission angle of the LED chip. The process is simple and convenient to manufacture and easy to mass-produce.

[0120] In an optional embodiment of this application, reference is made to Figure 9 As shown, a substrate 1 is provided, and an epitaxial stack is grown on the substrate 1;

[0121] like Figure 10 As shown, after step one and before step two: by etching the epitaxial stack, a cleavage Q is formed to expose a portion of the surface of the substrate 1, a first mesa T1 is formed to expose a portion of the first type semiconductor layer 2, and a second mesa T2 is formed to expose the second type semiconductor layer 3.

[0122] refer to Figure 11 As shown, the composite reflective structure 6 formed in step two covers the exposed surface of the epitaxial stack; the first opening K1 exposes part of the surface of the second mesa T2;

[0123] Before preparing the first electrode and the second electrode, the second DBR insulating layer 62 is first made to have a first electrode through hole 911 that exposes the surface of the first mesa T1 portion and a second electrode through hole 921 that exposes the surface of the first metal mirror 81 portion.

[0124] refer to Figure 1As shown, the first electrode 91 and the second electrode 92 are both located on the side of the composite reflective structure 6 away from the epitaxial stack. The first electrode 91 fills the first electrode through-hole 911 and forms an electrical connection with the first type semiconductor layer 2; the second electrode 92 fills the second electrode through-hole 921 and forms an electrical connection with the second type semiconductor layer 3, and the first electrode 91 and the second electrode 92 are disposed far apart.

[0125] Optionally, in this embodiment, dry etching processes such as inductively coupled plasma (ICP) can be used to etch the epitaxial stack.

[0126] It should be noted that the etching gas for the ICP etching process is not limited in this embodiment. Optionally, the etching gas for the ICP etching process is a mixture of Cl2, Ar and O2, with a gas ratio of Cl2:Ar:O2=5:1:2.

[0127] In an optional embodiment of this application, etching the epitaxial stack specifically includes the following steps:

[0128] S01, such as Figure 12 As shown, the epitaxial stack is formed by first photolithography etching to expose the first mesa T1 of the first type semiconductor layer 2 and the second mesa T2 of the second type semiconductor layer 3.

[0129] Specifically, the first region on the upper surface of the epitaxial stack is etched to form the first mesa T1 in the first region.

[0130] S02, Reference Figure 10 As shown, a second photolithography-based deep etching of the epitaxial stack is used to form a cleavage Q that exposes a portion of the surface of substrate 1;

[0131] Specifically, the second region on the upper surface of the epitaxial stack is etched to form a cutting path Q in the second region.

[0132] In another optional embodiment of this application, in step two, the epitaxial stack can be formed simultaneously by photolithography etching of the epitaxial stack, forming the first mesa T1, the second mesa T2, and the dicing channel Q.

[0133] In an optional embodiment of this application, a composite reflective structure 6 is formed, such as... Figure 13 As shown, the specific procedures include the following:

[0134] Step A01, as follows Figure 14 As shown, a patterned first photoresist 031 is formed on the first mesa T1 and the second mesa T2;

[0135] Step A02, as follows Figure 15 As shown, a first DBR insulating layer 61 is deposited on an epitaxial stack with a patterned first photoresist 031;

[0136] Step A03, as follows Figure 16 As shown, the first photoresist 031 is removed to form at least one first opening K1 and at least one first protrusion a1 corresponding to the first mesa T2 portion surface, and the first mesa T1 portion surface is exposed.

[0137] Step A04, as follows Figure 17 As shown, a first metal reflector 81 is deposited on the first opening K1 and the first protrusion structure a1;

[0138] Step A05, as follows Figure 18 As shown, a patterned second photoresist 032 is formed on the exposed portion of the first mesa T1 and on a portion of the first metal mirror 81;

[0139] Step A06, as follows Figure 19 As shown, a second DBR insulating layer 62 is deposited on the exposed surfaces of the first DBR insulating layer 61, the first metal reflector 81, and the first mesa T1.

[0140] Step A07, Reference Figure 11 As shown, the second photoresist 032 is removed, exposing the surface of the first mesa T1 portion to form a first electrode via 911, and exposing the surface of the first metal mirror 81 portion to form a second electrode via 921.

[0141] It should be noted that in this embodiment, a first DBR insulating layer 61 is formed by using a patterned first photoresist 031, and then the first photoresist 031 is removed to give the first DBR insulating layer 61 a first opening K1; a second DBR insulating layer 62 is formed by using a patterned second photoresist 032, and the second photoresist 032 is removed to obtain a first electrode via 911 and a second electrode via 921. This avoids the problems of high cost and long etching time caused by forming openings and vias through dry etching processes, and can effectively reduce costs and improve process efficiency.

[0142] Optionally, in this embodiment, the thickness of both the first photoresist 031 and the second photoresist 032 is greater than 4 μm.

[0143] Optionally, in this embodiment, ACE ultrasound is used to remove the first photoresist 031 and the second photoresist 032 by ultrasonic removal of the photoresist remover solution.

[0144] In an optional embodiment of this application, a high-temperature resistant negative photoresist can be used to form a patterned first photoresist 031 and a second photoresist 032, both of which have a structure that is wider at the top and narrower at the bottom.

[0145] It should be noted that in this embodiment, the process of forming patterned first photoresist 031 and second photoresist 032 using high-temperature resistant negative photoresist through homogenization, photolithography, development, and hardening exhibits an undercut phenomenon, resulting in both first photoresist 031 and second photoresist 032 having a structure that is wider at the top and narrower at the bottom. This allows for gaps between the first photoresist 031 and the first DBR insulating layer 61, and between the second photoresist 032 and the second DBR insulating layer 62, during subsequent deposition of the first DBR insulating layer 61 and the second DBR insulating layer 62. This facilitates the subsequent peeling of the first photoresist 031 and the second photoresist 032. The term "high-temperature resistant negative photoresist" indicates that even at high temperatures during DBR growth, the photoresist can maintain its shape without wrinkling, ensuring that the morphology of the first photoresist 031 and the second photoresist 032 remains unchanged.

[0146] In an optional embodiment of this application, both the first DBR insulating layer 61 and the second DBR insulating layer 62 are periodic structures consisting of alternating stacks of two materials with different refractive indices. The refractive index difference between the high-refractive-index material and the low-refractive-index material of the first DBR insulating layer 61 is y, and the refractive index difference between the high-refractive-index material and the low-refractive-index material of the second DBR insulating layer 62 is z. Therefore, y > z. Furthermore, the single-layer optical thickness of the first DBR insulating layer 61 is smaller than that of the second DBR insulating layer 62.

[0147] In one optional embodiment of this application, the high refractive index layer includes, but is not limited to, a Ti3O5 layer or a Ta2O5 layer, and the low refractive index layer includes, but is not limited to, a SiO2 layer or a MgF2 layer.

[0148] Optionally, in this embodiment, the first DBR insulating layer 61 may be formed by plasma-assisted deposition.

[0149] Optionally, in this embodiment, the following process conditions can be used when preparing the SiO2 layer: the ion source baffle is intermittently turned on for a duration of 2-5 seconds, including the endpoint; the oxygen flow rate is 10-40 sccm, including the endpoint; the ion source power is 400W-600W, including the endpoint; and the process vacuum is 1.0E. -4 Pa -1.0E -5 Pa, including endpoint values; coating temperature is 50℃-150℃, including endpoint values.

[0150] Furthermore, the following process conditions can be used when preparing the Ti3O5 layer: the ion source baffle is kept open, the oxygen gas flow rate is 40 sccm-60 sccm (inclusive); the ion source power range is 600W-1000W (inclusive); and the process vacuum is 2.0E. -2Pa-9.0E -2 Pa, including endpoint values; coating temperature is 50℃-150℃, including endpoint values.

[0151] Optionally, in this embodiment, after depositing each Ti3O5 layer by vapor deposition, oxygen ions are used to bombard the surface of each Ti3O5 layer to fully oxidize the Ti3O5 layer and reduce the film stress of the Ti3O5 layer. The O2 gas flow rate during oxygen ion bombardment of each Ti3O5 layer is 20-30 sccm, and the ion source power is 200-400 W. High / low refractive index DBR structures are prepared by controlling parameters such as ion energy, vacuum environment, and oxygen gas flow rate of the overlapping Ti3O5 / SiO2 layers.

[0152] In an optional embodiment of this application, the percentage of the first opening of the first DBR insulating layer refers to the percentage of the total area of ​​the vertical projection of the first opening K1 on the plane where the active region 4 is located to the luminous area of ​​the epitaxial stack. The percentage of the first opening of the first DBR insulating layer is S, and the value of S ranges from 15% to 40%, including the endpoint value.

[0153] It should be noted that in this embodiment, the total area ratio of the vertical projection of the first opening K1 on the plane of the active region 4 can be controlled by the patterned first photoresist 031, so as to avoid the first opening K1 being too small to reduce the reflection of the first incident angle θ1 light (including normal light and near normal light) by the first metal reflector 81, which would cause the first metal reflector 81 to be unable to efficiently capture the second incident angle θ2 light. At the same time, it is also to avoid the first opening K1 being too large, which would cause the first DBR insulating layer 61 to be unable to reflect the first incident angle θ1 light emitted by the active region 4.

[0154] In another optional embodiment of this application, reference is made to Figure 6 As shown, while forming the first metal reflector 81, a second metal reflector 82 is deposited on the exposed first platform T1. The first electrode 91 is electrically connected to the first type semiconductor layer 2 through the second metal reflector 82. The second metal reflector 82 can reflect light emitted from the active region 4 onto the first electrode 91 and also prevent the first electrode 91 from absorbing light.

[0155] In an optional embodiment of this application, in order to improve the current spreading effect, a transparent conductive layer 5 is first formed on the second platform T2 before forming the composite reflective structure 6, and the first opening K1 exposes part of the surface of the transparent conductive layer 5.

[0156] Optionally, in this embodiment, a transparent conductive layer 5 can be deposited using a magnetron sputtering process.

[0157] Optionally, in this embodiment, the radio frequency power of the transparent conductive layer 5 ranges from 200W to 400W, including the endpoint value, and the DC power of the transparent conductive layer 5 ranges from 50W to 100W, including the endpoint value.

[0158] Optionally, in this embodiment, after forming the transparent conductive layer 5, the transparent conductive layer 5 is alloyed by the RTA process to form a good ohmic contact with the second type semiconductor layer 3.

[0159] Specifically, the transparent conductive layer 5 is annealed in an O2 (oxygen) / N2 (nitrogen) atmosphere using an RTA (Rapid Thermal Annealing) process. The annealing temperature ranges from 500℃ to 650℃, including the endpoint values. The oxygen gas flow rate ranges from 2 sccm to 5 sccm, including the endpoint values. The nitrogen gas flow rate ranges from 1 LPM to 10 LPM, including the endpoint values.

[0160] In an optional embodiment of this application, the first electrode 91 and the second electrode 92 can be fabricated using a photolithographic mask.

[0161] In an optional embodiment of this application, step A01 further includes step B01, simultaneously forming a patterned first photoresist 031 on the sidewall of the epitaxial stack;

[0162] Step A03 also includes step B02, removing the first photoresist 031 to form the second opening K2 and the second protrusion structure a2;

[0163] refer to Figure 7 As shown, the first DBR insulating layer 61 has at least one second opening K2 that exposes a portion of the sidewall surface of the epitaxial stack and at least one second protrusion a2 corresponding to it, and the second DBR insulating layer 62 covers the second opening K2 and the second protrusion a2.

[0164] Those skilled in the art should understand that, in the disclosure of this invention, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.

[0165] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0166] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A micro LED chip, characterized in that, include: An epitaxial stack, wherein the epitaxial stack comprises at least a first type semiconductor layer, an active region, and a second type semiconductor layer stacked sequentially; A composite reflection structure is disposed on the side surface of the epitaxial stack opposite to the light-emitting surface, and reflects the light emitted from the active region at all angles. The composite reflection structure includes a first DBR insulating layer, a first metal mirror, and a second DBR insulating layer stacked sequentially along the direction opposite to the epitaxial stack. The first DBR insulating layer is used to reflect light at a first incident angle, and the second DBR insulating layer is used to reflect light at a second incident angle. The first incident angle is θ1, and the second incident angle is θ2, then θ1 < θ2, and the first DBR insulating layer and the second DBR insulating layer extend at least to the sidewall of the epitaxial stack. Wherein, the first DBR insulating layer has at least one first opening exposing the surface of the epitaxial stack portion and at least one first protrusion structure corresponding to it; the first metal mirror covers the first opening and the first protrusion structure; the second DBR insulating layer covers the exposed surfaces of the first DBR insulating layer and the first metal mirror. The first electrode is electrically connected to the first type of semiconductor layer, and the second electrode is electrically connected to the second type of semiconductor layer, with the first electrode and the second electrode disposed far apart from each other.

2. The micro LED chip according to claim 1, characterized in that: A substrate is disposed on one side of the light-emitting surface of the epitaxial stack, the micro LED chip has a dicing channel that exposes a portion of the surface of the substrate facing the epitaxial stack, and the composite reflective structure covers the exposed surface of the epitaxial stack. The epitaxial stack has a first mesa exposing a portion of the first type semiconductor layer and a second mesa exposing a portion of the second type semiconductor layer on the side opposite to the substrate. The first opening exposes a portion of the surface of the second mesa. The second DBR insulating layer has a first electrode via exposing a portion of the surface of the first mesa and a second electrode via exposing a portion of the surface of the first metal mirror. Both the first electrode and the second electrode are located on the side of the composite reflective structure away from the epitaxial stack. The first electrode fills the first electrode via and forms an electrical connection with the first type semiconductor layer, and the second electrode fills the second electrode via and forms an electrical connection with the second type semiconductor layer.

3. The micro LED chip according to claim 1 or 2, characterized in that: The θ1 includes 0°-50°, including the endpoint values; the θ2 includes 45°-90°, including the endpoint values; the reflection bandwidth range of both the first DBR insulating layer and the second DBR insulating layer is 400nm-800nm, including the endpoint values.

4. The micro LED chip according to claim 1 or 2, characterized in that: When θ1 is 0°, the single-layer optical thickness of the first DBR insulating layer is 1 / 4λ1; when θ1 is not equal to 0°, the single-layer optical thickness of the first DBR insulating layer is 1 / 4λ1*sinθ1, where λ1 represents the center reflection wavelength of the first DBR insulating layer. The single-layer optical thickness of the second DBR insulating layer is 1 / 4λ2*sinθ2, where λ2 represents the center reflection wavelength of the second DBR insulating layer.

5. The micro LED chip according to claim 1 or 2, characterized in that: Both the first DBR insulating layer and the second DBR insulating layer are periodic structures consisting of alternating stacks of two materials with different refractive indices. The refractive index difference between the high-refractive-index material and the low-refractive-index material in the first DBR insulating layer is y, and the refractive index difference between the high-refractive-index material and the low-refractive-index material in the second DBR insulating layer is z. Therefore, y > z. Furthermore, the single-layer optical thickness of the first DBR insulating layer is smaller than that of the second DBR insulating layer.

6. The micro LED chip according to claim 1 or 2, characterized in that: The percentage of the first opening in the first DBR insulating layer refers to the percentage of the total area of ​​the vertical projection of the first opening on the plane where the active region is located to the light-emitting area of ​​the epitaxial stack. The percentage of the first opening in the first DBR insulating layer is S, and the value of S ranges from 15% to 40%, including the endpoint value.

7. The micro LED chip according to claim 1 or 2, characterized in that: The contact interface between the first DBR insulating layer and the first metal reflector, and the contact interface between the first metal reflector and the second DBR insulating layer are both arranged in a concave-convex interlocking pattern.

8. The micro LED chip according to claim 2, characterized in that: The second DBR insulating layer has a first uneven structure on the side of its surface facing away from the first metal mirror, and the second electrode extends to a portion of the surface of the first uneven structure.

9. The micro LED chip according to claim 2, characterized in that: The first platform is provided with a second metal reflector, and the first electrode is electrically connected to the first type of semiconductor layer through the second metal reflector.

10. The micro LED chip according to claim 2, characterized in that: The epitaxial stack also includes a transparent conductive layer located on the second mesa, and each of the first openings exposes a portion of the surface of the transparent conductive layer.

11. The micro LED chip according to claim 1 or 2, characterized in that: The first DBR insulating layer further has at least one second opening that exposes a portion of the sidewall surface of the epitaxial stack and at least one second protrusion structure corresponding to it, and the second DBR insulating layer covers the second opening and the second protrusion structure.

12. The micro LED chip according to claim 11, characterized in that: The second DBR insulating layer has a second uneven structure on the side surface away from the sidewall of the epitaxial stack, and the first electrode covers a portion of the surface of the second uneven structure.

13. A method for fabricating a micro LED chip, characterized in that, include: Step 1: Prepare an epitaxial stack, wherein the epitaxial stack comprises at least a first type semiconductor layer, an active region, and a second type semiconductor layer stacked sequentially; Step 2: A composite reflection structure is formed on the surface of the epitaxial stack away from the light-emitting surface. The composite reflection structure reflects the light emitted from the active region at all angles. The composite reflection structure includes a first DBR insulating layer, a first metal mirror, and a second DBR insulating layer stacked sequentially along the direction away from the epitaxial stack. The first DBR insulating layer is used to reflect light at a first incident angle, and the second DBR insulating layer is used to reflect light at a second incident angle. The first incident angle is θ1, and the second incident angle is θ2, then θ1 < θ2, and the first DBR insulating layer and the second DBR insulating layer extend at least to the sidewall of the epitaxial stack. Wherein, the first DBR insulating layer has at least one first opening exposing the surface of the epitaxial stack portion and at least one first protrusion structure corresponding to it; the first metal mirror covers the first opening and the first protrusion structure; the second DBR insulating layer covers the exposed surfaces of the first DBR insulating layer and the first metal mirror. Step 3: Prepare the first electrode and the second electrode; The first electrode is electrically connected to the first type of semiconductor layer; the second electrode is electrically connected to the second type of semiconductor layer, and the first electrode and the second electrode are disposed far apart from each other.

14. The method for fabricating a micro LED chip according to claim 13, characterized in that: Fabricating an epitaxial stack includes providing a substrate and growing the epitaxial stack on the substrate; After step one and before step two: firstly, by etching the epitaxial stack, a cleavage is formed to expose the surface of the substrate portion, a first mesa is formed to expose a portion of the first type semiconductor layer, and a second mesa is formed to expose the second type semiconductor layer; The composite reflective structure formed in step two covers the exposed surface of the epitaxial stack; the first opening exposes a portion of the surface of the second platform. Before fabricating the first electrode and the second electrode, the second DBR insulating layer is first made to have a first electrode through hole that exposes the surface of the first mesa portion and a second electrode through hole that exposes the surface of the first metal mirror portion. Both the first electrode and the second electrode are located on the side of the composite reflective structure away from the epitaxial stack. The first electrode fills the first electrode via and forms an electrical connection with the first type semiconductor layer, and the second electrode fills the second electrode via and forms an electrical connection with the second type semiconductor layer.

15. The method for manufacturing a micro LED chip according to claim 14, characterized in that: The formation of the composite reflective structure specifically includes the following steps: Step A01: Form a patterned first photoresist on the first and second mesa surfaces; Step A02: Deposit a first DBR insulating layer on an epitaxial stack with a patterned first photoresist; Step A03: Remove the first photoresist to form at least one first opening and at least one first protrusion structure corresponding to the first mesa portion surface, and expose the first mesa portion surface. Step A04: Deposit a first metal reflector onto the first opening and the first protrusion structure; Step A05: Form a patterned second photoresist on the exposed portion of the first platform and on a portion of the first metal mirror; Step A06: Deposit a second DBR insulating layer on the exposed surfaces of the first DBR insulating layer, the first metal mirror, and the first platform. Step A07: Remove the second photoresist to expose the surface of the first mesa portion to form a first electrode via, and expose the surface of the first metal mirror portion to form a second electrode via.

16. The method for manufacturing a micro LED chip according to claim 15, characterized in that: Step A01 further includes step B01, forming a patterned first photoresist on the sidewall of the epitaxial stack; Step A03 further includes step B01, removing the first photoresist to form a second opening and a second protrusion structure; The first DBR insulating layer has at least one second opening that exposes a portion of the sidewall surface of the epitaxial stack and at least one corresponding second protrusion structure, and the second DBR insulating layer covers the second opening and the second protrusion structure.

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