Chip communication method for serial-to-parallel driving, chip and electronic equipment
By employing the I²C protocol and introducing an inverse code verification mechanism in the serial-to-parallel driver chip, the problems of excessive hardware resource consumption and insufficient flexibility in existing technologies are solved, achieving highly compatible and reliable communication, which is suitable for fields such as industrial control, automotive electronics, and smart homes.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SINOTECH MIXIC ELECTRONICS
- Filing Date
- 2026-03-09
- Publication Date
- 2026-05-19
AI Technical Summary
The communication protocols of existing serial-to-parallel driver chips are mostly custom protocols, which result in high hardware resource consumption, lack of flexibility and replaceability, and affect the resource allocation and control applications of microcontrollers.
Based on the I²C protocol, an inverse code verification mechanism is introduced. Through communication between the main controller and the serial-to-parallel driver chip, the inverse code verification of data bytes is realized, and the ACK/NACK signal is combined to ensure the reliability of data transmission.
It achieves high compatibility and low resource consumption, significantly improves communication reliability, can detect random bit errors during transmission, saves MCU resources, expands the adaptation range, and is suitable for industrial control, automotive electronics and smart home fields.
Smart Images
Figure CN122064628A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit communication technology, specifically to a chip communication method, chip, and electronic device for serial-to-parallel driving. Background Technology
[0002] A serial-to-parallel driver chip is an integrated circuit that converts serial input data into multiple parallel output signals. It is widely used in electronic devices that need to drive multiple loads but have limited GPIO pin resources on the main controller. Its typical application architecture is as follows: a serial-to-parallel driver chip connects to the preceding microcontroller via a few communication pins, receives serial commands, and then converts them into dozens or even hundreds of parallel control signals, thereby greatly saving the pin resources of the main MCU and simplifying the peripheral circuitry.
[0003] Currently, most serial-to-parallel converter chips on the market use communication protocols customized by each chip manufacturer. While these custom protocols achieve the desired functionality, they still present challenges for microcontrollers, such as excessive hardware resource consumption and a lack of flexibility. For example, the SPI communication used by the 74HC595 chip requires 3 or 4 communication lines, and the UART communication used by the CH432 chip, if occupying specific composite UART function GPIO pins of the microcontroller, will affect the allocation of microcontroller resources and control applications. Furthermore, different manufacturers, and even different models of chips from the same manufacturer, may use different communication protocols, resulting in a lack of flexibility and replaceability in system design. To address these issues, in-depth research is necessary. Summary of the Invention
[0004] This invention provides a chip communication method, chip, and electronic device for serial-to-parallel driving, which features high compatibility, low resource consumption, and low cost.
[0005] The basic solution provided by this invention is as follows:
[0006] A chip communication method for serial-to-parallel conversion driving, applied to a system including a master controller and a serial-to-parallel conversion driving chip as a slave device, characterized in that the method includes the following steps:
[0007] The main controller initiates the I²C communication start signal;
[0008] The master controller sends a first data byte, which includes the slave address and write operation flag of the serial-to-parallel driver chip;
[0009] After the serial-to-parallel driver chip correctly responds to the first data byte, the main controller sends at least one subsequent data byte.
[0010] Specifically, for at least one of the subsequent data bytes, the serial-to-parallel driver chip is configured to perform a verification step: determining whether the internal data bits of the currently received data byte satisfy a preset inverse code verification relationship; if the preset inverse code verification relationship is satisfied, the serial-to-parallel driver chip returns an ACK signal to the main controller; if the preset inverse code verification relationship is not satisfied, the serial-to-parallel driver chip does not return an ACK signal, keeping the data line SDA at a high level, i.e., returning a NACK signal.
[0011] This method is applied to systems containing a master controller (such as an MCU) and a serial-to-parallel converter chip as a slave device. It follows the physical layer and frame format of the I²C protocol but introduces a unique verification mechanism at the data content layer. The core steps include: the master controller initiates a standard I²C communication start condition (START). The master controller sends a first data byte containing a 7-bit slave address and a 1-bit write operation flag (typically 0). The serial-to-parallel converter chip returns an ACK signal after address matching. After correct addressing, the master controller begins sending one or more subsequent data bytes. A key improvement is that the serial-to-parallel converter chip is configured to perform an internal check on at least one received subsequent data byte. This check rule determines whether the internal data bits of the currently received data byte satisfy a preset one's complement check relationship.
[0012] Furthermore, the high four bits and low four bits of the data byte are inverses of each other. This is a simple and efficient verification method that provides stronger error detection capability (detecting all odd bit errors and most even bit errors) with a single-bit parity check without adding extra transmission bytes.
[0013] Furthermore, the subsequent data bytes include a second data byte and at least one third data byte; the second data byte is used to specify the target register address inside the serial-to-parallel driver chip; the at least one third data byte is used to write data into the target register.
[0014] Furthermore, the verification step is performed on at least the second data byte and / or the at least one third data byte.
[0015] Furthermore, after the main controller has sent all data bytes, it initiates an I²C communication stop signal to end the current communication.
[0016] Furthermore, it also includes a communication switching method, specifically comprising the following steps:
[0017] When at least the first data byte and the second data byte match the address and data of the preset mode selection in the data verification module, they are configured to select I²C communication and UART communication; when the data verification module receives a signal that the mode configuration is complete or an I²C communication stop signal, it completes the configuration of I²C communication or UART communication.
[0018] The second basic solution provided by this invention:
[0019] A serial-to-parallel driver chip, characterized in that it comprises:
[0020] The data line filtering and shaping module and the clock line filtering and shaping module are used to filter and shape the data line signals and clock line signals of the I²C bus, respectively.
[0021] The I²C slave interface circuit is connected to the data line filtering and shaping module and the clock line filtering and shaping module, and is used to receive and parse communication frames containing start signals, slave addresses, data bytes and stop signals;
[0022] A serial-to-parallel conversion module, connected to the I²C slave interface circuit, is used to convert received serial data into parallel data.
[0023] The slave control logic module includes:
[0024] The data verification module is used to perform inverse code verification on at least one data byte other than the address byte received by the I²C slave interface circuit;
[0025] The response control module controls the I²C slave interface circuit to generate a response signal based on the output result of the data verification module.
[0026] Specifically, when the data verification module determines that the received data byte satisfies the preset inverse code verification relationship, the acknowledgment control module controls the I²C slave interface circuit to generate an acknowledgment signal ACK; otherwise, it controls the I²C slave interface circuit not to generate an acknowledgment signal, so that the communication bus presents a non-acknowledgment signal NACK state.
[0027] Furthermore, the data verification module is specifically configured to: determine whether the high four bits of the data byte are inverses of the low four bits.
[0028] Furthermore, it also includes a UART interface circuit and a selection switch; the selection switch is configured to accept the trigger control of the data verification module, and when the data verification module obtains the address / data / switch configuration information that satisfies the mode selection, it is triggered to switch between UART communication serial to parallel output or I²C communication serial to parallel output.
[0029] The third basic solution provided by this invention:
[0030] An electronic device includes a main controller and the aforementioned serial-to-parallel driver chip. The main controller is connected to the serial-to-parallel driver chip via an I²C bus and communicates with it according to the aforementioned method.
[0031] The beneficial effects of this invention are as follows:
[0032] 1. High compatibility and low resource consumption: This invention is based on the I²C protocol, allowing the main controller to directly communicate using its built-in hardware I²C peripherals. Even in the absence of dedicated composite function pins, communication can be achieved through ordinary GPIO pins, expanding the microcontroller's adaptability and improving the flexibility of application scenarios. Furthermore, it eliminates the need for software timing simulation, significantly reducing MCU software overhead and CPU resources. Simultaneously, it requires only two lines, SDA and SCL, minimizing GPIO resource consumption.
[0033] 2. Significantly Improved Communication Reliability: By seamlessly embedding a one's complement verification mechanism into the standard protocol and binding the verification result to the core ACK / NACK acknowledgment mechanism, hardware-level validity confirmation is provided for every critical data transmission. The master controller can immediately determine whether the data has been reliably received by the slave device by detecting the ACK / NACK, achieving rapid error detection.
[0034] 3. Strong error detection capability: It adopts the check rule of "the high four bits and the low four bits are inverse codes of each other", which can effectively detect random bit errors that occur during transmission, including all single bit flip errors. Its error detection capability is better than simple parity check.
[0035] 4. Simple implementation and low cost: The verification logic (such as comparators or XOR gate combinations) can be implemented with very simple digital circuits inside the chip, which hardly increases the chip's manufacturing cost and power consumption, but brings a qualitative improvement in communication reliability.
[0036] 5. Flexible and convenient communication options: The same pin interface can switch between I²C and UART communication. For microcontrollers with spare UART interfaces but more GPIO interfaces, the microcontroller's proprietary communication interfaces TXD and RXD can be used to enhance the microcontroller's adaptability without occupying additional GPIO resources for switching or connection.
[0037] In summary, this invention ingeniously combines the universality of the standard I²C protocol with enhanced data verification, providing a communication solution for serial-to-parallel driver chips that is both easy to use and highly reliable. It is particularly suitable for fields with high requirements for communication reliability, such as industrial control, automotive electronics, and smart homes. Attached Figure Description
[0038] Figure 1 This is a typical application system block diagram of a serial-to-parallel driver chip in the existing technology;
[0039] Figure 2 This is a communication timing diagram for the standard I²C protocol (write operation).
[0040] Figure 3 This is a communication timing diagram of an embodiment of the present invention (performing inverse code verification on data bytes);
[0041] Figure 4 This is a schematic diagram of the internal structure of a serial-to-parallel driver chip according to an embodiment of the present invention.
[0042] Figure 5 This is a schematic diagram of the internal structure of a serial-to-parallel driver chip according to another embodiment of the present invention. Detailed Implementation
[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0044] Example 1:
[0045] Reference Figure 1 In a typical application system, the main controller acts as the master device and connects to the serial-to-parallel driver chip, which acts as the slave device, via the I²C bus (which includes SDA and SCL lines). The serial-to-parallel driver chip controls the state of its multiple parallel output pins (such as OUT0-OUTn) according to the received instructions to drive the subsequent load array (such as LEDs, relays, etc.).
[0046] This invention improves the communication behavior of serial-to-parallel driver chips. Figure 2 The standard I²C write operation timing is demonstrated: After the master device sends the start condition (S), it first sends a 7-bit slave address + a 1-bit write flag (0), and then waits for an ACK from the slave. Next, the master device can continuously send multiple data bytes (Data1, Data2, ...), each followed by an ACK generated by the slave. Finally, it ends with a stop condition (P). In the standard protocol, the slave unconditionally replies with an ACK for each data byte (unless there is an internal fault); the ACK only indicates that "the byte has been received," not that "the data content is correct."
[0047] Figure 3 The timing diagram of a preferred embodiment of the present invention is shown. It is related to... Figure 2 The key difference lies in the slave device's response behavior to data bytes. In this embodiment, we agree to perform a one's complement check on each data byte sent by the master device from the second to the subsequent bytes (i.e., all data bytes except the address byte). The specific check rule is: determine whether the high four bits (Bit7-Bit4) of a byte are equal to the bitwise inversion of the low four bits (Bit3-Bit0).
[0048] Suppose the master device needs to write the data 0xA5 to a register of the chip. In binary, this is 1010 0101. The lower four bits of the high four bits (1010, 0xA) are inverted to 0101 (0x5), which is exactly equal to the lower four bits of the byte (0101). Therefore, this data byte satisfies the one's complement check rule. If the check range includes the second data byte (address byte), the master device also needs to organize the address data according to the one's complement rule.
[0049] When chip 001 receives the byte and verifies it, it will pull the SDA line low in the corresponding ACK clock cycle and return an ACK signal (e.g., Figure 3 A after Data1.
[0050] Suppose that due to transmission interference, the data 0xA5 becomes 0xA4 (binary 1010 0100) on the SDA line. The high four bits 1010 inverted is 0101, which is not equal to the low four bits 0100. Therefore, this data byte does not satisfy the one's complement check rule.
[0051] At this time, the chip's acknowledgment (ACK) control module will not drive the SDA line low during the ACK clock cycle. Due to the pull-up resistor of the I²C bus, the SDA line will remain high. For the master device, it detects a NACK signal (e.g., ...). Figure 3 The dashed line indicates the possible response at the NACK position. After receiving a NACK, the master device can operate according to the preset error handling procedure (such as retransmitting data, recording error logs, entering a safe state, etc.), thereby avoiding the risk of subsequent parallel output status abnormalities due to erroneous data.
[0052] Example 2:
[0053] Reference Figure 4 This diagram illustrates an internal structure block diagram of a serial-to-parallel driver chip that implements the method of this invention. The chip includes:
[0054] The data line filtering and shaping module and the clock line filtering and shaping module are used to filter and shape the data line signals and clock line signals of the I²C bus, suppress bus noise and improve signal integrity;
[0055] The I²C slave interface circuit is connected to the aforementioned filtering and shaping module and is responsible for interacting with the physical bus, including start / stop condition detection, address matching, data shift register, clock synchronization, and generating ACK signals according to instructions.
[0056] A serial-to-parallel conversion module, connected to the I²C slave interface circuit, is used to convert received serial data into parallel data.
[0057] The slave control logic module includes a data verification module and a response control module;
[0058] The parallel output driver unit updates the status of the multiple parallel output pins according to the register contents after the data is successfully verified and written to the internal register.
[0059] Data verification module: Its input is connected to the internal data receive register of the I²C slave interface circuit. The verification module is triggered whenever the interface circuit receives a complete 8-bit data byte and is about to generate an acknowledgment. The verification module verifies the byte according to preset rules (such as comparing the high four bits with the low four bits inverse code) and outputs a "verification passed" or "verification failed" flag signal.
[0060] The acknowledgment control module receives the verification result flag from the data verification module and the original acknowledgment generation request from the I²C slave interface circuit. Internally, it contains a logic control unit. When it receives an acknowledgment request for an address byte, the control module allows the interface circuit to generate an ACK normally (provided the address matches). When it receives an acknowledgment request for a data byte, the control module checks the verification result: if the verification passes, it allows the interface circuit to generate an ACK; if the verification fails, it blocks the ACK generation logic of the interface circuit, causing the output driver of the interface circuit to remain in a high-impedance state during the ACK clock cycle, thereby generating a NACK on the bus.
[0061] Parallel output driver unit: After the data verification is passed and it is successfully written to the internal register, this unit updates the state of its multi-parallel output pins according to the register contents.
[0062] This embodiment provides a simple hardware implementation of a data verification module. The high four bits (D[7:4]) of the verification byte data are fed into a 4-bit inverter to obtain its inverse code ~D[7:4]. Simultaneously, the low four bits (D[3:0]) of the verification byte are directly output. The two inputs of a 4-bit comparator (such as 74HC85) are connected to ~D[7:4] and D[3:0] respectively. When the two are equal, the comparator outputs a high level, indicating "verification passed"; otherwise, it outputs a low level, indicating "verification failed". This signal can then be sent to the acknowledgment control module.
[0063] The SDA and SCL filtering and shaping modules include RC filter circuits and Schmitt triggers to suppress bus noise and improve signal integrity. The serial-to-parallel conversion module adopts a shift register structure and outputs a set of parallel signals to the slave control logic module after receiving 9 bits of data (8 bits of data + 1 bit of check trigger flag).
[0064] Example 3:
[0065] In another embodiment, to further improve communication reliability, the same one's complement check can be performed on the second byte (usually the register address byte) in the communication frame. That is, when the master device sends the address byte, it also needs to organize it into a form where the high four bits and low four bits are each other's complements (for example, to access address 0x23, the data byte sent should be 0x23, but it must be ensured that 0x2 is the one's complement of 0x3; otherwise, a mapping table or calculation method is needed to encode the actual address 0x23 into a form that satisfies the one's complement rule, such as 0xA5, before sending). After receiving the address byte, the chip first performs the one's complement check. If the check passes, it replies with ACK and prepares to receive subsequent data; if the check fails, it replies with NACK, allowing the master device to determine if there is an address transmission error. This method achieves end-to-end verification from addressing to data writing.
[0066] Example 4:
[0067] The verification rules of this invention are not limited to "the high four bits and the low four bits are each other's complements," and the verification can be applied to address bytes, data bytes, or combinations thereof, depending on the system configuration. In other embodiments, it can be defined as "the first half and the second half of the byte are each other's complements," or a more complex verification relationship can be used (such as dividing the byte into two 4-bit segments, but requiring them to satisfy a certain specific operational relationship, where the complement is just one of the simplest relationships). The core idea is to embed the verification logic into the data byte itself and use the standard I²C acknowledgment mechanism to provide feedback on the verification result. It should be noted that the working principles and beneficial effects of both are one-to-one, and therefore will not be elaborated further.
[0068] Example 5:
[0069] The difference between this embodiment and Embodiment 1 is that it also includes a communication switching method. In the communication switching mode, all bytes passing through the data verification module (including the mode selection address and subsequent configuration bytes) must satisfy a preset inverse code verification relationship. Specifically, it includes the following steps: when at least the first data byte and the second data byte match the preset mode selection address and data in the data verification module, they are configured to select between I²C communication and UART communication. When the data verification module receives a signal indicating that the mode configuration is complete or an I²C communication stop signal, it completes the configuration of I²C communication or UART communication.
[0070] Example 6:
[0071] Figure 5 A schematic diagram of the internal structure of a serial-to-parallel driver chip according to another embodiment of the present invention is shown. This chip... Figure 4 Based on the structure shown, a UART interface circuit and a selection switch are further included. The selection switch is configured to accept trigger control from the data verification module. When the data verification module obtains address / data / switch configuration information that satisfies the mode selection, it is triggered to switch between UART communication serial-to-parallel output and I²C communication serial-to-parallel output. For example, the preset data verification module includes the selection switch address 10100101. Therefore, only when the transmitted byte information passes the inverse code verification and matches the preset address, the data verification module triggers the selection switch and completes the configuration of the corresponding communication mode according to subsequent configuration information, such as 00001111 indicating I²C communication selection and 11110000 indicating UART communication selection. These configuration bytes also satisfy the inverse code verification rules to ensure the reliability of data transmission. There are no particular restrictions on whether the corresponding switch action terminals K1 and K2 of the selector switch K are between the first serial-to-parallel unit and the interface circuit for I²C communication, the second serial-to-parallel unit and the interface circuit for UART communication, or between the I²C slave interface circuit and the first serial-to-parallel unit, or the UART interface circuit and the second serial-to-parallel unit.
[0072] Example 7:
[0073] This embodiment proposes an electronic device, including a main controller and a serial-to-parallel driver chip as described above. The main controller is connected to the serial-to-parallel driver chip via an I²C bus and communicates with it according to the method described above.
[0074] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.
Claims
1. A chip communication method for serial-to-parallel conversion driving, applied to a system including a master controller and a serial-to-parallel conversion driving chip as a slave device, characterized in that, The method includes the following steps: The main controller initiates the I²C communication start signal; The master controller sends a first data byte, which includes the slave address and write operation flag of the serial-to-parallel driver chip; After the serial-to-parallel driver chip correctly responds to the first data byte, the main controller sends at least one subsequent data byte. Specifically, for at least one of the subsequent data bytes, the serial-to-parallel driver chip is configured to perform a verification step: determining whether the internal data bits of the currently received data byte satisfy a preset inverse code verification relationship; if the preset inverse code verification relationship is satisfied, the serial-to-parallel driver chip returns an ACK signal to the main controller; if the preset inverse code verification relationship is not satisfied, the serial-to-parallel driver chip does not return an ACK signal, keeping the data line SDA at a high level, i.e., returning a NACK signal.
2. The chip communication method for serial-to-parallel conversion driving as described in claim 1, characterized in that: The high four bits and low four bits of the data byte are inverses of each other.
3. A chip communication method for serial-to-parallel conversion driving as described in claim 1 or 2, characterized in that: The subsequent data bytes include a second data byte and at least one third data byte; the second data byte is used to specify the target register address inside the serial-to-parallel driver chip; the at least one third data byte is used to write data into the target register.
4. A chip communication method for serial-to-parallel driving as described in claim 3, characterized in that: The verification step is performed on at least the second data byte and / or the at least one third data byte.
5. A chip communication method for serial-to-parallel conversion driving as described in claim 1, characterized in that: After the main controller has sent all data bytes, it initiates an I²C communication stop signal to end the current communication.
6. A chip communication method for serial-to-parallel conversion driving as described in claim 3, characterized in that: It also includes a communication switching method, specifically comprising the following steps: When at least the first data byte and the second data byte match the address and data of the preset mode selection in the data verification module, they are configured to select I²C communication and UART communication; when the data verification module receives a signal that the mode configuration is complete or an I²C communication stop signal, it completes the configuration of I²C communication or UART communication.
7. A serial-to-parallel driver chip, characterized in that, include: The data line filtering and shaping module and the clock line filtering and shaping module are used to filter and shape the data line signals and clock line signals of the I²C bus, respectively. The I²C slave interface circuit is connected to the data line filtering and shaping module and the clock line filtering and shaping module, and is used to receive and parse communication frames containing start signals, slave addresses, data bytes and stop signals; A serial-to-parallel conversion module, connected to the I²C slave interface circuit, is used to convert received serial data into parallel data. The slave control logic module includes: The data verification module is used to perform inverse code verification on at least one data byte other than the address byte received by the I²C slave interface circuit; The response control module controls the I²C slave interface circuit to generate a response signal based on the output result of the data verification module. Specifically, when the data verification module determines that the received data byte satisfies the preset inverse code verification relationship, the acknowledgment control module controls the I²C slave interface circuit to generate an acknowledgment signal ACK; otherwise, it controls the I²C slave interface circuit not to generate an acknowledgment signal, so that the communication bus presents a non-acknowledgment signal NACK state.
8. The serial-to-parallel driver chip according to claim 7, characterized in that, The data verification module is specifically configured to: determine whether the high four bits of the data byte are inverses of the low four bits.
9. The serial-to-parallel driver chip according to claim 7 or 8, characterized in that, It also includes a UART interface circuit and a selection switch; the selection switch is configured to accept the trigger control of the data verification module, and when the data verification module obtains the address / data / switch configuration information that satisfies the mode selection, it is triggered to switch between UART communication serial to parallel output or I²C communication serial to parallel output.
10. An electronic device, characterized in that, It includes a main controller and a serial-to-parallel driver chip as described in any one of claims 7 to 9, wherein the main controller is connected to the serial-to-parallel driver chip via an I²C bus and communicates according to the method described in any one of claims 1 to 6.