Power semiconductor device junction temperature estimation method and device, electronic terminal and storage medium
By constructing and calibrating a thermal simulation model, and combining it with switching loss and conduction loss models, the problem of insufficient junction temperature estimation accuracy for power semiconductor devices in existing technologies has been solved, achieving higher accuracy junction temperature estimation and improving device performance and the thermal management efficiency of motor controllers.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIANGSU XCMG CONSTRUCTION MACHINERY RESEARCH INSTITUTE LTD
- Filing Date
- 2026-01-15
- Publication Date
- 2026-05-19
AI Technical Summary
Existing methods for estimating junction temperature of power semiconductor devices have insufficient accuracy. The thermistor parameter method has complex hardware design and large errors, while the thermal model method requires high modeling accuracy and is difficult to achieve high-precision estimation.
By adopting a method based on a pre-built thermal simulation model, combined with a parameter-calibrated switching loss and conduction loss model, and through K-coefficient calibration and transient thermal resistance testing, the thermal simulation model is corrected to improve accuracy, and a high-precision junction temperature estimation method is established.
It significantly improves the accuracy of junction temperature estimation for power semiconductor devices, ensuring that the estimated junction temperature is closer to the true value, thereby improving device performance and the thermal management efficiency of motor controllers.
Smart Images
Figure CN122065461A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method, apparatus, electronic terminal, and storage medium for estimating the junction temperature of power semiconductor devices, belonging to the field of junction temperature technology for power electronic devices. Background Technology
[0002] As a core component of motor controllers, the junction temperature of power semiconductors is closely related to their performance, lifespan, and reliability. Accurate estimation of power semiconductor junction temperature is of great significance for improving the performance utilization of power semiconductors, extending their service life, and enhancing the thermal management efficiency of motor controllers.
[0003] Currently, the main methods for estimating junction temperature in power semiconductors include the thermistor method and the thermal model method. The thermistor method estimates junction temperature based on the relationship between temperature and the on-state voltage drop of the power semiconductor. However, this method has complex hardware design, and the estimation results are easily affected by actual operating conditions, making it difficult to implement and resulting in large errors. The thermal model method estimates junction temperature by establishing the relationship between a thermal model and a loss model. It requires high accuracy in modeling both the loss model and the thermal model, but the hardware design is simple and easy to implement, making it the mainstream method for estimating junction temperature. However, its modeling process requires high accuracy in both the loss model and the thermal model, making it difficult to achieve high-precision estimation. Summary of the Invention
[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method, apparatus, electronic terminal and storage medium for estimating the junction temperature of power semiconductor devices, which can improve the accuracy of junction temperature estimation for power semiconductor devices.
[0005] To achieve the above objectives, the present invention is implemented using the following technical solution: In a first aspect, the present invention provides a method for estimating the junction temperature of a power semiconductor device, the method comprising: The junction-to-substrate total thermal resistance of the power semiconductor device is calculated based on a pre-built thermal simulation model. Based on the parameter-calibrated switching loss model and conduction loss model, the switching loss and conduction loss of the power semiconductor device are calculated and obtained respectively. The switching loss and the conduction loss are summed to calculate the total loss of the power semiconductor device. The junction temperature of the power semiconductor device is estimated by summing the products of the collected substrate temperature of the power semiconductor device, the total junction-to-substrate thermal resistance, and the total loss. The method for constructing the thermal simulation model includes: K-coefficient calibration of power semiconductor devices; Transient thermal resistance tests were performed on power semiconductor devices that had completed K-coefficient calibration under actual operating conditions to obtain the thermal resistance parameters of the power semiconductor devices. The thermal simulation model is constructed and corrected based on the thermal impedance parameters to obtain the constructed thermal simulation model.
[0006] Furthermore, the K-coefficient calibration of the power semiconductor device includes: Keeping the power semiconductor device in a conducting state, and under constant conducting current conditions, detecting the on-state voltage drop of the power semiconductor device at different junction temperatures; Based on the correlation data between different junction temperatures and corresponding on-state voltage drops, the on-state voltage drop at a preset reference junction temperature is selected as the reference on-state voltage drop. The ratio of the on-state voltage drop at each junction temperature to the reference on-state voltage drop is calculated to obtain the K coefficient at each junction temperature. Based on the mapping relationship between the K coefficient and the corresponding junction temperature, a K coefficient curve is generated by fitting, and the K coefficient calibration of the power semiconductor device is completed.
[0007] Furthermore, the method also includes pre-processing the power semiconductor device before calibrating the K coefficient of the power semiconductor device. The pre-processing includes removing the potting material of the power semiconductor device and applying black glue to the surface of the power semiconductor device.
[0008] Furthermore, transient thermal resistance tests are performed on the power semiconductor devices after K-coefficient calibration under actual operating conditions to obtain the thermal resistance parameters of the power semiconductor devices, including: For power semiconductor devices assembled under actual operating conditions, the power semiconductor device is controlled to remain in the on state, and a first on current is applied to the power semiconductor device within a set heating time to make the power semiconductor device continuously heat up. At the same time, the total loss and the measured junction temperature Tr of the power semiconductor device during the heating process are detected. In response to the end of the heating time, a second on-current is applied to the power semiconductor device to continuously cool the power semiconductor device, while the on-voltage drop of the power semiconductor device during the cooling process is detected; wherein, the second on-current is less than the first on-current; Based on the on-state voltage drop and the K coefficient curve during the cooling process of the power semiconductor device, the junction temperature decrease curve during the cooling process of the power semiconductor device is obtained by fitting. Based on the junction temperature change obtained from the junction temperature drop curve, and combined with the total loss during the heating process of the power semiconductor device, a correspondence between the junction temperature change and the total loss is established to determine the thermal impedance parameters of the power semiconductor device.
[0009] Furthermore, the method for correcting the thermal simulation model includes: Based on environmental parameters and coolant parameters flowing through the power semiconductor device that are the same as the actual operating conditions, the simulated junction temperature Ts output by the thermal simulation model is obtained; Using the measured junction temperature Tr as a reference, the thermal impedance parameters are corrected so that the error between the simulated junction temperature Ts and the measured junction temperature Tr does not exceed the set temperature difference threshold.
[0010] Furthermore, the parameter calibration method for the switching loss model includes: At different junction temperatures, double-pulse tests were performed on power semiconductor devices to obtain the switching loss test values corresponding to different bus voltages and different load currents. Based on the switching loss test values, a switching loss curve is obtained by fitting. Based on the switching loss curve and the preset switching loss calculation formula, the relevant parameters of the switching loss model are determined. Under the same bus voltage and load current, the temperature of the coolant flowing through the power semiconductor device is adjusted so that the junction temperature of the power semiconductor device is consistent at different carrier frequencies, and the actual switching loss of the power semiconductor device at different carrier frequencies is detected and obtained. Based on the measured value of the switching loss, and based on the deviation between the measured value of the switching loss and the test value of the switching loss, the relevant parameters of the switching loss model are calibrated to obtain the calibrated switching loss model.
[0011] Furthermore, the parameter calibration method for the conduction loss model includes: Extract relevant parameters from the power semiconductor device conduction loss model provided by the manufacturer under different ambient temperatures; Substitute the relevant parameters of the conduction loss model into the conduction loss calculation formula to calculate and obtain the conduction loss value; Under the same bus voltage and carrier frequency, the temperature of the coolant flowing through the power semiconductor device is adjusted so that the junction temperature of the power semiconductor device is consistent under different conduction currents, and the measured values of the conduction loss of the power semiconductor device under different conduction currents are obtained. Based on the measured conduction loss value, and taking into account the deviation between the calculated conduction loss value and the measured conduction loss value, the relevant parameters of the conduction loss model in the conduction loss calculation formula are calibrated to obtain the calibrated conduction loss model.
[0012] In a second aspect, the present invention provides a power semiconductor device junction temperature estimation apparatus, the apparatus comprising: First calculation module: used to calculate the junction-to-substrate total thermal resistance of power semiconductor devices based on a pre-built thermal simulation model; Query calibration module: Based on the parameter-calibrated switching loss model and conduction loss model, calculate and obtain the switching loss and conduction loss of the power semiconductor device respectively; The second calculation module is used to sum the switching loss and the conduction loss to calculate the total loss of the power semiconductor device. The third calculation module is used to sum the product of the collected substrate temperature of the power semiconductor device, the total thermal resistance from the junction to the substrate, and the total loss, thereby estimating the junction temperature of the power semiconductor device. The method for constructing the thermal simulation model includes: The power semiconductor device is calibrated using the K-coefficient; the calibrated power semiconductor device is then assembled in a simulation environment for transient thermal resistance testing to obtain the thermal impedance parameters of the power semiconductor device; the thermal simulation model is constructed and corrected based on the thermal impedance parameters to obtain the constructed thermal simulation model.
[0013] Thirdly, the present invention provides an electronic terminal including a processor and a memory connected to the processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the steps of the method as described in any of the first aspects are performed.
[0014] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of the first aspects.
[0015] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: In this application, the thermal impedance parameters of the thermal simulation model are obtained by applying actual operating conditions to the power semiconductor device with K-coefficient calibration and performing transient thermal resistance tests. This makes the total junction-to-substrate thermal resistance calculated by the corrected thermal simulation model closer to the true value and more accurate. At the same time, the switching loss model and conduction loss model used in this application are both calibrated with parameters, resulting in higher modeling accuracy. This allows for obtaining higher accuracy switching losses and conduction losses. Combined with the aforementioned high-precision thermal simulation model, the accuracy of junction temperature estimation for power semiconductor devices can be significantly improved. Attached Figure Description
[0016] Figure 1 This is a flowchart of a junction temperature estimation method for a power semiconductor device provided in one embodiment of this application; Figure 2 This is a flowchart of a method for constructing a thermal simulation model according to one embodiment of this application; Figure 3 This is a flowchart of a parameter calibration method for a switching loss model provided in one embodiment of this application; Figure 4 This is a flowchart of a parameter calibration method for a conduction loss model provided in one embodiment of this application. Detailed Implementation
[0017] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments and specific features in the embodiments are detailed descriptions of the technical solution of the present application, rather than limitations thereof. In the absence of conflict, the embodiments and technical features in the embodiments can be combined with each other.
[0018] Example 1
[0019] like Figure 1 The diagram shown is a flowchart of a method for estimating the junction temperature of a power semiconductor device provided in this embodiment, including the following steps: Step 1: Calculate the total junction-to-substrate thermal resistance of the power semiconductor device based on the pre-built thermal simulation model; Existing thermal simulation models are mostly based on ideal conditions and do not consider uneven heating caused by inconsistencies in power semiconductor devices and design layouts during actual operation. This results in discrepancies between the extracted thermal impedance parameters and their true values. Therefore, this embodiment provides a new method for constructing thermal simulation models. The thermal simulation model constructed using this method considers the impact of actual operating conditions on the thermal impedance parameters, resulting in higher accuracy. For details, see [link to details]. Figure 2 This is a flowchart of the method for constructing a thermal simulation model provided in this embodiment, including the following steps: Step S101: Perform K-coefficient calibration on the power semiconductor device; Step S102: Apply actual operating conditions to the power semiconductor device after K coefficient calibration and perform transient thermal resistance test to obtain the thermal resistance parameters of the power semiconductor device; Step S103: Construct and correct the thermal simulation model based on the thermal impedance parameters to obtain the constructed thermal simulation model.
[0020] Step 2: Based on the parameter-calibrated switching loss model and conduction loss model, calculate and obtain the switching loss and conduction loss of the power semiconductor device respectively; In the prior art, both the switching loss model and the conduction loss model adopt an open-loop modeling process, which lacks model calibration and correction processes, resulting in low modeling accuracy. In this embodiment, both the switching loss model and the conduction loss model are put into use after parameter calibration, resulting in higher model accuracy and thus enabling the acquisition of higher precision switching loss and conduction loss.
[0021] Step 3: Sum the switching loss and the conduction loss to calculate the total loss of the power semiconductor device; Step 4: Sum the products of the collected power semiconductor device substrate temperature, the total junction-to-substrate thermal resistance, and the total loss to estimate the junction temperature of the power semiconductor device.
[0022] In summary, the thermal impedance parameters of the thermal simulation model in this embodiment are obtained by applying actual operating conditions to the power semiconductor device with K-coefficient calibration and performing transient thermal resistance tests. This makes the junction-to-ambient temperature calculated and output by the corrected thermal simulation model closer to the true value and more accurate. At the same time, the switching loss model and conduction loss model used in this application have been calibrated with parameters, resulting in higher modeling accuracy. This allows for the acquisition of higher accuracy switching losses and conduction losses. Combined with the aforementioned high-precision junction-to-ambient temperature, the accuracy of junction temperature estimation for power semiconductor devices can be significantly improved.
[0023] As an embodiment of this application, step S101, which involves calibrating the K-coefficient of the power semiconductor device, specifically includes the following steps: Step S101-1: Keep the power semiconductor device in the on state, and under constant on current conditions, detect the on-state voltage drop of the power semiconductor device at different junction temperatures; The K coefficient is a parameter under the same conduction current. Changes in the conduction current will directly cause the K coefficient to be distorted. For example, the conduction voltage drop of an IGBT is affected by both junction temperature and collector current. Only when the current is constant is the relationship between the conduction voltage drop and the junction temperature unique.
[0024] As one embodiment, the power semiconductor device can be immersed in an oil bath to maintain its stability at the target junction temperature during testing. The temperature of the silicone oil in the oil bath can be set to 25°C, 50°C, 75°C, 100°C, 125°C, 150°C, or 175°C. Taking an IGBT as an example, when measuring the on-state voltage drop, the pre-treated IGBT can be connected to a T3STER transient thermal resistance tester. The IGBT's turn-on voltage Vge is set to 15V, and the on-state current Ice connected to the collector and emitter of the IGBT is constant and can be set to the level of hundreds of milliamperes; optionally, Ice = 200mA.
[0025] Step S101-2: Based on the correlation data between different junction temperatures and corresponding on-state voltage drops, select the on-state voltage drop at a preset reference junction temperature as the reference on-state voltage drop, calculate the ratio of the on-state voltage drop corresponding to each junction temperature to the reference on-state voltage drop, and obtain the K coefficient at each junction temperature. Step S101-3: Based on the mapping relationship between the K coefficient and the corresponding junction temperature, a K coefficient curve is generated by fitting, and the K coefficient calibration of the power semiconductor device is completed.
[0026] It should be noted that before calibrating the K-coefficient of a power semiconductor device, pretreatment is required to improve its thermal radiation performance. Taking a potted power semiconductor device as an example, the pretreatment may include: removing the silicone gel used for potting and applying black adhesive to the surface of the power semiconductor device. Blackening treatment can involve spraying black paint onto the surface of the power semiconductor device after removing the potting compound, thereby increasing the thermal emissivity of the power semiconductor device and improving the accuracy of subsequent thermal imaging tests.
[0027] As an embodiment of this application, in step S102, the power semiconductor device that has completed K coefficient calibration is subjected to actual operating conditions for transient thermal resistance testing to obtain the thermal resistance parameters of the power semiconductor device. This specifically includes the following steps: Step S102-1: For power semiconductor devices assembled under actual operating conditions, control the power semiconductor devices to remain in the on state, and apply a constant first on current to the power semiconductor devices within a set heating time so that the power semiconductor devices continue to heat up. At the same time, detect the total loss and the measured junction temperature Tr of the power semiconductor devices during the heating process. After the power semiconductor devices that have completed K-coefficient calibration are removed from the oil bath, cleaned, and dried, they are installed under actual operating conditions. Taking a motor controller as an example, the power semiconductor device can be installed on the water channel of the motor controller, and then connected to the T3STER transient thermal resistance testing equipment. The water channel is connected to a water tank, and coolant at a constant temperature and flow rate is introduced, ensuring there are no leaks in the water channel. The motor controller controls the power semiconductor device to remain on, and even if the gate and emitter of the IGBT are conducting, the first conduction current of the collector and emitter can be set to 200~600A to allow the power semiconductor device to heat up rapidly and continuously. During the heating process, a thermal imaging recorder can be used to record the measured junction temperature Tr of the power semiconductor device, and the T3STER transient thermal resistance testing equipment can be used to calculate the total loss of the power semiconductor device.
[0028] Step S102-2: In response to the end of the heating time, a constant second on-current is applied to the power semiconductor device to continuously cool the power semiconductor device, while the on-voltage drop of the power semiconductor device during the cooling process is detected; wherein, the second on-current is less than the first on-current; Because the junction temperature and on-state voltage drop of power semiconductor devices are linearly related under low current, and the linearity is optimal under low current, the error will increase under high current. Therefore, the second on-state current can be a small current of 200mA. As the on-state current of the power semiconductor device switches from 200~600A to a small current of 200mA, the junction temperature of the power semiconductor device will also decrease.
[0029] Step S102-3: Based on the on-state voltage drop during the cooling process of the power semiconductor device and the K coefficient curve, the junction temperature decrease curve during the cooling process of the power semiconductor device is obtained by fitting. Step S102-4: Based on the junction temperature change obtained from the junction temperature drop curve, and combined with the total loss during the heating process of the power semiconductor device, establish the correspondence between the junction temperature change and the total loss, and determine the thermal impedance parameters of the power semiconductor device.
[0030] The method for correcting the thermal simulation model described in step S103 may include: Step S103-1: Based on the environmental parameters and coolant parameters flowing through the power semiconductor device that are the same as the actual operating conditions, obtain the simulated junction temperature Ts output by the thermal simulation model; The so-called environmental parameters refer to the ambient temperature, while the coolant parameters include the coolant temperature and the coolant flow rate.
[0031] Step S103-2: Based on the measured junction temperature Tr, correct the thermal impedance parameters so that the error between the simulated junction temperature Ts and the measured junction temperature Tr does not exceed the set temperature difference threshold.
[0032] As one example, the temperature difference threshold can be set to 3°C.
[0033] like Figure 3 The diagram shown is a flowchart of the parameter calibration method for the switching loss model provided in this embodiment, which includes the following steps: Step S201: Perform double-pulse tests on the power semiconductor devices at different junction temperatures to obtain the switching loss test values corresponding to different bus voltages and different load currents. Before the double-pulse test, the power semiconductor device is first connected to the driver board, and then the double-pulse test is performed at 25℃, 150℃, and 175℃. 25℃ represents the junction temperature of the power semiconductor device as room temperature, 175℃ represents the maximum junction temperature of the power semiconductor device, and 150℃ represents the intermediate junction temperature. In order to keep the junction temperature stable during the test, the power semiconductor device can be immersed in the aforementioned oil bath.
[0034] Step S202: Based on the measured switching loss values, fit and obtain the switching loss curve; Specifically, the bus voltage can be kept constant, the load current can be adjusted to different levels, and the turn-on loss test value, turn-off loss test value, and reverse recovery loss can be collected for each level (whether reverse recovery loss is included depends on the device type and topology). The switching loss test value can be obtained by summing the turn-on loss test value, turn-off loss test value, and reverse recovery loss. Then, by keeping the load current constant and adjusting the bus voltage to different levels, the corresponding switching loss test value can be collected.
[0035] As one embodiment, based on the measured switching loss values, the least squares method can be used to fit the switching loss curves under different operating conditions.
[0036] Step S203: Based on the switching loss curve and the preset switching loss calculation formula, determine the relevant parameters of the switching loss model; Step S204: Under the same bus voltage and load current, adjust the temperature of the coolant flowing through the power semiconductor device to make the junction temperature of the power semiconductor device consistent at different carrier frequencies, and detect and obtain the measured value of the switching loss of the power semiconductor device at different carrier frequencies. In this embodiment, by adjusting the temperature of the coolant flowing through the power semiconductor device, the self-heating difference caused by the change of carrier frequency can be compensated, so that the junction temperature of the power semiconductor device remains constant under different carrier frequencies.
[0037] Step S205: Based on the measured value of the switching loss, and based on the deviation between the measured value of the switching loss and the test value of the switching loss, calibrate the relevant parameters of the switching loss model to obtain the calibrated switching loss model.
[0038] The parameters related to the switching loss model refer to the coefficients, exponents, or constants that need to be corrected in the expression of the switching loss model. Taking IGBT as an example, the parameters related to the switching loss model can be the inherent coefficients of IGBT turn-on and turn-off losses, the influence exponent of gate resistance, etc. If the switching loss model includes the reverse recovery loss of the anti-parallel diode, then the reverse recovery charge fitting coefficient is also a parameter related to the switching loss model.
[0039] See Figure 4 This is a flowchart of the parameter calibration method for the conduction loss model provided in this embodiment, including the following steps: Step 211: Extract relevant parameters from the power semiconductor device conduction loss model provided by the manufacturer under different ambient temperatures; Step 212: Substitute the relevant parameters of the conduction loss model into the conduction loss calculation formula to calculate and obtain the conduction loss value; Step 213: Under the same bus voltage and carrier frequency, adjust the temperature of the coolant flowing through the power semiconductor device to make the junction temperature of the power semiconductor device consistent under different conduction currents, and detect and obtain the measured values of the conduction loss of the power semiconductor device under different conduction currents. Step 214: Based on the measured conduction loss value, and based on the deviation between the calculated conduction loss value and the measured conduction loss value, calibrate the relevant parameters of the conduction loss model in the conduction loss calculation formula, thereby obtaining the calibrated conduction loss model.
[0040] The parameters related to the conduction loss model are the coefficients, exponents, or constants that need to be corrected in the expression of the conduction loss model. Taking IGBT as an example again, the parameters related to the conduction loss model can be the threshold voltage term of the collector-emitter on-state voltage drop, the collector-emitter on-state equivalent resistance Rce, and their corresponding temperature coefficients.
[0041] It should be noted that the measured losses in power analysis include bus capacitor losses, connecting copper busbar losses, and losses in the wiring from the power analyzer to the motor controller, and these losses are difficult to assess. However, the switching and conduction losses of power semiconductor devices are the main sources of motor controller losses. Therefore, when the estimated result of the loss model is 90%-95% of the measured losses of the power analyzer, the loss model can be considered accurate.
[0042] Example 2
[0043] This embodiment provides a power semiconductor device junction temperature estimation device, the device comprising: First calculation module: used to calculate the junction-to-substrate total thermal resistance of power semiconductor devices based on a pre-built thermal simulation model; Query calibration module: Based on the parameter-calibrated switching loss model and conduction loss model, calculate and obtain the switching loss and conduction loss of the power semiconductor device respectively; The second calculation module is used to sum the switching loss and the conduction loss to calculate the total loss of the power semiconductor device. The third calculation module is used to sum the product of the collected substrate temperature of the power semiconductor device, the total thermal resistance from the junction to the substrate, and the total loss, thereby estimating the junction temperature of the power semiconductor device. The method for constructing the thermal simulation model includes: The power semiconductor device is calibrated using the K-coefficient; the calibrated power semiconductor device is then assembled in a simulation environment for transient thermal resistance testing to obtain the thermal impedance parameters of the power semiconductor device; the thermal simulation model is constructed and corrected based on the thermal impedance parameters to obtain the constructed thermal simulation model.
[0044] The apparatus provided in this embodiment can be used to implement the method provided in Embodiment 1. For the specific implementation methods of each module function and the parameter calibration methods of the switching loss model and the conduction loss model, please refer to Embodiment 1, which will not be repeated here.
[0045] Example 3
[0046] This invention also provides an electronic terminal, including a processor and a memory connected to the processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the steps of the method described in Embodiment 1 are performed.
[0047] The electronic terminal provided in this embodiment of the invention can execute the method provided in Embodiment 1 of the invention, and has the corresponding functional modules and beneficial effects for executing the method.
[0048] Example 4
[0049] This invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the method described in Embodiment 1.
[0050] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0051] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0052] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0053] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0054] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A method for estimating the junction temperature of a power semiconductor device, characterized in that, The method includes: The junction-to-substrate total thermal resistance of the power semiconductor device is calculated based on a pre-built thermal simulation model. Based on the parameter-calibrated switching loss model and conduction loss model, the switching loss and conduction loss of the power semiconductor device are calculated and obtained respectively. The switching loss and the conduction loss are summed to calculate the total loss of the power semiconductor device. The junction temperature of the power semiconductor device is estimated by summing the products of the collected substrate temperature of the power semiconductor device, the total junction-to-substrate thermal resistance, and the total loss. The method for constructing the thermal simulation model includes: K-coefficient calibration of power semiconductor devices; Transient thermal resistance tests were performed on power semiconductor devices that had completed K-coefficient calibration under actual operating conditions to obtain the thermal resistance parameters of the power semiconductor devices. The thermal simulation model is constructed and corrected based on the thermal impedance parameters to obtain the constructed thermal simulation model.
2. The method for estimating the junction temperature of a power semiconductor device according to claim 1, characterized in that, The K-coefficient calibration of the power semiconductor device includes: Keeping the power semiconductor device in a conducting state, and under constant conducting current conditions, detecting the on-state voltage drop of the power semiconductor device at different junction temperatures; Based on the correlation data between different junction temperatures and corresponding on-state voltage drops, the on-state voltage drop at a preset reference junction temperature is selected as the reference on-state voltage drop. The ratio of the on-state voltage drop at each junction temperature to the reference on-state voltage drop is calculated to obtain the K coefficient at each junction temperature. Based on the mapping relationship between the K coefficient and the corresponding junction temperature, a K coefficient curve is generated by fitting, and the K coefficient calibration of the power semiconductor device is completed.
3. The method for estimating the junction temperature of a power semiconductor device according to claim 2, characterized in that, It also includes pre-processing the power semiconductor device before calibrating the K coefficient. The pre-processing includes removing the potting material of the power semiconductor device and applying black glue to the surface of the power semiconductor device.
4. The method for estimating the junction temperature of a power semiconductor device according to claim 2, characterized in that, Transient thermal resistance tests are performed on power semiconductor devices that have completed K-coefficient calibration under actual operating conditions to obtain the thermal resistance parameters of the power semiconductor devices, including: For power semiconductor devices assembled under actual operating conditions, the power semiconductor device is controlled to remain in the on state, and a first on current is applied to the power semiconductor device within a set heating time to make the power semiconductor device continuously heat up. At the same time, the total loss and the measured junction temperature Tr of the power semiconductor device during the heating process are detected. In response to the end of the heating time, a second on-current is applied to the power semiconductor device to continuously cool the power semiconductor device, while the on-voltage drop of the power semiconductor device during the cooling process is detected; wherein, the second on-current is less than the first on-current; Based on the on-state voltage drop and the K coefficient curve during the cooling process of the power semiconductor device, the junction temperature decrease curve during the cooling process of the power semiconductor device is obtained by fitting. Based on the junction temperature change obtained from the junction temperature drop curve, and combined with the total loss during the heating process of the power semiconductor device, a correspondence between the junction temperature change and the total loss is established to determine the thermal impedance parameters of the power semiconductor device.
5. The method for estimating the junction temperature of a power semiconductor device according to claim 4, characterized in that, The correction method for the thermal simulation model includes: Based on environmental parameters and coolant parameters flowing through the power semiconductor device that are the same as the actual operating conditions, the simulated junction temperature Ts output by the thermal simulation model is obtained; Using the measured junction temperature Tr as a reference, the thermal impedance parameters are corrected so that the error between the simulated junction temperature Ts and the measured junction temperature Tr does not exceed the set temperature difference threshold.
6. The method for estimating the junction temperature of a power semiconductor device according to claim 1, characterized in that, The parameter calibration method for the switching loss model includes: At different junction temperatures, double-pulse tests were performed on power semiconductor devices to obtain the switching loss test values corresponding to different bus voltages and different load currents. Based on the measured switching loss values, a switching loss curve is obtained by fitting. Based on the switching loss curve and the preset switching loss calculation formula, the relevant parameters of the switching loss model are determined. Under the same bus voltage and load current, the temperature of the coolant flowing through the power semiconductor device is adjusted so that the junction temperature of the power semiconductor device is consistent at different carrier frequencies, and the actual switching loss of the power semiconductor device at different carrier frequencies is detected and obtained. Based on the measured value of switching loss, and based on the deviation between the measured value of switching loss and the test value of switching loss, the relevant parameters of the switching loss model are calibrated to obtain the calibrated switching loss model.
7. The method for estimating the junction temperature of a power semiconductor device according to claim 1, characterized in that, The parameter calibration method for the conduction loss model includes: Extract relevant parameters from the power semiconductor device conduction loss model provided by the manufacturer under different ambient temperatures; Substitute the relevant parameters of the conduction loss model into the conduction loss calculation formula to calculate the conduction loss value; Under the same bus voltage and carrier frequency, the temperature of the coolant flowing through the power semiconductor device is adjusted so that the junction temperature of the power semiconductor device is consistent under different conduction currents, and the measured values of the conduction loss of the power semiconductor device under different conduction currents are obtained. Based on the measured conduction loss value, and taking into account the deviation between the calculated conduction loss value and the measured conduction loss value, the relevant parameters of the conduction loss model in the conduction loss calculation formula are calibrated to obtain the calibrated conduction loss model.
8. A device for estimating the junction temperature of a power semiconductor device, characterized in that, The device includes: First calculation module: used to calculate the junction-to-substrate total thermal resistance of power semiconductor devices based on a pre-built thermal simulation model; Query calibration module: Based on the parameter-calibrated switching loss model and conduction loss model, calculate and obtain the switching loss and conduction loss of the power semiconductor device respectively; The second calculation module is used to sum the switching loss and the conduction loss to calculate the total loss of the power semiconductor device. The third calculation module is used to sum the product of the collected power semiconductor device substrate temperature, the total junction-to-substrate thermal resistance, and the total loss, thereby estimating the junction temperature of the power semiconductor device. The method for constructing the thermal simulation model includes: The power semiconductor device is calibrated using the K-coefficient; the calibrated power semiconductor device is then assembled in a simulation environment for transient thermal resistance testing to obtain the thermal impedance parameters of the power semiconductor device; the thermal simulation model is then constructed and corrected based on the thermal impedance parameters to obtain the constructed thermal simulation model.
9. An electronic terminal, characterized in that, The method includes a processor and a memory connected to the processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the steps of the method as described in any one of claims 1 to 7 are performed.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the program implements the steps of the method according to any one of claims 1 to 7.