A pulse magnetizer

Abstract

The present application relates to the technical field of pulse power and electromagnetic manufacturing, and discloses a pulse magnetizing machine, which comprises a charging module, a capacitor matrix module, an acquisition module and a control module; the acquisition module synchronously acquires voltage and current discrete sequences at the discharge moment in a Kelvin four-wire structure; the control module is based on a heterogeneous architecture of a digital signal processor and a field programmable gate array, uses a regularized least square algorithm to identify equivalent resistance and inductance parameters of a load in real time, and adopts a closed-loop control logic based on single waveform reverse analysis as a system core; a Newton iteration method is used to solve nonlinear equations to reconstruct the capacitor matrix and accurately lock the pulse width; at the same time, the charging voltage is corrected by combining an iterative learning algorithm, the capacitor discrete quantization deviation is compensated, and the peak current is locked. The present application realizes adaptive compensation of the magnetizing waveform to load parameter drift, and significantly improves the current repetition accuracy and the operation life of the system.

Description

Technical Field

[0001] This invention relates to the field of pulse power and electromagnetic manufacturing technology, specifically to a pulse magnetizer. Background Technology

[0002] Pulse magnetization is a crucial step in the production of permanent magnet materials. Its core principle is to saturate the magnet by using the high-intensity magnetic field generated by the instantaneous release of energy stored in a capacitor. However, during continuous high-frequency production, the magnetization coil, acting as the load, is affected by the thermal effect of the large current pulse, causing its impedance characteristics to dynamically change. As the coil temperature rises, the equivalent resistance increases, and the electromagnetic stress-induced micro-deformation of the coil causes nonlinear fluctuations in the inductive reactance parameter. Existing magnetization equipment often relies on experience to use fixed capacitor combinations and preset voltages, making it difficult to perceive and compensate for these dynamically changing load parameters in real time. This results in uncontrollable deviations in the peak value and pulse width of the magnetization current, directly affecting the consistency of magnetic product performance.

[0003] The management logic and stray parameters of energy storage systems are also core factors limiting equipment performance. Traditional magnetizers generally lack monitoring strategies for the health status of individual capacitors in capacitor matrix scheduling. Power branches are in a state of disordered switching operation for a long time, which can easily lead to premature failure of some units due to heat accumulation or fatigue damage, reducing the mean time between failures (MTBF) of the entire system. In terms of physical layout, traditional cable or simple busbar connection methods introduce significant stray inductance due to spatial current path mismatch. This not only generates severe voltage spikes at the moment of switching action, threatening device safety, but also prevents the acquisition system from obtaining high-fidelity discharge waveforms, limiting the accuracy of subsequent control commands from the hardware source.

[0004] At the signal processing and closed-loop control levels, existing technologies typically lack the ability to perform real-time reverse analysis of microsecond-level pulse waveforms. Due to poor electromagnetic compatibility of the sampling link and the lack of efficient parameter identification algorithms, the system cannot adaptively correct the magnetization parameters for the next module based on the actual waveform data generated in the previous module. When faced with quantization errors caused by discrete capacitor adjustment, existing control logic struggles to achieve absolute locking of current peak values. This results in the output waveform repeatability failing to meet the stringent standards of high-precision magnetization processes when dealing with load characteristic drift and complex operating conditions, thus limiting the intelligence level of automated production lines. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a pulse magnetizer that solves the problem that traditional magnetizers struggle to detect load impedance drift and uneven power branch losses, resulting in limited waveform accuracy and premature device failure.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a pulse magnetizer, comprising a charging module, a capacitor matrix module, a data acquisition module, and a control module;

[0007] The charging module is connected to the capacitor matrix module; the capacitor matrix module contains multiple independent switched capacitor units connected in parallel.

[0008] The acquisition module is connected in series between the capacitor matrix module and the load to be magnetized, and is used to acquire the discrete voltage sequence and discrete current sequence generated by the load to be magnetized during the discharge process.

[0009] The control module is connected to the charging module, the capacitor matrix module, and the acquisition module;

[0010] The control module is used to calculate the circuit parameters of the load to be magnetized based on the voltage discrete sequence and the current discrete sequence.

[0011] The control module is also used to determine the target capacitance value of the capacitor matrix module and the target charging voltage value of the charging module according to the circuit parameters, and to generate switch combination instructions and voltage setting instructions.

[0012] Preferably, the capacitor matrix module is connected using low-inductance stacked busbars;

[0013] The low-inductance multilayer busbar includes a positive copper busbar, a negative copper busbar, and an insulating layer disposed between the positive copper busbar and the negative copper busbar;

[0014] The positive copper busbar and the negative copper busbar are parallel and overlapped, and are used to counteract the inductive reactance of the circuit by using the reverse magnetic field generated by the current.

[0015] Preferably, the acquisition module uses a Kelvin four-wire connection to the load to be magnetized;

[0016] The acquisition module includes a high-voltage divider and a coaxial sensorless shunt.

[0017] The high-voltage divider is used to measure the load voltage;

[0018] The coaxial inductive shunt is used to measure the load current.

[0019] Preferably, the control module adopts a heterogeneous architecture consisting of a digital signal processor and a field-programmable gate array;

[0020] The digital signal processor is used to run a parameter identification algorithm to calculate the circuit parameters;

[0021] The field-programmable gate array is used to control the operation of the independent switched capacitor unit according to the switch combination command.

[0022] Preferably, the control module calculates the circuit parameters using a least squares regression algorithm with regularization coefficients;

[0023] The circuit parameters include resistance parameters and inductance parameters;

[0024] The least squares regression algorithm solves the mapping relationship between the discrete voltage sequence, the discrete current sequence, and the circuit parameters through matrix operations.

[0025] Preferably, the control module determines the target capacitance value by solving the nonlinear transcendental equation using the Newton-Raphson iteration method;

[0026] The nonlinear transcendental equation is constructed based on the target current peak value, charging voltage, inductance parameters, resistance parameters, damped oscillation angular frequency, and the current peak time.

[0027] The control module uses the Newton-Raphson iteration method to numerically approximate the target capacitance value, so that the error between the theoretical peak current and the target peak current is less than a preset accuracy threshold.

[0028] Preferably, the control module generates the switch combination command using a selection strategy based on a comprehensive cost index;

[0029] The comprehensive cost index is calculated based on the temperature monitoring value, cumulative discharge count, and static cooling time of the independent switched capacitor unit.

[0030] The control module selects the independent switched capacitor units to be put into operation in ascending order of the comprehensive cost index.

[0031] Preferably, the control module generates the voltage setting command using a correction algorithm based on iterative learning control;

[0032] The correction algorithm updates the voltage correction amount based on the current deviation generated by the previous magnetization cycle, and superimposes the voltage correction amount on the voltage reference value, thereby compensating for the quantization deviation generated by capacitor reconstruction and locking the peak discharge current.

[0033] Preferably, the system includes a main unit cabinet, a control panel is provided on the outside of the main unit cabinet, a ventilation duct interface is fixedly connected to the top of the main unit cabinet, a magnetizing coil assembly is provided on the outside of the main unit cabinet, and a central magnetizing hole is provided inside the magnetizing coil assembly.

[0034] This invention provides a pulse magnetizer. It has the following beneficial effects:

[0035] 1. This invention captures the single discharge waveform in real time through the acquisition module and dynamically identifies the load impedance using the physical model built into the control module. This cycle-by-cycle closed-loop logic of sampling-identification-reconstruction can automatically compensate for parameter drift caused by load coil temperature rise, deformation, or aging, solving the drawbacks of traditional equipment with fixed parameters and difficulty in coping with load characteristic fluctuations, and ensuring the consistency of pulse width and peak current.

[0036] 2. This invention introduces a selection strategy based on a comprehensive cost index through a capacitor matrix module, enabling dynamic scheduling by combining the real-time temperature, cumulative discharge count, and cooling time of each capacitor unit. This mechanism achieves power loss amortization among physical units, preventing premature failure of local devices due to overheating or overuse. Combined with low-inductance multilayer busbar technology to suppress overvoltage spikes, it effectively extends the mean time between failures (MTBF) of the system under high-frequency pulse conditions.

[0037] 3. This invention employs a heterogeneous parallel architecture of a digital signal processor and a field-programmable gate array (FPGA) in its control module, coupled with a voltage correction algorithm based on iterative learning, to physically solve the mismatch between discrete capacitor adjustment and the continuous target current requirement. Through a composite control of model feedforward and historical error feedback, the system can automatically compensate for stray impedance and switching losses, achieving extremely high current peak repeatability even with limited capacitor configuration, meeting the requirements of high-precision magnetization processes. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the overall architecture of the adaptive pulse magnetization system of the present invention;

[0039] Figure 2 This is a detailed circuit architecture diagram of the capacitor matrix module of the present invention;

[0040] Figure 3 This is a schematic diagram of the physical topology and low-inductance interconnect of the capacitor matrix module of the present invention;

[0041] Figure 4 This is a schematic diagram of the circuit principle and signal link of the acquisition module of the present invention;

[0042] Figure 5 This is a schematic diagram of the hardware circuit architecture and data interaction link of the control module of the present invention;

[0043] Figure 6 This is a flowchart of the parameter identification logic based on waveform reverse analysis of the present invention.

[0044] Figure 7 This is a schematic diagram of the capacitor matrix reconstruction logic and lifetime equalization control principle of the present invention;

[0045] Figure 8 This is a schematic diagram of the peak current locking and charging voltage adaptive correction logic of the present invention;

[0046] Figure 9 This is a schematic diagram of the main unit cabinet of the present invention;

[0047] Figure 10 This is a diagram showing the evolution of the current waveform during the adaptive compensation process of the present invention;

[0048] Figure 11 This is the peak error convergence curve for 1000 consecutive magnetization cycles of the present invention.

[0049] The components include: 1. Main unit cabinet; 2. Control panel; 3. Ventilation duct interface; 4. Magnetizing coil assembly; 5. Central magnetizing hole; 100. Charging module; 200. Capacitor matrix module; 300. Acquisition module; 400. Control module. Detailed Implementation

[0050] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] See attached document Figure 1 The diagram shows the overall architecture of an adaptive pulse magnetization system according to an embodiment of the present invention. The present invention provides an adaptive pulse magnetization system, comprising: a charging module 100, a capacitor matrix module 200, a data acquisition module 300, and a control module 400.

[0052] The charging module 100 has its output terminal electrically connected to the input terminal of the capacitor matrix module 200. The charging module 100 is equipped with a voltage adjustment interface, which is communicatively connected to the control module 400. The charging module 100 receives a voltage setting command calculated by the control module 400 based on the impedance characteristics of the load to be charged, and adjusts the DC voltage at its output terminal to the target charging voltage value according to the voltage setting command, thereby adding energy to the capacitor matrix module 200.

[0053] The capacitor matrix module 200 consists of several independent switched capacitor units connected in parallel. The capacitor matrix module 200 is provided with a control signal input terminal, which is electrically connected to the control module 400. The capacitor matrix module 200 is used to receive the switching combination command generated by the control module 400 based on the inductive reactance characteristics of the load to be magnetized. The capacitor matrix module 200 changes the on / off state of each independent power switching device inside according to the switching combination command, thereby reconstructing the effective total capacitance value of the capacitor matrix module 200 connected to the main discharge circuit of the system.

[0054] The acquisition module 300 is connected in series between the capacitor matrix module 200 and the load to be magnetized. The acquisition module 300 includes a main discharge thyristor, a magnetization coil load interface, and a high-frequency signal acquisition unit. The high-frequency signal acquisition unit is configured with a Kelvin four-wire connection structure and is used to synchronously acquire the instantaneous voltage value applied to both ends of the load to be magnetized and the instantaneous current value flowing through the circuit of the load to be magnetized at the moment of discharge. The acquisition module 300 converts the instantaneous voltage value and the instantaneous current value into a discrete voltage sequence and a discrete current sequence, and sends the discrete voltage sequence and the discrete current sequence to the control module 400.

[0055] The control module 400, as the core of the system's operation and decision-making, adopts a field-programmable gate array or digital signal processor architecture. The control module 400 establishes bidirectional or unidirectional electrical signal connections with the charging module 100, the capacitor matrix module 200 and the acquisition module 300, respectively.

[0056] The core working logic of this system adopts a closed-loop feedback control mode based on a single discharge waveform. When the system performs the k-th magnetization operation, where the variable k is a positive integer, the control module 400 drives the acquisition module 300 to perform the discharge action and simultaneously receives the voltage discrete sequence and current discrete sequence generated by the acquisition module 300. The control module 400 uses the built-in circuit physical model algorithm to perform regression calculation on the voltage discrete sequence and current discrete sequence to calculate the equivalent resistance value and equivalent inductance value of the load to be magnetized under the k-th magnetization condition.

[0057] The control module 400 uses the calculated equivalent inductance value and the preset target pulse width to perform matching calculations to determine the target capacitance value required for the next module, and generates a corresponding switch combination command to send to the capacitor matrix module 200 to lock the discharge pulse width. At the same time, the control module 400 uses the calculated equivalent resistance value, equivalent inductance value, and reconstructed target capacitance value, combined with the preset target peak current, to perform energy balance calculations, and generates a corresponding voltage setting command to send to the charging module 100 to lock the discharge peak current.

[0058] Through data interaction and collaborative work among the charging module 100, capacitor matrix module 200, acquisition module 300, and control module 400, the system uses the waveform data generated during the kth magnetization to guide the parameter correction for the (k+1)th magnetization during continuous production, forming a cycle-by-cycle closed-loop control process of sampling-identification-reconstruction-execution.

[0059] Combined with appendix Figure 2 The diagram shows a detailed circuit architecture of the capacitor matrix module 200. In this embodiment, the capacitor matrix module 200 serves as the system's dynamic energy storage and regulation center. Its input terminal is connected in parallel with the DC output terminal of the charging module 100, and its output terminal is connected to the acquisition module 300 after being connected via a stacked busbar. From the perspective of energy flow, this module achieves real-time discrete modulation of the discharge circuit time constant through physical-level topology reconstruction.

[0060] The capacitor matrix module 200 consists of N independent switched capacitor units connected in parallel in the electrical topology, where N is a natural number greater than 1. Each independent switched capacitor unit serves as a controllable energy storage branch and is connected in parallel to the DC high-voltage bus. In order to ensure the effective implementation of the system regulation linearity and life balance strategy, in this embodiment, it is preferred that each independent switched capacitor unit has the same or a specific proportional nominal capacitance value.

[0061] The internal structure of a single independent switched capacitor unit includes: a pulse capacitor, a high-power semiconductor switching device, and a RC snubber circuit. The positive terminal of the pulse capacitor is connected to the positive bus of the capacitor matrix module 200, and the negative terminal is connected in series with the anode of the high-power semiconductor switching device. The cathode of the high-power semiconductor switching device is connected to the negative bus of the capacitor matrix module 200. Considering the instantaneous current change rate under pulse magnetization conditions (… With extremely high characteristics, high-power semiconductor switching devices specifically select high-voltage high-power thyristors or insulated-gate bipolar transistor modules. Their control terminals are gates or gates, which are connected to the control signal input terminals through fiber optic drive circuits or magnetic isolation drive circuits to achieve electrical isolation between the high-voltage main circuit and the low-voltage control circuit, preventing common-mode interference from causing false triggering.

[0062] A resistor-capacitor (RC) snubber circuit is connected in parallel between the anode and cathode of a high-power semiconductor switching device to absorb and dissipate the overvoltage energy induced by stray inductance during device turn-off or turn-on. In this embodiment, the parameters of the RC snubber circuit are designed according to the damping matching principle, and its resistance value is... The selection range is typically from 5Ω to 50Ω, capacitance value The selected range is 0.1μF to 2μF, with the specific value based on the stray inductance. With commutation capacitor Parasitic oscillation frequency Determine and ensure the damping ratio This suppresses voltage spikes to within 80% of the rated withstand voltage of the power device.

[0063] To complement the aforementioned high-frequency parameter identification algorithm and minimize system errors introduced by hardware, the physical connection structure of the capacitor matrix module 200 adopts low-inductance stacked busbar technology. The low-inductance stacked busbar includes a positive copper busbar, a negative copper busbar, and an insulating dielectric layer disposed between them. The positive and negative copper busbars are closely fitted and parallel to each other in geometric space, forming a flat transmission line structure. Based on the law of electromagnetic induction, when the system discharges, the discharge current flowing through the positive copper busbar is equal in magnitude and opposite in direction to the return current flowing through the negative copper busbar. The magnetic flux generated by the two currents cancels each other out in space, significantly reducing the equivalent series inductance of the circuit. According to actual measurements, this structure can limit the distributed inductance of the busbar to the nanohenry level, ensuring the purity of the voltage waveform obtained by the acquisition module 300.

[0064] At the control logic level, the capacitor matrix module 200 receives switching combination commands from the control module 400 through the control signal input terminal. These switching combination commands are a set of control vectors mapped one-to-one with the physical branches, corresponding to the control... In each independent switched capacitor unit, the on / off state of the high-power semiconductor switching device should be controlled. It should be noted that the on / off control is only performed in the non-discharge state, i.e., before the current crosses zero or before charging, in order to avoid arcing or damage to the device during load switching.

[0065] Based on the above hardware architecture, the effective total capacitance value of the capacitor matrix module 200 connected to the main discharge circuit is... The numerical relationship between the on / off state of each independent switched capacitor unit and the on / off state is expressed as follows:

[0066] ;

[0067] In the formula: This represents the total equivalent capacitance value after the reconstruction of the capacitor matrix module 200, in farads. This represents the total number of independent switched capacitor units, and its value determines the system's adjustment range and redundancy. This indicates the index number of the independent switched capacitor unit, with a value ranging from 1 to... ; Indicates the first The switching state coefficients of each independent switched capacitor unit belong to a binary set. When the control command enables the unit, The value is 1 if it is set to 1, otherwise the value is 0. Indicates the first The nominal capacitance value of the pulse capacitor inside each independent switched capacitor unit.

[0068] To prevent the total system capacitance from reaching zero under extreme control commands, which could lead to an open circuit in the LC circuit or voltage overshoot during charging, a minimum capacity constraint is set in the control logic, i.e., satisfying... By changing the sequence of switch state coefficients The combination of capacitor matrix module 200 enables it to... That is, the minimum unit capacitance is the minimum step resolution, in to The total capacitance value can be discretized within a certain range. This adjustment mechanism enables the system to physically change the inherent resonant frequency of the RLC discharge circuit at the hardware level, and achieve two degrees of freedom control of the discharge waveform in conjunction with voltage regulation.

[0069] See attached document Figure 3 , Figure 3 The diagram illustrates the physical topology and low-inductance interconnection of a capacitor matrix module 200 according to an embodiment of the present invention. In this embodiment, the capacitor matrix module 200 serves as the core entity in the system for performing pulse width modulation and energy release, and its physical architecture is based on an array arrangement of modular high-frequency power units.

[0070] The capacitor matrix module 200 is topologically composed of multiple independently connected switched capacitor units in parallel. Each independently connected switched capacitor unit is physically packaged as an independent module, containing an energy storage element, a power semiconductor switching device, and a transient suppression circuit. Specifically, the energy storage element is a high-energy-density metallized thin-film pulse capacitor, which has self-healing properties and a low dielectric loss tangent. To ensure the system's lifespan under frequent charge and discharge conditions, the rated voltage of the energy storage element is set to 1.2 to 1.5 times the system's highest operating voltage. Power semiconductor switching devices are connected in series in the discharge path of the energy storage element. Specifically, they are high-voltage high-power thyristors or insulated-gate bipolar transistor (IGBT) assemblies. The selection of power semiconductor switching devices is determined based on the system's rated discharge current peak value, with at least a current safety margin of 2 times to prevent thermal breakdown during a single discharge.

[0071] To address the voltage stress problem generated during the rapid turn-on and turn-off processes of high-voltage, high-power switching devices, each independent switched capacitor unit is equipped with a local RC snubber circuit. This circuit is connected in parallel between the anode and cathode of the power semiconductor switching device and consists of a non-inductive snubber resistor and a high-voltage snubber capacitor connected in series. The non-inductive snubber resistor is a solid ceramic resistor or a non-inductive wire-wound resistor to eliminate its own parasitic inductance. The high-voltage snubber capacitor is a polypropylene film capacitor. In this embodiment, the parameter design of the RC snubber circuit follows the impedance matching principle, with the resistor value ranging from 5Ω to 50Ω and the capacitor value ranging from 0.1μF to 1.0μF. This aims to match the oscillation frequency formed by the stray inductance and parasitic capacitance of the circuit, providing a damping channel to clamp the voltage spikes generated by the switching transients within the rated withstand voltage range of the power semiconductor switching device.

[0072] In terms of interconnection technology, the capacitor matrix module 200 adopts low-inductance stacked busbar technology to replace the traditional cable connection method. The low-inductance stacked busbar consists of a positive conductive layer, a negative conductive layer, and an insulating dielectric layer between them, forming a compact stacked composite structure. Both the positive and negative conductive layers are made of wide copper plates, maintaining a large area of ​​parallel overlap in geometric space. The insulating dielectric layer is made of polyimide film or epoxy glass cloth laminate, and its thickness is determined according to the dielectric withstand voltage strength of the dielectric, which is usually greater than 20kV / mm, and is generally controlled between 0.2mm and 1mm. Under the premise of ensuring electrical insulation strength, the physical distance between the positive and negative conductive layers is minimized as much as possible.

[0073] From the perspective of electromagnetic field distribution, when the capacitor matrix module 200 performs a discharge operation, the discharge current flows out from the positive conductive layer, passes through the load, and then the return current flows back from the negative conductive layer. Because the positive and negative conductive layers are tightly bonded, the currents flowing through the two copper busbars are equal in magnitude and opposite in direction. The magnetic field vectors generated by these two reverse currents in the space around the busbar cancel each other out, thereby significantly reducing the equivalent series inductance of the transmission line.

[0074] The equivalent inductance characteristics of low-inductance multilayer busbars are described by the following physical relationship:

[0075] ;

[0076] In the formula: The equivalent loop inductance of the stacked busbar is expressed in Henry (H). This represents the self-inductance of a single-layer conductor; This indicates the mutual inductance between the positive and negative conductors; Represents the vacuum permeability, with values ​​ranging from 1 to 10. ; Indicates the physical length of the busbar; This indicates the thickness of the insulating layer between the positive and negative conductive layers. Indicates the width of the busbar conductive layer; This represents the geometric correction factor that takes into account edge effects and skin effects. This factor is usually determined by finite element electromagnetic simulation. Under the conventional geometric dimensions of this embodiment, its value ranges from 0.95 to 1.05.

[0077] Based on the above relationship, it can be seen that by increasing the width of the busbar conductive layer... And reduce the thickness of the insulation layer This maximizes mutual inductance to offset self-inductance, reducing the stray inductance of the system to the Nahen level. This low inductance characteristic ensures that the waveform acquired by the voltage sensor truly reflects the characteristics of the load end, avoiding measurement errors caused by voltage division due to line inductance, and providing a high-fidelity data foundation for subsequent parameter identification algorithms.

[0078] In terms of control signal transmission, the capacitor matrix module 200 is equipped with a fiber optic trigger interface board. The fiber optic trigger interface board converts the electrical signals from the control module 400 into optical pulse signals, which are then transmitted via optical fiber to the drive circuit of each independent switched capacitor unit. After receiving the optical signals, the drive circuit converts them back into electrical drive signals and amplifies them to drive the power semiconductor switching devices to conduct. The fiber optic transmission method utilizes the insulating properties of light to physically cut off the path of electromagnetic interference conducted from the high-voltage discharge circuit to the low-voltage control circuit, preventing the ground potential rebound at the moment of discharge from interfering with the logic operation of the control system.

[0079] The capacitor matrix module 200 can dynamically combine the number of capacitor units connected to the system based on the received binary encoded instructions. The calculation of the total effective capacitance of the system follows the following discrete summation logic:

[0080] ;

[0081] In the formula: This represents the total capacitance value connected to the discharge circuit after reconstruction; This indicates the total number of independent switched capacitor units contained in the capacitor matrix module 200; Indicates the sequence index of an independent switched capacitor unit; Indicates the first The switching state variable of each independent switched capacitor unit is obtained by parsing the instruction frame issued by the control module 400. The value is 1 when the unit is selected, and 0 otherwise. Indicates the first The nominal capacitance value of each independent switched capacitor unit.

[0082] This array-type topology not only enables dynamic adjustment of the capacitance value but also implicitly includes a redundancy and fault-tolerance mechanism. When the system detects a fault in an independent switched capacitor unit, such as capacitor breakdown or switch damage, the control module 400 can logically adjust the corresponding switch state variable. By forcibly setting the value to 0, the remaining healthy cells can continue to complete the subsequent magnetization task, thereby improving the reliability and online maintainability of the entire system.

[0083] See attached document Figure 4 , Figure 4 The circuit principle and signal link diagram of the acquisition module 300 according to an embodiment of the present invention are shown. In this embodiment, the acquisition module 300 is connected in series between the capacitor matrix module 200 and the load to be magnetized, serving as the physical interface between the high-voltage power circuit and the low-voltage control circuit. Its main functions are to perform on / off control of the main discharge circuit and high-fidelity digital conversion of the discharge waveform.

[0084] The acquisition module 300 mainly includes a main discharge switch assembly in the power path. The main discharge switch assembly is connected in series between the positive output terminal of the capacitor matrix module 200 and the input terminal of the load to be magnetized. In this embodiment, the main discharge switch assembly uses a high-voltage, high-power thyristor stack. Its off-state repetitive peak voltage is selected to be 1.5 to 2.0 times the highest operating voltage of the system, and its surge current is selected to be 3 to 5 times the maximum expected discharge current. In addition, it is equipped with a static voltage equalizing resistor and a dynamic voltage equalizing capacitor to adapt to the high voltage level of the capacitor matrix module 200. The gate of the main discharge switch assembly is connected to the isolation drive unit to receive trigger pulses from the control module 400. In the non-discharge state, the main discharge switch assembly is in the off state, isolating the high voltage of the energy storage capacitor. At the discharge moment, it receives the trigger signal and turns on, forming an instantaneous high-current discharge path.

[0085] To minimize the impact of line impedance on measurement accuracy, the acquisition module 300 integrates a high-frequency signal acquisition unit and uses a Kelvin four-wire connection structure to physically connect to the load to be magnetized. The Kelvin four-wire connection structure includes a pair of power current transmission cables and a pair of independent voltage sensing cables. The power current transmission cables are used to carry the kiloampere-level discharge current of the main circuit, while the voltage sensing cables are directly connected to the root of the terminals of the load to be magnetized. Since the current flowing through the voltage sensing cables is extremely small, the voltage drop on its line can be ignored. This connection method physically eliminates the interference of the power cable contact resistance and the impedance of the transmission wires themselves on the voltage measurement signal, ensuring that the acquired voltage signal truly reflects the potential difference across the load, rather than the line voltage drop.

[0086] In the voltage detection branch, the voltage sensing cable is connected to a wideband high-voltage divider. The wideband high-voltage divider adopts a hybrid RC voltage divider topology, which is composed of multiple non-inductive precision resistors and high-voltage ceramic capacitors connected in parallel and then in series. The parallel capacitors are used to compensate for the high-frequency spurious parameters of the resistors, improve the step response characteristics of the voltage divider, and make its frequency response bandwidth -3dB bandwidth cover the range from DC to 5MHz. This enables it to track pulse voltages with microsecond-level rising edges without distortion. The low-voltage analog signal after voltage division is input to the signal conditioning circuit.

[0087] In the current detection branch, in order to capture the dynamic characteristics of high-frequency pulse current, this embodiment selects a coaxial non-inductive shunt as the current sensor. The coaxial non-inductive shunt is connected in series on the low potential side of the main discharge circuit, i.e., between the load and ground. Its structure includes an inner conductor and an outer conductor arranged coaxially. The measured current flows through the inner conductor and returns through the outer conductor. Based on the electromagnetic shielding principle of the coaxial cable, the magnetic fields generated by the inner and outer conductors cancel each other out outside the shunt, making the self-inductance coefficient of the shunt extremely low, usually less than 10 nanohenries. The coaxial non-inductive shunt converts the current signal flowing through the load into a weak voltage signal that is linearly proportional to its amplitude. This voltage signal is also input to the signal conditioning circuit.

[0088] The signal conditioning circuit is located at the analog front end and includes an instrumentation amplifier and an anti-aliasing filter. The instrumentation amplifier is configured in differential input mode to suppress common-mode electromagnetic interference noise and amplify the weak analog signals from the voltage and current sensors to the full-scale input range of the analog-to-digital converter. The anti-aliasing filter is set as a second-order or fourth-order Butterworth low-pass filter with a cutoff frequency of [missing information]. Set as sampling frequency Below 1 / 2, it is usually set to 2 to 5 times the main spectral energy bandwidth of the discharge waveform to filter out high-frequency thermal noise and prevent spectral aliasing.

[0089] Conditioned voltage analog signal With current analog signal The signal is fed into a high-rate analog-to-digital converter (ADC). The ADC employs a synchronous sampling architecture to ensure that the voltage and current channels are triggered and converted on the same clock edge, avoiding phase deviation between the two signals. Driven by this, continuous analog waveforms are discretized into digital sequences.

[0090] The data ultimately output by the acquisition module 300 to the control module 400 is represented as two time-synchronized discrete sequences: a voltage discrete sequence and a voltage discrete sequence. With current discrete sequence The numerical transformation relationship between these two sequences is defined as follows:

[0091] ;

[0092] In the formula: Represents the time index of discrete sampling points, with a value range of 100. ; Indicates the first The actual voltage value across the load at each sampling time, in volts; Indicates the analog-to-digital converter in the first... The original digital encoded value of the voltage channel output at any given time, its value range is: to ; The resolution bit depth of the analog-to-digital converter is indicated. In this embodiment, it is preferably 12 to 16 bits, and the corresponding quantization signal-to-noise ratio needs to be greater than 72dB to ensure that the quantization error meets the accuracy requirements of the parameter identification algorithm. This represents the reference voltage value of the analog-to-digital converter, typically a high-precision, low-temperature-drift reference source such as 2.5V or 4.096V, and the temperature drift coefficient. ; This indicates the voltage division ratio coefficient of the broadband high voltage divider, which is the ratio of the input high voltage to the output low voltage. This coefficient is obtained through factory calibration.

[0093] ;

[0094] In the formula: Indicates the first The actual current flowing through the load at each sampling time, in amperes; Indicates the analog-to-digital converter in the first... The original digital encoded value of the current channel output at any given time; This indicates the nominal resistance value of the coaxial inductive shunt, typically in the milliohm range, such as 0.5mΩ to 5mΩ. This is required... To ensure the physical meaning of the division operation.

[0095] Through the aforementioned hardware links and signal processing, the acquisition module 300 can convert the transient magnetization physical process into a precise digital sequence that the control module 400 can compute under strong electromagnetic interference. This digital sequence not only retains the amplitude information of the waveform but also completely preserves the slope and curvature characteristics of the waveform over time, providing a complete data foundation for subsequent parameter regression calculations based on the circuit model.

[0096] See attached document Figure 5 , Figure 5A schematic diagram of the hardware circuit architecture and data interaction link of the control module 400 according to an embodiment of the present invention is shown. In this embodiment, the control module 400 serves as the computational core and logic control unit of the entire pulsed strong magnetic field system. At the hardware level, it adopts a heterogeneous dual-core architecture in which a high-performance floating-point digital signal processor and a field-programmable gate array work together. The initial design intention of this architecture is to use the digital signal processor to process complex floating-point matrix operations, while using the field-programmable gate array to realize nanosecond-level parallel timing logic, thereby solving the bottleneck problem that traditional single-core processors cannot simultaneously handle high-order algorithm solving and multi-channel high-speed input / output control.

[0097] The core board of the control module 400 is equipped with a 32-bit floating-point digital signal processor with a main frequency set between 150 MHz and 300 MHz. It integrates a floating-point arithmetic unit and a trigonometric function acceleration unit that conforms to the IEEE-754 standard. The digital signal processor is mainly responsible for executing the upper-level application logic, including: running parameter identification algorithms based on the resistor-inductor-capacitor circuit model, calculating the switching strategy of the capacitance matrix, and executing closed-loop feedback control laws. Considering that the waveform data generated by the pulse discharge process is huge and the access speed requirement is extremely high, the processor is externally expanded with a large-capacity synchronous dynamic random access memory and a non-volatile flash memory chip. The synchronous dynamic random access memory is used as a dynamic data stack and heap during algorithm operation, and its bus frequency is synchronized with the processor's main frequency. The non-volatile flash memory chip is used to save historical operation logs and fault waveform records when power is off.

[0098] The Field Programmable Gate Array (FPGA) establishes a high-speed communication link with the Digital Signal Processor (DSP) via an external memory bus or a 16-bit / 32-bit parallel bus. The FPGA primarily undertakes the parallel logic control and timing management tasks of the underlying hardware, specifically including: generating synchronous trigger pulses for the power switching devices in the driving capacitor matrix module 200, receiving and parsing the high-speed analog-to-digital conversion data stream from the acquisition module 300, and implementing hardware-level fault protection logic. In this embodiment, the FPGA uses an industrial-grade chip with more than 50,000 logic units, internally configured with multiple parallel logic blocks, capable of independently processing multiple input / output signals, ensuring that the generation of control signals is not affected by processor interrupt response delays.

[0099] In terms of the physical interface design of the data link, the control module 400 adopts different communication protocols and physical media for different controlled objects in order to build an industrial-grade communication network with high electromagnetic compatibility.

[0100] For communication with the charging module 100, the control module 400 is equipped with a controller local area network bus interface or a serial communication interface based on the RS-485 standard. The interface circuit has an optocoupler and a common-mode choke connected in series, and the isolation voltage is not less than 2500 volts RMS value. This is used to isolate common-mode noise that may be conducted from the charging module 100 side to the control side. The control module 400 sends charging voltage setting commands through this interface and periodically queries the operating status and fault codes of the charging module 100.

[0101] For the control of the capacitor matrix module 200, the output terminal of the field-programmable gate array of the control module 400 is connected to the multi-channel fiber optic transmitter array. Since the capacitor matrix module 200 is at a high-voltage floating ground potential, in order to achieve strict high-voltage electrical isolation, the trigger signal is transmitted in the form of optical pulses. The high-precision timer inside the field-programmable gate array modulates the on / off state of the fiber optic transmitter head according to the timing calculated by the algorithm, generating an optical signal corresponding to the binary switch state coefficient sequence. The optical signal is transmitted to the drive circuit of the capacitor matrix module 200 through the bend-resistant industrial-grade plastic optical fiber, and the non-conductive characteristics of the optical signal are used to cut off the conductive interference path.

[0102] For data reception by the acquisition module 300, the control module 400 is designed with a high-speed differential signal interface, such as a low-voltage differential signal interface or a serial peripheral interface. The analog-to-digital converter in the acquisition module 300 sends the quantized voltage and current data to the field-programmable gate array (FPGA) in the form of a serial data stream. To prevent the loss of high-speed data streams during cross-clock domain transmission, the FPGA internally includes a dual-port random access memory (RAM) as a ping-pong buffer. When the digital signal processor (DSP) reads data from buffer A, the FPGA simultaneously writes the newly acquired data to buffer B, using a direct memory access mechanism to alternate between the two buffers, thereby achieving seamless data transfer with zero waiting time and freeing up the processor core's computing resources.

[0103] Regarding timing control principles, to ensure accurate execution of control commands, the clock management unit within the control module 400 provides a unified, low-jitter system clock source for the entire digital logic. The field-programmable gate array (FPGA) uses this clock source to convert the duty cycle or delay parameters issued by the digital signal processor into physical count values. This process essentially discretizes continuous time quantities into the number of clock cycles for the digital logic. (Hardware timer register configuration values...) The mapping relationship between the target time parameter and the target time parameter follows the physical formula:

[0104] ;

[0105] In the formula: This represents the integer count value written to the timer hardware register. Its bit width is typically 16 bits or 32 bits, and the maximum count value must meet the following requirements. , To prevent overflow; This represents the target pulse width or trigger delay time calculated by the algorithm, in seconds, and must meet the following conditions: ; This indicates the master clock frequency of the internal logic of the field-programmable gate array, which is typically set to 50 MHz to 200 MHz. This represents the division factor of the prescaler, used to extend the maximum counting range of the timer; its value is usually a power of 2. The selection criterion is to make Achieve the highest time resolution without overflowing registers; This represents the floor function, used to quantize the calculation result into a discrete register value; This indicates a correction term, because digital counters typically start counting from 0, i.e., counting to... Actual consumption One clock cycle.

[0106] In addition, the control module 400 also carries a hardware watchdog timer and a power management chip. The power management chip is responsible for converting the externally input 24V DC power supply into multiple low-voltage power supplies such as 1.2V and 3.3V required by the processor core, and provides power-on reset and power-off detection functions. The hardware watchdog timer monitors the processor's feed pulse and can forcibly reset the digital signal processor and field-programmable gate array when the program runs away or crashes, ensuring that the system will not be in an uncontrolled state for a long time.

[0107] This dual-core hardware architecture, based on a digital signal processor and a field-programmable gate array, separates algorithm operation and logic control at the physical level, ensuring both the real-time solution capability of complex parameter identification algorithms and the determinism and synchronization of nanosecond-level pulse control signals.

[0108] See attached document Figure 6 , Figure 6 A flowchart illustrating the parameter identification logic based on waveform reverse analysis according to an embodiment of the present invention is shown. In this embodiment, the parameter identification function is executed by the digital signal processor in the control module 400. Its operating mechanism is to use the acquired pulse discharge waveform data to deduce the current equivalent resistance and equivalent inductance values ​​of the load coil through a mathematical inversion algorithm, thereby establishing a dynamic circuit model that can reflect the load temperature rise and deformation characteristics.

[0109] The digital signal processor first executes preprocessing logic for the raw waveform data. To accurately extract the valid data segment for parameter identification, the processor employs a dual-threshold detection algorithm: the moment when the current sample value first exceeds the noise threshold, such as 0.5% of full scale, is marked as the starting index. The moment when the subsequent current first crosses zero is marked as the end index. Before this interval, the processor is configured to read the pre-triggered data segment, calculate the arithmetic mean of the voltage and current samples within the data segment as the reference zero bias, and subtract the reference zero bias point by point from the main discharge waveform sequence to eliminate the DC drift inherent in the analog front-end circuit. In addition, for broadband electromagnetic noise under high-voltage discharge environment, the processor uses a finite impulse response low-pass filter with adjustable cutoff frequency to smooth the corrected data sequence.

[0110] After data cleaning, the system constructs a load equivalent circuit model based on a resistor-inductor series circuit. Based on Kirchhoff's voltage law, the transient voltage across the load and the transient current flowing through the load are constrained by a first-order linear differential equation. Considering the discrete characteristics of the digital control system, this embodiment uses the forward difference method or bilinear transform method to discretize the continuous differential equation. For the first... The physical relationships at each sampling time are described as follows:

[0111] ;

[0112] In the formula: Indicates the effective discharge range The index of sampling points within; Indicates time The sampled value of the load terminal voltage, in volts (V); and Representing time respectively Compared to the previous moment The load current sample value, in amperes; This represents the sampling period of the analog-to-digital converter, in seconds; its reciprocal is the sampling frequency. This serves as the time reference for the difference operation; This represents the equivalent inductance of the load to be identified, in Henry. This indicates the equivalent resistance value of the load to be identified, in ohms; This represents the fitting error term introduced by model mismatch, nonlinear hysteresis effect, or measurement noise.

[0113] To simultaneously calculate inductance and resistance parameters from time-series data, the processor constructs a linear regression model based on the least squares method. This model reconstructs the aforementioned difference equation into a vector inner product form. The data from the entire effective sampling interval are stacked into a matrix. Since the rate of change of current approaches zero near the current peak, multicollinearity in the regression matrix may occur, leading to singularity or numerical instability in matrix inversion. Therefore, this embodiment employs the Tikhonov regularization algorithm for solving the problem. The calculation of the optimal parameter estimates follows the matrix operation formulas:

[0114] ;

[0115] In the formula: This represents the output parameter estimation vector. ; This represents the regression observation matrix, with dimension 1. ( (where the number of sampling points is), its first... The row vector consists of the current rate of change component. With current amplitude component constitute; Represents the voltage observation vector, derived from the voltage sampling sequence. constitute; express identity matrix; This represents the regularization coefficient, whose value is determined by the matrix. The condition number is dynamically adjusted, and is usually set at... to In the meantime, it is physically used to maintain the unbiasedness of parameter estimation while suppressing noise amplification; and These represent matrix inversion and transpose operations, respectively.

[0116] Digital signal processors obtain parameter estimation vectors After that, the physical constraint verification logic will be executed. Specifically, the processor checks... and Whether it falls within a preset reasonable physical range, for example If the parameters are out of range or a non-numerical anomaly occurs during calculation, the system will determine that the identification is invalid and maintain the parameter values ​​from the previous cycle or revert to the default safe parameter set to prevent incorrect model parameters from causing subsequent control divergence.

[0117] Based on the real-time resistance identified above With real-time inductance The control module 400 further utilizes the analytical solution of the underdamped oscillator circuit to predict the waveform characteristics of the next discharge. Specifically, the processor predicts the waveform characteristics of the next discharge based on the target peak current set by the user. The total capacitance value of the capacitance matrix required to satisfy the objective is solved in reverse. The solution process involves finding the roots of the following nonlinear transcendental equation:

[0118] ;

[0119] In the formula: This represents the current charging voltage of the capacitor matrix, in volts (V). and This represents the load inductance (Henry) and load resistance identified in the previous steps; The damped oscillation angular frequency of a circuit is defined as follows: To ensure the circuit operates in oscillating discharge mode, the underdamped condition must be met. ; The value indicates the time when the current reaches its peak value, expressed in seconds (s). It should be noted that, in embodiments of the present invention, It is not an independent input variable, but a derived quantity determined by the circuit parameters. Its value corresponds to the moment when the first derivative of the current with respect to time is zero. The calculation relationship is as follows: .

[0120] From the above formula, we can see that the target capacitance value to be solved is... Not only does it appear directly in frequency In addition, through Coupled in the sine term With exponential decay term and peak time This makes the above equation a equation about... The highly nonlinear transcendental equations cannot be solved analytically directly. Therefore, the processor uses the Newton-Raphson iterative method to numerically approximate the solution. The exact solution is obtained. The iterative process uses the currently recorded capacitance value as the initial guess, and calculates the equation residual and its effect on the capacitance. The partial derivatives are used to continuously correct the estimated value until the calculated theoretical peak current is close to the target value. The error is less than the preset accuracy threshold, for example, 0.1%. Through this closed-loop correction mechanism based on waveform reverse analysis, the present invention can adaptively compensate for parameter drift caused by load coil aging, ensuring that the peak accuracy and pulse width consistency of the output waveform of the system always meet the experimental requirements throughout the entire life cycle.

[0121] See attached document Figure 7 , Figure 7A schematic diagram of the capacitor matrix reconstruction logic and lifetime equalization control principle according to an embodiment of the present invention is shown. In this embodiment, the control module 400 not only undertakes the task of calculating the theoretical capacitance value, but also is responsible for accurately mapping this continuous physical calculation quantity into discrete physical capacitor unit switching combinations. Addressing the common problems of uneven capacitor branch aging and hot spot effects in high-energy pulse systems operating at high frequencies, the digital signal processor internally runs a matrix topology reconstruction algorithm based on multi-objective weighted optimization. The core mechanism of this algorithm lies in establishing a dynamic balance between waveform accuracy and device health. While ensuring that the output waveform meets experimental requirements, it achieves loss equalization of the power units throughout the system through a polling scheduling mechanism.

[0122] As the data foundation for algorithm operation, the non-volatile storage space of the control module 400 maintains a dynamic state mapping table covering the entire system topology. This mapping table records the current physical state of each independent capacitor unit in real time. The data dimensions include, but are not limited to: the nominal capacitance value at the factory, the measured capacitance value after correction by the preceding online identification algorithm, the module temperature sampling value fed back by the distributed sensors, the cumulative number of discharges since commissioning, and the absolute timestamp of the last discharge action. Before each discharge task is issued, the processor uses the direct memory access mechanism to fully refresh the state table based on the latest sensor data.

[0123] To transform the health status of devices into computationally quantifiable mathematical indicators, the system introduces a comprehensive cost function as an evaluation criterion. This function, based on the theory of physical damage accumulation, maps the device's thermal stress, mechanical fatigue, and recovery time into normalized values. For indexed... The calculation of the comprehensive cost index Ji of the capacitor unit is based on the following physical model:

[0124] ;

[0125] In the formula: Indicates the first The comprehensive cost index of each capacitor unit, with a value range of [value range missing]. The smaller the value, the higher the current health margin of the unit, and the higher its priority for selection; Indicates the first The current temperature monitoring value of each capacitor unit, in degrees Celsius; The ambient reference temperature is typically measured from a sensor reading at the air inlet of the server rack. Verification is required before the algorithm is executed. If the ambient temperature is too high and the denominator approaches zero, the system will trigger the high-temperature lockout protection. This indicates the upper limit threshold of the safe operating temperature of the capacitor cell, which is determined by the thermal breakdown characteristics of the capacitor dielectric. This indicates the cumulative number of discharges of the unit since it left the factory; This indicates the number of charge-discharge cycles throughout the design life of this type of capacitor, used to normalize lifespan loss; Indicates the current system clock time; This indicates the timestamp of the last action taken by this unit. This reflects the duration of time it is left to cool naturally. The thermal time constant of the capacitor module, expressed in seconds, represents the time required for the capacitor temperature to drop by 63.2%. This parameter was determined through offline thermal characteristic experiments.

[0126] These represent the thermal stress weighting coefficient, the life loss weighting coefficient, and the recovery time weighting coefficient, respectively, and their values ​​satisfy the normalization condition. In a preferred configuration of this embodiment, the following is set: This indicates that the control strategy prioritizes thermal safety and secondarily considers lifetime balance.

[0127] After calculating the cost exponents of all available units, the processor executes combined optimization logic based on the preferred queue and residual approximation. The system first performs a safety screening, automatically eliminating all... Units exceeding a preset safety threshold (e.g., 0.9) or in a fault-locked state will then be processed according to the following procedures: The values ​​are sorted quickly from smallest to largest to form a queue of candidates to be selected. Based on the order of the queue, the algorithm uses a greedy approximation strategy to accumulate the capacitance values ​​one by one until the sum equals the target capacitance value. The deviation falls within the allowable error window. This process is essentially solving a constrained combinatorial optimization problem, mathematically described as finding a set of binary switch state vectors. To achieve the waveform accuracy target function Minimize:

[0128] ;

[0129] Simultaneously satisfy auxiliary optimization constraints:

[0130] ;

[0131] In the formula: - Indicates the first The switching state variable of each capacitor unit has a value of 1 indicating that it is engaged and a value of 0 indicating that it is disengaged; Indicates the first The current actual capacitance value of each capacitor unit; This indicates the total number of capacitor cells in a healthy state in the current system; - This represents absolute value operations. Considering that the quantization granularity of large-capacity capacitor cells may lead to inaccurate matching of the target value, this embodiment configures a group of small-capacity fine-tuning capacitor cells in the capacitor matrix, for example, with capacities ranging from 10 microfarads to 100 microfarads. Once the main capacitor cell combination is selected, the processor calculates the remaining capacitance residual. The residual is then approximated twice using a fine-tuning unit to ensure that the final total capacitance synthesis error is controlled within 0.5% of the total system capacity.

[0132] After determining the final switching state vector S, the digital signal processor converts it into a parallel logic level signal and sends it to the field programmable gate array (FPGA) via a high-speed bus. The FPGA performs nanosecond-level synchronous control based on the vector, modulating the on / off state of the fiber optic transmitting circuit, thereby driving the corresponding thyristor or insulated gate bipolar transistor to operate.

[0133] Through the aforementioned cost function-based dynamic reconstruction strategy, this embodiment not only achieves accurate synthesis of the target waveform, but more importantly, establishes an adaptive thermal management mechanism for the capacitance matrix at the physical level. This mechanism ensures that the temperature rise distribution of the entire system tends to be uniform over long-term operation, preventing the bottleneck effect caused by overheating or excessive aging of individual units, thereby significantly extending the overall mean time between failures (MTBF) of the pulsed high magnetic field system.

[0134] See attached document Figure 8 , Figure 8 A schematic diagram of peak current locking and adaptive charging voltage correction logic according to an embodiment of the present invention is shown. In this embodiment, after the control module 400 completes the discretization reconstruction of the capacitor matrix, given the inherent capacitance quantization characteristics of physical capacitors, discrete capacitor combinations often cannot accurately match the theoretically calculated continuous capacitance requirements, resulting in a non-negligible quantization deviation between the peak output current and the target value in the open-loop state. To compensate for this deviation and suppress nonlinear losses caused by stray line parameters, the digital signal processor is equipped with a voltage accuracy solution algorithm based on inverse model feedforward plus iterative learning feedback. This algorithm utilizes the continuously adjustable characteristics of the charging voltage to compensate for the discreteness of the capacitor capacitance.

[0135] During the voltage reference value calculation phase, the processor obtains the actual total capacitance value of the capacitance matrix based on direct memory access. Based on the real-time parameter identification results of the load coil, an inverse energy transfer model of the second-order RLC circuit is constructed. The processor calculation enables the loop current to accurately reach the target value at the peak moment. Required feedforward voltage reference value This calculation process is based on a reverse deduction of the physical topology parameters currently in use, under the condition of satisfying underdamped oscillation, i.e. Given that the number is a real number and greater than 0, its mathematical expression follows the following analytical relationship:

[0136] ;

[0137] In the formula: This represents the theoretical charging voltage reference value calculated based on the current discrete capacitor combination, in volts. This indicates the target pulse current peak value set by the user, in amperes. This represents the sum of the measured capacitance values ​​of all selected cells in the capacitance matrix, i.e. ; and These represent the equivalent inductance (H) and equivalent resistance (Ω) of the load coil obtained from the previous steps, respectively. This represents the damped oscillation angular frequency under the current actual circuit topology. If the calculation results show that the system is in an overdamped or critically damped state, the processor will automatically adjust the capacitor matrix combination to ensure oscillating discharge. This indicates the moment when the current reaches its peak value, which is determined by the equation. Confirmed, and .

[0138] While the above-mentioned open-loop calculations based on the physical model provide a basic setpoint, the actual output current is often slightly lower than the theoretical value due to unmodelable non-ideal factors in real high-energy pulse discharge circuits, such as stray inductance of the bus, on-state voltage drop of switching devices, and high-frequency dielectric losses of capacitors. To achieve absolute locking of the peak current, this invention introduces a feedback correction mechanism based on batch-to-batch iterative learning control.

[0139] In practice, the control module 400 maintains a historical error observer in non-volatile memory. This observer records the most recent... For example, the deviation ratio between the voltage setpoint and the actual current peak value during the last 5 discharge processes is used to generate the current discharge sequence. Before issuing a charging command, the processor determines the charging time based on the previous (…). The execution result updates the cumulative voltage correction. The correction logic employs an iterative update law with a forgetting factor, described as follows:

[0140] ;

[0141] voltage correction amount The iterative update formula is:

[0142] ;

[0143] In the formula: - This indicates the current discharge sequence index, for the first discharge after the system's initial operation or reset. ),set up ;- This indicates the final voltage setting command issued to the charging module 100; This represents the learning law coefficient, with a value range of 0.1 to 0.3. This parameter is used to balance calibration speed and system stability; a smaller value can suppress control oscillations caused by single-measurement noise. This indicates the peak value of the current waveform measured in the previous test; This represents the approximate characteristic impedance of the system, i.e., the voltage-to-current sensitivity gradient. This is used to convert the current error dimension into the voltage correction dimension. To ensure that the capacitor is not damaged due to overcompensation during the voltage correction process, the system calculates the final set value. Immediately afterwards, a hardware security boundary check is performed, and the processor compares the calculation result with the rated operating voltage of the lowest voltage-rated cell in the capacitor matrix. Compare them. If Exceeding the safety threshold, this example assumes it is set to... The 5% margin is reserved to cope with the voltage drop caused by power grid fluctuations and capacitor aging. The control module 400 will forcibly limit the voltage command and simultaneously trigger an insufficient capacity alarm signal to prompt the operator to replace the coil with a larger inductor or increase the number of capacitor modules.

[0144] After successful verification, the voltage command is sent to the high-voltage charging module 100 via a highly interference-resistant opto-isolated serial communication interface. The closed-loop regulator inside the charging module 100 precisely controls the oscillation stop time of the resonant converter based on this command, ensuring that the actual voltage across the capacitor matrix matches the voltage calculated by the algorithm. With the error controlled within 0.1%, this composite control strategy, which combines model feedforward and historical data feedback, effectively solves the problem of the inability to continuously adjust discrete capacitor systems, ensuring that the repeatability accuracy of the current peak of the pulsed strong magnetic field system is better than the preset experimental standard during long-term operation.

[0145] See attached document Figure 9 It includes a main unit cabinet 1, a control panel 2 on the outside of the main unit cabinet 1, a ventilation duct interface 3 fixedly connected to the top of the main unit cabinet 1, a magnetizing coil assembly 4 on the outside of the main unit cabinet 1, and a central magnetizing hole 5 inside the magnetizing coil assembly 4.

[0146] In this embodiment, the load to be magnetized is a set of hollow magnetizing coils used for producing high-performance magnetic materials. According to process requirements, the target magnetization parameters are set as follows: target peak current ( ):20000A - Target pulse width ( 500 - System hardware configuration: The capacitor matrix contains 8 capacitors with a nominal capacitance of 1000. The main capacitor unit and two 100 The fine-tuning unit; the control core adopts a heterogeneous board composed of a digital signal processor and a field-programmable gate array.

[0147] After 500 continuous magnetization cycles on the production line, the coil temperature rises from 25°C to 85°C due to the current heating effect. At this time, the system's adaptive logic operates according to the following steps: 1. Real-time parameter identification: The acquisition module 300 captures the 500th discharge waveform using a Kelvin four-wire system. The control module 400 uses a regularized least squares algorithm to analyze and discover that due to the temperature rise of the copper wire and electromagnetic stress, the equivalent resistance of the load... The equivalent inductance drifts from an initial 20mΩ to 26mΩ. Approximately 2% fluctuation was caused by microscopic deformation. 2. Dynamic reconstruction of the capacitance matrix: Based on the identified new parameters, the digital signal processor recalculates using Newton's iterative method to maintain 500 The system automatically adjusts the switching combination of the next module from the original 4 main capacitors to a 4 main capacitors + 1 fine-tuning combination to compensate for the waveform distortion caused by the increased resistance. 3. Voltage Iterative Correction: The system detected that the actual peak current of the 500th magnetization was 19650A. The iterative learning algorithm, based on historical errors, superimposed a voltage on the theoretical feedforward voltage. The correction component automatically compensates for line losses.

[0148] To verify the technological advancement of this invention, a comparative experiment was conducted between the system of this invention and a traditional fixed-parameter magnetizer under the same working conditions.

[0149] The table below records the fluctuations in the peak output current of the two systems during 1000 consecutive magnetization cycles:

[0150] Number of magnetizations peak value of control group control group error Peak values ​​of this invention This invention group error 1 (Cold State) 20050 +0.25 19995 -0.02 500 (temperature rise) 19420 -2.90 20012 +0.06 1000 (thermal steady state) 19150 -4.25 19988 -0.06

[0151] Based on the experimental data table and Figure 10 and Figure 11As can be seen, during 1000 consecutive high-frequency magnetization cycles, the traditional control group equipment was significantly affected by the load temperature rise. As the coil resistance increased from 20mΩ to 26mΩ, its peak output current drifted significantly downwards, with the error rapidly expanding from +0.25% initially to -4.25% in thermal steady state. This magnitude of deviation directly leads to substandard magnetic performance in permanent magnet products. In contrast, the present invention exhibits extremely strong adaptive compensation capabilities. Through real-time collaboration between regularized parameter identification and iterative learning algorithms, the system can automatically fine-tune the capacitor matrix combination and compensate for the charging voltage after detecting load drift. Data demonstrates that the peak current deviation of the present invention remained consistently within ±0.1% throughout the entire cycle, with a maximum deviation of only +0.06%, ensuring a high degree of consistency in the magnetization field strength.

[0152] By introducing a scheduling strategy based on a comprehensive cost index, this invention fundamentally solves the bottleneck effect of uneven power device losses. Experimental observations show that the system successfully controls the maximum temperature difference between each unit of the capacitor matrix within 5°C, avoiding insulation aging or capacitor breakdown caused by local overheating. Compared with traditional equipment, this invention is expected to improve the overall mean time between failures (MTBF) of the system by approximately 40% while maintaining high-precision output. Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A pulse magnetizer, comprising a charging module, a capacitor matrix module, a data acquisition module, and a control module; characterized in that, The charging module is connected to the capacitor matrix module; the capacitor matrix module contains multiple independent switched capacitor units connected in parallel. The acquisition module is connected in series between the capacitor matrix module and the load to be magnetized, and is used to acquire the discrete voltage sequence and discrete current sequence generated by the load to be magnetized during the discharge process. The control module is connected to the charging module, the capacitor matrix module, and the acquisition module; The control module generates switch combination commands using a selection strategy based on a comprehensive cost index. The comprehensive cost index is calculated based on the temperature monitoring value, cumulative discharge count, and static cooling time of the independent switched capacitor unit. The control module selects the independent switched capacitor units to be put into operation in ascending order of the comprehensive cost index; The control module is used to calculate the circuit parameters of the load to be magnetized based on the voltage discrete sequence and the current discrete sequence. The control module is also used to determine the target capacitance value of the capacitor matrix module and the target charging voltage value of the charging module according to the circuit parameters, and to generate switch combination instructions and voltage setting instructions. The control module generates the voltage setting command using a correction algorithm based on iterative learning control; The correction algorithm updates the voltage correction amount based on the current deviation generated by the previous magnetization cycle, and superimposes the voltage correction amount on the voltage reference value, thereby compensating for the quantization deviation generated by capacitor reconstruction and locking the peak discharge current.

2. The pulse magnetizer according to claim 1, characterized in that, The independent switched capacitor unit includes a pulse capacitor, a high-power semiconductor switching device, and a resistor-capacitor absorption circuit. The pulse capacitor is connected in series with the high-power semiconductor switching device; The resistor-capacitor absorption circuit is connected in parallel across the high-power semiconductor switching device.

3. The pulse magnetizer according to claim 1, characterized in that, The capacitor matrix module is connected using low-inductance stacked busbars. The low-inductance multilayer busbar includes a positive copper busbar, a negative copper busbar, and an insulating layer disposed between the positive copper busbar and the negative copper busbar; The positive copper busbar and the negative copper busbar are parallel and overlapped, and are used to counteract the inductive reactance of the circuit by using the reverse magnetic field generated by the current.

4. The pulse magnetizer according to claim 1, characterized in that, The acquisition module uses a Kelvin four-wire structure to connect to the load to be magnetized. The acquisition module includes a high-voltage divider and a coaxial sensorless shunt. The high-voltage divider is used to measure the load voltage; The coaxial inductive shunt is used to measure the load current.

5. The pulse magnetizer according to claim 1, characterized in that, The control module adopts a heterogeneous architecture consisting of a digital signal processor and a field-programmable gate array; The digital signal processor is used to run a parameter identification algorithm to calculate the circuit parameters; The field-programmable gate array is used to control the operation of the independent switched capacitor unit according to the switch combination command.

6. The pulse magnetizer according to claim 1, characterized in that, The control module calculates the circuit parameters using a least squares regression algorithm with regularization coefficients; The circuit parameters include resistance parameters and inductance parameters; The least squares regression algorithm solves the mapping relationship between the discrete voltage sequence, the discrete current sequence, and the circuit parameters through matrix operations.

7. The pulse magnetizer according to claim 6, characterized in that, The control module determines the target capacitance value by solving the nonlinear transcendental equation using Newton's iterative method. The nonlinear transcendental equation is constructed based on the target current peak value, charging voltage, inductance parameters, resistance parameters, damped oscillation angular frequency, and the current peak time. The control module uses the Newton-Raphson iteration method to numerically approximate the target capacitance value, so that the error between the theoretical peak current and the target peak current is less than a preset accuracy threshold.

8. A pulse magnetizer according to claim 1, comprising a main unit cabinet (1), characterized in that, The main unit cabinet (1) is provided with a control panel (2) on the outside, and a ventilation duct interface (3) is fixedly connected to the top of the main unit cabinet (1). A magnetizing coil assembly (4) is provided on the outside of the main unit cabinet (1), and a central magnetizing hole (5) is opened inside the magnetizing coil assembly (4).

Images