Double-loop sub-sampling phase-locked loop circuit switched by TDC auxiliary control loop

Abstract

The invention relates to the field of integrated circuits, in particular to a double-loop sub-sampling phase-locked loop with TDC auxiliary control loop switching and a loop control method.The phase-locked loop comprises a fast phase-locked loop cppll, a sub-sampling phase-locked loop sspll and a TDC loop switching module, wherein the fast phase-locked loop comprises a dead-zone-free phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency divider which are connected in sequence; the sub-sampling phase-locked loop comprises a sub-sampling phase discriminator and a sub-sampling charge pump which are connected in sequence; and the TDC loop switching module comprises a bidirectional TDC and a decision device which are connected in sequence. The TDC is used for measuring the phase difference between a reference clock and a feedback clock, the phase difference data is sent to the decision device, the decision device determines whether to switch the loop or not by using a method capable of judging the loop locking condition through the phase difference, phase locking and re-locking after lock losing are achieved, and the static phase error during locking is reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a PLL circuit and its control method. Background Technology

[0002] A phase-locked loop (PLL) is a type of clock generation circuit based on a feedback mechanism. Its core function is to generate an output clock signal synchronized with the input reference clock signal. A typical architecture includes a phase-frequency discriminator (PFD), a charge pump (CP), a loop filter (LPF), a voltage-controlled oscillator (VCO), and a frequency divider (DIV), achieving output clock synchronization with the input reference clock through closed-loop feedback. However, in actual circuits, the components inevitably generate noise, resulting in the output clock carrying a significant amount of noise. In high-precision applications such as RF and wired communications, this noise can cause clock phase noise or jitter, disrupting the integrity of constellation diagrams and eye diagrams, thereby degrading the bit error rate of the communication system and even leading to communication failures.

[0003] Sub-sampling PLLs remove the frequency divider from traditional architectures, while retaining the frequency multiplication function. This allows the noise of the PFD, CP, and frequency divider to be attenuated by a factor of N² (where N is the multiplication factor) when it is transmitted to the PLL output. Therefore, it has better noise performance than traditional charge pump PLLs and has become the preferred solution for high-precision clock generation scenarios.

[0004] The core working mechanism of a subsampling phase-locked loop (PLL) is to align the edge of the reference clock signal (hereinafter referred to as the "reference signal") with the nearest zero-crossing point of the voltage-controlled oscillator (VCO) output signal. However, this mechanism can only achieve phase alignment and cannot directly achieve frequency alignment, and its locking range is limited to one cycle of the VCO output signal. It should be noted that the target locking point of the subsampling PLL is the zero-crossing point of phase 0 or 2nπ (n is an integer), not the zero-crossing point of (2n-1)π (n is an integer) corresponding to half a cycle; the zero-crossing point at 2nπ (n is an integer) will be referred to as the "zero-crossing point" in the following text. In high-frequency applications, this locking range is extremely narrow—for example, the period of a 30GHz output signal is only 33ps. Therefore, at the initial stage of the subsampling PLL startup, an additional frequency-locking loop must be used to assist in initial locking; after the phase difference between the feedback signal and the reference signal is reduced to a preset range, the subsampling loop is switched to complete precise locking.

[0005] In existing technologies, the core solution for loop switching is to use a phase detector with a dead time: by determining whether the phase difference between the reference signal and the feedback signal enters a preset dead time, the switching of the subsampling loop is triggered. Specifically, a delay signal is typically generated using an inverter delay chain and a D flip-flop, which is then processed by logic gates to obtain a dead time indication signal—where the duration of the delay signal directly corresponds to the phase difference range of the dead time. The delay introduced by this type of structure is typically in the range of tens to hundreds of picoseconds, leading to the following two key technical issues:

[0006] Technical Issue 1: Excessive dead zone width in high-frequency scenarios leads to ambiguity in locking and slow re-locking response. For high-frequency output signals, the dead zone width corresponding to the aforementioned delays in the tens to hundreds of picoseconds range exceeds a reasonable range: for example, the period of a 10GHz output signal is only 100ps, and the period of a 25GHz output signal is only 40ps. In this case, the dead zone may contain two or more zero-crossing points of the VCO output signal. This makes it difficult for the subsampling loop to accurately determine the zero-crossing point of the target, resulting in ambiguity in locking. On the other hand, when the subsampling loop loses lock (i.e., the phase difference between the feedback signal and the reference signal exceeds the dead zone range, and the subsampling loop cannot maintain tracking lock), it is necessary to wait for the phase difference to leave the dead zone before switching back to the frequency-locked loop for re-locking. During this period, the quality of the output clock signal deteriorates sharply; at the same time, the continuous retry locking behavior of the subsampling loop further prolongs the overall response time from loss of lock to re-locking, affecting system stability.

[0007] Technical Issue 2: Feedback signal delay causes phase shift, leading to unstable loop locking. When the frequency-locked loop is operating, the VCO output signal needs to be frequency-divided before being input to the dead-zone phase detector as the feedback signal. This frequency division process inevitably introduces a delay, causing a deviation between the zero-crossing point of the feedback signal and the actual zero-crossing point of the VCO output signal. When the loop switches from the frequency-locked loop to the subsampling loop, the zero-crossing point of the tracked target will change abruptly. If, after locking in the subsampling loop, the fixed phase difference between the feedback signal and the reference signal exceeds the dead-zone width, it will trigger the loop to mistakenly switch back to the frequency-locked loop before the subsampling loop completes precise locking. Ultimately, this causes the loop to repeatedly switch between the two modes, failing to achieve stable locking. Summary of the Invention

[0008] The purpose of this application is to provide a dual-loop subsampling phase-locked loop circuit and its control method with TDC-assisted control loop switching, which can solve the technical problems of locking ambiguity, slow relock response and unstable locking in the prior art.

[0009] This application provides a dual-loop subsampling phase-locked loop circuit with TDC-assisted control loop switching, including a fast phase-locked loop, a subsampling phase-locked loop, a TDC loop switching control circuit, and a loop filter, a voltage-controlled oscillator, and a frequency divider connected in series. The fast phase-locked loop includes a dead-zone-free phase-frequency detector and a charge pump connected in series; the subsampling phase-locked loop includes a subsampling phase detector and a subsampling charge pump connected in series; the TDC loop switching control circuit includes a TDC and a decision unit connected in series; the output of the fast phase-locked loop is connected to the input of the loop filter, and the output of the subsampling phase-locked loop is also connected to the input of the loop filter; the input of the frequency divider is connected to the output of the voltage-controlled oscillator, and the output of the frequency divider is connected to the input of the dead-zone-free phase-frequency detector and the input of the TDC; the output of the decision unit is connected to the control terminals of the fast phase-locked loop and the subsampling phase-locked loop, respectively, to enable selective opening or closing of the two loops.

[0010] Furthermore, the TDC is a bidirectional TDC, used to detect the time difference between the rising edge of the reference signal (clkref) and the rising edge of the feedback signal (clkfb), and output the time difference signal (td).

[0011] Further, the decision unit includes: a first comparator circuit, used to compare the decimal number corresponding to the time difference signal (td) output by the TDC with the magnitude of the time difference threshold (td_islock), and output a counting control signal (counteren); a counter, used to increment or clear the output period number (periods_sum) according to the counting control signal (counteren) when triggered by the rising edge of the reference signal (clkref); a second comparator circuit, used to compare the magnitude of the period number (periods_sum) with the period threshold (periods_islock), and control the level switching of the loop control signal (loopctrl); and a third comparator, used to compare the magnitude of the time difference signal (td) with the time difference unlock threshold (td_unlock), and control the level switching of the loop control signal (loopctrl), while simultaneously controlling the clearing operation of the counter and the reset operation of the second comparator.

[0012] Furthermore, the functions of each module are defined as follows: The dead-zone-free frequency and phase detector is used to receive the reference signal (clkref) and the feedback signal (clkfb), and generate a pull-up signal (up) and a pull-down signal (dn) representing the time difference between the two; the charge pump is used to receive the pull-up signal (up) and the pull-down signal (dn), and generate a current signal (Imcp) based on the signal duration; the subsampling phase detector is used to receive the reference signal (clkref) and the output signal (clkout), and generate a sampled voltage signal (Vsamn, Vsamp) representing the time difference between the two; the subsampling charge pump is used to receive the sampled voltage... The system receives the reference signal (clkref) and the feedback signal (clkfb) and generates a time difference signal (td) representing the time difference between them. The decision unit is used to: 1) receive the time difference signal (td) and generate a counting control signal (counteren) through a first comparator, the counting control signal being determined by comparing the time difference signal (td) with a time difference threshold (td_islock); 2) adjust the period based on the counting control signal (counteren). 1) Perform increment or reset operation on s_sum; 2) Control the level switching of the loop control signal (loopctrl) through the second comparator, the level switching of the loop control signal is determined by the comparison result of the number of cycles (periods_sum) and the period threshold (periods_islock); 3) Control the level switching of the loop control signal (loopctrl) through the third comparator, the level switching of the loop control signal is determined by the comparison result of the time difference signal (td) and the time difference unlock threshold (td_unlock), and simultaneously control the counter to be reset and the second comparator to be reset; the loop control signal (loopctrl) is used to control the sub The sampling charge pump and its operating states are as follows: at level one, the fast phase-locked loop is open and the subsampling loop is closed; at level two, the subsampling loop is open and the fast loop is closed. The loop filter is used to receive the current signal (Imcp) and the subsampling current signal (Isscp) and generate a control signal (vtune). The voltage-controlled oscillator is used to receive the control signal (vtune) and generate an output signal (clkout) regulated by the gain (kvco) and the center frequency (clkcen). The frequency divider is used to receive the output signal (clkout) and generate the feedback signal (clkfb) based on the division ratio (div).

[0013] Furthermore, the loop switching logic of the subsampling phase-locked loop is as follows: after the circuit starts, the loop control signal (loopctrl) outputs a default level of one, the fast phase-locked loop is enabled by default, and the subsampling phase-locked loop is disabled by default; the dead-zone-free frequency and phase detector detects the time difference between the reference signal (clkref) and the feedback signal (clkfb), outputs a pull-up signal (up) and a pull-down signal (dn), the charge pump generates a current signal (Imcp) based on the signals, the loop filter converts it into a control voltage (vtune), the voltage-controlled oscillator adjusts the frequency of the output signal (clkout) based on the control voltage (vtune), and the frequency divider generates a feedback signal (clkfb). The TDC continuously monitors the phase difference between the reference signal (clkref) and the feedback signal (clkfb), and outputs a time difference signal (td) according to its minimum range (tdlsb). The decision unit receives the time difference signal (td) and performs the following operations: The first comparator compares the time difference signal (td) with the time difference threshold (td_islock): If the time difference signal (td) < the time difference threshold (td_islock), the counting control signal (counteren) is high, and the counter increments the period count (periods_sum) by one on the rising edge of the reference signal (clkref); if the time difference signal (td) ≥ the time difference threshold (td_islock), the counter increments the period count (periods_sum) by one. If the counter is low, the counter control signal (counteren) is low, the counter is cleared, and the period count (periods_sum) is zero. The second comparator compares the period count (periods_sum) with the period threshold (periods_islock): if the period count (periods_sum) > the period threshold (periods_islock), the control loop control signal (loopctrl) switches from level one to level two, the subsampling charge pump starts and stops, the subsampling loop opens and the fast phase-locked loop closes; if the period count (periods_sum) ≤ the period threshold (periods_islock), the counter control signal (counteren) is low, the counter is cleared, and the period count (periods_sum) is zero. If the loop control signal (loopctrl) is at level 1, the fast loop continues to operate, and the subsampling phase-locked loop remains closed. After the subsampling loop is opened (loopctrl is at level 2), the third comparator is turned on and compares the time difference signal (td) with the time difference unlock threshold (td_unlock) in real time. If the time difference signal (td) > the time difference unlock threshold (td_unlock), the control loop control signal (loopctrl) switches from level 2 to level 1, the control counter is cleared and the second comparator is reset, and the fast phase-locked loop restarts and relocks. After the phase-locked loop is locked, the loop control signal (loopctrl) remains at level 2, and the subsampling loop continues to operate.After the subsampling phase-locked loop (PLL) is enabled, the subsampling phase detector samples the output signal (clkout) to generate sampling voltage signals (Vsamn, Vsamp). The subsampling charge pump converts these into subsampling current signals (Isscp), and the loop filter generates a control voltage (vtune) to maintain synchronization between the voltage-controlled oscillator (VCO) output signal (clkout) and the reference signal (clkref). When the frequency and phase of the feedback signal (clkfb) and the reference signal (clkref) are consistent, and the frequency of the output signal (clkout) is a multiple of the frequency division ratio (div) of the reference signal (clkref), and the zero-crossing time difference between the reference signal (clkref) and the output signal (clkout) is 0, the net current output by the subsampling charge pump is 0, the control voltage (vtune) is constant, and the circuit is considered locked. After locking, the subsampling PLL remains open, and the fast PLL remains closed.

[0014] Furthermore, the second input terminal of the dead-zone-free frequency and phase detector is connected to a reference signal (clkref), the first output terminal outputs a pull-up signal (up), and the second output terminal outputs a pull-down signal (dn); the two input terminals of the charge pump are respectively connected to the first and second output terminals of the dead-zone-free frequency and phase detector, and the output terminal outputs a current signal (Imcp).

[0015] Furthermore, the first input terminal of the subsampling phase detector is connected to the output signal (clkout) of the voltage-controlled oscillator, the second input terminal is connected to the reference signal (clkref), and the output terminal outputs a pair of differential sampling voltage signals (Vsamn / Vsamp); the two input terminals of the subsampling charge pump are respectively connected to the two output terminals of the subsampling phase detector, and the output terminal outputs a subsampling current signal (Isscp).

[0016] Furthermore, the input terminal of the loop filter is connected to the output terminal of the charge pump and the output terminal of the subsampling charge pump, respectively, and the output terminal outputs a control voltage signal (Vtune); the input terminal of the voltage-controlled oscillator is connected to the output terminal of the loop filter, and the output terminal outputs one or more pairs of differential output clock signals (clkout).

[0017] Another aspect of this application provides a loop switching control method for a dual-loop subsampling phase-locked loop circuit with TDC-assisted control loop switching. The method includes: first, starting the circuit, defaulting to enabling the fast phase-locked loop and disabling the subsampling phase-locked loop; second, continuously receiving feedback signals (clkfb) and reference signals (clkref) through the TDC to generate a time difference signal (td) representing the difference between their rising edges; finally, judging the time difference signal (td) through a decision unit, specifically including: (1) a first comparator judging whether the time difference signal (td) is less than the time difference threshold (td_islock). If so, the number of cycles (periods_sum) of the control counter is incremented by one; otherwise, the control counter is cleared and the number of cycles (periods_sum) is reset. (1) ds_sum) is returned to zero; (2) The second comparator compares the number of cycles (periods_sum) with the period threshold (periods_islock). If the number of cycles (periods_sum) > the period threshold (periods_islock), the level of the loop control signal (loopctrl) is switched, and the subsampling phase-locked loop is then opened; (3) When the subsampling phase-locked loop is opened (i.e. the loop control signal is not at the initial level), the third comparator compares the time difference signal (td) with the time difference unlock threshold (td_unlock) in real time. If the time difference signal (td) > the time difference unlock threshold (td_unlock), the loop control signal is switched back to the initial level, and the fast phase-locked loop is then switched back.

[0018] Furthermore, the loop control signal (loopctrl) is an enable signal used to control the current output state of the charge pump and the subsampling charge pump, thereby enabling the corresponding loop to open or close. The initial level of the loop control signal is level one, and the non-initial level is level two. When the loop control signal is level one, the charge pump outputs current (Imcp), the subsampling charge pump does not output current, the fast phase-locked loop is open, and the subsampling phase-locked loop is closed. When the loop control signal is level two, the subsampling charge pump outputs current (Isscp), the charge pump does not output current, the subsampling phase-locked loop is open, and the fast phase-locked loop is closed. At the same time, only one of the charge pump and the subsampling charge pump outputs current, while the other stops outputting.

[0019] Furthermore, the method also includes level switching control: during the operation of the phase-locked loop, when the loop control signal is at level one (fast phase-locked loop is open), only the second comparator can control the loop control signal to switch to level two; when the loop control signal is at level two (subsampling phase-locked loop is open), only the third comparator can control the loop control signal to switch to level one.

[0020] Furthermore, the time difference threshold (td_islock), period threshold (periods_islock), and time difference unlock threshold (td_unlock) are all adjustable parameters, and their values ​​are determined by the operating frequency of the voltage-controlled oscillator, and can be set by register assignment.

[0021] Compared with existing technologies, the dual-loop subsampling phase-locked loop circuit and loop switching control method of this application with TDC-assisted control loop switching have the following advantages: 1) It is compatible with the direct combination of traditional charge pump phase-locked loops and subsampling phase-locked loops, and the loop switching function does not affect the core working principle and performance of each phase-locked loop; 2) It uses TDC to monitor the time difference between the reference signal and the feedback signal and generate digital output, which is not easily affected by analog circuit offset, and can accurately feed back the loop locking status, providing a reliable basis for loop switching control; 3) The decision device performs judgment processing based on digital signals. Compared with analog signal processing, the judgment threshold is easier to adjust, the implementation difficulty is lower, and the resistance to process PVT is stronger; 4) When the operating frequency of the phase-locked loop changes, the judgment thresholds of the decision device can be flexibly adjusted according to the input signal and output signal frequency, effectively avoiding the loop locking at the wrong zero crossing point. At the same time, after the lock is lost, the relocking process can be quickly started, which significantly improves the locking accuracy of the phase-locked loop, shortens the locking time, and enhances the robustness of the system. Once the TDC and decision unit are packaged as IP, they can be directly used in dual-loop lure sampling phase-locked loops at various operating frequencies. There is no need to redesign the dead-time phase detector; only the TDC bit width and decision unit threshold need to be adjusted, which greatly reduces design costs. Attached Figure Description

[0022] Figure 1 This is the overall structure diagram of a dual-loop subsampling phase-locked loop circuit with TDC-assisted control loop switching.

[0023] Figure 2 This is a circuit diagram for one implementation of a loop control decision device.

[0024] Figure 3 This is a circuit diagram for one implementation of a bidirectional TDC.

[0025] Figure 4 This is a diagram showing the transition of the loop's operating state.

[0026] Figure 5 Here is an example of a timing diagram before and after a loop switch.

[0027] Figure 6 This is an example of a timing diagram for relocking after a lock loss. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0029] Example: Figure 1 A general block diagram of the dual-loop subsampling phase-locked loop circuit with TDC-assisted control loop switching is given in the embodiments of this application. Figure 1 As shown, the dual-loop subsampling phase-locked loop circuit with TDC-assisted control loop switching includes a fast phase-locked loop, a subsampling phase-locked loop, a TDC loop switching control circuit, and a loop filter, a voltage-controlled oscillator, and a frequency divider connected in series. The fast phase-locked loop consists of a dead-zone-free phase and frequency detector and a charge pump connected in series; the subsampling phase-locked loop consists of a subsampling phase detector and a subsampling charge pump connected in series; and the TDC loop switching control circuit consists of a TDC and a decision unit connected in series.

[0030] When the phase-locked loop starts working, according to the initial startup steps of the loop switching control method S1: the fast phase-locked loop is enabled by default and the subsampling phase-locked loop is disabled. At this time, the loop control signal (loopctrl) is low level 0V (set in this embodiment). During this phase, the pre-monitoring logic of control methods S2 and S3 is executed synchronously: the fast phase-locked loop determines the phase difference between the reference signal (clkref) and the feedback signal (clkfb) through a dead-zone-free frequency and phase detector, and outputs pulse signals (up) and (dn); the (up) and (dn) signals control the duration of the charge pump output current, which is converted into voltage (vtune) by a low-pass filter, and (vtune) regulates the frequency of the voltage-controlled oscillator output signal (clkout); the output signal generates a feedback signal (clkfb) with a frequency reduction of N times through a frequency divider with a frequency division ratio of N, and feeds it back to the input of the dead-zone-free frequency and phase detector, which is continuously compared with the reference signal (clkref). Through negative feedback, the frequency of the final output signal (clkout) is close to N times that of the reference signal (clkref), and the phase of the feedback signal (clkfb) and the reference signal (clkref) tends to be aligned. Meanwhile, the TDC and the decision unit are always in working state (corresponding to control method S2). The TDC monitors the time difference between the rising edges of the reference signal and the feedback signal in real time (in this embodiment, the minimum detection scale of the TDC is 8ps), generates a time difference signal (td), and outputs it to the decision unit. The decision unit makes a real-time judgment on the time difference signal (corresponding to control method S3) and decides whether to trigger loop switching based on a preset threshold. When the switching conditions are met, the switching logic of control method S32 is executed: the subsampling loop is opened and the fast phase-locked loop is closed. At this time, the loop control signal (loopctrl) is switched to a high level of 0.9V (set in this embodiment). The unlock monitoring logic of control method S33 corresponds to the subsampling loop operation phase: the subsampling phase detector samples the output of the voltage-controlled oscillator and inputs the voltage value into the subsampling charge pump in the form of (vsamp) and (vsamn); the subsampling charge pump controls the magnitude of the output current (Isscp) through the voltage difference between (vsamp) and (vsamn), and generates a control voltage (vtune) through the loop filter to continue to regulate the output frequency of the voltage-controlled oscillator; when the subsampling loop is locked, the voltages (vsamp) and (vsamn) tend to be equal, the net output of the subsampling charge pump is close to 0, and (vtune) remains relatively constant. At this time, the rising edge of the reference signal (clkref) is aligned with the target zero-crossing point of the output signal (clkout), completing the lock-up maintenance logic of the control method.

[0031] Figure 2An implementation structure of the loop control decision device is given, which can realize the loop switching control method. In this embodiment, the subsampling loop is enabled when the loop control signal (loopctrl) is high (0.9V) and the fast phase-locked loop is enabled when it is low (0V). The oscillator output signal frequency is 12.5GHz. The control method S31 is implemented using a first comparator: the input of the first comparator is connected to the time difference signal (td) and the time difference threshold (td_islock). The time difference signal (td) is compared with the time difference threshold (set to 2 in this embodiment) in real time. When (td) < 2, the time difference between the reference signal and the feedback signal is < 16ps (8ps × 2), and the output (counteren) is high. When (td) ≥ 2, the output (counteren) is low.

[0032] The setting of the time difference threshold needs to take into account both the locking judgment accuracy and the locking speed of the fast phase-locked loop: if the time difference threshold is too small (such as 0 or 1), although the judgment accuracy is higher, it will significantly prolong the phase difference convergence time; when (td) = 2, it corresponds to a delay interval of 12~18ps. The output signal below 55.5GHz usually contains at most one zero crossing point in this time range, which helps to reduce the locking ambiguity problem caused by multiple locking points in the delay interval during subsampling locking.

[0033] The enable pin of the counter is controlled by counteren and counter_rst. In this embodiment, the inverted loop control signal loopctrlb is used as the counter_rst signal, and the result of the AND operation between counteren and loopctrlb is used as the counter enable signal. If the AND operation between counteren and loopctrlb is high, the counter outputs the period count (periods_sum) by one when the rising edge of the reference signal (clkref) arrives; if the AND operation between counteren and loopctrlb is low, the counter is turned off and the period count (periods_sum) is reset to zero.

[0034] The control method S32 is implemented using a second comparator, such as... Figure 2As shown, the input of the second comparator is connected to the counter output cycle count (periods_sum) and the cycle threshold (periods_islock). The comparator enable terminal is connected to loopctrlb, so that it is enabled when the loop control signal (loopctrl) is low. After enabling, it checks whether (periods_sum) is greater than the cycle threshold (periods_islock) (set to 16 in this embodiment). If it is greater than 16, it is determined that the loop is approaching stable locking. The loop control signal (loopctrl) is switched to a high level of 0.9V through the RS latch, the subsampling loop is enabled and the comparator itself is disabled, and the third comparator is enabled.

[0035] The period threshold setting is adapted to the loop damping factor and bandwidth requirements: the value is 8 to 16 reference periods. If it is too small, it is easy to misjudge the lock at the first phase difference zero point in the ringing stage of the fast phase-locking process. If it is too large, it may prolong the lock time.

[0036] Control method S33 is implemented using a third comparator: (e.g.) Figure 2 As shown, the input of the third comparator is connected to the time difference signal (td) and the time difference threshold (td_islock), and the enable terminal is connected to loopctrl, so that it is turned on when the loop control signal (loopctrl) is high. After it is turned on, it monitors in real time whether (td) is greater than the unlock threshold (td_unlock) (set to 10 in this embodiment); if it is greater than 10, it is determined that the subsampling loop is unlocked, and the loop control signal (loopctrl) is switched to low level 0V through the RS latch, the fast phase-locked loop is restarted and it is turned off and the second comparator and counter are turned on.

[0037] The unlock threshold (td_unlock) setting is related to the output signal period: the 12.5GHz signal period is 80ps, and the allowable lock range can be set to ± one period (80ps), corresponding to a TDC output of 10 (80ps / 8ps). This setting helps to reduce accidental unlocking errors caused by overshoot and ringing during the lock process.

[0038] The switching of the loop control signal (loopctrl) is achieved through a simple RS latch. The input of the RS latch is connected to the output of the second and third comparators as shown in the figure, and outputs the loop control signal (loopctrl) and its inverse signal (loopctrllb), which control the current output state of the charge pump and the subsampling charge pump in the two loops respectively: when the loop control signal (loopctrl) is 0V, the charge pump outputs current (Imcp) and the subsampling charge pump stops outputting; when the loop control signal (loopctrl) is 0.9V, the subsampling charge pump outputs current (Isscp) and the charge pump stops outputting, ensuring that only one loop works at a time.

[0039] Figure 3 A circuit diagram for a bidirectional TDC is provided. This bidirectional TDC consists of delay units comprised of two CMOS inverter chains with delays of 8ps and 16ps respectively, D flip-flops, and AND gates. Feedback and reference signals are input from the start and stop ports, respectively. The delay units generate signals with delay intervals of 16ps (delay1, delay2…delay31) and 8ps (delay'1, delay'2…delay'31). At the rising edge of (delay'1, delay'2…delay'31), the D flip-flops adjust the delay signals (delay1, delay2…delay'31). Sample the signal (T[1], T[2]...T

[31] ) using ay31), and obtain the sampled signal (T[1], T[2]...T

[31] ). Then, through a set of identical circuits, input the feedback signal from the stop port and the reference signal from the start port to obtain the sampled signal (T'[1], T'[2]...T'

[31] ). Perform pairwise OR operation on (T[1] and T'[1], T[2] and T'[2]...T

[31] and T'

[31] ), and finally obtain the number of high-level signals. The absolute value of the delay between start and stop is represented in the form of thermometer code, which is the time difference signal (td). The binary code of (td) can be obtained through a thermometer code-binary code decoder. Figure 3 As shown, T[0] and T'[0] are obtained by sampling the start and stop, and are used to characterize the delay direction between the start and stop, i.e. the lead / lag signal: when T[0] is high, it indicates that the start leads the stop; when T[0] is low, it indicates that the start lags the stop; and T'[0] is the opposite.

[0040] Figure 4The state transition diagram of a dual-loop subsampling phase-locked loop circuit with TDC-assisted control loop switching is given. 1. After the phase-locked loop (PLL) is activated, it directly enters the fast PLL state. The loop control signal (loopctrl) is low. At this time, the frequency and phase detector controls the charge pump to execute the PLL logic. The second comparator in the decision unit is turned on and the third comparator is turned off. 2. Lock judgment state: When td < 2, the counter (periods_sum) increments by one. When td ≥ 2, the counter is reset to zero. 3. Trigger switching state: When (periods_sum) > 16 (period threshold), the trigger state transitions to the sub-sampling PLL state. At this time, the loop control signal (loopctrl) switches to a high level. The third comparator in the decision unit is turned on and the second comparator is turned off. The counting no longer affects the loop switching. 4. Unlocked and relocked state: When (td) > 10 (unlocked threshold), the trigger state transitions back to the fast PLL state and the PLL process is restarted. 5. Stable locked state: In the sub-sampling PLL state, when (td) ≤ 10, the sub-sampling PLL state is maintained until the unlocked trigger condition occurs.

[0041] Figure 5 The timing diagrams for the transition from the fast phase-locked loop (PLL) to the subsampled PLL are presented. In this example, the time difference threshold is set to 2, and the loop control signal (loopctrl) is 0.9V high and 0V low. Initially, the loop control signal (loopctrl) is 0V, and the PLL is open. During the locking process, the time difference signal (td) gradually decreases from 4 to 2, and the period count (periods_sum) begins counting. During this period, the time difference signal (td) never exceeds 2, while (period_sum) continuously increases. When (period_sum) exceeds the period threshold (periods_islock=16), the loop control signal (loopctrl) jumps from 0V to 0.9V, completing the state transition from fast PLL to subsampled PLL, and (period_sum) is reset to zero. It should be noted that the locking point of the subsampling loop is the zero-crossing point of the output signal, while TDC monitors the time delay between the rising edge of the reference signal and the rising edge of the feedback signal. Due to the delay of the frequency divider, there is a time interval between the zero-crossing point of the output signal and the zero-crossing point of the feedback signal. Therefore, after switching (td), it may be greater than 2. However, at this time, the subsampling loop has entered the working state. Therefore, the decision device will not switch the loop control signal (loopctrl) to 0V, but compare the time difference signal (td) and the unlock threshold (td_unlock). This is equivalent to introducing a hysteresis characteristic, which helps to reduce the false unlocking caused by the time difference between the two loop locking points exceeding the dead zone. This corresponds to the logic of level switching control in the control method.

[0042] Figure 6The timing diagram for the transition from subsampled PLL to fast PLL operation is shown in the figure. When the subsampled PLL is stably locked, the time difference signal (td) is constant at 5, which is less than the unlock threshold (td_unlock) of 10. The subsampled PLL continues to operate, the counter remains off, and the cycle count output is 0. When the reference clock phase undergoes its first abrupt change, the time difference signal (td) becomes 9, which is still less than the unlock threshold of 10. The loopctrl remains at 0.9V, and the subsampled PLL continues to operate. After relocking, the time difference signal (td) returns to 5. When the reference clock phase undergoes another abrupt change, the time difference signal (td) outputs 11, which is greater than the unlock threshold of 10. The decision unit switches the loop control signal (loopctrl) from 0.9V to 0V through the RS latch, and simultaneously controls the counter and the second comparator to turn on. The PLL switches to the fast PLL operation and restarts the fast relock process. Because the time difference threshold (td) is greater than the time difference threshold (td_islock), the cycle count output is 0.

[0043] It should be noted that the above embodiments are not intended to limit the scope of protection of the present invention. Equivalent transformations or substitutions made based on the above technical solutions all fall within the scope of protection of the claims of the present invention.

Claims

1. A dual-loop subsampling phase-locked loop circuit with TDC-assisted control loop switching, characterized in that, It includes a fast phase-locked loop, a subsampling phase-locked loop, a TDC loop switching control circuit, and a loop filter, a voltage-controlled oscillator, and a frequency divider connected in series; wherein: The fast phase-locked loop includes a dead-zone-free frequency and phase detector and a charge pump connected in sequence. The subsampling phase-locked loop includes a subsampling frequency and phase detector and a subsampling charge pump connected in sequence. The TDC loop switching control circuit includes a TDC and a decision unit connected in sequence; The output of the fast phase-locked loop is connected to the input of the loop filter, and the output of the subsampling phase-locked loop is connected to the input of the loop filter. The input of the frequency divider is connected to the output of the voltage-controlled oscillator, and the output of the frequency divider is connected to the input of the dead-zone-free frequency and phase detector and the input of the TDC, respectively. The output of the decision unit is connected to the control terminals of the fast phase-locked loop and the subsampling phase-locked loop, respectively, to enable one of the two loops to be turned on or off.

2. The dual-loop subsampling phase-locked loop circuit with TDC-assisted control loop switching according to claim 1, characterized in that, The TDC is a bidirectional TDC used to detect the time difference between the rising edge of the reference signal (clkref) and the rising edge of the feedback signal (clkfb). It outputs the absolute value of the time difference as a time difference signal (td) and uses the lead / lag signal (pre / lag) to indicate the positive or negative direction of the time difference.

3. The dual-loop subsampling phase-locked loop circuit with TDC-assisted control loop switching according to claim 1, characterized in that, The decision unit includes: a first comparator circuit for comparing the time difference signal (td) output by the TDC with the time difference threshold (td_islock) and outputting a counting control signal (counteren); a counter for incrementing or resetting the output period number (periods_sum) according to the counting control signal (counteren) triggered by the rising edge of the reference signal (clkref); a second comparator circuit for comparing the period number (periods_sum) with the period threshold (periods_islock) and controlling the level switching of the loop control signal (loopctrl); a third comparator for comparing the time difference signal (td) with the time difference unlock threshold (td_unlock) and controlling the level switching of the loop control signal (loopctrl); and a logic gate circuit for generating a counter reset signal (counter_rst) according to the loopctrl level. The reset signal (counter_rst) is used to control the counter, the second comparator, and the third comparator to be turned on or off.

4. The dual-loop subsampling phase-locked loop circuit with TDC-assisted control loop switching according to claim 1, characterized in that, The functions of each module are defined as follows: The dead-zone-free frequency and phase detector is used to receive the reference signal (clkref) and the feedback signal (clkfb), and generate a pull-up signal (up) and a pull-down signal (dn) representing the time difference between the two; the charge pump is used to receive the pull-up signal (up) and the pull-down signal (dn), and generate a current signal (Imcp) based on the signal duration; the subsampling phase detector is used to receive the reference signal (clkref) and the voltage-controlled oscillator output signal (clkout), and generate a sampled voltage signal (Vsamn, Vsamp) representing the time difference between the two; the subsampling charge pump is used to receive the sampled voltage signal (Vsamn, Vsamp), and generate a current signal (Imcp) based on the sampled voltage signal duration. The voltage value of the pressure signal generates a subsampled current signal (Isscp); TDC is used to receive the reference signal (clkref) and the feedback signal (clkfb), and generate a time difference signal (td) characterizing the time difference between the two; the decision unit is used to receive the time difference signal (td) and perform the following operations: 1) Generate a counting control signal (counteren) through a first comparator, the counting control signal being determined by comparing the time difference signal (td) with the time difference threshold (td_islock); 2) Perform an increment or reset operation on the number of periods (periods_sum) according to the counting control signal (counteren); 3) Control the loop control signal (loopc) through a second comparator. The level switching of the loop control signal (loopctrl) is determined by comparing the number of cycles (periods_sum) with the period threshold (periods_islock); 4) The level switching of the loop control signal (loopctrl) is controlled by a third comparator, and the level switching of the loop control signal is determined by comparing the time difference signal (td) with the time difference unlock threshold (td_unlock); The loop control signal (loopctrl) is used to control the subsampling charge pump and the working state of the charge pump: at level one, the fast phase-locked loop is open and the subsampling loop is closed; at level two, the subsampling loop is open and the fast loop is closed; 5) The level switching of the loop control signal (loopctrl) is determined by comparing the time difference signal (td) with the time difference unlock threshold (td_unlock); The generator generates a counter reset signal (counter_rst). When loopctrl is at level one, counter_rst controls the counter and the second comparator to work normally, while the third comparator is turned off. When loopctrl is at level two, counter_rst controls the counter to be cleared, and turns off the counter and the second comparator, while turning on the third comparator. The loop filter is used to receive the current signal (Imcp) and the subsampled current signal (Isscp), and generate a control voltage signal (vtune). The voltage-controlled oscillator is used to receive the control voltage signal (vtune) and generate an output signal (clkout) that is controlled by the gain (kvco) and the center frequency (clkcen).The frequency divider is used to receive the output signal (clkout) and generate a feedback signal (clkfb) based on the division ratio (div).

5. The dual-loop subsampling phase-locked loop circuit with TDC-assisted control loop switching according to claim 1, characterized in that, The loop switching logic of the subsampling phase-locked loop is as follows: After the circuit starts, the loop control signal (loopctrl) outputs a level of one by default, the fast phase-locked loop is enabled by default, and the subsampling phase-locked loop is disabled by default; the dead-zone-free frequency and phase detector detects the time difference between the reference signal (clkref) and the feedback signal (clkfb), outputs a pull-up signal (up) and a pull-down signal (dn), the charge pump generates a current signal (Imcp) based on the signal, the loop filter converts it into a control voltage (vtune), the voltage-controlled oscillator adjusts the frequency of the output signal (clkout) based on the control voltage (vtune), and the frequency divider generates a feedback signal (clkfb); the TDC continuously monitors the reference signal (clkref) and the time difference between the reference signal (clkref) and the feedback signal (clkfb). The feedback signal (clkfb) is used to determine the phase difference, and a time difference signal (td) is output based on its minimum range (tdlsb). The decision unit receives the time difference signal (td) and performs the following operations: A first comparator compares the time difference signal (td) with the time difference threshold (td_islock): If the time difference signal (td) < the time difference threshold (td_islock), the counting control signal (counteren) is high, and the counter increments the period count (periods_sum) by one on the rising edge of the reference signal (clkref); if the time difference signal (td) ≥ the time difference threshold (td_islock), the counting control signal (counteren) is low, the counter is reset, and the period is reset. The period count (periods_sum) is reset to zero; the second comparator compares the period count (periods_sum) with the period threshold (periods_islock): if the period count (periods_sum) > the period threshold (periods_islock), the control loop control signal (loopctrl) switches from level one to level two, the reset signal (counter_rst) controls the counter to clear zero and shuts down the counter and the second comparator, turns on the third comparator, the subsampling charge pump starts and stops, the subsampling loop starts and the fast phase-locked loop stops; if the period count (periods_sum) ≤ the period threshold (periods_islock). When the loop control signal (loopctrl) remains at level one, the fast loop continues to operate, and the subsampling phase-locked loop remains closed. After the subsampling loop is opened (loopctrl is at level two), the third comparator is turned on, and the time difference signal (td) is compared with the time difference unlock threshold (td_unlock) in real time. If the time difference signal (td) > the time difference unlock threshold (td_unlock), the loop control signal (loopctrl) is switched back to level one, the reset signal (counter_rst) controls the counter, the second comparator to turn on, and the third comparator to turn off, and the fast phase-locked loop is restarted and relocked. After locking, the loop control signal (loopctrl) remains at level two, and the subsampling loop continues to operate.After the subsampling phase-locked loop (PLL) is enabled, the subsampling phase detector samples the output signal (clkout) to generate sampling voltage signals (Vsamn, Vsamp). The subsampling charge pump converts these into subsampling current signals (Isscp), and the loop filter generates a control voltage (vtune) to maintain synchronization between the voltage-controlled oscillator (VCO) output signal (clkout) and the reference signal (clkref). When the frequency and phase of the feedback signal (clkfb) and the reference signal (clkref) are consistent, and the frequency of the output signal (clkout) is a multiple of the frequency division ratio (div) of the reference signal (clkref), and the zero-crossing time difference between the reference signal (clkref) and the output signal (clkout) is 0, the net current output by the subsampling charge pump is 0, the control voltage (vtune) is constant, and the circuit is considered locked. After locking, the subsampling PLL remains open, and the fast PLL remains closed.

6. The dual-loop subsampling phase-locked loop circuit with TDC-assisted control loop switching according to claim 1, characterized in that: The second input terminal of the dead-zone-free frequency and phase detector is connected to a reference signal (clkref), the first output terminal outputs a pull-up signal (up), and the second output terminal outputs a pull-down signal (dn); the two input terminals of the charge pump are respectively connected to the first and second output terminals of the dead-zone-free frequency and phase detector, and the output terminal outputs a current signal (Imcp).

7. The dual-loop subsampling phase-locked loop circuit with TDC-assisted control loop switching according to claim 1, characterized in that: The first input terminal of the subsampling phase detector is connected to the output signal (clkout) of the voltage-controlled oscillator, the second input terminal is connected to the reference signal (clkref), and the output terminal outputs a pair of differential sampled voltage signals (Vsamn / Vsamp). The two input terminals of the subsampling charge pump are respectively connected to the two output terminals of the subsampling phase detector, and the output terminal outputs a subsampling current signal (Isscp). The input terminal of the loop filter is connected to the output terminal of the charge pump and the output terminal of the subsampling charge pump, and the output terminal outputs a control voltage signal (Vtune). The input terminal of the voltage-controlled oscillator is connected to the output terminal of the loop filter, and the output terminal outputs one or more pairs of differential output clock signals (clkout).

8. A loop switching control method for a dual-loop subsampling phase-locked loop circuit with TDC-assisted control loop switching, characterized in that, The method includes the following steps: S1: Start the circuit, with the fast phase-locked loop enabled by default and the subsampling phase-locked loop disabled; S2: Continuously receive the feedback signal (clkfb) and the reference signal (clkref) through the TDC to generate a time difference signal (td) representing the difference between their rising edges; S3: Judge the time difference signal through the decision unit to realize loop switching control, specifically including: S31: The first comparator judges whether the time difference signal (td) is less than the time difference threshold (td_islock). If so, it controls the counter's period count (periods_sum) to increment by one; otherwise, it controls the counter to be cleared and the period count (periods_sum) to be zero; S32: The second comparator compares the period count (periods_sum) with the period threshold (periods_islock). If the number of periods (periods_sum) > the period threshold (periods_islock), the level of the loop control signal (loopctrl) is switched, thereby enabling the subsampling phase-locked loop and disabling the fast phase-locked loop; S33: When the subsampling phase-locked loop is enabled (the loop control signal is not at the initial level), the third comparator compares the time difference signal (td) with the time difference unlock threshold (td_unlock) in real time. If the time difference signal (td) > the time difference unlock threshold (td_unlock), the loop control signal is switched back to the initial level, thereby enabling the fast phase-locked loop and disabling the subsampling phase-locked loop; The loop control signal is an enable signal used to control the current output state of the charge pump and the subsampling charge pump to realize the opening or closing of the corresponding loop.

9. The loop switching control method according to claim 8, characterized in that, The initial level of the loop control signal (loopctrl) is level one, and the non-initial level is level two. When the loop control signal is level one, the charge pump outputs current (Imcp), the subsampling charge pump does not output current, the fast phase-locked loop is open, and the subsampling phase-locked loop is closed. When the loop control signal is level two, the subsampling charge pump outputs current (Isscp), the charge pump does not output current, the subsampling phase-locked loop is open, and the fast phase-locked loop is closed. At the same time, only one of the charge pump and the subsampling charge pump outputs current, while the other stops outputting.

10. The loop switching control method according to claim 8, characterized in that, The method also includes level switching control: during the operation of the phase-locked loop, when the loop control signal (loopctrl) is at level one (fast phase-locked loop is open), only the second comparator can control the loop control signal to switch to level two; when the loop control signal is at level two (subsampling phase-locked loop is open), only the third comparator can control the loop control signal to switch to level one. Among them, the time difference unlock threshold (td_unlock), period threshold (periods_islock), and time difference threshold (td_islock) are all adjustable parameters that can be set through registers according to different output frequencies of the voltage-controlled oscillator.

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