Delay device and method, artificial intelligence processor and electronic equipment

Abstract

At least one embodiment of the invention provides a delay device and method, an artificial intelligence processor and electronic equipment. The delay device comprises a delay chain, a phase discriminator and a controller, the delay chain is configured to receive an input signal, delay the input signal to generate an output signal, and the delay chain comprises a plurality of delay units connected in series, each delay unit in the plurality of delay units comprises a plurality of delay subunits which are connected in parallel in a switchable manner; the phase discriminator is configured to identify a phase difference between an output signal and an input signal of the delay chain; the controller is configured to, for each of at least a portion of the plurality of delay units, adjust a number of delay subunits connected in parallel among the plurality of delay subunits by comparing the phase difference with a reference phase difference to obtain a target number of delay subunits connected in parallel. According to the delay device disclosed by the invention, automatic delay adjustment can be realized.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuits, and particularly to delay devices and methods, artificial intelligence processors, and electronic devices. Background Technology

[0002] Delay-locked loop (DLL) circuits can generate an output signal that is delayed by a certain phase from the input signal, thereby eliminating the propagation delay of the internal clock path and effectively compensating for clock skew. DLL circuits can delay the input signal using an adjustable delay chain. However, adjusting the delay amount presents several challenges. Specifically, the adjustment parameters of the delay chain are affected by variations in process technology, voltage, and temperature (PVT). Furthermore, excessively large delay chain step sizes lead to insufficient phase resolution, while excessively small step sizes cause a surge in the number of delay chain stages, significantly increasing the difficulty of phase locking. These challenges demand high precision, robustness, and adaptability in the phase adjustment of DLL circuits.

[0003] Therefore, a delay scheme that adaptively and precisely adjusts the delay amount is desired. Summary of the Invention

[0004] A delay device is provided according to at least one embodiment of the present disclosure, comprising: a delay chain configured to receive an input signal and delay the input signal to generate an output signal, wherein the delay chain includes a plurality of delay units connected in series, and each of the plurality of delay units includes a plurality of delay sub-units connected in parallel in a switchable manner; a phase detector configured to identify a phase difference between the output signal of the delay chain and the input signal; and a controller configured to adjust the number of delay sub-units connected in parallel among the plurality of delay sub-units for each delay unit in at least a portion of the plurality of delay units by comparing the phase difference with a reference phase difference, thereby obtaining a target number of delay sub-units connected in parallel.

[0005] For example, in a delay device according to at least one embodiment of the present disclosure, the controller is further configured to, for each of at least a portion of the plurality of delay units, reduce the number of the delay sub-units connected in parallel in response to the number of delay sub-units connected in parallel not being the minimum number that can be switched in parallel and the phase difference being less than a reference phase difference; or increase the number of delay sub-units connected in parallel in response to the number of delay sub-units connected in parallel not being the maximum number that can be switched in parallel and the phase difference being greater than a reference phase difference.

[0006] For example, in a delay device according to at least one embodiment of the present disclosure, the controller is further configured to, for each of at least a portion of the plurality of delay units, adjust the number of delay subunits connected in parallel, starting from a maximum number of delay subunits that are switchably connected in parallel.

[0007] For example, in a delay device according to at least one embodiment of the present disclosure, the controller is further configured to, for each of at least a portion of the plurality of delay units: increase the number of the delay sub-units connected in parallel in response to the number of delay sub-units connected in parallel not being the maximum number of switchable parallel connections and the phase difference being greater than a reference phase difference; and set the increased number of the delay sub-units connected in parallel as a target number.

[0008] For example, in a delay device according to at least one embodiment of the present disclosure, the controller is further configured to, for each of at least a portion of the plurality of delay units, determine the maximum number as a target number in response to the number of delay subunits connected in parallel being a maximum number that can be switched to be connected in parallel and the phase difference being greater than a reference phase difference.

[0009] For example, in a delay device according to at least one embodiment of the present disclosure, the controller is further configured to, for each of at least a portion of the plurality of delay units, determine the minimum number as a target number in response to the number of delay subunits connected in parallel being a minimum number that can be switched in parallel and the phase difference being less than a reference phase difference.

[0010] For example, in a delay device according to at least one embodiment of the present disclosure, the controller is further configured to maintain the control voltage of the delay unit at a predetermined voltage for each of at least a portion of the plurality of delay units while adjusting the number of the delay sub-units connected in parallel.

[0011] For example, in a delay device according to at least one embodiment of the present disclosure, the predetermined voltage is less than the maximum control voltage of the delay unit, and the difference between the predetermined voltage and the maximum control voltage of the delay unit is less than a predetermined threshold and greater than zero.

[0012] For example, according to at least one embodiment of the delay device of the present disclosure, wherein the controller is further configured to, for each of at least a portion of the plurality of delay units, adjust the control voltage of the delay unit by comparing the phase difference with a reference phase difference in response to obtaining a target number of parallel-connected delay sub-units.

[0013] For example, in a delay device according to at least one embodiment of the present disclosure, the controller is further configured to, for each of at least a portion of the plurality of delay units, decrease the control voltage of the delay unit in response to the phase difference being less than a reference phase difference; and increase the control voltage of the delay unit in response to the phase difference being greater than a reference phase difference.

[0014] A delay method is provided according to at least one embodiment of the present disclosure for a delay device, wherein the delay device includes a delay chain, a phase detector, and a controller. The method includes: receiving an input signal through the delay chain; delaying the input signal to generate an output signal; wherein the delay chain includes a plurality of delay units connected in series, and each of the plurality of delay units includes a plurality of delay sub-units connected in parallel in a switchable manner; identifying a phase difference between the output signal of the delay chain and the input signal through the phase detector; and adjusting the number of delay sub-units connected in parallel among the plurality of delay sub-units by comparing the phase difference with a reference phase difference, for each delay unit among at least a portion of the plurality of delay units, through the controller, to obtain a target number of delay sub-units connected in parallel.

[0015] An artificial intelligence processor is provided according to at least one embodiment of the present disclosure, including the delay device described above.

[0016] An electronic device is provided according to at least one embodiment of the present disclosure, including a delay device as described above or an artificial intelligence processor as described above.

[0017] For example, the delay device according to at least one embodiment of the present disclosure can ensure the number of phases output by the delay device.

[0018] For example, when some existing DLL circuits adjust the delay by changing the length of the delay chain, the number of phases that the DLL circuit can output will change. However, when adjusting the delay by reducing the length of the delay chain, the number of phases that the DLL circuit can output will decrease, resulting in some phases of the output signal becoming unavailable. For example, according to at least one embodiment of the present disclosure, the delay device can adjust the length of the delay chain in the delay device without adjusting the delay amount. In this way, embodiments of the present disclosure can ensure that the output signal of the required phase is always available.

[0019] The delay device according to at least one embodiment of the present disclosure can reduce the difficulty of implementing the delay device.

[0020] For example, in cases where the adjustment range of an existing DLL circuit is increased by increasing the total length of the delay chain (e.g., the adjustable length of the delay chain), the delay amount corresponding to each delay unit will be extremely small in high-frequency signal scenarios. Since the minimum delay amount of each delay unit is finite (e.g., due to physical factors such as manufacturing processes), the phase-locking process for high-speed or high-frequency signals will be very difficult. However, the delay device according to at least one embodiment of this disclosure can adjust the length of the delay chain in the delay device without needing to do so during the adjustment of the delay amount. Furthermore, the delay device according to at least one embodiment of this disclosure can reduce the difficulty of the phase-locking process by not significantly increasing the total length of the delay chain. In this way, embodiments of this disclosure can reduce the difficulty of the delay device in the phase-locking process.

[0021] The delay device according to at least one embodiment of the present disclosure can reduce the manual cost of delay adjustment and improve the tolerance to process deviations and chip yield. For example, the delay device according to at least one embodiment of the present disclosure can automatically adjust the delay amount without incurring significant manual costs in determining delay configuration parameters.

[0022] For example, in embodiments of this disclosure, delay devices with different PVTs can automatically lock the input signal and determine the corresponding delay amount without requiring manual determination of the delay configuration parameters of the delay device in advance or discarding the corresponding delay device.

[0023] The delay device according to at least one embodiment of the present disclosure can improve the delay adjustment range and accuracy. For example, the delay device according to at least one embodiment of the present disclosure can achieve two-stage adjustment of the delay amount by adjusting both the number of parallel-connected delay sub-units and the control voltage of the delay units. In this way, the delay adjustment range and delay adjustment accuracy of the delay device can be improved. Attached Figure Description

[0024] The above and other aspects, features, and advantages of specific embodiments of the present disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which:

[0025] Figure 1 A schematic diagram of the delay chain is shown.

[0026] Figure 2A A schematic diagram of a delay device according to at least one embodiment of the present disclosure is shown.

[0027] Figure 2B A schematic diagram of a delay chain according to at least one embodiment of the present disclosure is shown.

[0028] Figures 3A-3C A schematic diagram of a delay scenario according to at least one embodiment of the present disclosure is shown.

[0029] Figure 4 A schematic diagram of a process for adjusting the delay amount according to at least one embodiment of the present disclosure is shown.

[0030] Figures 5A to 5C A schematic diagram showing a comparison of phase difference with a reference phase difference according to at least one embodiment of the present disclosure is shown.

[0031] Figure 6 A schematic diagram of a process for adjusting the delay amount according to at least one embodiment of the present disclosure is shown.

[0032] Figure 7 A flowchart of a delay method according to at least one embodiment of the present disclosure is shown.

[0033] Figure 8 A schematic structural diagram of an artificial intelligence processor according to at least one embodiment of the present disclosure is shown.

[0034] Figure 9 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0035] Before proceeding with the detailed description below, it may be advantageous to define certain words and phrases used throughout this disclosure. The terms “comprising” and “including” and their derivatives mean including but not limited to. The term “or” is inclusive, meaning and / or. The phrase “associated with” and its derivatives mean including, comprising, interconnecting, containing, contained within, connected or connected to, coupled or coupled to, communicating with, cooperating, intertwining, juxtaposing, proximate, binding or bound to, having, possessing attributes, having a relationship or being related to, etc. The term “controller” means any device, system, or part thereof that controls at least one operation. Such a controller may be implemented in hardware, or a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, local or remote. The phrase “at least one,” when used with a list of items, means that different combinations of one or more of the listed items may be used, and that only one item from the list may be required. For example, "at least one of A, B, and C" includes any one of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0036] Definitions of other specific words and phrases are provided throughout this disclosure. Those skilled in the art will understand that, in many, if not most, cases, such definitions apply to the prior and future use of the words and phrases thus defined.

[0037] The various embodiments of the principles of this disclosure described below with reference to the accompanying drawings are for illustrative purposes only and should not be construed as limiting the scope of this disclosure in any way. Those skilled in the art will understand that the principles of this disclosure can be implemented in any suitably arranged system or device. In some cases, the actions described in the specification may be performed in a different order and the desired result may still be achieved. Furthermore, the processes depicted in the drawings do not necessarily require a specific order or sequential sequence to achieve the desired result. In certain embodiments, multitasking and parallel processing may be advantageous.

[0038] Figure 1 A schematic diagram of the delay chain is shown. (For example...) Figure 1 As shown, the delay chain 1000 may include multiple delay units connected in series, such as delay unit 1100 to delay unit 1400.

[0039] For example, delay chain 1000 can receive input signal 1001 and delay it to generate output signal 1002. For example, the number of delay chains 1000 can be controlled by adjusting the number of connected delay units. However, such delay control cannot guarantee the output of the desired number of phases and may increase the difficulty of locking onto the input signal.

[0040] Specifically, delay units 1100 to 1400 included in delay chain 1000 can each output a signal delayed by a corresponding phase. For example, the output signal with a corresponding phase output by each delay unit in delay units 1100 to 1400 can be used for subsequent processing. However, when the delay amount of the delay chain is adjusted by operably reducing the length of delay chain 1000 (e.g., disabling a portion of delay units 1100 to 1400), the number of delayed signals output by the remaining delay units will decrease, and their phases may also be undesirable.

[0041] Furthermore, the total number of delay units included in the delay chain 1000 can be increased; for example, the number of delay units included in the delay chain 1000 can be increased to 16. However, increasing the adjustment range and ensuring the phase quantity of the output signal by increasing the delay chain length will be difficult to implement. For example, with a large increase in delay units, the phase-locking process for high-speed or high-frequency signals will be very difficult.

[0042] Figure 2A A schematic diagram of a delay device according to at least one embodiment of the present disclosure is shown. Figure 2B A schematic diagram of a delay chain according to at least one embodiment of the present disclosure is shown. Figures 3A-3C A schematic diagram of a delay scenario according to at least one embodiment of the present disclosure is shown.

[0043] According to at least one embodiment of this disclosure, the delay device 2000 can be implemented in the form of a delay phase-locked loop circuit, but this disclosure is not limited thereto. Figure 2A As shown, the delay device 2000 may include a delay chain 2100, a phase detector 2200, and a controller 2300.

[0044] According to at least one embodiment of this disclosure, delay chain 2100 can be configured to receive an input signal and delay the input signal to generate an output signal. For example, the input signal can be a first clock signal, and the output signal can be a second clock signal delayed by a certain amount. That is, the output signal can have a certain phase difference with the output signal. According to at least one embodiment of this disclosure, delay chain 2100 may include a voltage-controlled delay line (VCDL), but this disclosure is not limited thereto.

[0045] According to at least one embodiment of this disclosure, the delay chain 2100 may include a plurality of delay units connected in series, and each of the plurality of delay units may respectively include a plurality of delay sub-units connected in switchable parallel. Figure 2B As shown, the delay chain 2100 may include n series-connected delay units, such as delay unit 2110, delay unit 2120, ..., delay unit 21n0, where n is a positive integer greater than or equal to 2.

[0046] According to at least one embodiment of this disclosure, each of the plurality of delay units 2110 to 21n0 may respectively include m delay sub-units that are switchably connected in parallel. For example, delay unit 2110 may include m delay sub-units 2111 to 211m that are switchably connected in parallel, delay unit 2120 may include m delay sub-units 2121 to 212m that are switchably connected in parallel, ..., and delay unit 21n0 may include m delay sub-units 21n1 to 21nm that are switchably connected in parallel, where m is a positive integer greater than or equal to 2.

[0047] According to at least one embodiment of this disclosure, such as Figure 2B As shown, each of the n series-connected delay units 2110 to 21n0 may include m delay sub-units that are switchably connected in parallel. For each delay unit, the delay of the corresponding delay unit can be reduced by increasing the number of actually parallel-connected delay sub-units among the m delay sub-units, and the delay of the corresponding delay unit can be increased by reducing the number of actually parallel-connected delay sub-units among the m delay sub-units.

[0048] According to at least one embodiment of this disclosure, phase detector 2200 can be configured to identify the phase difference between the output signal and the input signal of delay chain 2100. For example, phase detector 2200 can receive the phase difference between the input signal and the output signal of delay chain 2100, but this disclosure is not limited thereto. Phase detector 2200 can output the phase difference to controller 2300.

[0049] According to at least one embodiment of this disclosure, the controller 2300 can be configured to adjust the number of delay sub-units connected in parallel among at least a portion of the multiple delay units by comparing a phase difference with a reference phase difference for each delay unit in a plurality of delay units, thereby obtaining a target number of delay sub-units connected in parallel. According to at least one embodiment of this disclosure, the controller 2300 can receive a phase difference from the phase detector 2200. According to at least one embodiment of this disclosure, the reference phase difference can be a desired phase difference of the delay chain; for example, the reference phase difference can be 360 ​​degrees, but this disclosure is not limited thereto.

[0050] According to at least one embodiment of the present disclosure, controller 2300 may include a digital controller, but the present disclosure is not limited thereto.

[0051] According to at least one embodiment of this disclosure, the controller 2300 can be configured to obtain a target number of parallel-connected delay sub-units by adjusting the number of parallel-connected delay sub-units among a subset or all of the multiple delay units. For example, for each delay unit among a subset of the multiple delay units, the controller 2300 can be configured to adjust the delay amount of the corresponding delay unit by adjusting the number of parallel-connected delay sub-units among the multiple delay sub-units of that delay unit. As another example, for each delay unit among all the multiple delay units, the controller 2300 can be configured to adjust the delay amount of the corresponding delay unit by adjusting the number of parallel-connected delay sub-units among the multiple delay sub-units of that delay unit.

[0052] The delay device according to at least one embodiment of the present disclosure can receive an input signal (e.g., an input clock) and generate a delayed output signal (e.g., an output clock). The delay device according to at least one embodiment of the present disclosure eliminates the need to adjust the number of delay units connected in series in the delay chain during the adjustment of the delay amount. Therefore, in scenarios with input signals of different speeds or frequencies, a precise multi-phase clock signal can be output through multiple delay units. Furthermore, since it is not necessary to increase the delay adjustment accuracy by increasing the number of series-connectable delay units, the delay device according to at least one embodiment of the present disclosure is relatively easy to implement.

[0053] According to at least one embodiment of this disclosure, the delay amount generated by the delay unit in the delay chain 2100 can be affected by the control voltage.

[0054] For example, such as Figure 3A As shown, by using a power supply ( Figure 2A Increasing the control voltage (not shown) can improve the driving capability of the delay unit, thereby reducing the delay amount. Conversely, decreasing the control voltage by using a power supply can decrease the driving capability of the delay unit, thereby increasing the delay amount. The delay amount can be adjusted linearly and continuously by changing the control voltage applied to the delay unit. However, the adjustable range corresponding to the control voltage is limited by the swing of the power supply voltage, making it difficult to independently cover a wide frequency range of input signals, from low frequencies (e.g., requiring relatively large delay amounts) to high frequencies (e.g., requiring relatively small delay amounts).

[0055] According to at least one embodiment of this disclosure, the delay amount generated by the delay unit in the delay chain 2100 can be affected by the number of delay sub-units connected in parallel in the delay unit.

[0056] For example, such as Figure 3B As shown, for each delay unit, increasing the number of parallel delay sub-units can improve the driving capability of the delay unit, thereby reducing the delay amount. This allows for adaptation to high-frequency input signals. Conversely, for each delay unit, decreasing the number of parallel delay sub-units can reduce the driving capability of the delay unit, thereby increasing the delay amount. This allows for adaptation to low-frequency input signals.

[0057] In some scenarios, delay configuration parameters can be predetermined. For example, delay configuration parameters may include a mapping relationship between the frequency of the input signal, the number of parallel delay sub-cells, and the corresponding control voltage. During application, the corresponding number of parallel cells and control voltage can be determined based on the frequency of the input signal. However, such a scheme of predetermining delay configuration parameters may exhibit low robustness and low practicality during application. For example, the delay sub-cells in a delay chain may include pairs of complementary metal-oxide-semiconductor (CMOS) devices (e.g., P-channel MOS and N-channel MOS (NMOS) for charging and discharging). However, the delay characteristics of the delay sub-cells are extremely sensitive to process variations, exhibiting significant deviations at different process corners. For example, the delay characteristics of fast-fast (FastNMOS-Fast PMOS, FF) and slow-slow (SlowNMOS-Slow PMOS, SS) process corners may differ significantly from those of typical-typical (Typical NMOS-Typical PMOS, TT) process corners, but this disclosure is not limited to this, and other process corner scenarios exist.

[0058] like Figure 3CAs shown, for any fixed number of parallel-connected delay sub-units, the actual frequency range (i.e., the available bandwidth) that the corresponding delay unit can stably lock onto may change due to process variations. For example, the lower limit of this bandwidth may be determined by the FF process corner with the smallest delay and fastest speed, while the upper limit may be determined by the SS process corner with the largest delay and slowest speed. This causes the continuous frequency range covered by the delay units, including the number of parallel-connected delay sub-units, to change. The above reasons directly result in the inability to reuse predetermined delay configuration parameters, which must be manually reconfigured. Since the effective bandwidth is significantly different under different process corners, the delay configuration parameters predetermined for one process condition (e.g., TT process corner) may not enable the delay device to lock onto the frequency at all under another process corner (e.g., FF or SS process corner), or may be at the edge of a poor-performing bandwidth. Therefore, in order to achieve reliable bandwidth coverage under different process conditions, it is necessary to re-characterize the circuit characteristics, which is time-consuming and complex, and manually determine the delay configuration parameters for each process corner condition. This process not only increases the cost and complexity of design, testing, and calibration, but also makes it impossible for delay devices to adapt to unknown or changing process conditions.

[0059] According to at least one embodiment of the delay device of this disclosure, since the number of parallel-connected delay sub-units in the corresponding delay unit is adjusted by the phase difference between the output signal and the input signal of the delay chain, the manual cost of the delay device in the delay adjustment process can be reduced and the tolerance to process deviations and chip yield can be improved. For example, the delay device according to at least one embodiment of this disclosure can automatically adjust the delay amount without incurring significant manual costs in determining the delay configuration parameters. For example, delay devices with different PVTs can automatically lock the input signal and determine the corresponding delay amount without requiring manual pre-determination of the delay configuration parameters of the delay device or discarding the corresponding delay device.

[0060] Figure 4 A schematic diagram of a process for adjusting the delay amount according to at least one embodiment of the present disclosure is shown. Figure 4 The process of adjusting the delay amount shown in the figure can be achieved by... Figure 2A and Figure 2B The delay device shown is used to perform this. Figures 5A to 5C A schematic diagram showing a comparison of phase difference with a reference phase difference according to at least one embodiment of the present disclosure is shown.

[0061] According to at least one embodiment of this disclosure, the controller (e.g., controller 2300) may also be configured to adjust the number of parallel-connected delay sub-units for each of at least a portion of the delay units by comparing a phase difference with a reference phase difference.

[0062] Figures 5A to 5CA schematic diagram showing a comparison of phase difference with a reference phase difference according to at least one embodiment of the present disclosure is shown. Figure 5A and Figure 5B A schematic diagram is shown where the phase difference between the input signal and the output signal is less than the reference phase difference. Figure 5C A schematic diagram is shown showing that the phase difference between the input signal and the output signal is greater than the reference phase difference.

[0063] According to at least one embodiment of this disclosure, for each of at least a portion of delay units, the controller can adjust the number of delay subunits connected in parallel starting from a maximum number of switchably parallel connections of delay subunits (e.g., m, where m is a positive integer greater than or equal to 2, as described above). According to at least one embodiment of this disclosure, for each of at least a portion of delay units, by adjusting the number of parallel-connected delay subunits starting from the maximum number of switchably parallel connections of delay subunits, adjustment can begin from a relatively small delay amount (e.g., the smallest delay amount at the level of adjusting the delay amount by changing the number of parallel delay subunits). For example, the reference phase difference (e.g., the desired phase difference or delay amount) could be A. For each of at least a portion of delay units, when adjusting the delay amount starting from other numbers (e.g., the minimum number of switchably parallel connections of delay subunits), adjustment can begin from a relatively large delay amount (e.g., the largest delay amount at the level of adjusting the delay amount by changing the number of parallel delay subunits). However, such a large delay can result in a phase difference of A+360 degrees in the delay chain, making it difficult for the phase detector to accurately distinguish the actual delay. By starting the adjustment with a relatively small delay, the delay generated by the delay chain in the initial stage of adjustment can be ensured to be no greater than the reference phase difference A. Furthermore, the delay device can gradually bring the phase difference generated by the delay chain closer to the reference phase difference A during the adjustment process, thereby avoiding the situation where the phase detector cannot accurately distinguish the actual delay.

[0064] According to at least one embodiment of the present disclosure, for each of at least a portion of the delay units, in response to the number of delay sub-units connected in parallel being a maximum number that can be switched to be connected in parallel and the phase difference being greater than a reference phase difference, the controller can determine the maximum number as the target number.

[0065] Reference Figure 4 For each delay unit in at least a subset of the delay units, the controller can adjust the delay amount starting from a maximum number m. When the number of parallel-connected delay sub-units is m and the phase difference is greater than a reference phase difference, the controller can determine the maximum number m as the target number.

[0066] According to at least one embodiment of this disclosure, for each of at least a portion of the delay units, in response to the number of delay sub-units connected in parallel not being the minimum number for switchable parallel connection (e.g., 1) and the phase difference being less than a reference phase difference, the controller can reduce the number of delay sub-units connected in parallel. When the number of delay sub-units connected in parallel is m to 2 (i.e., not the minimum number for switchable parallel connection) and the phase difference is less than a reference phase difference, the controller can reduce the number of delay sub-units connected in parallel.

[0067] Reference Figure 4 For each delay unit in at least a subset of the delay units, the controller can adjust the delay amount starting from a maximum number m. When the number of parallel-connected delay sub-units is m and the phase difference is less than a reference phase difference, the controller can reduce the number of parallel-connected delay sub-units, for example, to m-1. When the number of parallel-connected delay sub-units is m-1 and the phase difference is less than a reference phase difference, the controller can reduce the number of parallel-connected delay sub-units, for example, to m-2. In other cases where the number of parallel-connected delay sub-units is not the minimum number for switchable parallel connection, the number of parallel-connected delay sub-units can be reduced similarly, and will not be described again here.

[0068] According to at least one embodiment of this disclosure, for each of at least a portion of the delay units, in response to the number of parallel-connected delay sub-units not being the maximum number of switchable parallel connections and the phase difference being greater than a reference phase difference, the controller can increase the number of parallel-connected delay sub-units and set the increased number of parallel-connected delay sub-units as a target number. When the number of parallel-connected delay sub-units is adjusted from m to m-1 to 1 (i.e., not the maximum number of switchable parallel connections) and the phase difference is greater than a reference phase difference, the controller can increase the number of parallel-connected delay sub-units and set the increased number of parallel-connected delay sub-units as a target number. For example, when the number of parallel-connected delay sub-units is adjusted from m to m-1 and the phase difference is greater than a reference phase difference, the controller can increase the number of parallel-connected delay sub-units to m and set the increased number of parallel-connected delay sub-units m as a target number. For example, when the number of parallel-connected delay sub-units is adjusted from m to m-2 (e.g., from m to m-1, and further from m-1 to m-2) and the phase difference is greater than the reference phase difference, the controller can increase the number of parallel-connected delay sub-units to m-1, and use the increased number of parallel-connected delay sub-units m-1 as the target number. In other cases where the number of parallel-connected delay sub-units is not the maximum number m that can be switchably connected in parallel, the number of parallel-connected delay sub-units can be increased similarly, and the target number can be determined; these will not be described again here.

[0069] According to at least one embodiment of this disclosure, for each of at least a portion of the delay units, in response to the number of delay sub-units connected in parallel being the minimum number that can be switched to be connected in parallel and the phase difference being less than a reference phase difference, the controller can determine the minimum number as the target number. For each of the at least a portion of the delay units, the controller can adjust the delay amount starting from the maximum number m and gradually reduce the number of parallel units to 1. When the number of delay sub-units connected in parallel is 1 and the phase difference is less than the reference phase difference, the controller can determine the minimum number 1 as the target number.

[0070] According to at least one embodiment of this disclosure, the process of determining the target number of parallel-connected delay sub-units through the above-described adjustment process for each of at least a portion of the delay units can cover scenarios with input signals of different frequencies.

[0071] According to at least one embodiment of this disclosure, for a scenario with a high-frequency input signal, for a single delay unit, if the number of delay sub-units connected in parallel is the maximum number that can be switched to be connected in parallel and the phase difference is still greater than the reference phase difference, it indicates that the current delay amount is still large. In this case, the controller can determine the maximum number as the target number and reduce the delay amount by adjusting the control voltage (e.g., gradually increasing it).

[0072] According to at least one embodiment of this disclosure, for a scenario with an intermediate frequency input signal, for a single delay unit, during a scan process that gradually decreases from the maximum number of switchably connected parallel units, in response to the number of parallel-connected delay sub-units not being the maximum number of switchably connected parallel units and the phase difference being greater than a reference phase difference, the controller can increase the number of parallel-connected delay sub-units (i.e., revert to the previous number of parallel-connected delay sub-units), and set the increased number of parallel-connected delay sub-units as a target number. After determining the target number, the controller can reduce the delay amount by adjusting the control voltage.

[0073] According to at least one embodiment of this disclosure, for a low-frequency input signal scenario, for a single delay unit, if the number of delay sub-units connected in parallel is the minimum number that can be switched to be connected in parallel and the phase difference is still less than the reference phase difference, it indicates that the current delay amount is still small. In this case, the controller can determine the minimum number as the target number and increase the delay amount by adjusting the control voltage (e.g., gradually decreasing it).

[0074] According to at least one embodiment of this disclosure, for each of the at least a subset of delay units, the controller can maintain the control voltage of the corresponding delay unit at a predetermined voltage while adjusting the number of parallel-connected delay sub-units. That is, the control voltage of the corresponding delay unit can remain fixed while adjusting the number of parallel-connected delay sub-units.

[0075] According to at least one embodiment of this disclosure, the predetermined voltage can be less than the maximum control voltage of the delay unit. By setting the predetermined voltage to be less than the maximum control voltage of the corresponding delay unit, the smoothness of delay adjustment can be increased, and delay jumps can be avoided or mitigated. For example, since the predetermined voltage is not the maximum control voltage, once the number of parallel-connected delay sub-units is determined, when a reduction in delay is needed (e.g., due to changes in environmental factors such as temperature), the control voltage can be increased without increasing the number of parallel-connected delay sub-units. By avoiding frequent adjustments to the number of parallel-connected delay sub-units due to changes in environmental factors during use, delay jumps can be avoided or mitigated. Furthermore, according to at least one embodiment of this disclosure, if the frequency of the input signal changes, the delay can be adjusted by further changing the number of parallel-connected corresponding delay sub-units.

[0076] According to at least one embodiment of this disclosure, the difference between a predetermined voltage and the maximum control voltage of the delay unit can be less than a predetermined threshold and greater than zero. For example, the predetermined threshold can be 10%, 20%, or 30% of the maximum control voltage, and this disclosure is not limited thereto. That is, the predetermined voltage can be a relatively large control voltage. According to at least one embodiment of this disclosure, for each delay unit in at least a portion of the delay units, by adjusting the number of parallel-connected delay sub-units under a relatively large control voltage, the adjustment of the number of parallel-connected delay sub-units can begin at a relatively small delay amount. For example, the reference phase difference (e.g., the desired phase difference or delay amount) can be A. For each delay unit in at least a portion of the delay units, when adjusting the delay amount under a relatively small control voltage, the adjustment of the number of parallel-connected delay sub-units can begin at a relatively large delay amount. However, such a large delay amount can result in a phase difference of A+360 degrees generated by the delay chain, making it difficult for the phase detector to accurately distinguish the actual delay amount. By starting the adjustment from a relatively small delay amount, the delay amount generated by the delay chain at the beginning of the adjustment can be made no greater than the reference phase difference A. Furthermore, the delay device can gradually bring the phase difference generated by the delay chain closer to the reference phase difference A during the adjustment process, thereby avoiding the situation where the phase detector has difficulty in accurately distinguishing the actual delay amount.

[0077] Figure 6 A schematic diagram of a process for adjusting the delay amount according to at least one embodiment of the present disclosure is shown. Figure 6 The process of adjusting the delay amount shown in the figure can be achieved by... Figure 2A and Figure 2B The delay device shown is used to perform this.

[0078] According to at least one embodiment of this disclosure, for each of at least a portion of the delay units, in response to obtaining a target number of parallel-connected delay sub-units, the controller can adjust the control voltage of the delay unit by comparing a phase difference with a reference phase difference. That is, after determining the target number, the controller can further adjust the delay amount by adjusting the control voltage of the delay unit. The controller can output a first signal to the delay chain to control the number of parallel-connected delay sub-units in the corresponding delay unit, and output a second signal to the delay chain to control the control voltage of the corresponding delay unit. The delay device according to at least one embodiment of this disclosure can achieve two-stage adjustment of the delay amount by adjusting both the number of parallel-connected delay sub-units and the control voltage of the delay unit. In this way, the delay adjustment range and delay adjustment accuracy of the delay device can be improved.

[0079] According to at least one embodiment of this disclosure, such as Figure 6 As shown, for each of at least a portion of the delay units, in response to a phase difference less than a reference phase difference, the controller reduces the control voltage of the delay unit.

[0080] like Figure 6 As shown, for each delay unit in at least a subset of delay units, in response to a phase difference greater than a reference phase difference, the controller can increase the control voltage of the delay unit. According to at least one embodiment of this disclosure, after determining the target quantity, the controller can adjust the control voltage from a predetermined voltage. For example, a phase detector can continuously generate a phase difference, and the controller can continuously compare the phase difference with the reference phase difference, thereby adjusting the delay amount by changing the control voltage. By repeating the above control voltage changing process, the controller can gradually bring the delay amount of the delay chain closer to the desired delay amount. Since the control voltage adjustment process is performed after the target quantity is determined, when the delay device enters a locked state, the control voltage can periodically jump between two adjacent control voltage values ​​(adjacent voltage control code values), causing the phase difference to oscillate slightly around the locked point. In this way, the delay device can maintain dynamic stability.

[0081] Figure 7 A flowchart of a delay method according to at least one embodiment of the present disclosure is shown. Figure 7 As shown, method 7000 may include steps S7100 to S7300. Method 7000 can be used with a delay device, and is executed by the delay device, which may include reference... Figures 2A to 2B The delay device described. For example, the delay device may include a delay chain, a phase detector, and a controller.

[0082] In step S7100, an input signal can be received through a delay chain, and the input signal can be delayed to generate an output signal. The delay chain includes multiple delay units connected in series, and each of the multiple delay units includes multiple delay sub-units that are switchably connected in parallel.

[0083] In step S7200, the phase difference between the output signal and the input signal of the delay chain can be identified by a phase detector.

[0084] In step S7300, the controller can adjust the number of delay sub-units connected in parallel among the multiple delay sub-units by comparing the phase difference with the reference phase difference for each delay sub-unit among at least a portion of the multiple delay units, so as to obtain the target number of delay sub-units connected in parallel.

[0085] The delay method according to at least one embodiment of the present disclosure further includes, via the controller, for each of at least a portion of the plurality of delay units: in response to the number of delay sub-units connected in parallel not being the minimum number of switchable parallel connections and the phase difference being less than a reference phase difference, reducing the number of delay sub-units connected in parallel; or in response to the number of delay sub-units connected in parallel not being the maximum number of switchable parallel connections and the phase difference being greater than a reference phase difference, increasing the number of delay sub-units connected in parallel; and setting the increased number of delay sub-units connected in parallel as a target number.

[0086] The delay method according to at least one embodiment of the present disclosure further includes, via the controller, adjusting the number of delay sub-units connected in parallel, starting from a maximum number of switchably connected delay sub-units, for each of at least a portion of the plurality of delay units.

[0087] The delay method according to at least one embodiment of the present disclosure further includes, via the controller, for each of at least a portion of the plurality of delay units: in response to a situation where the number of delay sub-units connected in parallel is not the maximum number that can be switched to be connected in parallel and the phase difference is greater than a reference phase difference, increasing the number of the delay sub-units connected in parallel to obtain a target number.

[0088] The delay method according to at least one embodiment of the present disclosure further includes, via the controller, determining, for each delay unit among at least a portion of the plurality of delay units, the maximum number as a target number in response to the number of delay subunits connected in parallel being a switchably maximum number of parallel connections and the phase difference being greater than a reference phase difference.

[0089] The delay method according to at least one embodiment of the present disclosure further includes, via the controller, determining, for each delay unit among at least a portion of the plurality of delay units, the minimum number as a target number in response to the number of delay subunits connected in parallel being a minimum number that can be switched in parallel and the phase difference being less than a reference phase difference.

[0090] The delay method according to at least one embodiment of the present disclosure further includes, via the controller, maintaining the control voltage of the delay unit at a predetermined voltage for each of at least a portion of the plurality of delay units while adjusting the number of the delay sub-units connected in parallel.

[0091] According to at least one embodiment of the delay method of the present disclosure, the predetermined voltage is less than the maximum control voltage of the delay unit, and the difference between the predetermined voltage and the maximum control voltage of the delay unit is less than a predetermined threshold and greater than zero.

[0092] The delay method according to at least one embodiment of the present disclosure further includes, via the controller, adjusting the control voltage of each delay unit for at least a portion of the plurality of delay units by comparing the phase difference with a reference phase difference in response to obtaining a target number of parallel-connected delay sub-units.

[0093] The delay method according to at least one embodiment of the present disclosure further includes, via the controller, for each of at least a portion of the plurality of delay units: decreasing the control voltage of the delay unit in response to the phase difference being less than a reference phase difference; and increasing the control voltage of the delay unit in response to the phase difference being greater than a reference phase difference.

[0094] Figure 8 A schematic structural diagram of an artificial intelligence processor according to at least one embodiment of the present disclosure is shown.

[0095] Artificial intelligence processors may include graphics processing units (GPUs), general-purpose graphics processing units (GPGPUs), tensor processing units (TPUs), deep learning processing units (DPUs), accelerated processing units (APUs), neural network processing units (NPUs), application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs), but this disclosure is not limited thereto.

[0096] like Figure 8 As shown, an example of an artificial intelligence processor is an array of programmable multiprocessors that can be used in the latency methods of this disclosure. For example, the programmable multiprocessors of this artificial intelligence processor can be a Streaming Processor Cluster (SPC), such as including streaming processor cluster 1, ..., streaming processor cluster M as shown in the figure, where M is a positive integer greater than 1. In the artificial intelligence processor, one streaming processor cluster processes one computational task, or multiple streaming processor clusters process one computational task. Multiple streaming processor clusters share data through a global cache or global memory.

[0097] like Figure 8 As shown, taking streaming processor cluster 1 as an example, one streaming processor cluster includes multiple computing units, such as... Figure 8 The system is structured as Computation Unit 1, Computation Unit 2, ..., Computation Unit N, where N is a positive integer. Each Computation Unit (CU) performs arithmetic and logical operations, such as accumulation, reduction, and standard addition, subtraction, multiplication, and division. A Computation Unit includes multiple Cores (also called computational cores), each of which includes an Arithmetic Logic Unit (ALU), a floating-point unit, etc. These Cores are used to execute specific computational tasks. Furthermore, a Computation Unit may also include registers (e.g., ...). Figure 8 The register file and shared memory in a computing unit are used to store source and destination data related to computing tasks in a hierarchical manner. The shared memory in a computing unit is used to share data between the cores of that computing unit.

[0098] like Figure 8 As shown, each computing unit also provides a tensor core for performing tensor-related computations, such as tensor shrinking operations. Tensor cores can accelerate tensor operations such as matrix multiplication. Tensor cores in multiple computing units can be scheduled and controlled uniformly.

[0099] like Figure 8 As shown, each streaming processor cluster also provides a buffer for caching data from the N computing units within the streaming processor cluster.

[0100] In parallel computing, computational tasks are typically executed through multiple threads. These threads are divided into multiple thread blocks before execution in the artificial intelligence processor (or general-purpose graphics processor or parallel computing processor), and then dispatched via a thread block dispatch module. Figure 8 (Not shown in the diagram) Multiple thread blocks are distributed to various computing units. All threads in a thread block must be assigned to the same computing unit for execution. Simultaneously, thread blocks are divided into minimum execution thread bundles (or simply thread bundles, warps), each containing a fixed number (or less than this fixed number) of threads, for example, 32 threads. Multiple threads from multiple thread blocks can execute on multiple computing cores within the same computing unit, or on multiple computing cores in different computing units, sharing registers, shared memory, etc., for data transfer. The delay method according to at least one embodiment of this disclosure can be executed by a single thread bundle.

[0101] In each computing unit, the thread beam scheduling / distribution module ( Figure 8 (Not shown in the diagram) Thread bundles are scheduled and allocated so that multiple computing cores within the computing unit can run thread bundles. Depending on the number of computing cores in the computing unit, multiple thread bundles within a thread block can execute concurrently or in a time-sharing manner. Multiple threads within each thread bundle execute the same instructions. Memory-executed instructions are issued to shared memory within the computing unit or further issued to intermediate-level caches, global caches, or global memory (e.g., [example cache]). Figure 8 It is used for reading and writing operations in high-bandwidth memory (HBM).

[0102] The delay device according to at least one embodiment of the present disclosure may include: Figure 8 In the artificial intelligence processor shown. The delay method according to at least one embodiment of this disclosure can be... Figure 8The artificial intelligence processor shown performs the operation. However, the disclosure is not limited thereto. The delay device according to at least one embodiment of the present disclosure may be included in a system-on-a-chip (SOC), and the delay method according to at least one embodiment of the present disclosure may be executed by the SOC.

[0103] Figure 9 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure is shown.

[0104] like Figure 9 As shown, the electronic device 300 is, for example, suitable for implementing the data transmission method for an artificial intelligence processor provided in embodiments of this disclosure. It should be noted that... Figure 9 The components of the electronic device 300 shown are merely exemplary and not limiting. The electronic device 300 may have other components as needed for the actual application.

[0105] For example, such as Figure 9 As shown, in some examples, electronic device 300 includes a processing device (e.g., including as referenced). Figure 4 Artificial intelligence processors, such as parallel processors like graphics processing units (GPUs) and general-purpose graphics processing units (GPRS), or including... Figures 2A-2B The delay device 301 shown can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 302 or a program loaded from a storage device 308 into a random access memory (RAM) 303 to achieve various functions, such as performing the delay method provided in at least one embodiment of the present disclosure.

[0106] For example, when the computer-readable instructions are executed by the processing device 301, one or more steps of the delay method according to any of the above embodiments can be performed. It should be noted that a detailed description of the processing procedure of the delay method can be found in the relevant descriptions in the embodiments of the delay method described above, and repeated details will not be repeated here.

[0107] RAM 303 also stores various programs and data required for the operation of the computer system. Processing device 301, ROM 302, and RAM 303 are connected via bus 304. Input / output (I / O) interface 305 is also connected to bus 304.

[0108] For example, the memory may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) 303 and / or cache memory, etc., whereby computer-readable instructions can be loaded from storage device 308 into RAM 303 to execute. Non-volatile memory may include, for example, read-only memory (ROM) 302, hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB storage, flash memory, etc. Various applications and various data, such as style images, and various data used and / or generated by the applications, may also be stored in the computer-readable storage medium.

[0109] Typically, the following devices can be connected to I / O interface 305: input devices 306 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 307 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 308 including, for example, magnetic tapes, hard disks, flash memory, etc.; and communication devices 309. Communication device 309 allows electronic device 300 to communicate wirelessly or wiredly with other electronic devices to exchange data. Drive 310 is also connected to I / O interface 305 as needed. Removable media 311, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 310 as needed so that computer programs read from them can be installed into storage device 308 as needed. Although Figure 9 An electronic device 300 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively. For example, a processing device 301 may control other components in the electronic device 300 to perform desired functions. The processing device 301 may be a device with data processing and / or program execution capabilities, such as a central processing unit (CPU), a general-purpose graphics processing unit (GPGPU), a parallel processor, an artificial intelligence processor, a tensor processor (TPU), or a graphics processing unit (GPU). The CPU may be based on an x86 or ARM architecture, etc. The GPU may be integrated directly onto the motherboard or built into the motherboard's northbridge chip. Alternatively, the GPU may be built into the CPU.

[0110] For example, the electronic device 300 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 309 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0111] For example, electronic device 300 can be any device such as mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, etc., or any combination of electronic devices and hardware. The embodiments disclosed herein do not limit this.

[0112] For example, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For instance, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication device 309, or installed from storage device 308, or installed from ROM 302. When the computer program is executed by processing device 301, the aforementioned delay method defined in the methods of embodiments of this disclosure is performed.

[0113] According to at least one embodiment of this disclosure, the electronic device 300 may include the artificial intelligence processor or delay device described in the above embodiments.

[0114] It should be noted that the computer-readable medium described above in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In embodiments of this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In embodiments of this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0115] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device. For example, a computer-readable storage medium provided according to at least one embodiment of the present disclosure may store instructions thereon that, when executed by one or more processors, cause the processors to perform the methods described above.

[0116] The delay device according to at least one embodiment of the present disclosure can ensure the number of phases output by the delay device. For example, when some DLL circuits adjust the delay amount by changing the length of the delay chain, the number of phases that the DLL circuit can output will change. For example, in the process of adjusting the delay amount by reducing the length of the delay chain, the number of phases that the DLL circuit can output will decrease, thereby causing the output signal with some phases to be unavailable. The delay device according to at least one embodiment of the present disclosure can adjust the length of the delay chain in the delay device without adjusting it during the adjustment of the delay amount. In this way, it can be ensured that the output signal of the required phase is always available.

[0117] The delay device according to at least one embodiment of the present disclosure can reduce the implementation difficulty of the delay device. For example, in schemes that increase the adjustment range of the DLL circuit by increasing the total length of the delay chain (e.g., the adjustable length of the delay chain), the phase-locking process for high-speed or high-frequency signals will be very difficult. The delay device according to at least one embodiment of the present disclosure can adjust the length of the delay chain in the delay device without adjusting the delay amount. Furthermore, the delay device according to at least one embodiment of the present disclosure can reduce the difficulty of the phase-locking process of the delay device without significantly increasing the total length of the delay chain.

[0118] The delay device according to at least one embodiment of the present disclosure can reduce the manual cost of delay adjustment and improve the tolerance to process deviations and chip yield. For example, the delay device according to at least one embodiment of the present disclosure can automatically adjust the delay amount without incurring significant manual costs in determining the delay configuration parameters. For example, delay devices with different PVTs can automatically lock the input signal and determine the corresponding delay amount without requiring manual pre-determination of the delay configuration parameters or discarding the corresponding delay device.

[0119] The delay device according to at least one embodiment of the present disclosure can improve the delay adjustment range and accuracy. For example, the delay device according to at least one embodiment of the present disclosure can achieve two-stage adjustment of the delay amount by adjusting both the number of parallel-connected delay sub-units and the control voltage of the delay units. In this way, the delay adjustment range and delay adjustment accuracy of the delay device can be improved.

[0120] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0121] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0122] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0123] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0124] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0125] The following points should be noted regarding this disclosure:

[0126] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0127] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0128] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A delay device, characterized in that, include: A delay chain is configured to receive an input signal and delay the input signal to generate an output signal, wherein the delay chain includes a plurality of delay units connected in series, and each of the plurality of delay units includes a plurality of delay sub-units that are switchably connected in parallel; A phase detector is configured to identify the phase difference between the output signal and the input signal of the delay chain; as well as The controller is configured to adjust the number of delay sub-units connected in parallel among the plurality of delay sub-units by comparing the phase difference with a reference phase difference for each delay sub-unit among at least a portion of the plurality of delay sub-units, so as to obtain a target number of delay sub-units connected in parallel.

2. The delay device according to claim 1, characterized in that, The controller is also configured to, for each of at least a subset of the plurality of delay units: In response to the fact that the number of delay sub-units connected in parallel is not the minimum number that can be switched to be connected in parallel and the phase difference is less than the reference phase difference, the number of delay sub-units connected in parallel is reduced; or In response to the fact that the number of parallel-connected delay sub-units is not the maximum number that can be switched to be connected in parallel and the phase difference is greater than the reference phase difference, the number of the parallel-connected delay sub-units is increased.

3. The delay device according to claim 1, characterized in that, The controller is also configured to, for each of at least a subset of the plurality of delay units: The number of delay sub-units connected in parallel is adjusted starting from the maximum number of switchable parallel connections of the delay sub-units.

4. The delay device according to claim 3, characterized in that, The controller is also configured to, for each of at least a subset of the plurality of delay units: In response to the fact that the number of delay sub-units connected in parallel is not the maximum number that can be switched to be connected in parallel and the phase difference is greater than the reference phase difference, the number of the delay sub-units connected in parallel is increased; as well as The target number is the number of additional parallel-connected delay sub-units.

5. The delay device according to claim 1, characterized in that, The controller is also configured to, for each of at least a subset of the plurality of delay units: In response to the number of delay sub-units connected in parallel being the maximum number that can be switched in parallel and the phase difference being greater than the reference phase difference, the maximum number is determined as the target number.

6. The delay device according to claim 1, characterized in that, The controller is also configured to, for each of at least a subset of the plurality of delay units: In response to the number of delay sub-units connected in parallel being the minimum number that can be switched in parallel and the phase difference being less than the reference phase difference, the minimum number is determined as the target number.

7. The delay device according to claim 1, characterized in that, The controller is also configured to, for each of at least a subset of the plurality of delay units: During the adjustment of the number of the delay sub-units connected in parallel, the control voltage of the delay unit is maintained at a predetermined voltage.

8. The delay device according to claim 7, characterized in that, The predetermined voltage is less than the maximum control voltage of the delay unit, and the difference between the predetermined voltage and the maximum control voltage of the delay unit is less than a predetermined threshold and greater than zero.

9. The delay device according to claim 1, characterized in that, The controller is also configured to, for each of at least a subset of the plurality of delay units: In response to obtaining the target number of parallel-connected delay sub-units, the control voltage of the delay unit is adjusted by comparing the phase difference with a reference phase difference.

10. The delay device according to claim 9, characterized in that, The controller is also configured to, for each of at least a subset of the plurality of delay units: In response to the phase difference being less than the reference phase difference, the control voltage of the delay unit is reduced; and In response to the phase difference being greater than the reference phase difference, the control voltage of the delay unit is increased.

11. A delay method for a delay device, characterized in that, The delay device includes a delay chain, a phase detector, and a controller; the method includes: The delay chain receives an input signal and delays the input signal to generate an output signal. The delay chain includes multiple delay units connected in series, and each of the multiple delay units includes multiple delay sub-units that are switchably connected in parallel. The phase detector identifies the phase difference between the output signal and the input signal of the delay chain; and The controller adjusts the number of parallel-connected delay sub-units among at least a portion of the multiple delay units by comparing the phase difference with a reference phase difference for each delay unit, thereby obtaining a target number of parallel-connected delay sub-units.

12. An artificial intelligence processor, characterized in that, Includes the delay device as described in any one of claims 1-10.

13. An electronic device, characterized in that, Includes the delay device as described in any one of claims 1-10 or the artificial intelligence processor as described in claim 12.

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