Structural silicon fluid interconnection 3D integrated packaging structure and preparation method
By using a structured silicon fluid interconnect 3D integrated packaging structure, the problems of high interface thermal resistance, high risk of fluid interface sealing, and height difference in 3D IC packaging are solved, achieving efficient heat dissipation and high reliability, and improving the overall performance of the packaging system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- PEKING UNIV
- Filing Date
- 2026-01-05
- Publication Date
- 2026-05-19
AI Technical Summary
Existing 3D IC packaging technologies suffer from high interface thermal resistance, significant sealing risks at the fluid interface of thin adapter boards, and challenges related to differences in 3D stacking height and fluid interconnection, resulting in low heat dissipation efficiency and poor reliability.
A structured silicon fluid interconnect 3D integrated packaging structure is adopted, which connects the logic chip and the microchannel heat dissipation adapter through a hybrid bonding process. The structured silicon pad is used as a fluid transport manifold, and the high thermal conductivity medium connection of all silicon/copper is realized in the packaging structure. The fluid interface sealing interface is transferred to the top surface of the thicker structured silicon pad, and an integrated fluid transport path is designed.
It achieves near-junction cooling, reduces interfacial thermal resistance, improves the manufacturing yield and long-term reliability of the packaging system, increases volume utilization and integration, reduces the risk of short circuits caused by fluid leakage, and has excellent material compatibility and structural reliability.
Smart Images
Figure CN122069734A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of advanced packaging technology for semiconductor integrated circuits, and in particular to a structured silicon fluid interconnect 3D integrated packaging structure and its fabrication method. Background Technology
[0002] With the rapid development of high-performance computing (HPC), artificial intelligence (AI), and big data technologies, the slowdown of Moore's Law has prompted the semiconductor industry to shift towards three-dimensional integrated circuit (3D IC) technology. By vertically stacking high-bandwidth memory (HBM / DRAM) directly on top of logic dies, interconnect bandwidth can be significantly improved and latency reduced. However, this high-density 3D stacking structure presents extremely high heat flux challenges. In particular, the bottom logic dies, as the primary heat source, are covered by memory dies, obstructing heat dissipation paths; while the upper memory dies (especially DRAM) are typically extremely temperature-sensitive (e.g., operating temperatures must usually be controlled below 85°C or 95°C), and overheating will severely impact data retention time and system stability. Therefore, efficient thermal management for 3D heterogeneous integrated systems has become a critical issue that urgently needs to be addressed.
[0003] To address the challenge of high heat flux heat dissipation, embedded microfluidic liquid cooling technology is considered one of the most promising solutions. This technology typically involves etching microfluidic channels inside a silicon substrate, allowing coolant to flow directly beneath or near the heat source to remove heat. However, existing microfluidic packaging technologies suffer from high interfacial thermal resistance due to the connection method between the logic chip and the silicon substrate. Furthermore, designing fluid input / output (I / O) interconnects on the silicon substrate presents significant engineering risks, and the height difference caused by 3D stacking presents challenges for fluid interconnection. Summary of the Invention
[0004] The main objective of this invention is to provide a structured silicon fluid interconnect 3D integrated packaging structure and its fabrication method, aiming to solve at least one of the above-mentioned technical problems.
[0005] To achieve the above objectives, this invention proposes a structured silicon fluid interconnect 3D integrated packaging structure, comprising: a microchannel heat dissipation adapter plate, wherein the microchannel heat dissipation adapter plate has a microchannel structure inside; a logic chip, wherein the active surface of the logic chip faces the microchannel heat dissipation adapter plate and is directly connected to the microchannel heat dissipation adapter plate through a hybrid bonding dielectric layer; a memory chip stack, wherein the memory chip stack is vertically stacked above the back side of the logic chip; a structured silicon pad, wherein the structured silicon pad is arranged around the logic chip stack and is located on the front side of the microchannel heat dissipation adapter plate; wherein the structured silicon pad has a vertically penetrating fluid input via and a fluid output via inside; the bottom of the fluid input via communicates with the inlet of the microchannel structure, and the bottom of the fluid output via communicates with the outlet of the microchannel structure; wherein the top surface of the structured silicon pad is flush with the top surface of the memory chip stack.
[0006] In some embodiments of the present invention, the microchannel heat dissipation adapter plate includes a first silicon wafer and a second silicon wafer arranged opposite each other. The microchannel structure is formed on the opposing surfaces of the first silicon wafer and the second silicon wafer by an etching process. The first silicon wafer and the second silicon wafer are formed into an integrated structure by silicon-silicon direct bonding.
[0007] In some embodiments of the present invention, the structured silicon fluid interconnect 3D integrated packaging structure further includes a packaging structure, which is pressed onto the top surface of the structured silicon pad by a sealing gasket, and the sealing gasket is disposed around the fluid inlet or fluid outlet through-hole.
[0008] In some embodiments of the present invention, the packaging structure has a coolant interface integrally formed on the fluid inlet and fluid outlet through-holes respectively.
[0009] In some embodiments of the present invention, the hybrid bonding medium layer between the logic chip and the microfluidic heat dissipation adapter is Cu-Cu diffusion bonding and SiO2-SiO2 covalent bonding.
[0010] In some embodiments of the present invention, the microchannel structure is selected from one of the following: straight-through microchannel, microneedle-fin microchannel, and manifold-type microchannel.
[0011] In some embodiments of the present invention, the structured silicon fluid interconnect 3D integrated packaging structure further includes: an organic substrate connected to the back side of the microchannel heat dissipation adapter plate; and a PCB motherboard connected to the back side of the organic substrate.
[0012] To achieve the above objectives, the present invention also proposes a method for fabricating the above-mentioned silicon fluid interconnect 3D integrated packaging structure, comprising the following steps: A microchannel heat dissipation adapter plate with an embedded microchannel structure is prepared; logic chips are bonded to the microchannel heat dissipation adapter plate using a hybrid bonding process; a structural silicon pad with fluid input vias and fluid output vias is installed on the front side of the microchannel heat dissipation adapter plate and around the logic chips; memory chips are stacked on the logic chips to obtain a memory chip stack.
[0013] In some embodiments of the present invention, the bonding of logic chips to the microchannel heat dissipation adapter plate via a hybrid bonding process includes the following steps: preparing Cu-SiO2 hybrid bonding interfaces on the top surface of the microchannel heat dissipation adapter plate and the top surface of the logic chips respectively; achieving surface planarization of the Cu-SiO2 hybrid bonding interfaces by chemical mechanical polishing; flip-chip aligning the logic chips with the microchannel heat dissipation adapter plate, pre-bonding at room temperature, and then performing thermal annealing to achieve Cu-Cu diffusion bonding and SiO2-SiO2 covalent bonding.
[0014] In some embodiments of the present invention, the mounting of the structural silicon pad and the stacking of the memory chips include the following steps: Fabricate a structured silicon pad with fluid inlet and fluid outlet vias; bond or mount the structured silicon pad to a preset area of the adapter board to ensure that the fluid inlet and fluid outlet vias are precisely aligned with the inlet and outlet of the microchannel structure, respectively; vertically stack multiple layers of memory chips on the back side of the logic chip using microbumping or hybrid bonding processes.
[0015] Compared with the prior art, the present invention achieves the following technical effects: 1. Eliminating interfacial thermal resistance and achieving true "near-junction cooling": Unlike the existing technology that commonly uses "microbumps + bottom filler" to connect the chip and the heat dissipation substrate, this invention uses a hybrid bonding process. This technology completely eliminates the solder layer and low thermal conductivity organic adhesive layer located between the active area (heat source) of the logic chip and the cooling channel, shortening the heat conduction path to the micrometer level and achieving a high thermal conductivity all-silicon / copper medium connection. This significantly reduces interfacial thermal resistance, allowing the cooling medium to more directly and efficiently remove the heat generated by the high heat flux logic chip, thus greatly reducing the chip junction temperature.
[0016] 2. Solved the sealing and stress risk problem of fluid interface in thin adapter boards: This invention innovatively utilizes a structural silicon gasket as a vertical manifold for fluid transmission. Unlike existing technologies that require direct mechanical pressure to be applied to the surface of an extremely thin (e.g., <100μm) adapter board filled with precision circuits for sealing, this invention transfers the sealing interface of the fluid interface to the top surface of a thicker, higher mechanical strength structural silicon gasket. This design successfully achieves physical decoupling between "mechanical sealing stress" and "electrical interconnection structure," avoiding the risk of electrical layer breakage or damage to the adapter board due to the installation of sealing joints, and significantly improving the manufacturing yield and long-term reliability of the packaging system.
[0017] 3. Improved volume utilization and integration of 3D stacked packaging: To address the chip height difference problem caused by Logic+DRAM stacking, the structural silicon pad in this invention not only plays the traditional role of "mechanical leveling" and "support", but is also endowed with an active function of fluid transport. This integrated design avoids the need to arrange complex lateral pipelines or occupy substrate area to arrange independent fluid connectors on the periphery of the package, making the package structure more compact, improving the volume utilization of the system, and facilitating high-density deployment in confined spaces such as servers.
[0018] 4. Excellent material compatibility and structural reliability: Unlike existing technologies that use glass wafers bonded to silicon substrates, the microchannel heat dissipation adapter and structural silicon pads of this invention are made of homogeneous single-crystal silicon material. This means that the entire packaging structure has perfect coefficient of thermal expansion (CTE) matching. Under the severe thermal cycling generated by the high-power operation of the chip, thermal stress caused by material mismatch will not cause the bonding layer to crack or warp. In addition, the Si-Si bonding channel without dielectric layer has a bonding strength much higher than that of glass bonding, and can withstand higher fluid pressure (>50 bar), allowing the use of higher flow rates of working fluid to further improve heat dissipation performance.
[0019] 5. Reduced risk of short circuit due to fluid leakage: The fluid transmission path of this invention is strictly limited to the vertical through-holes of the structured silicon pad and the deep buried channels inside the adapter board. The fluid channel and the electrical connection area of the logic chip / memory chip are highly isolated in physical space. Even if a small amount of leakage occurs at the interface, the leakage point is located on the structured silicon surface at the top of the package, rather than directly contacting the dense electrical pads on the bottom layer, thereby minimizing the risk of short circuit and burnout caused by leakage. Attached Figure Description
[0020] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a schematic diagram of the overall structure of the silicon fluid interconnect 3D integrated packaging structure of the present invention; Figure 2 This is a top view of the silicon fluid interconnect 3D integrated packaging structure of the present invention; Figure 3 This is a schematic diagram showing some structural details between the logic chip and the microchannel heat dissipation adapter plate of the present invention; Figure 4 This is a detailed schematic diagram of the fluid interface of the silicon pad structure of the present invention; Figure 5 This is a schematic diagram of a straight-through microchannel structure; Figure 6 This is a schematic diagram of the microneedle fin microchannel structure; Figure 7 This is a schematic diagram of a manifold-type microchannel structure; Figures 8-13 This is a process flow diagram of the preparation method of the present invention.
[0021] The reference numerals in the attached diagram represent the following: 1. Microchannel heat dissipation adapter plate; 100. Microchannel structure; 103. Through-silicon via; 2. Logic chip; 201. Active region; 3. Memory chip stack; 4. Structural silicon pad; 401. Fluid input via; 402. Fluid output via; 5. Package structure; 501. Coolant interface; 502. Sealing gasket; 503. Groove; 6. Organic substrate; 7. PCB motherboard; 8. C2 solder ball; 9. C4 solder ball; 10. C2 microbump; 11. Cu bump; 12. Redistribution layer; 13. Solder sealing ring; 14. Hybrid bonding dielectric layer. Detailed Implementation
[0022] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.
[0023] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0024] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. Furthermore, in the description of this application, unless otherwise stated, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.
[0025] In existing technologies, microfluidic encapsulation technology mainly suffers from the following problems: First, the interface thermal resistance is too high. Most existing microfluidic packaging structures use traditional flip-chip technology, where the chip is connected to the microfluidic heat dissipation substrate via microbumps and underfill adhesive. This connection method introduces a thermal resistance layer composed of solder, polymer colloid, and multiple passivation layers between the chip's active area and the cooling medium. For advanced node chips with heat flux exceeding several hundred watts per square centimeter, this interface thermal resistance becomes a heat dissipation bottleneck, making it difficult to achieve true "near-junction cooling."
[0026] Secondly, achieving reliable fluid input / output (I / O) interconnects on extremely thin interposer boards presents significant engineering risks. To optimize electrical performance and shorten the TSV path, the intermediate silicon interposer board typically requires thinning. This extremely thin and brittle physical characteristic makes fluid interface placement extremely difficult, resulting in high surface sealing risks. For vertical fluid inlet, current technologies usually require applying mechanical pressure directly to the outer surface of the interposer board to tighten the O-ring. However, the interposer board surface is covered with a high-density redistribution layer (RDL) and tiny electrical pads; directly applying mechanical sealing stress here can easily lead to breakage, delamination, or damage to the underlying electrical interconnect layer. Furthermore, even a small leak at the interface can allow conductive coolant to directly contact the exposed electrical structure, posing a risk of short circuit and burnout.
[0027] Furthermore, 3D stacking introduces challenges related to height differences and fluid interconnects. In Logic+DRAM stacking systems, the area of the bottom logic chips is typically smaller than the package substrate, leading to significant height differences due to the stacking of upper layers. To facilitate packaging or heat dissipation through cover plates, existing technologies (such as some AMD 3D V-Cache technologies) typically fill the logic chips with solid silicon blocks for mechanical leveling and support. However, these existing structural silicon blocks only serve as mechanical supports or assist in solid-state heat conduction and are not utilized for fluid transport. Current fluid inlet / outlet (I / O) designs often require drilling holes in the side of the adapter board or consuming valuable substrate space to implement complex sealing structures. This not only increases the package size but also makes the installation and sealing of the top heatsink extremely complex.
[0028] In summary, existing technologies lack an integrated packaging structure that can simultaneously achieve extremely low interface thermal resistance, high structural reliability, and cleverly solve the height difference of 3D stacking while realizing vertical fluid interconnection.
[0029] Therefore, in view of the shortcomings of existing 3D heterogeneous integrated packaging technology, such as high interface thermal resistance, high risk of sealing of fluid interface of thin adapter board and single function of auxiliary structure, this invention provides an embedded liquid cooling packaging structure for high heat flux 3D IC, and in particular a structural silicon fluid interconnect 3D integrated packaging structure and preparation method for achieving near junction heat dissipation.
[0030] This application discloses a 3D integrated packaging structure for silicon fluid interconnects. For example... Figure 1-4 As shown, the structured silicon fluid interconnect 3D integrated packaging structure 5 includes a microchannel heat dissipation adapter plate 1, a logic chip 2, a memory chip stack 3, and a structured silicon pad 4.
[0031] The microchannel heat dissipation adapter plate 1 has a microchannel structure 100 inside; the active surface of the logic chip 2 faces the microchannel heat dissipation adapter plate 1, and the logic chip 2 is directly connected to the microchannel heat dissipation adapter plate 1 through the hybrid bonding dielectric layer 14; the memory chip stack 3 is vertically stacked above the back side of the logic chip 2; the structural silicon pad 4 is arranged around the stack of logic chip 2, and the structural silicon pad 4 is located on the front side of the microchannel heat dissipation adapter plate 1; the structural silicon pad 4 has a vertically penetrating fluid input through-hole 401 and a fluid output through-hole 402 inside; the bottom of the fluid input through-hole 401 is connected to the inlet of the microchannel structure 100, and the bottom of the fluid output through-hole 402 is connected to the outlet of the microchannel structure 100; wherein, the top surface of the structural silicon pad 4 is flush with the top surface of the memory chip stack 3, forming a coplanar support structure.
[0032] In this invention, in a first aspect, the present invention employs a hybrid bonding process to connect the active surface of the logic chip 2 and the microfluidic heat dissipation adapter 1. Compared with the "microbumps + bottom filler" commonly used in the prior art to connect the chip and the heat dissipation substrate, the present invention completely eliminates the solder layer and the low thermal conductivity organic adhesive layer located between the active region 201 (heat source) of the logic chip and the cooling channel, realizing near-junction heat conduction and electrical conduction without a solder layer. It can shorten the heat conduction path to the micrometer level and realize the connection of high thermal conductivity medium, significantly reducing the interface thermal resistance and realizing true "near-junction cooling". This allows the cooling medium to more directly and efficiently remove the heat generated by the high heat flux logic chip, greatly reducing the chip junction temperature.
[0033] Secondly, this invention innovatively utilizes the structured silicon gasket 4 as a vertical manifold for fluid transmission. Unlike existing technologies that require direct mechanical pressure to be applied to the surface of an extremely thin (e.g., <100μm) adapter board filled with precision circuitry for sealing, this invention utilizes fluid inlet holes 401 and fluid outlet holes 402 on the structured silicon gasket 4 to transfer the sealing interface of the fluid interface to the top surface of the thicker, mechanically stronger structured silicon gasket 4. This design successfully achieves physical decoupling between "mechanical sealing stress" and "electrical interconnection structure," avoiding the risk of breakage or damage to the electrical layer of the adapter board due to the installation of sealing joints. This significantly improves the manufacturing yield and long-term reliability of the packaging system and effectively solves the sealing and stress risk problems of the fluid interface of thin adapter boards.
[0034] Thirdly, regarding the chip height difference problem caused by Logic+DRAM stacking, the structural silicon pad 4 in this invention not only plays a role in "mechanical leveling" and "support"—that is, the height of the structural silicon pad 4 is designed to be consistent with the total stacking height of "Logic Chip 2 + Memory Chip Stack 3"—providing a flat support surface for the top packaging structure 5 and protecting the fragile memory chip, but also, by being endowed with an active function of fluid transport, this integrated design avoids the need to arrange complex lateral pipelines or occupy substrate area to arrange independent fluid connectors outside the package, making the packaging structure 5 more compact, improving the system's volume utilization, facilitating high-density deployment in confined spaces such as servers, and greatly improving the volume utilization and integration of 3D stacked packaging.
[0035] In addition, the fluid transport path of the present invention is strictly limited to the vertical through holes of the structural silicon pad 4 and the deep buried channels inside the microchannel heat dissipation adapter plate 1. The fluid channel and the electrical connection area of the logic chip / memory chip are highly isolated in physical space. Even if a small amount of leakage occurs at the interface, the leakage point is located on the surface of the structural silicon pad 4 at the top of the package, rather than directly contacting the dense electrical pads at the bottom, thereby minimizing the risk of short circuit and burnout caused by leakage.
[0036] In some embodiments of the present invention, the microchannel heat dissipation adapter plate 1 includes a first silicon wafer and a second silicon wafer arranged opposite each other. The opposing surfaces of the first silicon wafer and the second silicon wafer are etched to form a microchannel structure 100. The first silicon wafer and the second silicon wafer are bonded together to form an integrated structure.
[0037] Preferably, the microchannel heat dissipation adapter plate 1 (first silicon wafer and second silicon wafer) and the structural silicon pad 4 are both made of homogeneous single-crystal silicon material.
[0038] In this embodiment, both the microchannel heat dissipation adapter plate 1 and the structural silicon pad 4 of the present invention are made of highly thermally conductive homogeneous single-crystal silicon material. Compared with the prior art which uses fragile glass wafers to bond to silicon substrates, the double-layer Si-Si bonded heat dissipation adapter plate of the present invention enables the entire packaging structure 5 to have perfect coefficient of thermal expansion (CTE) matching, eliminating thermal stress caused by CTE mismatch. Under the severe thermal cycling generated by the high-power operation of the chip, the possibility of bonding layer cracking or warping caused by thermal stress due to material mismatch is greatly reduced. Thus, it has excellent material matching and structural reliability. In addition, the Si-Si bonded flow channels of the first silicon wafer and the second silicon wafer without dielectric layer have a bonding strength much higher than that of glass bonding, and can withstand higher fluid pressure (>50 bar), thereby allowing the use of higher flow rates of working fluid to further improve heat dissipation performance.
[0039] In some embodiments of the present invention, silicon-silicon direct bonding includes, but is not limited to, silicon-silicon fusion bonding, silicon-silicon room temperature bonding, and other processes.
[0040] In some embodiments of the present invention, a first silicon wafer may be set as the bottom layer and a second silicon wafer as the top layer, with the second wafer used to connect with the logic chip 2 and the structural silicon pad 4; or, a second silicon wafer may be set as the bottom layer and a first silicon wafer as the top layer, with the first wafer used to connect with the logic chip 2 and the structural silicon pad 4.
[0041] In some embodiments of the present invention, the microchannel structure 100 may be formed separately on the first silicon wafer, or separately on the second silicon wafer, or may be formed by splicing together the first microchannel structure 100 formed on the first silicon wafer and the second microchannel structure 100 formed on the second silicon wafer.
[0042] In some embodiments of the present invention, such as Figure 1 As shown, the structured silicon fluid interconnect 3D integrated packaging structure 5 also includes a packaging structure 5, which is pressed onto the top surface of the structured silicon gasket 4 by a sealing gasket 502, and the sealing gasket 502 is arranged around the fluid inlet through-hole 401 or the fluid outlet through-hole 402.
[0043] In some embodiments of the present invention, such as Figure 1As shown, coolant interfaces 501 are integrally formed on the encapsulation structure 5 corresponding to the fluid inlet through hole 401 and the fluid outlet through hole 402.
[0044] It should be understood that the coolant interface 501 is located on the outside of the package structure 5. The coolant enters vertically from the top, passes through the structural silicon pad 4, and is directly injected into the microchannel structure 100 at the bottom. The sealing stress of the coolant interface 501 is borne by the robust structural silicon pad 4, rather than acting directly on the thin and circuit-covered surface of the adapter board, thus completely solving the engineering problem of "fragile / leaky fluid I / O of thin adapter boards".
[0045] Furthermore, a groove 503 for accommodating the sealing gasket 502 can be formed on the side of the encapsulation structure 5 facing the structural silicon gasket 4 at the position corresponding to the sealing gasket 502. The depth of the groove 503 is less than the thickness of the sealing gasket 502. The sealing gasket 502 is positioned by the groove 503 to achieve stable compression of the sealing gasket 502.
[0046] In some embodiments of the present invention, in addition to being integrally formed with the packaging structure 5, the coolant interface 501 can also be fixed to the packaging structure 5 by means of welding or other methods.
[0047] In some embodiments of the present invention, the encapsulation structure 5 includes, but is not limited to, an encapsulation cover or a heat sink.
[0048] In some embodiments of the present invention, the structural silicon pad 4 can be bonded or attached to a predetermined area of the microchannel heat dissipation adapter plate 1; such as Figure 4 As shown, the structural silicon pad 4 and the microchannel heat dissipation adapter plate 1 are sealed together by a solder sealing ring 13.
[0049] In some embodiments of the present invention, there may be two or more structural silicon pads 4; such as Figure 2 As shown, there are two structural silicon pads 4, which are respectively set as the inlet and outlet of the microchannel structure 100. Fluid inlet through hole 401 and fluid outlet through hole 402 are respectively opened on the two structural silicon pads 4.
[0050] In some embodiments of the present invention, the hybrid bonding medium layer 14 between the logic chip 2 and the microfluidic heat dissipation adapter plate 1 is Cu-Cu diffusion bonding and SiO2-SiO2 covalent bonding.
[0051] In this embodiment, the logic chip 2 and the microfluidic heat dissipation adapter plate 1 are connected by Cu-Cu diffusion and SiO2-SiO2 covalent bonding, realizing a high thermal conductivity medium connection of all silicon / copper, reducing the interface thermal resistance, and ensuring that the cooling medium can directly and efficiently remove the heat generated by the high heat flux logic chip.
[0052] The hybrid bonding dielectric layer 14 (Cu-Cu diffusion bonding and SiO2-SiO2 covalent bonding) of the present invention, with its solderless connection, can shorten the distance between the active region 201 of the logic chip 2 and the cooling channel (microchannel structure 100) to within 10 μm and eliminate the low thermal conductivity adhesive layer, thereby achieving true "near junction cooling" and greatly reducing the interfacial thermal resistance.
[0053] In some embodiments of the present invention, the microchannel structure 100 is selected from one of the following: straight-through microchannel, microneedle fin microchannel, and manifold microchannel.
[0054] like Figure 5 As shown, straight-through microchannels are suitable for scenarios requiring low pressure drop and have low fluid resistance. Figure 6 As shown, the microchannel with microneedle fins features a high-density array of silicon needle fins within the flow channel, significantly increasing the heat transfer area and making it suitable for regions with extremely high heat flux (such as below the core hotspot of Logic Chip 2). Figure 7 As shown, the manifold-type microchannel adopts a graded flow distribution design, which can ensure temperature uniformity under large-area chips and avoid the phenomenon of "cold inlet and hot outlet".
[0055] In some embodiments of the present invention, such as Figure 1 As shown, the structured silicon fluid interconnect 3D integrated packaging structure 5 also includes a carrier substrate layer, which includes an organic substrate 6 and a PCB motherboard 7; the organic substrate 6 is connected to the back side of the microchannel heat dissipation adapter plate 1; the PCB motherboard 7 is connected to the back side of the organic substrate 6.
[0056] Specifically, the PCB motherboard 7 is connected to the organic substrate 6 via C2 solder balls 8. The back side of the PCB motherboard 7 is provided with C4 solder balls 9. The organic substrate 6 is electrically interconnected with the microchannel heat dissipation adapter board 1 above via C2 micro-bumps 10.
[0057] In some embodiments of the present invention, such as Figure 1 As shown, the microchannel heat dissipation adapter 1 has through silicon vias 103 (TSVs) that penetrate its upper and lower surfaces, which are responsible for transmitting signals / power from the logic chip and memory chip to the bottom carrier substrate. The back of the microchannel heat dissipation adapter 1 has a redistribution layer 12 (RDL) for fan-out signals.
[0058] It should be understood that the TSV is offset from the microchannel structure 100 inside the microchannel heat dissipation adapter plate 1.
[0059] In some embodiments of the present invention, such as Figure 1 and Figure 2 As shown, the logic chip 2 is located in the center area of the front of the microchannel heat dissipation adapter plate 1.
[0060] This embodiment also proposes a method for fabricating the above-described silicon fluid interconnect 3D integrated packaging structure, which includes the following steps: S1. Prepare a microchannel heat dissipation adapter plate with an embedded microchannel structure.
[0061] S2. Logic chips are bonded to the microchannel heat dissipation adapter board using a hybrid bonding process.
[0062] S3. Install a structured silicon pad with fluid input and fluid output vias on the front side of the microchannel heat dissipation adapter plate and around the logic chip.
[0063] S4. Stack memory chips on logic chips to obtain a memory chip stack.
[0064] S5. Complete the assembly of the load-bearing substrate and encapsulation structure, as well as the connection of the coolant interface.
[0065] In some embodiments of the present invention, bonding logic chips to a microchannel heat dissipation adapter plate via a hybrid bonding process includes the following steps: Cu-SiO2 hybrid bonding interfaces were prepared on the top surface of the microchannel heat dissipation adapter plate and the top surface of the logic chip, respectively.
[0066] Surface planarization of the Cu-SiO2 mixed bonding interface was achieved through chemical mechanical polishing.
[0067] The logic chip is flip-chip aligned with the microchannel heat dissipation adapter plate, pre-bonded at room temperature, and then thermally annealed to achieve Cu-Cu diffusion bonding and SiO2-SiO2 covalent bonding.
[0068] In some embodiments of the present invention, the Cu-SiO2 mixed bonding interface on the logic chip can be prepared and chemically mechanically polished at the logic wafer stage, and then the logic chip is obtained by dicing the logic wafer.
[0069] In some embodiments of the present invention, the mounting of the structural silicon pads and the stacking of memory chips include the following steps: First, a silicon pad with fluid inlet and fluid outlet through-holes is prepared.
[0070] Then, the structural silicon pads are bonded or mounted to the preset area of the adapter board to ensure that the fluid inlet and fluid outlet through holes are precisely aligned with the inlet and outlet of the microchannel structure, respectively.
[0071] Then, multiple layers of memory chips are vertically stacked on the back of the logic chip using microbump technology or hybrid bonding technology.
[0072] To enable those skilled in the art to better understand the technical solution of this invention, the following description is provided in conjunction with the appendix. Figure 8-13The present invention will be further described in detail below with reference to specific embodiments.
[0073] Example 1 Step S1: Fabrication of microchannel heat dissipation adapter plate Select the first silicon wafer (bottom layer), and use deep reactive ion etching (DRIE) to etch microchannel trenches with optimized aspect ratios (e.g., Figure 8 (Structure shown).
[0074] Select a second silicon wafer (top layer) and thin it to the designed thickness.
[0075] Performing Si-Si hydrophilic bonding, followed by high-temperature annealing (>300℃) to form an atomically bonded sealed cavity, such as... Figure 9 As shown.
[0076] TSV vias are fabricated on the bonded wafer and filled with copper, such as... Figure 10 As shown; an RDL redistribution layer is fabricated on the back side, as follows. Figure 11 As shown.
[0077] Step S2: Hybrid bonding of logic chips Cu-SiO2 mixed bonding interfaces were prepared on the top surface of the adapter plate and the top surface of the logic wafer, respectively.
[0078] Surface planarization (roughness <0.5nm) is achieved through CMP (chemical mechanical polishing).
[0079] The logic chips were flip-chip aligned with the adapter board and pre-bonded at room temperature, followed by thermal annealing to achieve Cu-Cu diffusion bonding and SiO2-SiO2 covalent bonding, such as... Figure 12 As shown, this process does not use any flux or underfill adhesive.
[0080] Step S3: Stacking of integrated structure silicon pads and memory chips Prepare a single-crystal silicon block (structural silicon pad) with pre-drilled fluid through holes.
[0081] Bond or mount the structural silicon pad to the preset area of the adapter board, ensuring that its vias are precisely aligned with the fluid inlet and outlet of the adapter board, such as... Figure 13 As shown.
[0082] On the back of the logic chip, multiple layers of memory chips (DRAM) are vertically stacked using traditional microbump technology or hybrid bonding technology, such as... Figure 13 As shown.
[0083] Step S4: Substrate Assembly and Fluid Interconnection The above-mentioned adapter board assembly is flip-chip reflow soldered onto the organic substrate using C2 microbumps, and the bottom filler is filled (this is only used between the adapter board and the organic substrate).
[0084] The organic substrate is mounted to the PCB motherboard via C2 solder balls.
[0085] A sealing gasket (O-ring) and a metal / plastic coolant connector are installed at the top port of the structural silicon pad and secured with mechanical fasteners.
[0086] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A 3D integrated packaging structure with silicon fluid interconnect, characterized in that, include: A microchannel heat dissipation adapter plate, wherein the microchannel heat dissipation adapter plate has a microchannel structure inside; A logic chip, the active surface of which is disposed facing the microchannel heat dissipation adapter plate, is directly connected to the microchannel heat dissipation adapter plate through a hybrid bonding medium layer; Storage chip stacks, wherein the storage chip stacks are vertically stacked above the back side of the logic chip; A structural silicon pad is arranged around the logic chip stack and located on the front side of the microchannel heat dissipation adapter plate; the structural silicon pad has vertically penetrating fluid inlet and fluid outlet through-holes inside; the bottom of the fluid inlet through-hole is connected to the inlet of the microchannel structure, and the bottom of the fluid outlet through-hole is connected to the outlet of the microchannel structure; wherein, the top surface of the structural silicon pad is flush with the top surface of the memory chip stack.
2. The structural silicon fluid interconnect 3D integrated packaging structure according to claim 1, characterized in that, The microchannel heat dissipation adapter plate includes a first silicon wafer and a second silicon wafer arranged opposite each other. The microchannel structure is formed on the opposing surfaces of the first silicon wafer and the second silicon wafer through an etching process. The first silicon wafer and the second silicon wafer are bonded together to form an integrated structure.
3. The structural silicon fluid interconnect 3D integrated packaging structure according to claim 1, characterized in that, It also includes a packaging structure, which is pressed onto the top surface of the structural silicon pad by a sealing gasket, and the sealing gasket is arranged around the fluid inlet or fluid outlet through-hole.
4. The structural silicon fluid interconnect 3D integrated packaging structure according to claim 3, characterized in that, The encapsulation structure has coolant interfaces integrally formed on the fluid inlet and fluid outlet through holes, respectively.
5. The structural silicon fluid interconnect 3D integrated packaging structure according to claim 1, characterized in that, The hybrid bonding medium layer between the logic chip and the microfluidic heat dissipation adapter plate consists of Cu-Cu diffusion bonding and SiO2-SiO2 covalent bonding.
6. The structural silicon fluid interconnect 3D integrated packaging structure according to claim 1, characterized in that, The microchannel structure is selected from one of the following: straight-through microchannel, microneedle-fin microchannel, and manifold microchannel.
7. The structural silicon fluid interconnect 3D integrated packaging structure according to claim 1, characterized in that, Also includes: An organic substrate, the organic substrate being connected to the back side of the microchannel heat dissipation adapter plate; A PCB motherboard, which is connected to the back side of the organic substrate.
8. A method for fabricating a structured silicon fluid interconnect 3D integrated packaging structure as described in any one of claims 1 to 7, characterized in that, Includes the following steps: Fabrication of a microchannel heat dissipation adapter plate with an embedded microchannel structure; The logic chips are bonded to the microchannel heat dissipation adapter plate using a hybrid bonding process. A structured silicon pad with fluid input and fluid output vias is installed on the front side of the microchannel heat dissipation adapter plate and around the logic chip. Storage chips are stacked on the logic chips to obtain a storage chip stack.
9. The preparation method according to claim 8, characterized in that, The process of bonding logic chips to the microchannel heat dissipation adapter plate using a hybrid bonding process includes the following steps: Cu-SiO2 hybrid bonding interfaces were prepared on the top surface of the microchannel heat dissipation adapter plate and the top surface of the logic chip, respectively. The surface planarization of the Cu-SiO2 mixed bonding interface was achieved by chemical mechanical polishing. The logic chip is flip-chip aligned with the microchannel heat dissipation adapter plate, pre-bonded at room temperature, and then thermally annealed to achieve Cu-Cu diffusion bonding and SiO2-SiO2 covalent bonding.
10. The preparation method according to claim 8, characterized in that, The mounting of the structured silicon pads and the stacking of the memory chips include the following steps: Fabrication of a silicon pad with fluid inlet and fluid outlet vias; The structural silicon pads are bonded or mounted to the preset area of the adapter board to ensure that the fluid inlet and fluid outlet through holes are precisely aligned with the inlet and outlet of the microchannel structure, respectively. Multilayer memory chips are vertically stacked on the back of the logic chip using microbump technology or hybrid bonding technology.