A novel GaN HEMT device and its fabrication method

Abstract

The application relates to the technical field of semiconductors, in particular to a novel GaN HEMT device and a preparation method thereof. The device comprises an active region; the active region comprises a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a cap layer which are sequentially stacked on the substrate, and a gate region, a drain region, a source field plate and a clamping field plate; the gate region is located on the cap layer; the source field plate is located on the gate region and covers the gate region and the cap layer; the drain region is located on the barrier layer; the clamping field plate is located on the barrier layer and between the gate region and the drain region, and is isolated from the source field plate, and the positions of the clamping field plate and the source field plate do not overlap. Through the device structure, the inhibition effect of current collapse of the device is improved, the degradation of the on-resistance is inhibited, the reliability and stability of the device are improved, the cost of the device is reduced, and the practicability of the device is enhanced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a novel GaN HEMT device and its fabrication method. Background Technology

[0002] Gallium nitride high electron mobility transistors (GaN HEMTs), as representatives of third-generation semiconductor power devices, have shown great application potential in modern power electronic systems, such as fast charging, data center power supplies, and new energy vehicles, thanks to their excellent characteristics such as high electron saturation velocity and high critical breakdown electric field. However, GaN HEMT devices, especially those based on AlGaN / GaN heterojunctions, have long been severely constrained by an effect known as "current collapse" or "dynamic on-resistance degradation." To suppress this effect, GaN HEMT devices employ a field plate structure.

[0003] Currently, GaN HEMT devices typically employ field plate structures with fixed potentials, such as gate, drain, and source field plates, to modulate the electric field distribution in the channel. However, these field plate structures can lead to uneven electric field distribution in GaN HEMT devices, generating localized high-electric-field regions, such as excessively high electric field peaks near the gate edge. This can trigger thermionic injection, causing a large amount of charge to be trapped on the device surface and in bulk traps, forming a "virtual gate" that reduces the 2DEG (Two-Dimensional Electron Gas) concentration. Consequently, existing GaN HEMT devices exhibit poor current collapse suppression and degraded on-resistance, i.e., increased on-resistance. Summary of the Invention

[0004] This application provides a novel GaN HEMT device and its fabrication method, which solves the technical problems of poor current collapse suppression and on-resistance degradation in existing GaN HEMT devices. It achieves technical effects such as improving the current collapse suppression effect of GaNHEMT devices, suppressing on-resistance degradation, improving device reliability and stability, reducing device cost, and enhancing device practicality.

[0005] In a first aspect, embodiments of the present invention provide a novel GaN HEMT device, comprising: an active region; the active region comprising: a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a capping layer sequentially stacked on the substrate, and a gate region, a drain region, a source field plate and a clamping field plate;

[0006] The gate region is located above the capping layer;

[0007] The source field plate is located above the gate region, and the source field plate covers the gate region and the capping layer;

[0008] The drain region is located on the barrier layer;

[0009] The clamping field plate is located above the barrier layer, between the gate region and the drain region, and isolated from the source field plate, and the positions of the clamping field plate and the source field plate do not overlap.

[0010] Optionally, it may also include: a terminal area, the terminal area surrounding the active area;

[0011] In the terminal region, a high-resistivity layer is laid on top of the barrier layer;

[0012] On the layout of the device, in a designated area of ​​the high-resistivity layer located between the drain and source of the chip, a first high-resistivity region of the designated area is electrically connected to the clamping field plate through wiring vias. The designated area includes a first high-resistivity region and a second high-resistivity region. One end of the first high-resistivity region is connected to the drain of the chip, and the other end is connected to one end of the second high-resistivity region. The other end of the second high-resistivity region is connected to the source of the chip.

[0013] Optionally, the distance between the right end of the source field plate and the right end of the capping layer is in the range of 700-800 nm.

[0014] Optionally, the clamping field plate is positioned close to the drain region, and the length of the clamping field plate is a specified length, which is 1 / 4 to 1 / 3 of the gate-drain spacing between the gate region and the drain region.

[0015] Optionally, the center of the clamping field plate is located within 1 / 2 to 2 / 3 of the grid-slot spacing.

[0016] Optionally, it also includes: a source region; the source region is located on the barrier layer, and the source field plate also covers the source region.

[0017] Optionally, it may also include: a first passivation layer;

[0018] Optionally, the first passivation layer covers the surfaces of the cap layer, the gate region, and the barrier layer, the first passivation layer is located between the source region and the drain region, and the first passivation layer is located under the source field plate.

[0019] Optionally, it may also include: a second passivation layer;

[0020] The second passivation layer is located above the source field plate and the first passivation layer, and covers the source region, the source field plate, the first passivation layer and the drain region, and the second passivation layer is located below the clamping field plate.

[0021] Optionally, a third passivation layer may also be included;

[0022] The third passivation layer is located above the clamping field plate and covers the second passivation layer and the clamping field plate.

[0023] Based on the same inventive concept, in a second aspect, the present invention also provides a method for fabricating a novel GaN HEMT device, used to fabricate the novel GaN HEMT device as described in the first aspect, the method comprising:

[0024] In the active region, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a capping layer are formed sequentially on the substrate.

[0025] A gate region is formed on the cap layer;

[0026] A drain region is formed on the barrier layer;

[0027] A source field plate is formed over the gate region, wherein the source field plate covers the gate region and the capping layer;

[0028] A clamping field plate is formed above the barrier layer and between the gate region and the drain region, wherein the clamping field plate is isolated from the source field plate and the positions of the clamping field plate and the source field plate do not overlap.

[0029] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0030] The GaN HEMT device of this invention employs a composite structure of a source field plate and a clamping field plate, enabling the device to dynamically adjust its potential according to the source-drain voltage. In the off-state, the device effectively optimizes the electric field distribution throughout the drift region, achieving electric field homogenization and improving the breakdown voltage. Simultaneously, the source and clamping field plates prevent the generation of hot electrons by optimizing the electric field distribution; furthermore, the dynamic adjustment of the clamping field plate's potential cancels out the "virtual gate" effect formed by trapped charges in real time, thereby significantly suppressing the degradation of dynamic on-resistance. Thus, the structural design of the device in this invention suppresses on-resistance degradation, improves device reliability and stability, reduces device cost, and enhances device practicality. Attached Figure Description

[0031] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0032] Figure 1 A schematic diagram of the structure of the novel GaN HEMT device in an embodiment of the present invention is shown;

[0033] Figure 2 A schematic diagram of the layout of the novel GaN HEMT device in an embodiment of the present invention is shown;

[0034] Figure 3 A schematic diagram of the structural principle of a GaN HEMT device without a field plate structure in an embodiment of the present invention is shown in the on state (Vgs > Vth) and with an applied voltage (Vds > 0).

[0035] Figure 4 This diagram illustrates the structural principle of a GaN HEMT device without a field plate structure in the off state (Vgs≤0) and with an applied voltage (Vds>0) according to an embodiment of the present invention.

[0036] Figure 5 A schematic diagram of the structural principle of the novel GaN HEMT device in the embodiment of the present invention is shown in the on state (Vgs > Vth) and with applied voltage (Vds > 0).

[0037] Figure 6 A schematic diagram of the structural principle of the novel GaN HEMT device in the embodiment of the present invention is shown in the cutoff state (Vgs≤0) and with applied voltage (Vds>0).

[0038] Figure 7 A schematic diagram comparing the electric field intensity curves of the novel GaN HEMT device in this embodiment of the invention with those of a HEMT device without a field plate structure, a HEMT device with only a source field plate, and a HEMT device with a composite structure of a source field plate and a floating field plate.

[0039] Figure 8 A schematic diagram comparing the breakdown voltage curves of the novel GaN HEMT device in this embodiment of the invention with those of a HEMT device without a field plate structure, a HEMT device using only a source field plate, and a HEMT device using a composite structure of a source field plate and a floating field plate.

[0040] Figure 9 This diagram illustrates a structure in an embodiment of the present invention in which a nucleation layer, a first buffer layer, a second buffer layer, a channel layer, a barrier layer, and a capping layer are sequentially formed on a substrate.

[0041] Figure 10 This diagram illustrates a structure in an embodiment of the present invention in which a Schottky metal layer and a hard mask layer are sequentially formed on top of a cap layer.

[0042] Figure 11 This diagram illustrates the structure of the final cap layer and gate region etched and stacked sequentially in an embodiment of the present invention.

[0043] Figure 12 This diagram illustrates a structure in which a first passivation layer is formed on the surface of the capping layer, the gate region, and the barrier layer in an embodiment of the present invention.

[0044] Figure 13 This diagram illustrates a structure in an embodiment of the present invention in which a drain region and a source region are formed on a barrier layer, and a source field plate is formed on a first passivation layer.

[0045] Figure 14 This diagram illustrates a structure in which a second passivation layer is formed on the surfaces of the source field plate, the first passivation layer, and the drain region, according to an embodiment of the present invention.

[0046] Figure 15 This diagram illustrates a structure in which a clamping field plate is formed on the second passivation layer in an embodiment of the present invention.

[0047] Figure 16 A schematic flowchart of the fabrication method of the novel GaN HEMT device in an embodiment of the present invention is shown.

[0048] In the attached figures, 110 is the substrate; 120 is the nucleation layer; 121 is the first buffer layer; 122 is the second buffer layer; 123 is the channel layer; 124 is the barrier layer; 125 is the capping layer; 130 is the gate region; 131 is the drain region; 132 is the source region; 140 is the source field plate; 150 is the clamping field plate; 160 is the first passivation layer; 161 is the second passivation layer; and 162 is the third passivation layer. Detailed Implementation

[0049] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0050] Example 1

[0051] The first embodiment of the present invention provides a novel GaN HEMT device, such as... Figure 1As shown, the active region includes: a substrate 110, a nucleation layer 120, a buffer layer, a channel layer 123, a barrier layer 124, and a capping layer 125 sequentially stacked on the substrate 110, and a gate region 130, a drain region 131, a source field plate 140, and a clamping field plate 150. The gate region 130 is located on the capping layer 125. The source field plate 140 is located on the gate region 130 and covers the gate region 130 and the capping layer 125. The drain region 131 is located on the barrier layer 124. The clamping field plate 150 is located on the barrier layer 124 and is located between the gate region 130 and the drain region 131, and is isolated from the source field plate 140, and the positions of the clamping field plate 150 and the source field plate 140 do not overlap.

[0052] It should be noted that in this embodiment, the stacking is configured as a sequential stacking arrangement from bottom to top. That is, in Figure 1 In this structure, nucleation layer 120 is located above substrate 110, buffer layer is located above nucleation layer 120, channel layer 123 is located above buffer layer, barrier layer 124 is located above trench layer, and capping layer 125 is located above barrier layer 124.

[0053] The GaN HEMT device in this embodiment employs a composite structure of a source field plate 140 and a clamping field plate 150. This allows the device to dynamically adjust its potential according to the source-drain voltage. In the off-state (i.e., under high voltage stress, also known as withstand voltage), the device effectively optimizes the electric field distribution throughout the drift region, achieving electric field homogenization and improving the breakdown voltage. Simultaneously, the source field plate 140 and the clamping field plate 150, on the one hand, prevent the generation of hot electrons by optimizing the electric field distribution; on the other hand, the dynamic adjustment of the clamping field plate's potential cancels out the "virtual gate" effect formed by trapped charges in real time, thereby significantly suppressing the degradation of dynamic on-resistance. Thus, the structural design of the device in this embodiment suppresses on-resistance degradation, improves device reliability and stability, reduces device cost, and enhances device practicality.

[0054] Below, in conjunction with Figure 1 The specific structure of the GaN HEMT device in this embodiment is described in detail below:

[0055] Substrate 110 is a silicon-based substrate. Nucleation layer 120 is made of aluminum nitride (AlN) with a thickness ranging from 150-250 nm. The buffer layer includes a first buffer layer 121 and a second buffer layer 122 sequentially stacked on top of nucleation layer 120. The first buffer layer 121 is made of Al with different doping concentrations. x1 Ga 1-x1N-gradient buffer layer. The Al content of AlGaN closer to the AlN nucleation layer 120 is higher, and in this case, x1 can be set between 0.5 and 0.7. The Al content of AlGaN closer to the second buffer layer 122 is lower, and in this case, x1 can be set between 0.05 and 0.1. The thickness of each layer in the first buffer layer 121 can be set according to actual needs. For example, as Figure 1 As shown, the first buffer layer 121 includes: A1 layers stacked sequentially. 0.5 Ga 0.5 N layer, Al 0.25 Ga 0.75 N layer and Al 0.05 Ga 0.95 N layers. Al 0.5 Ga 0.5 The thickness of the N layer ranges from 150-250 nm, and the Al layer... 0.25 Ga 0.75 The thickness of the N layer ranges from 300-400 nm, Al 0.05 Ga 0.95 The thickness of the N-layer ranges from 350 to 450 nm. The second buffer layer 122 is a GaN buffer layer with a thickness ranging from 500 to 800 nm. The channel layer 123 is an i-GaN channel layer, i.e., an intrinsic GaN layer, with a thickness ranging from 200 to 400 nm. The barrier layer 124 is made of Al. x2 Ga 1-x2 N, x2 is 0.1-0.3. For example, Al 0.23 Ga 0.77 N-type barrier layer 124. The thickness of barrier layer 124 ranges from 10-20 nm. Capping layer 125 is made of PGaN, where Al is aluminum, Ga is gallium, N is nitrogen, and P is phosphorus.

[0056] The device in this embodiment also includes a source region 132. The source region 132 is located on the barrier layer 124, and the source field plate 140 also covers the source region 132. The device structure in this embodiment is the smallest unit structure of the device, that is, a cell structure. In the cell structure, the drain region 131 can represent the drain of the device, the source region 132 can represent the source of the device, and the gate region 130 can represent the gate of the device. In addition, the material of the gate region 130 in this embodiment includes, but is not limited to, silicon dioxide (SiO2), titanium (Ti), and titanium nitride (TiN), that is, a Ti / TiN Schottky metal layer and a SiO2 layer stacked sequentially. The material of the gate region 130 can also be set to other materials according to actual needs. The source, drain, and source field plate 140 are all multilayer metal structures of Ti / Al / Ti / TiN stacked sequentially, and can also be set to multilayer metal structures of other materials stacked sequentially according to actual needs. The thickness range of each metal layer in the source, drain, and source field plate 140 can be set according to actual needs. For example, in a multilayer metal structure of Ti / Al / Ti / TiN, the thickness of the Ti metal layer is 50 nm, the thickness of the Al metal layer is 300 nm, the thickness of the Ti metal layer is 20 nm, and the thickness of the TiN metal layer is 30 nm.

[0057] The device in this embodiment further includes a first passivation layer 160. The first passivation layer 160 covers the surfaces of the cap layer 125, the gate region 130, and the barrier layer 124. The first passivation layer 160 is located between the source region 132 and the drain region 131, and is located below the source field plate 140. The first passivation layer 160 is made of SiN. x3 The range of x3 can be set according to actual needs. For example, the material of the first passivation layer 160 is Si3N4. The thickness range of the first passivation layer 160 can also be set according to actual needs, such as a thickness range of 100-200nm.

[0058] The device in this embodiment further includes a second passivation layer 161. The second passivation layer 161 is located above the source field plate 140 and the first passivation layer 160, and covers the source region 132, the source field plate 140, the first passivation layer 160, and the drain region 131. The second passivation layer 161 is located below the clamping field plate 150. The material of the second passivation layer 161 includes, but is not limited to, SiO2. The thickness of the second passivation layer 161 can be determined according to actual needs, such as a thickness range of 200-600 nm.

[0059] The device in this embodiment also includes a third passivation layer 162. The third passivation layer 162 is located above the clamping field plate 150 and covers the second passivation layer 161 and the clamping field plate 150. The material of the third passivation layer 162 includes, but is not limited to, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), and silicon phosphosilicate glass (PSG). The third passivation layer 162 is typically a silicon-containing inorganic insulating material, and its thickness range can be set according to actual needs.

[0060] In the device structure of this embodiment, the source field plate 140 is located above the first passivation layer 160, covering a portion of the first passivation layer 160 and the source region 132, and the source field plate 140 covers the gate region 130 and the capping layer 125. By wrapping the gate region 130 and the capping layer 125 with the source field plate 140, the peak electric field at the edge of the gate region 130 is transferred to the drift region, optimizing the electric field distribution of the gate region 130, preventing the gate region 130 and the device from being prematurely broken down, and improving the breakdown voltage of the device. Furthermore, the source field plate 140 is at the same potential as the source region 132, which to some extent suppresses current collapse and reduces dynamic on-resistance. The drift region is the area between the gate region 130 and the drain region 131 located in the trench layer.

[0061] The distance between the right end of the source field plate 140 (i.e., the rightmost edge) and the right end of the capping layer 125 (i.e., the rightmost edge) ranges from 700 to 800 nm. Based on the function of the source field plate 140 in transferring the peak electric field at the edge of the gate region 130 to the drift region, if this distance is too small, it means the corresponding distance of the source field plate 140 extending into the drift region is too short. This will prevent the source field plate 140 from effectively or ideally transferring the peak electric field of the gate region 130 to the drift region, leading to premature device breakdown, affecting gate reliability, increasing gate leakage current, and increasing hot carriers. If this distance is too large, it means the corresponding distance of the source field plate 140 extending into the drift region is too long. Electrons in the channel will be affected by the electric field of the source field plate 140 and discharged into the drift region, resulting in a decrease in the 2DEG (Two-Dimensional Electron Gas) concentration, and consequently, an increase in the device's on-resistance. The channel is the contact surface between the channel layer 123 and the barrier layer 124, and is located on the channel layer 123. 2DEGs exist within the channel.

[0062] The clamping field plate 150 is located above the second passivation layer 161, between the gate region 130 and the drain region 131, and isolated from the source field plate 140. The positions of the clamping field plate 150 and the source field plate 140 do not overlap. The thickness of the clamping field plate 150 ranges from 300 to 500 nm and can be set according to actual needs. The spacing between the clamping field plate and the source field plate 140 is 0.25-0.5 μm, i.e., the spacing between the left end of the clamping field plate 150 and the right end of the source field plate 140, such as 0.25 μm. The spacing between the clamping field plate 150 (i.e., the right end of the clamping field plate 150) and the drain region 131 (i.e., the left end of the drain region 131) is greater than 0.3 μm. The clamping field plate 150 is made of highly doped polysilicon, resulting in excellent conductivity. It should be noted that the clamping field plate 150 in this embodiment is not a floating field plate. The clamping field plate 150 in this embodiment is electrically connected to the high-resistivity material in the terminal area, which will be described in detail later.

[0063] Through the structural arrangement of the clamping field plate 150, the clamping field plate 150 covers the middle and rear sections of the drift region. When the device is in the off state, the clamping field plate can reduce the electric field peak near the source field plate 140, raise the electric field value in the middle of the drift region, and make the electric field distribution in the drift region more flat, thus optimizing the electric field distribution of the device. Furthermore, through the structural arrangement of the source field plate 140 and the clamping field plate 150, especially when the device is in the off state, the electric field distribution of the entire drift region can be effectively optimized, achieving electric field homogenization in the drift region. This further improves the breakdown voltage of the device, enhancing its reliability and practicality. In addition, through the synergistic effect of the source field plate 140 and the clamping field plate 150, the device can dynamically adjust its potential according to the source-drain voltage. When the device is in the off state, it can effectively optimize the electric field distribution of the entire drift region, achieving electric field homogenization in the drift region and improving the breakdown voltage. Meanwhile, through the composite field plate structure of the source field plate 140 and the clamping field plate 150, the generation of hot electrons is prevented by optimizing the electric field distribution; on the other hand, the "virtual gate" effect formed by the trapped charge is offset in real time by dynamically adjusting the potential of the field plate, thereby significantly suppressing the degradation of dynamic on-resistance.

[0064] The clamping field plate 150 is positioned close to the drain region 131, and its length is a specified length, which is 1 / 4 to 1 / 3 of the gate-drain pitch between the gate region 130 and the drain region 131. The gate-drain pitch is the distance between the starting point (gate region 130) and the ending point (drain region 131). If the clamping field plate 150 is too short, it cannot effectively cover the middle and later sections of the drift region, resulting in insufficient smoothing of the electric field spikes at the gate edge and limited breakdown voltage rise. Simultaneously, its compensation effect on trapped charges is weak, and its effect on suppressing current collapse is poor. If the clamping field plate 150 is too long, it is too close to the drain region 131, and strong capacitive coupling will interfere with or even overwhelm the clamping potential set by the resistor divider network, causing the clamping field plate 150 to lose its dynamic bias characteristics. Meanwhile, the excessively small metal spacing between the clamping field plate 150 and the drain will exacerbate the electric field stress of the first passivation layer 160 and the second passivation layer 161, reduce the long-term reliability of the device, introduce additional parasitic capacitance, and degrade the frequency characteristics of the device.

[0065] The center of the clamping field plate 150 is located within 1 / 2 to 2 / 3 of the gate-drain pitch. For example, the center of the clamping field plate 150 coincides with the position at 2 / 3 of the gate-drain pitch. Aligning the center of the clamping field plate with the position within 1 / 2 to 2 / 3 of the gate-drain pitch ensures a safe distance between the clamping field plate 150 and the source field plate 140 and the drain region 131, respectively, preventing the second passivation layer 161 from being broken down and causing leakage. It also forms an effective second electric field peak near the drain region 131, increasing the breakdown voltage.

[0066] The device in this embodiment also includes a termination region surrounding the active region. In the termination region, a high-resistivity layer is deposited above the barrier layer 124. Specifically, a first passivation layer 160, a second passivation layer 161, and a third passivation layer 162 are sequentially disposed above the barrier layer 124, and a high-resistivity layer is formed above the third passivation layer 162. A fourth passivation layer is also formed above the high-resistivity layer. The material of the high-resistivity layer (i.e., the high-resistivity material) includes, but is not limited to, TiN and TaN. Ta is tantalum. The resistivity of the high-resistivity layer is moderate and precisely controllable, enabling kΩ to MΩ level resistance within a very small chip area. It also possesses excellent high-temperature resistance and CMOS process compatibility, making it possible to integrate a voltage divider network within the chip, thereby achieving low-cost, highly integrated dynamic clamping functionality.

[0067] like Figure 2As shown, on the device layout, in a designated area of ​​the high-resistivity layer located between the drain and source of the chip, a first high-resistivity region within this designated area is electrically connected to the clamping field plate 150 via a via. The designated area includes a first high-resistivity region and a second high-resistivity region. One end of the first high-resistivity region is connected to the drain of the chip, and the other end is connected to one end of the second high-resistivity region. The other end of the second high-resistivity region is connected to the source of the chip. The first high-resistivity region is considered a first resistor, and the second high-resistivity region is considered a second resistor.

[0068] Specifically, in Figure 2 In the diagram, the clamping field plate 150 is integrated into each cell structure. Each structure circled in red represents a HEMT unit, i.e., a single cell structure. S represents source region 132, G represents source region 132, D represents drain region 131, and CPFP represents clamping field plate 150. The source field plate 140 is located within... Figure 2 The layout structure is not shown. The layout structure shows the HEMT cells from row N to row N and column M, i.e., N×M HEMT cells. Both N and M are greater than 0, and their specific values ​​can be set according to actual needs.

[0069] In each HEMT cell, the gate region 130 is connected to the chip's gate via the gate bus, and the source region 132 is connected to the chip's source via a high-resistivity layer. The drain region 131 is connected to the chip's drain via a high-resistivity layer. On the device layout, there is a designated area of ​​the high-resistivity layer between the chip's drain and source. This designated area is the region of the high-resistivity layer between the chip's drain and source, such as... Figure 2 As shown. The designated region can also be interpreted as the area of ​​the high-resistivity layer between the drain and source of the chip, starting from the drain and ending at the source. The designated region includes a first resistor (i.e., the first high-resistivity region) and a second resistor (i.e., the second high-resistivity region). The first and second resistors are connected sequentially between the drain and source of the chip. The first resistor in the designated region is electrically connected to the clamping field plate 150 through wiring vias.

[0070] The resistance value of the first resistor is determined by the node at the wiring hole (i.e., Figure 2 The location of the wiring via (as shown) determines the resistance; the node at the wiring via is also called the voltage divider point. The first resistor is the resistance value of the high-resistivity material between the node at the wiring via in the specified area and the drain region 131, i.e., the resistance value of the first high-resistivity region. The second resistor is the resistance value of the high-resistivity material between the node at the wiring via in the specified area and the source region 132, i.e., the resistance value of the second high-resistivity region. The connection point of the first and second resistors (i.e., the wiring via in the specified area) is directly electrically connected to the clamping field plate through a contact hole or metal interconnect.

[0071] For example, on the device layout, in a designated area of ​​the high-resistivity layer between the drain and source of the chip, a wiring via is drilled at one-third of the designated area to electrically connect to the clamping field plate 150. This one-third segment of the high-resistivity material in the designated area serves as the first high-resistivity region, i.e., the first resistor. The remaining two-thirds of the high-resistivity material in the designated area serves as the second high-resistivity region, i.e., the second resistor. The one-third mark of the designated area is defined as the position one-third of the drain-source distance between the chip's drain and source, starting from the chip's drain and ending at the chip's source.

[0072] It can be seen that the potential of the clamping field plate 150 is determined by the voltage across the drain and source terminals of the chip (i.e., the drain-source voltage of the chip), according to the formula V 钳位场板 =R1 / (R1+R2)×V ds R1 represents the first resistor, R2 represents the second resistor, and V 钳位场板 This represents the potential voltage of the clamping field plate 150, V. ds This represents the drain-source voltage of the chip. By changing the ratio of R1 / R2, the potential of the clamping field plate will change. The electric field strength of the clamping field plate 150 is related to the potential difference (also called electric potential difference). The greater the potential difference of the clamping field plate 150, the greater its electric field strength. The closer the voltage divider point (i.e., the node at the wiring via) is to the drain, the smaller the voltage division of R1, and the smaller the electric field strength of the clamping field plate 150. The closer the voltage divider point is to the source, the larger the voltage division of R1, and the greater the electric field strength of the clamping field plate 150.

[0073] By forming a voltage divider network with the clamping field plate 150 and the high-resistivity material (i.e., R1 and R2) in a designated area of ​​the terminal region, a field plate structure capable of dynamically adjusting its potential according to the source and drain voltage is realized within the chip and device. This eliminates the need for complex external drive circuits; the dynamically biased field plate structure can be achieved through internal integration, thereby improving device integration density. Therefore, by integrating the voltage divider resistors (i.e., R1 and R2) inside the chip, the complex, expensive, and parasitic external active drive circuits are eliminated. This not only reduces the cost and size of the chip system without increasing the device area but also improves reliability, consistency, and stability, making it ideal for cost-sensitive low-to-medium voltage applications. Furthermore, by integrating the voltage divider network of resistors R1 and R2, the clamping field plate transforms the potential establishment mechanism of the clamping field plate 150 from "passive sensing" to "active clamping," enabling the potential of the clamping field plate 150 to follow the drain voltage changes in real time and without loss, completely solving the inherent defects of floating field plates such as response hysteresis, modulation failure, and charge accumulation under high-frequency switching. This achieves a dynamic bias field plate structure that provides good frequency characteristics for the GaN HEMT device in this embodiment.

[0074] To gain a clearer understanding of the structural principles of the device in this embodiment, it is necessary to elaborate on the current collapse effect of typical GaN HEMT devices:

[0075] The current collapse effect in HEMT devices is also known as dynamic on-resistance degradation. The physical root of this effect lies in the fact that when the device operates in a high-voltage off-state, the gateless region between the gate and drain regions experiences extremely high vertical and lateral electric fields. Under this strong electric field, a "hot electron injection" effect occurs, causing a large number of charge carriers to be trapped by the surface states of the AlGaN barrier layer or the bulk traps of the GaN buffer layer. These trapped charges (predominantly electrons) form an equivalent "virtual gate" above the conductive channel, and the resulting depletion effect significantly reduces the density of the two-dimensional electron gas (2DEG).

[0076] Although applying a normal gate-on voltage can turn on the channel beneath the main gate region (i.e., the original gate region), the "virtual gate" effect caused by trapped charges still exists. This leads to a significant increase in the device's on-resistance after experiencing high-voltage stress, resulting in a decrease in its output current capability. This instability in dynamic characteristics not only reduces energy conversion efficiency, causing additional power loss and heat generation, but also poses a serious challenge to circuit design and reliability.

[0077] To reduce the current collapse effect, common field plate technologies are as follows:

[0078] 1. Gate Field Plate (GFP): The gate metal extends towards the drain, actively modulating the drain-side electric field through the gate potential, which can increase the breakdown voltage (BV) by 2-3 times. However, it significantly increases the gate-drain capacitance (Cgd), resulting in a decrease in switching speed, weak longitudinal electric field control in the off state, and insignificant reduction in dynamic resistance.

[0079] 2. Source Gate Field Plate (SFP): The source metal extends into the region between the gate and drain regions, and is at the same potential as the source region. Grounding at this potential suppresses charge accumulation, shortens the turn-on time by 40% (e.g., 2.75μs → 1.6μs), and reduces dynamic resistance by over 80%. The breakdown voltage is increased by approximately 1.5–2 times, though weaker than a gate field plate. However, a large area of ​​metal coverage introduces additional parasitic capacitance, affecting high-frequency response.

[0080] 3. Drain Field Plate (DFP): The drain region metal extends in an arc-shaped or S-shaped layout, often using resistive materials (such as oxygen-doped polysilicon). This bend in the path covers a larger drift region, reducing electric field abrupt changes, such as increasing BV by >300%; however, it requires high-precision etching, such as electron beam etching, increasing manufacturing costs. Furthermore, the resistive material degrades at high temperatures, affecting device reliability.

[0081] 4. Floating Field Plate (FFP): A metal field plate with an embedded passivation layer is not directly connected to any electrode. The electric field is modulated by electrostatic induction, resulting in a Cgd increase of less than 5%, which has almost no impact on high-frequency characteristics. However, the BV increase is relatively small, such as 20-30%. Furthermore, charge accumulation under dynamic operating conditions can lead to instability in electric field modulation, reducing the reliability and stability of the device.

[0082] Therefore, existing field plate structures and technologies suffer from poor current collapse suppression and degraded on-resistance.

[0083] The structural principle of the novel GaN HEMT device in this embodiment is as follows:

[0084] The principle of current collapse (on-resistance degradation) is as follows:

[0085] Figure 3 and Figure 4 This is a structural diagram of a HEMT device without a field plate structure. (Example) Figure 3 As shown, when the device is in the on state (Vgs > Vth) and an external voltage is applied (Vds > 0), the interface traps between the barrier layer (i.e., barrier layer 124) and the passivation layer above the barrier layer 124, as well as the volume traps of the buffer layer (i.e., buffer layer), are mostly filled. A 2DEG exists at the interface between the channel layer (i.e., channel layer 123) and the barrier layer (i.e., barrier layer 124). The region of the channel layer 123 between the gate region 130 and the drain region 131 is called the drift region. The channel is the contact surface between the channel layer 123 and the barrier layer 124, and the region located on the channel layer 123. Because the interface traps between the barrier layer 124 and the first passivation layer 160 are filled with electrons, they form a negatively charged "virtual gate" region, repelling electrons in the 2DEG, narrowing the 2DEG, and increasing the on-resistance.

[0086] like Figure 4As shown, when the device is in the off state (Vgs≤0) and an external voltage is applied (Vds>0), a large number of electrons trapped in the traps have enough energy to break through the trap barrier under the influence of a high electric field, becoming hot carriers and participating in leakage current. This results in the interface traps of the barrier layer (i.e., barrier layer 124) and the bulk traps of the buffer layer (i.e., buffer layer) being partially filled. Electrons of the 2DEG also move towards the drain under the applied electric field, forming leakage current, which leads to a decrease in the concentration of the 2DEG.

[0087] When the gate voltage of the device is turned on, i.e., Vgs > Vth, the source-drain voltage begins to decrease, and the traps will recapture electrons. During this stage, most electrons are used to fill the traps, resulting in a very small source-drain conduction current. Therefore, the device exhibits current collapse and a very high on-resistance, leading to dynamic on-resistance degradation.

[0088] In the novel GaN HEMT device of this embodiment, a composite structure of source field plate 140 and clamping field plate 150 is adopted. When the device in this embodiment is in the on state (Vgs > Vth) and an external voltage is applied (Vds > 0), the interface traps between the barrier layer (i.e., the barrier layer 124) and the first passivation layer 160, as well as the volume traps of the buffer layer (i.e., the buffer layer), are all in a partially filled state. For example... Figure 5 As shown, at this time, an electric field strength E2 is generated between the clamping field plate 150 and the channel, and an electric field strength E1 is generated between the source field plate 140 and the channel. Electrons in the interface trap will gain sufficient energy under the electric fields E1 and E2, thereby breaking through the trap barrier and being swept into the channel to participate in conduction, increasing the concentration of 2DEG and thus reducing the on-resistance. When the device is in the off state (Vgs≤0) and an external voltage (Vds>0) is applied, as... Figure 6 As shown, due to the increased voltage stress at the source and drain, most electrons in the traps will break through the potential barrier and be swept into the drift region. Therefore, most traps will be in an unfilled state at this time, a process similar to that of fieldless devices. However, when the device transitions from the off state to the on state, the number of electrons filling the traps decreases due to the presence of electric fields E1 and E2, meaning the decrease in source and drain current becomes smaller, current collapse is suppressed, and dynamic on-resistance decreases.

[0089] Furthermore, based on the introduction of E1 and E2, the electric field in the drift region is optimized, and the breakdown voltage BV of the device is improved. If the clamping field plate 150 is replaced with a floating field plate, E2 will decrease, weakening the current collapse suppression and electric field optimization, or even resulting in poor optimization. In addition, since the clamping field plate introduces an electric field strength from the drift region towards the clamping field plate in the drift region near the drain region 131, it can release some electrons trapped by the barrier layer 124, increasing the 2DEG concentration and thus effectively suppressing the current collapse effect.

[0090] By changing the ratio of R1 and R2 in the voltage divider network, and by using first passivation layers 160 and 161 with different thicknesses and dielectric constants, the potential of the CPFP can be altered, i.e., the strength of E2 can be changed. Thus, the potential of the clamping field plate 150 is no longer a fixed 0V or a certain positive voltage, but a voltage that dynamically changes with the drain voltage, achieving a dynamic and adaptive field plate potential. The voltage change of the clamping field plate 150 is determined by the clamping structure outside the device integrated within the chip, while the potential of the floating field plate is determined by charge coupling. In terms of response speed, the frequency characteristics of the clamping field plate are superior to those of the floating field plate, improving the high-frequency characteristics of the device.

[0091] In this embodiment, the composite field plate structure of clamping field plate 150 and source field plate 140 effectively optimizes the electric field distribution throughout the drift region when the device is off, achieving electric field homogenization in the drift region and improving the breakdown voltage. Simultaneously, it addresses the current collapse problem from two dimensions: prevention and compensation. On the one hand, it prevents the generation of hot electrons by optimizing the electric field distribution; on the other hand, it uses the dynamic potential of the field plate to offset the "virtual gate" effect formed by trapped charges in real time, thereby significantly suppressing the degradation of dynamic on-resistance.

[0092] To verify the performance of the GaN HEMT device in this embodiment, some simulation comparisons were performed on the device:

[0093] exist Figure 7 In the diagram, the horizontal axis represents the lateral distance from the cap layer 125 to the drain region 131, and the vertical axis represents the electric field strength corresponding to that lateral distance. Figure 7 and Figure 8 In this context, NO FP indicates a HEMT device without a field plate structure, SFP indicates a HEMT device using only the source field plate 140, SFP+FFP indicates a HEMT device using a composite structure of the source field plate 140 and a floating field plate, and SFP+CPFP indicates a HEMT device in this embodiment using a composite structure of the source field plate 140 and a clamping field plate 150. These devices differ only in their field plate structure; other structures are identical to those of the HEMT device in this embodiment. Figure 7 As shown in the electric field distribution curve, compared with the floating field plate FFP, the clamping field plate CPFP can increase the electric field intensity in the drift region and reduce the electric field spike at the drain terminal.

[0094] exist Figure 8 In the diagram, the horizontal axis represents the drain region voltage (131), and the vertical axis represents the drain region current (131). For example... Figure 8 As can be seen from the BV curve of the voltage-current of the drain region 131, the composite field plate structure of the source field plate 140 and the clamping field plate 150 adopted in this embodiment can improve the breakdown voltage BV of the device.

[0095] Below, in conjunction with Figure 1 The fabrication process of the novel GaN HEMT device in this embodiment is described in detail:

[0096] like Figure 9 As shown, epitaxial layers are grown on a Si substrate 110 whose size (e.g., 8 or 12 inches) can be set according to actual needs, in the following order and thickness:

[0097] AlN nucleation layers of 120 nm (150-250 nm) are stacked sequentially. 0.5 Ga 0.5 N (150-250nm) / Al 0.25 Ga 0.75 N (300-400nm) / Al 0.05 Ga 0.95 A gradient first buffer layer 121 with N (350-450nm), a GaN buffer layer (i.e., the second buffer layer 122) 500-800nm, an i-GaN channel layer 123 (200-400nm), and Al 0.23 Ga 0.77 The N-type barrier layer is 124 (10-20nm), and the PGaN capping layer is 125 (80-110nm). The capping layer 125 exists only in the active region, and no capping layer is set in the termination region.

[0098] like Figure 10 As shown, a Ti / TiN Schottky metal layer is deposited on the PGaN capping layer 125 using a PVD (Physical Vapor Deposition) process. A hard mask layer of SiO2 is then deposited on the surface of the Schottky metal layer using plasma-enhanced chemical vapor deposition (PECVD). The thickness of the Ti / TiN Schottky metal layer is 50 / 50 nm, but this thickness can be adjusted according to specific requirements. The thickness of the hard mask layer SiO2 is 160 nm, and this thickness can also be adjusted as needed.

[0099] like Figure 11 As shown, a suitable length of PGaN capping layer 125 region and gate metal region are defined using negative adhesive. After development, SiO2 / Ti / TiN / PGaN are etched away to form gate region 130 (i.e., gate electrode) and final capping layer 125 (i.e., PGaN gate).

[0100] like Figure 12 As shown, a first passivation layer 160 was deposited using plasma-enhanced chemical vapor deposition (PECVD). The material of the first passivation layer 160 is SiN. x3For example, Si3N4. The thickness of the first passivation layer 160 ranges from 100 to 200 nm.

[0101] like Figure 13 As shown, positive resist is used to define the photolithographic regions of the source and drain. Inductively Coupled Plasma (ICP) is used to etch the first passivation layer 160 and barrier layer 124 of the photolithographic regions of the source and drain, forming grooves for the source and drain. Positive resist is then used to define the photolithographic regions of the source, drain, and source field plate 140. After development, ohmic contact metal is deposited on the grooves of the source and drain and the first passivation layer 160 using a metal evaporation apparatus or a magnetron sputtering apparatus. After the metal is stripped and annealed, the source region 132, drain region 131, and source field plate 140 are formed. The metal materials and thicknesses of the source region 132, drain region 131, and source field plate 140 are all sequentially stacked Ti / Al / Ti / TiN metal layers with thicknesses of 50 / 300 / 20 / 30 nm.

[0102] like Figure 14 As shown, a second passivation layer 161 is deposited on the surfaces of the source field plate 140, the first passivation layer 160, and the drain region 131 using an HDP (High Density Plasma)-CVD (Chemical Vapor Deposition) process. The second passivation layer 161 is made of SiO2 and has a thickness ranging from 200 to 600 nm.

[0103] like Figure 15 As shown, positive photoresist is used to define the metal region of the clamp potential field plate. After development, a clamp potential field plate (CPFP) is deposited on the second passivation layer 161 and between the gate region 130 and the drain region 131 using a metal evaporation device or a magnetron sputtering device. The clamp potential field plate 150 is isolated from the source field plate 140 and their positions do not overlap.

[0104] like Figure 1 As shown, a third passivation layer 162 is deposited on the surfaces of the second passivation layer 161 and the clamping field plate 150 using an MOCVD (Metal-Organic Chemical Vapor Deposition) process, resulting in the complete HEMT device structure of this embodiment. It should also be noted that the third passivation layer 162 is formed above the barrier layer 124 in the termination region. After forming the third passivation layer 162 in the termination region, a high-resistivity material is deposited on the third passivation layer 162 to form a high-resistivity layer. By setting the high-resistivity layer, the layout structure of the HEMT device of this embodiment is formed.

[0105] The HEMT device of this embodiment is manufactured using the fabrication process described in this embodiment, which is compatible with existing processes, does not increase the device area, improves the device integration, and reduces manufacturing costs.

[0106] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0107] 1. When the device is in the off state, the clamping field plate can reduce the peak electric field near the source field plate and raise the electric field value in the middle of the drift region, making the electric field distribution in the drift region more flat. Compared with the floating field plate, it significantly improves the breakdown voltage.

[0108] 2. Because the clamping field plate introduces an electric field strength from the drift region to the clamping field plate in the drift region near the drain, some electrons trapped by the barrier layer are released, increasing the 2DEG concentration, thereby effectively suppressing the current collapse effect.

[0109] 3. Dynamic and Adaptive Field Plate Potential: In this embodiment, the clamped field plate potential is no longer a fixed 0V or a certain positive voltage, but a voltage that dynamically changes with the drain voltage. This voltage change is determined by the external clamping structure, while the potential of the floating field plate is determined by charge coupling. In terms of response speed, the frequency characteristics of the clamped field plate are superior to those of the floating field plate, improving the high-frequency characteristics of the device.

[0110] 4. High integration and low cost: By integrating the voltage divider resistors inside the chip, the complex, expensive, and parasitic external active drive circuitry is eliminated. This not only reduces the cost and size of the chip system but also improves reliability and consistency, making it ideal for cost-sensitive low- and medium-voltage applications.

[0111] 5. Perfect balance between performance and reliability: Particularly suitable for medium and low voltage applications. In these scenarios, the response speed of the integrated resistor fully meets the requirements. Furthermore, the electric field strength borne by the dielectric layer is far below the breakdown threshold, ensuring extremely high long-term reliability while achieving excellent dynamic on-resistance.

[0112] Example 2

[0113] Based on the same inventive concept, the second embodiment of the present invention also provides a method for fabricating a novel GaN HEMT device, such as... Figure 16 As shown, the method for fabricating the novel GaN HEMT device as described in Example 1 includes:

[0114] S201, in the active region, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a capping layer are formed sequentially on the substrate;

[0115] S202, a gate region is formed on the capping layer;

[0116] S203, a drain region is formed on the barrier layer;

[0117] S204, a source field plate is formed over the gate region, wherein the source field plate covers the gate region and the capping layer;

[0118] S205, a clamping field plate is formed above the barrier layer and between the gate region and the drain region, wherein the clamping field plate is isolated from the source field plate and the positions of the clamping field plate and the source field plate do not overlap.

[0119] Since the fabrication method of the novel GaN HEMT device described in this embodiment is the same as the fabrication method used in Embodiment 1 of this application, those skilled in the art can understand the specific implementation method and various variations of the fabrication method of the novel GaN HEMT device in this embodiment based on the novel GaN HEMT device described in Embodiment 1 of this application. Therefore, how the fabrication method of this novel GaN HEMT device implements the novel GaN HEMT device in Embodiment 1 of this application will not be described in detail here. As long as those skilled in the art implement the fabrication method used in Embodiment 1 of this application, it falls within the scope of protection of this application.

[0120] Those skilled in the art will understand that although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0121] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A GaN HEMT device, characterized in that, include: Active region; The active region includes: a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a capping layer stacked sequentially on the substrate, as well as a gate region, a drain region, a source field plate and a clamping field plate; The gate region is located above the capping layer; The source field plate is located above the gate region, and the source field plate covers the gate region and the capping layer; The drain region is located on the barrier layer; The clamping field plate is located above the barrier layer, between the gate region and the drain region, and isolated from the source field plate, and the positions of the clamping field plate and the source field plate do not overlap. A terminal area, which surrounds the active area; In the terminal region, a high-resistivity layer is laid on top of the barrier layer; On the layout of the device, in a designated area of ​​the high-resistivity layer located between the drain and source of the chip, a first high-resistivity region of the designated area is electrically connected to the clamping field plate through wiring vias. The designated area includes a first high-resistivity region and a second high-resistivity region. One end of the first high-resistivity region is connected to the drain of the chip, and the other end is connected to one end of the second high-resistivity region. The other end of the second high-resistivity region is connected to the source of the chip.

2. The GaN HEMT device as described in claim 1, characterized in that, The distance between the right end of the source field plate and the right end of the capping layer is 700-800 nm.

3. The GaN HEMT device as described in claim 2, characterized in that, The clamping field plate is positioned close to the drain region, and the length of the clamping field plate is a specified length, which is 1 / 4 to 1 / 3 of the gate-drain spacing between the gate region and the drain region.

4. The GaN HEMT device as described in claim 3, characterized in that, The center of the clamping field plate is located within 1 / 2 to 2 / 3 of the grid-leakage spacing.

5. The GaN HEMT device according to any one of claims 1 to 4, characterized in that, Also includes: Source region; the source region is located on the barrier layer, and the source field plate also covers the source region.

6. The GaN HEMT device as described in claim 5, characterized in that, Also includes: First passivation layer; The first passivation layer covers the surfaces of the capping layer, the gate region, and the barrier layer, and is located between the source region and the drain region, and is located below the source field plate.

7. The GaN HEMT device as described in claim 6, characterized in that, Also includes: Second passivation layer; The second passivation layer is located above the source field plate and the first passivation layer, and covers the source region, the source field plate, the first passivation layer and the drain region, and the second passivation layer is located below the clamping field plate.

8. The GaN HEMT device as described in claim 7, characterized in that, Also includes: Third passivation layer; The third passivation layer is located above the clamping field plate and covers the second passivation layer and the clamping field plate.

9. A method for fabricating a GaN HEMT device, characterized in that, The method for fabricating the GaN HEMT device according to any one of claims 1 to 8 comprises: In the active region, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a capping layer are formed sequentially on the substrate. A gate region is formed on the cap layer; A drain region is formed on the barrier layer; A source field plate is formed over the gate region, wherein the source field plate covers the gate region and the capping layer; A clamping field plate is formed above the barrier layer and between the gate region and the drain region, wherein the clamping field plate is isolated from the source field plate and the positions of the clamping field plate and the source field plate do not overlap.

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