Converter valve submodule IGBT (Insulated Gate Bipolar Translator) chip layout and packaging method for improving overcurrent capability

Abstract

The invention relates to a converter valve submodule IGBT (Insulated Gate Bipolar Translator) chip layout and packaging method for improving overcurrent capability, which belongs to the technical field of power semiconductor devices, and comprises the following steps of: designing a chip layout scheme of a converter valve submodule crimping type IGBT device; analyzing parasitic parameters of the chip; the packaging structure of the crimping type IGBT device is optimized; and carrying out overcurrent performance verification on the improved crimping type IGBT device. According to the invention, the parasitic inductance difference between the parallel branches is effectively reduced, and the current sharing characteristic under the overcurrent working condition is improved, so that the first overheating failure of local chips due to current concentration is avoided. According to the invention, the heat conduction performance from the chip to the heat dissipation path is optimized, the formation of local hot spots under the short-time high-power impact condition is inhibited, and the highest junction temperature of the device under the overcurrent working condition is obviously reduced.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device technology, and relates to a method for the layout and packaging of IGBT chips for a converter valve submodule to improve overcurrent capability. Background Technology

[0002] In flexible DC transmission systems, the converter valve submodule, as the core unit for power conversion and control, directly affects the safe and stable operation of the system due to the reliability of its internal power devices. Press-fit IGBT devices are widely used in converter valve submodules due to their advantages such as high current carrying capacity, low thermal resistance, and high reliability. To meet the demands of high-current operation, these devices typically employ a parallel structure of multiple IGBT chips to improve the overall current-carrying capacity. However, in actual operation, the converter valve submodule often needs to withstand short-term overcurrent surges during startup, fault ride-through, or system disturbances. In this case, the current distribution and temperature rise characteristics among the chips in the multi-chip parallel structure have a decisive impact on the device's overcurrent capability. Due to differences in chip spatial location, inconsistent parasitic inductance in parallel branches, and different heat dissipation paths, uneven current distribution and temperature distribution can easily occur among the chips under overcurrent conditions, causing some chip junction temperatures to exceed the safety threshold first, thus limiting the overall overcurrent withstand capability of the device.

[0003] Existing IGBT devices in converter valve submodules mostly employ regular arrays or empirical arrangements for chip layout, primarily prioritizing compact structure or ease of manufacturing. This approach fails to adequately consider the combined impact of chip spatial distribution on parasitic inductance uniformity, current sharing characteristics, and thermal coupling effects. Furthermore, in terms of device packaging, traditional packaging typically uses a single thermally conductive medium as the interface material between the chip and the electrode plate. Under short-duration, high-power surge conditions, its heat dissipation capability is limited, making it difficult to effectively suppress the formation of localized hot spots.

[0004] Furthermore, existing research on improving the overcurrent capability of press-fit IGBT devices focuses primarily on improving chip material performance or external heat dissipation conditions, while paying insufficient attention to the synergistic optimization between chip layout structure and packaging interface materials. There is a lack of a systematic technical solution that takes into account the overall chip spatial layout and packaging structure.

[0005] Therefore, how to improve the current sharing and heat distribution uniformity of multi-chip parallel devices under overcurrent conditions by rationally designing the spatial layout structure of IGBT chips in the commutation valve submodule and combining it with the application of high-efficiency packaging interface materials, thereby enhancing the overall overcurrent withstand capability of the device, has become an urgent technical problem to be solved. Summary of the Invention

[0006] In view of this, the purpose of this invention is to address the problems of uneven current distribution and excessive local temperature rise caused by unreasonable chip layout and insufficient thermal diffusion capability of the packaging structure in existing converter valve submodule press-fit IGBT devices under overcurrent conditions. This invention provides a chip layout and packaging method for improving the overcurrent capability of converter valve submodule IGBTs. By optimizing the chip space layout of multi-chip parallel IGBT devices and introducing high-efficiency packaging interface materials between the chips and adjacent components, the uniformity of parasitic inductance in the parallel branches and the uniformity of heat distribution inside the device are improved. This effectively reduces the maximum junction temperature under overcurrent conditions without changing the chip body structure, thereby improving the overcurrent withstand capability and operational reliability of the converter valve submodule IGBT devices.

[0007] To achieve the above objectives, the present invention provides the following technical solution: A method for laying out and packaging IGBT chips for improving overcurrent capability in a converter valve submodule includes the following steps: S1: Design the chip layout scheme for the press-fit type IGBT device of the converter valve submodule; S2: Analyze the parasitic parameters of the chip; S3: Optimize the packaging structure of the press-fit IGBT device; S4: Verify the overcurrent performance of the improved press-fit IGBT device.

[0008] Furthermore, the chip layout scheme described in step S1 is designed as follows: S11: Determine the number of chips, rated current per chip, and chip size parameters used in the press-fit IGBT device based on the rated current level and overcurrent operation requirements of the converter valve submodule. S12: While keeping the number of chips constant, construct a chip spatial layout scheme that optimizes the magnetic field distribution of the device, so that each chip has a different spatial distribution relative to the geometric center of the device.

[0009] Furthermore, through the chip layout design in step S1, the chips are distributed in a dispersed and symmetrical manner relative to the geometric center of the press-fit IGBT device.

[0010] Furthermore, step S2, which involves analyzing the parasitic parameters of the chip, includes: S21: For different chip layout schemes, calculate the spatial magnetic field distribution characteristics of each chip parallel branch under the conduction condition, so as to reflect the influence of different layout structures on electromagnetic coupling relationship. S22: Based on the spatial magnetic field distribution results, the parasitic inductance parameters corresponding to each parallel branch are extracted, and the uniformity of parasitic inductance under different layout schemes is compared and analyzed to evaluate the impact of chip layout on current sharing characteristics.

[0011] Furthermore, the optimization of the packaging structure of the press-fit IGBT device described in step S3 includes: S31: Select a high thermal conductivity interface material as the packaging medium between the chip and the molybdenum sheet or electrode plate; S32: Combining the chip layout scheme and interface material type, construct a chip-interface material-electrode plate packaging structure model to improve the thermal conductivity of the chip to the heat dissipation path.

[0012] Furthermore, the interface material includes one or more of liquid metal, thermally conductive silicone, or molybdenum-copper alloy.

[0013] Furthermore, the overcurrent performance verification in step S4 includes: S41: Under the same ambient temperature and heat dissipation conditions, apply overcurrent excitation to different chip layouts and packaging structures, perform electro-thermal coupling simulation analysis, and calculate the junction temperature distribution characteristics of the device under overcurrent conditions. S42: Extract the highest junction temperature of different schemes during the overcurrent duration and compare it with the allowable junction temperature threshold of the device to evaluate the improvement effect of different chip layouts and packaging structures on the overcurrent capability of the IGBT in the commutation valve submodule.

[0014] The beneficial effects of this invention are as follows: This invention proposes an IGBT chip layout and packaging structure for improving the overcurrent capability of a converter valve submodule. By optimizing the chip space layout of multi-chip parallel IGBT devices, the chips are distributed in a dispersed and symmetrical manner relative to the geometric center of the device, effectively reducing the parasitic inductance difference between parallel branches and improving the current sharing characteristics under overcurrent conditions, thereby preventing local chips from overheating and failing first due to current concentration. Simultaneously, this invention optimizes the thermal conductivity of the chip to the heat dissipation path by introducing a high-efficiency packaging interface material between the chip and adjacent components, suppressing the formation of local hot spots under short-term high-power impact conditions, and significantly reducing the maximum junction temperature of the device under overcurrent conditions. This invention does not require changes to the IGBT chip body structure and is suitable for the packaging upgrade of existing converter valve submodule press-fit IGBT devices. It can effectively improve the overcurrent withstand capability and operational reliability while ensuring device structural compatibility, and has good engineering practical value.

[0015] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0016] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 A flowchart illustrating the layout and packaging method of the IGBT chip for the converter valve submodule used to improve overcurrent capability; Figure 2 Finite element model of a press-fit IGBT device; Figure 3 The layout of IGBT devices is shown, where (a) is the original layout and (b) is the loop layout; Figure 4 The magnetic field distribution of the IGBT device is shown in (a) and (b) is the original layout. Figure 5 The thermal distribution of the device is shown in (a) and (b) is the original layout. Figure 6 The image shows a comparison of optimized liquid metal layouts, where (a) is the original layout and (b) is the loop layout. Detailed Implementation

[0017] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0018] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0019] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0020] Example 1: like Figure 1As shown, this invention provides a method for the layout and packaging of IGBT chips in a converter valve submodule to improve overcurrent capability, comprising the following steps: S1: Chip layout design.

[0021] S11: Based on the rated current level and overcurrent operation requirements of the converter valve submodule, determine the number of chips, rated current per chip, and chip size parameters used in the press-fit IGBT device, providing a basis for subsequent chip layout design.

[0022] S12: While keeping the number of chips constant, construct a chip spatial layout scheme that optimizes the magnetic field distribution of the device, so that each chip has a different spatial distribution relative to the geometric center of the device.

[0023] S2: Parasitic parameter analysis.

[0024] S21: For different chip layout schemes, calculate the spatial magnetic field distribution characteristics generated by the parallel branches of each chip under the conduction condition, so as to reflect the influence of different layout structures on the electromagnetic coupling relationship.

[0025] S22: Based on the spatial magnetic field distribution results, the parasitic inductance parameters corresponding to each parallel branch are extracted, and the uniformity of parasitic inductance under different layout schemes is compared and analyzed to evaluate the impact of chip layout on current sharing characteristics.

[0026] S3: Optimized packaging structure.

[0027] S31: Select a high thermal conductivity interface material as the encapsulation medium between the chip and the molybdenum sheet or electrode plate, wherein the interface material includes one or more of liquid metal, thermally conductive silicone, or molybdenum-copper alloy.

[0028] S32: Combining the chip layout scheme and interface material type, construct a chip-interface material-electrode plate packaging structure model to improve the thermal conductivity of the chip to the heat dissipation path.

[0029] S4: Overcurrent performance verification.

[0030] S41: Under the same ambient temperature and heat dissipation conditions, apply overcurrent excitation to different chip layouts and packaging structures, perform electro-thermal coupling simulation analysis, and calculate the junction temperature distribution characteristics of the device under overcurrent conditions.

[0031] S42: Extract the highest junction temperature of different schemes during the overcurrent duration and compare it with the allowable junction temperature threshold of the device to evaluate the improvement effect of different chip layouts and packaging structures on the overcurrent capability of the IGBT in the commutation valve submodule.

[0032] This embodiment takes the press-fit IGBT device used in the converter valve submodule of a flexible DC transmission system as the research object, such as... Figure 2 As shown, while keeping the total number of chips and rated current level unchanged, the chip space layout and packaging structure are optimized to verify the effectiveness of the present invention in improving the overcurrent capability of the device.

[0033] This embodiment uses the original chip layout as a comparison scheme, and on this basis, adopts the loop-shaped chip layout structure proposed in this invention, so that each chip is distributed in a ring shape along the periphery of the device, thereby improving the spatial symmetry of the parallel branches, such as... Figure 3 As shown in (a) and (b) below. Subsequently, the spatial magnetic field distribution of the device under conduction conditions is analyzed for both the original layout and the loop-shaped layout. (See figure below.) Figure 4 As shown in (a) and (b), after adopting the U-shaped chip layout, the magnetic field distribution inside the device is more uniform, and the magnetic field superposition effect between parallel branches is significantly reduced, thereby reducing the non-uniformity of parasitic inductance distribution and improving the current sharing characteristics under overcurrent conditions. The maximum, minimum, and variance of parasitic inductance under the two layout methods are shown in Table 1.

[0034] Table 1

[0035] Based on this, the thermal characteristics of the device under the U-shaped layout structure are further analyzed. This embodiment selects an overcurrent ratio of 2 P.U. and a duration of 10 s to perform electro-thermal coupling simulation calculations on the device. For example... Figure 5 As shown in (a) and (b), under the same overcurrent conditions, the highest junction temperature of the device with the loop layout structure is significantly lower than that of the regular array layout scheme, indicating that the loop layout structure can effectively suppress the formation of local hot spots.

[0036] Furthermore, based on the optimized chip layout, the device packaging structure is further improved. In this embodiment, a liquid metal thermally conductive material is introduced at the chip-molybdenum sheet contact interface to replace the traditional packaging interface medium, thereby improving the thermal conductivity between the chip and the electrode plate. A comparative analysis of the devices before and after the introduction of the liquid metal is performed under the same overcurrent conditions, and the junction temperature distribution results are as follows: Figure 6 As shown in (a) and (b), the results indicate that the introduction of liquid metal significantly enhances the internal thermal diffusion capability of the device and further reduces the maximum junction temperature.

[0037] In summary, through the optimized design of the chip layout structure and packaging interface material of the press-fit IGBT device in the converter valve submodule, it can be seen that the proposed loop-shaped chip layout structure can effectively improve the current sharing characteristics of multi-chip parallel devices under overcurrent conditions and reduce the risk of local current concentration. Simultaneously, the introduction of liquid metal thermally conductive material at the chip-molybdenum contact interface significantly enhances the internal heat diffusion capability of the device and suppresses the formation of local hot spots under short-term overcurrent impact conditions. Simulation results show that under the same overcurrent conditions, the device using the structure of this invention has a significantly lower maximum junction temperature than the traditional structure, fully verifying the effectiveness and engineering practicality of this invention in improving the overcurrent withstand capability of the IGBT in the converter valve submodule.

[0038] Example 2: An electronic device, comprising a memory and a processor; The memory is used to store computer programs; The processor is configured to implement the method described in Embodiment 1 when executing the computer program.

[0039] Example 3: A computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described in Embodiment 1.

[0040] Example 4: A computer program product includes a computer program that, when executed by a processor, implements the method described in Example 1.

[0041] In the above embodiments, the reference to "this embodiment" in the specification indicates that a specific feature, structure, or characteristic described in connection with the embodiment is included in at least some embodiments, but not necessarily all embodiments. Multiple appearances of "this embodiment" do not necessarily refer to the same embodiment.

[0042] In the above embodiments, although the invention has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory structures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed. The embodiments of the invention are intended to cover all such substitutions, modifications, and variations falling within the broad scope of the appended claims.

[0043] As will be understood by those skilled in the art, the computer-readable storage medium described in this embodiment allows for the implementation of all or part of the steps in the above method embodiments by computer program-related hardware. The aforementioned computer program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0044] The electronic terminal provided in this embodiment includes a processor, a memory, a transceiver, and a communication interface. The memory and the communication interface are connected to the processor and the transceiver and complete communication between them. The memory is used to store computer programs, the communication interface is used to perform communication, and the processor and the transceiver are used to run the computer programs, so that the electronic terminal performs the steps of the above method.

[0045] In this embodiment, the memory may include random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device.

[0046] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0047] This invention can be used in a wide range of general-purpose or special-purpose computing system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices, etc.

[0048] This invention can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This invention can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for layout and packaging IGBT chips in a converter valve submodule to improve overcurrent capability, characterized in that: Includes the following steps: S1: Design the chip layout scheme for the press-fit type IGBT device of the converter valve submodule; S2: Analyze the parasitic parameters of the chip; S3: Optimize the packaging structure of the press-fit IGBT device; S4: Verify the overcurrent performance of the improved press-fit IGBT device.

2. The IGBT chip layout and packaging method for improving overcurrent capability of the converter valve submodule according to claim 1, characterized in that: The chip layout scheme designed in step S1 is as follows: S11: Determine the number of chips, rated current per chip, and chip size parameters used in the press-fit IGBT device based on the rated current level and overcurrent operation requirements of the converter valve submodule. S12: While keeping the number of chips constant, construct a chip spatial layout scheme that optimizes the magnetic field distribution of the device, so that each chip has a different spatial distribution relative to the geometric center of the device.

3. The IGBT chip layout and packaging method for the converter valve submodule for improving overcurrent capability according to claim 2, characterized in that: The chip layout design in step S1 makes the chips distributed in a dispersed and symmetrical manner relative to the geometric center of the pressure-fit IGBT device.

4. The IGBT chip layout and packaging method for improving overcurrent capability of the converter valve submodule according to claim 1, characterized in that: Step S2, which involves analyzing the parasitic parameters of the chip, includes: S21: For different chip layout schemes, calculate the spatial magnetic field distribution characteristics of each chip parallel branch under the conduction condition, so as to reflect the influence of different layout structures on electromagnetic coupling relationship. S22: Based on the spatial magnetic field distribution results, the parasitic inductance parameters corresponding to each parallel branch are extracted, and the uniformity of parasitic inductance under different layout schemes is compared and analyzed to evaluate the impact of chip layout on current sharing characteristics.

5. The IGBT chip layout and packaging method for improving overcurrent capability of the converter valve submodule according to claim 1, characterized in that: Step S3, which involves optimizing the packaging structure of the press-fit IGBT device, includes: S31: Select a high thermal conductivity interface material as the packaging medium between the chip and the molybdenum sheet or electrode plate; S32: Combining the chip layout scheme and interface material type, construct a chip-interface material-electrode plate packaging structure model to improve the thermal conductivity of the chip to the heat dissipation path.

6. The IGBT chip layout and packaging method for improving overcurrent capability of the converter valve submodule according to claim 5, characterized in that: The interface material includes one or more of liquid metal, thermally conductive silicone, or molybdenum-copper alloy.

7. The IGBT chip layout and packaging method for improving overcurrent capability of the converter valve submodule according to claim 1, characterized in that: The overcurrent performance verification in step S4 includes: S41: Under the same ambient temperature and heat dissipation conditions, apply overcurrent excitation to different chip layouts and packaging structures, perform electro-thermal coupling simulation analysis, and calculate the junction temperature distribution characteristics of the device under overcurrent conditions. S42: Extract the highest junction temperature of different schemes during the overcurrent duration and compare it with the allowable junction temperature threshold of the device to evaluate the improvement effect of different chip layouts and packaging structures on the overcurrent capability of the IGBT in the commutation valve submodule.

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