Back contact battery, battery assembly and photovoltaic system

Abstract

The invention is applicable to the field of photovoltaic technology, and provides a back contact battery, a battery assembly and a photovoltaic system, the back contact battery comprises a silicon substrate which comprises a back surface and a front surface, and the back surface is provided with a first area and a second area; bulges are formed on the silicon substrate between the first region and the second region which are adjacent to each other; the first doping layer is arranged in the first region and is at least one of a doped amorphous silicon layer, a doped microcrystalline silicon layer and a doped nanocrystalline silicon layer; the second doping layer is arranged in the second region and is at least one of a doped polycrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer and a doped nanocrystalline silicon layer; the doping concentration of the isolation layer is less than or equal to 1E18 / cm < 3 >; a first transparent conductive film; the first metal electrode is electrically connected with the first doping layer; and the second metal electrode is electrically connected with the second doped layer. According to the back contact battery, the electrical isolation effect between the first doping layer and the second doping layer can be improved, and the risk of short-circuit electric leakage is reduced.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and in particular to a back-contact battery, battery module, and photovoltaic system. Background Technology

[0002] A solar cell is a semiconductor device that converts solar energy into electrical energy. Under sunlight, a solar cell generates a photocurrent, which is then output as electrical energy through electrodes. In recent years, solar cell manufacturing technology has continuously advanced, production costs have decreased, and conversion efficiency has increased. Solar cell power generation has become increasingly widespread and is an important energy source for electricity supply. In particular, because the metal electrodes of the back-contact cell are all located on the back side, the metal electrodes can avoid obstructing the front of the cell. Compared to bifacial cells with metal electrodes on both the front and back, this improves cell efficiency.

[0003] In related technologies, the back side of a back contact battery is usually provided with a first doped layer and a second doped layer with opposite doping types. The silicon substrate of the back contact battery is usually provided with a trench between the first doped layer and the second doped layer to isolate the first doped layer and the second doped layer and prevent short circuit between the first doped layer and the second doped layer. However, there is still a problem that the electrical isolation effect between the first doped layer and the second doped layer is poor. Summary of the Invention

[0004] This invention provides a back-contact battery, which aims to solve the problem of poor electrical isolation between the first doped layer and the second doped layer in existing back-contact batteries.

[0005] This invention is implemented by providing a back contact battery, comprising: A silicon substrate includes a back side and a front side disposed opposite to each other. The back side has a first region and a second region disposed alternately along a first direction. The first region and the second region extend along a second direction, which intersects the first direction. The silicon substrate has at least one protrusion formed between adjacent first regions and second regions. A first doped layer is disposed in the first region, wherein the first doped layer is at least one of amorphous silicon doped layer, microcrystalline silicon doped layer, and nanocrystalline silicon doped layer. A second doped layer is disposed in the second region, wherein the second doped layer is at least one of a doped polycrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer; An isolation layer is disposed on the back side and between the first doped layer and the second doped layer. The doping concentration of the isolation layer is less than that of the first doped layer and the second doped layer, and the doping concentration of the isolation layer is less than or equal to 1E18 / cm. 3 ; A first transparent conductive film is disposed on the surface of the first doped layer opposite to the silicon substrate; A first metal electrode in contact with the first transparent conductive film, wherein the first metal electrode forms an electrical connection with the first doped layer through the first transparent conductive film; and A second metal electrode electrically connected to the second doped layer.

[0006] Preferred, including: A second transparent conductive film is disposed between the second metal electrode and the second doped layer. The second metal electrode is electrically connected to the second doped layer through the second transparent conductive film, and the first transparent conductive film and the second transparent conductive film are spaced apart.

[0007] Preferably, the second doped layer is a doped polycrystalline silicon layer, and the second metal electrode is in contact with the second doped layer to form an electrical connection.

[0008] Preferred options also include: A first dielectric layer is disposed in the first region, located between the silicon substrate and the first doped layer; and The second dielectric layer is disposed in the second region and is located between the silicon substrate and the second doped layer.

[0009] Preferably, the first dielectric layer is an intrinsic amorphous silicon layer.

[0010] Preferably, the second dielectric layer is a tunneling layer and the second doped layer is a doped polycrystalline silicon layer; or, the second dielectric layer is an intrinsic amorphous silicon layer and the second doped layer is at least one of a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer.

[0011] Preferably, the tunneling layer is one or a combination of at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, and silicon carbide layer.

[0012] Preferably, the first region is provided with a first velvet structure.

[0013] Preferably, the second doped layer is a doped polycrystalline silicon layer, and the second region is set as a polished surface.

[0014] Preferably, the second doped layer is at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon, and the second region is provided with a second textured surface structure.

[0015] Preferably, the isolation layer is at least partially disposed on the protrusion.

[0016] Preferably, the isolation layer has trenches that partially or completely penetrate the isolation layer along the thickness direction of the silicon substrate.

[0017] Preferably, the trench partially penetrates the isolation layer along the thickness direction of the silicon substrate, and the ratio of the depth of the trench to the thickness of the isolation layer is 0.5 to 0.9.

[0018] Preferably, the trench completely penetrates the isolation layer along the thickness direction of the silicon substrate, with the center plane along the thickness direction of the silicon substrate as the reference plane, and the distance from the bottom surface of the trench to the center plane is greater than the distance from the plane containing the first region to the center plane and the distance from the plane containing the second region to the center plane.

[0019] Preferably, the trench penetrates the isolation layer along the second direction.

[0020] Preferably, the trench completely penetrates the isolation layer along the thickness direction of the silicon substrate, and the protrusion has a third textured structure corresponding to the position of the trench.

[0021] Preferably, the third textured structure includes at least one of a regular pyramid, an inverted pyramid, a nanopillar, and a nanopore.

[0022] Preferably, the width of the groove along the first direction is 10 to 200 micrometers.

[0023] Preferably, the height of the protrusion is 2 to 15 micrometers.

[0024] Preferably, the width of the protrusion along the first direction is 20 to 350 micrometers.

[0025] Preferably, the difference between the width of the protrusion along the first direction and the width of the groove along the first direction is greater than 20 micrometers.

[0026] Preferably, the trench is filled with a polymer insulating material.

[0027] Preferred options also include: A third dielectric layer is disposed between the isolation layer and the raised surface, and the trench penetrates the third dielectric layer.

[0028] Preferably, the insulating layer is doped with at least one of oxygen, nitrogen, and carbon. The oxygen concentration in the isolation layer is 1×10⁻⁶. 16 ~2×10 22 atoms / cm 3 And / or, the nitrogen concentration in the isolation layer is 1×10⁻⁶. 16 ~2×10 22 atoms / cm 3 And / or, the concentration of carbon in the isolation layer is 1×10⁻⁶.16 ~2×10 22 atoms / cm 3 .

[0029] Preferably, the number of protrusions between adjacent first and second regions is 1 to 3.

[0030] Preferably, the isolation layer further includes: A first extension extending into the first region, the first extension covering a portion of the first region, the first extension being connected to the first doped layer along the first direction; A second extension extending into the second region, the second extension covering a portion of the second region, the second extension being connected to the second doped layer along the first direction.

[0031] Preferably, along the thickness direction of the silicon substrate, the protrusion includes a first end portion away from the front surface and a second end portion close to the front surface, wherein the width of the first end portion along the first direction is greater than the width of the second end portion along the first direction.

[0032] Preferably, the height of the first metal electrode and the height of the second metal electrode are both greater than the height of the protrusion.

[0033] Preferably, the isolation layer is an intrinsic semiconductor layer or a doped semiconductor layer.

[0034] Preferably, the intrinsic semiconductor layer is at least one of an intrinsic polycrystalline silicon layer, an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, and an intrinsic nanocrystalline silicon layer.

[0035] Preferably, the doped semiconductor layer is at least one of a doped polycrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer.

[0036] Preferably, the doping concentration of the isolation layer is less than 2E17 / cm. 3 .

[0037] Preferably, the doping concentration of the isolation layer is less than 1E17 / cm. 3 .

[0038] Preferably, the doping concentration of both the second doped layer and the first doped layer is greater than 1E19 / cm. 3 .

[0039] The present invention also provides a battery assembly including the aforementioned back contact battery.

[0040] The present invention also provides a photovoltaic system including the above-described battery module.

[0041] The present invention provides a back-contact battery having alternating first and second regions along a first direction on the back side of a silicon substrate. A first doped layer is disposed in the first region, and a second doped layer is disposed in the second region. The first doped layer is at least one of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. The second doped layer is at least one of doped polycrystalline silicon, doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. At least one protrusion is formed between adjacent first and second regions on the silicon substrate, and the first and second doped layers are separated by at least one protrusion, achieving electrical isolation between the first and second doped layers. Simultaneously, an isolation layer is disposed on the back side, located between the first and second doped layers. The doping concentration of the isolation layer is less than the doping concentrations of the first and second doped layers, and the doping concentration of the isolation layer is less than or equal to 1E18 / cm². 3 This controls the doping concentration of the isolation layer to be less than or equal to 1E18 / cm. 3 By utilizing a low-doping concentration isolation layer, the current transmission capability of the isolation layer is relatively weak. Under this doping concentration, the isolation layer can prevent conduction between the first doped layer and the second doped layer. The back contact battery of the present invention uses the isolation layer and the protrusions in combination to achieve isolation between the first doped layer and the second doped layer, which can improve the electrical isolation effect between the first doped layer and the second doped layer, greatly reduce the risk of short circuit leakage between the first doped layer and the second doped layer, and improve the performance of the back contact battery. Attached Figure Description

[0042] Figure 1 A cross-sectional schematic diagram of the back contact battery of the first embodiment provided in this invention; Figure 2 This is a schematic diagram of the back contact battery portion structure of the first embodiment of the present invention; Figure 3 for Figure 1 A magnified view of part A in the middle; Figure 4 A cross-sectional schematic diagram of the back contact battery according to a second embodiment of the present invention; Figure 5 A cross-sectional schematic diagram of the back contact battery according to a third embodiment of the present invention; Figure 6 This is a schematic diagram of the back contact battery portion structure of the third embodiment provided in this invention. Figure 7 for Figure 5 A magnified view of part B in the middle; Figure 8 A cross-sectional schematic diagram of the back contact battery according to the fourth embodiment of the present invention; Figure 9A cross-sectional schematic diagram of the back contact battery according to the fifth embodiment of the present invention; Figure 10 A cross-sectional schematic diagram of the back contact battery according to the sixth embodiment of the present invention; Figure 11 This is a cross-sectional schematic diagram of the back contact battery according to the seventh embodiment of the present invention.

[0043] Explanation of key symbols: Back contact battery 100, silicon substrate 1, back side 11, front side 12, first direction X, second direction Y, first region 111, second region 112, first textured structure 1111, second textured structure 1121, protrusion 13, first doped layer 2, second doped layer 3, isolation layer 4, trench 40, third textured structure 1311, first metal electrode 5, second metal electrode 6, first transparent conductive film 16, second transparent conductive film 17, insulating opening 18, polymer insulating material 7, first dielectric layer 8, second dielectric layer 9, third dielectric layer 10, first extension 41, second extension 42, top surface 130, first side surface 131, second side surface 132. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. Examples of embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the invention, and should not be construed as limiting the invention. Furthermore, it should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0045] In the description of this invention, it should be understood that the terms "upper", "lower", "back", "front", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0046] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0047] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0048] Please refer to Figures 1-3 This invention provides a back contact battery 100, comprising: The silicon substrate 1 includes a back side 11 and a front side 12 disposed opposite to each other. The back side 11 has a first region 111 and a second region 112 disposed alternately along a first direction X. The first region 111 and the second region 112 extend along a second direction Y, which intersects with the first direction X. The silicon substrate 1 has at least one protrusion 13 formed between adjacent first regions 111 and second regions 112. A first doped layer 2 is provided in the first region 111. The first doped layer 2 is at least one of amorphous silicon doping, microcrystalline silicon doping, and nanocrystalline silicon doping. A second doped layer 3 is provided in the second region 112. The second doped layer 3 is at least one of a doped polycrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer. An isolation layer 4 is disposed on the back side 11 and located between the first doped layer 2 and the second doped layer 3. The doping concentration of the isolation layer 4 is less than that of the first doped layer 2 and the second doped layer 3, and the doping concentration of the isolation layer 4 is less than or equal to 1E18 / cm. 3 ; A first transparent conductive film 16 is disposed on the surface of the first doped layer 2 away from the silicon substrate 1; The first metal electrode 5 is in contact with the first transparent conductive film 16, and the first metal electrode 5 forms an electrical connection with the first doped layer 2 through the first transparent conductive film 16; and The second metal electrode 6 is electrically connected to the second doped layer 3.

[0049] An embodiment of the present invention provides a back-contact battery 100 by forming a first region 111 and a second region 112 alternately spaced along a first direction X on the back side 11 of a silicon substrate 1. A first doped layer 2 is formed in the first region 111, and a second doped layer 3 is formed in the second region 112. The first doped layer 2 is at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon, and the second doped layer 3 is at least one of polycrystalline silicon, amorphous silicon, microcrystalline silicon, and nanocrystalline silicon. At least one protrusion 13 is formed between adjacent first regions 111 and second regions 112 on the silicon substrate 1, and the first doped layer 2 and the second doped layer 3 are separated by at least one protrusion 13, which can achieve electrical isolation between the first doped layer 2 and the second doped layer 3. At the same time, an isolation layer 4 is formed on the back side 11, located between the first doped layer 2 and the second doped layer 3. The doping concentration of the isolation layer 4 is less than the doping concentration of the first doped layer 2 and the second doped layer 3, and the doping concentration of the isolation layer 4 is less than or equal to 1E18 / cm. 3 Thus, the doping concentration of isolation layer 4 is controlled to be less than or equal to 1E18 / cm. 3 By utilizing the low doping concentration of the isolation layer 4, the current transmission capability of the isolation layer 4 is relatively weak. Under this doping concentration, the isolation layer 4 can prevent conduction between the first doped layer 2 and the second doped layer 3. The back contact battery 100 of the present invention utilizes the combination of the isolation layer 4 and the protrusion 13 to greatly improve the electrical isolation effect between the first doped layer 2 and the second doped layer 3, greatly reduce the risk of short circuit leakage between the first doped layer 2 and the second doped layer 3, thereby improving the performance of the back contact battery 100.

[0050] In this embodiment of the invention, the silicon substrate 1 includes a back side 11 and a front side 12 disposed opposite to each other along the thickness direction Z of the silicon substrate 1. The front side 12 of the silicon substrate 1 is the side of the silicon substrate 1 that mainly receives sunlight when the back contact battery 100 is working normally, and the back side 11 of the silicon substrate 1 is the surface opposite to the front side 12 of the silicon substrate 1.

[0051] In this embodiment of the invention, the first region 111 and the second region 112 extend along the second direction Y, that is, the length direction of both the first region 111 and the second region 112 is along the second direction Y. There are multiple first doped layers 2 and second doped layers 3, which are alternately arranged along the first direction X, and both the first doped layers 2 and the second doped layers 3 extend along the second direction Y. Furthermore, the protrusion 13 and the isolation layer 4 also extend along the second direction Y, that is, the length direction of the first doped layer 2, the second doped layer 3, the protrusion 13, and the isolation layer 4 is all along the second direction Y. Preferably, the dimension of the protrusion 13 along the second direction Y is equal to the dimension of the isolation layer 4 along the second direction Y, and the dimension of the protrusion 13 along the second direction Y is equal to the dimension of either the first doped layer 2 or the second doped layer 3 along the second direction Y. The first direction X and the second direction Y can be perpendicular or not perpendicular. Preferably, the first direction X and the second direction Y are perpendicular.

[0052] In this embodiment of the invention, the first doped layer 2 is at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon. This can be understood as the first doped layer 2 being one of these three types, or a stack of at least two of them. The second doped layer 3 is at least one of polycrystalline silicon, amorphous silicon, microcrystalline silicon, and nanocrystalline silicon. This can be understood as the second doped layer 3 being one of these three types, or a stack of at least two of them. For example, the first doped layer 2 can be amorphous silicon and the second doped layer 3 can be polycrystalline silicon; or, for another example, the first doped layer 2 can be amorphous silicon and the second doped layer 3 can be amorphous silicon.

[0053] In this embodiment of the invention, one of the first doped layer 2 and the second doped layer 3 is a P-type doped layer, and the other is an N-type doped layer, and the specific doping types of the first doped layer 2 and the second doped layer 3 are not limited. Specifically, the first doped layer 2 can be a P-type doped layer and the second doped layer 3 can be an N-type doped layer; or the first doped layer 2 can be an N-type doped layer and the second doped layer 3 can be a P-type doped layer. The P-type doped layer is doped with a P-type dopant element, that is, it is doped with P-type dopant atoms; the N-type doped layer is doped with an N-type dopant element, that is, it is doped with N-type dopant atoms. The P-type dopant element is a Group IIIA element in the periodic table, and the N-type dopant element is a Group VA element in the periodic table. For example, the P-type dopant element can be boron, and the N-type dopant element can be phosphorus.

[0054] In this embodiment of the invention, the isolation layer 4 may or may not be disposed on the surface of the protrusion 13. That is, the surface of the protrusion 13 may have the isolation layer 4 disposed on it, or the surface of the protrusion 13 may not have the isolation layer 4 disposed on it. When the isolation layer 4 is disposed on the surface of the protrusion 13, the isolation layer 4 covers at least a portion of the surface of the protrusion 13, that is, the isolation layer 4 may cover a portion of the surface of the protrusion 13 or cover the entire surface of the protrusion 13. In this case, a portion or all of the surface of the protrusion 13 is covered by the isolation layer 4.

[0055] like Figure 1 As shown, in one embodiment of the present invention, the isolation layer 4 is at least partially disposed on the protrusion 13.

[0056] In this embodiment, the insulating layer 4 is at least partially disposed on the protrusion 13. This can be understood as the insulating layer 4 covering at least a portion of the surface of the protrusion 13, that is, the insulating layer 4 is at least partially located on the protrusion 13, and part or all of the surface of the protrusion 13 is covered by the insulating layer 4. In practical applications, the back contact battery 100 may have the insulating layer 4 disposed on a portion of the surface of the protrusion 13, or the insulating layer 4 may be disposed on all the surface of the protrusion 13. Since the isolation layer 4 is at least partially disposed on the protrusion 13, that is, the design of adding the isolation layer 4 on the protrusion 13, the isolation layer 4 superimposed on the surface of the protrusion 13 can improve the electrical isolation effect between the first doped layer 2 and the second doped layer 3. Moreover, due to the presence of the protrusion 13, the isolation layer 4 is disposed on the surface of the protrusion 13, and the isolation layer 4 can extend from the first region 111 to the second region 112 along the surface of the protrusion 13, which is conducive to increasing the size of the isolation layer 4 along the surface of the protrusion 13, that is, increasing the creepage distance between the first doped layer 2 and the second doped layer 3, thereby greatly improving the electrical isolation effect between the first doped layer 2 and the second doped layer 3. Therefore, the isolation layer 4 is at least partially disposed on the protrusion 13, which can further increase the electrical isolation effect between the first doped layer 2 and the second doped layer 3, further reduce the short circuit leakage risk of the first doped layer 2 and the second doped layer 3, and better improve the performance of the back contact battery 100.

[0057] In this embodiment, at least one protrusion 13 is provided between adjacent first doped layer 2 and second doped layer 3, and an isolation layer 4 is provided on the surface of the protrusion 13. The first doped layer 2 and the second doped layer 3 are isolated by the protrusion 13 and the isolation layer 4, so as to achieve good electrical isolation between the second doped layer 3 and the first doped layer 2.

[0058] In some embodiments, the isolation layer 4 may not be disposed on the protrusion 13, that is, the surface of the protrusion 13 may not be provided with the isolation layer 4. The isolation layer 4 may be disposed in the region between the first doped layer 2 and the second doped layer 3 where the protrusion 13 is not disposed. For example, the isolation layer 4 may be disposed in the region of the first region 111 near the protrusion 13, and / or, the isolation layer 4 may be disposed in the region of the second region 112 near the protrusion 13. Electrical isolation between the first doped layer 2 and the second doped layer 3 can also be achieved using the protrusion 13 and the isolation layer 4. In addition, in some embodiments, when multiple protrusions 13 are disposed between adjacent first doped layers 2 and second doped layers 3, the isolation layer 4 may only cover the region between adjacent protrusions 13 on the back surface 11, or the isolation layer 4 may only cover the surface of the protrusion 13, or the isolation layer 4 may cover the surface of the protrusion 13 and the region between adjacent protrusions 13 on the back surface 11.

[0059] In this embodiment of the invention, the protrusion 13 protrudes towards the back surface 11 away from the silicon substrate 1, relative to the plane of the first region 111 and the plane of the second region 112. This causes the first doped layer 2 and the second doped layer 3 to be located on opposite sides of the protrusion 13 along the first direction X. Thus, the protrusion 13 physically isolates the first doped layer 2 and the second doped layer 3, achieving electrical isolation between them. The number of protrusions 13 formed on the silicon substrate 1 between adjacent first regions 111 and second regions 112 is unlimited. For example, as... Figure 1 As shown, a protrusion 13 is formed on the silicon substrate 1 between adjacent first regions 111 and second regions 112. An isolation layer 4 is disposed on the protrusion 13, and the first doped layer 2 and the second doped layer 3 are isolated by the protrusion 13 and the isolation layer 4; or, for example, Figure 4 As shown, the silicon substrate 1 forms two protrusions 13 between adjacent first regions 111 and second regions 112. The two protrusions 13 are spaced apart in the first direction X. An isolation layer 4 is disposed on the protrusions 13. The first doped layer 2 and the second doped layer 3 are isolated by the two protrusions 13 and the isolation layer 4, which helps to further increase the isolation effect of the protrusions 13 between the first doped layer 2 and the second doped layer 3. For example, the silicon substrate 1 forms three protrusions 13 between adjacent first regions 111 and second regions 112. The three protrusions 13 are spaced apart in the first direction X. The first doped layer 2 and the second doped layer 3 are isolated by the three protrusions 13, which helps to further improve the isolation effect between the first doped layer 2 and the second doped layer 3. Of course, the number of protrusions 13 formed on the silicon substrate 1 between adjacent first regions 111 and second regions 112 can be greater than three, which can further improve the electrical isolation effect between the first doped layer 2 and the second doped layer 3.

[0060] In a preferred embodiment of the present invention, the number of protrusions 13 between adjacent first regions 111 and second regions 112 is 1 to 3.

[0061] In this embodiment, the number of protrusions 13 between adjacent first regions 111 and second regions 112 is controlled to be 1 to 3. This can achieve good electrical isolation between the first doped layer 2 and the second doped layer 3, and avoid the excessive number of protrusions 13 between the first regions 111 and second regions 112, which would result in an excessively large area ratio of the protrusions 13 on the back side 11. This ensures sufficient area for the first regions 111 and second regions 112, thereby guaranteeing good power generation efficiency of the battery.

[0062] In this embodiment of the invention, the isolation layer 4 may cover only a portion of the protrusion 13, or it may cover the entire protrusion 13. Specifically, when there is one protrusion 13 between adjacent first regions 111 and second regions 112, the isolation layer 4 covers at least a portion of the protrusion 13. This can be understood as the isolation layer 4 covering a portion or all of the protrusion 13; when there are two or more protrusions 13 between adjacent first regions 111 and second regions 112, that is, when there are two or more protrusions 13, the isolation layer 4 covers a portion or all of at least one protrusion 13.

[0063] In this embodiment of the invention, the specific shape of the protrusion 13 is not limited, and the protrusion 13 can specifically be a boss. The cross-sectional shape of the protrusion 13 can be at least one of square, semi-circular, and trapezoidal.

[0064] As an embodiment of the present invention, the protrusion 13 includes a top surface 130 disposed away from the front surface 12 along the thickness direction Z of the silicon substrate 1, a first side surface 131 and a second side surface 132 disposed opposite to each other along the first direction X, the first side surface 131 and the second side surface 132 being connected to the top surface 130 respectively, and the isolation layer 4 covering at least one of the top surface 130, the first side surface 131 and the second side surface 132.

[0065] In this embodiment, the isolation layer 4 covers at least one of the top surface 130, the first side surface 131, and the second side surface 132. This can be understood as the isolation layer 4 covering only a portion of at least one of the top surface 130, the first side surface 131, and the second side surface 132, or covering the entire area of ​​at least one of the top surface 130, the first side surface 131, and the second side surface 132. Preferably, the isolation layer 4 simultaneously covers the top surface 130, the first side surface 131, and the second side surface 132, which can significantly increase the spread length of the isolation layer 4 along the surface of the protrusion 13, further enhancing the isolation effect of the isolation layer 4 on the first doped layer 2 and the second doped layer 3.

[0066] In this embodiment of the invention, the isolation layer 4 may be doped with p-type or n-type doped atoms, or it may not be doped with p-type or n-type doped atoms. When the isolation layer 4 is not doped with p-type or n-type doped atoms, the doping concentration of the isolation layer 4 is 0 / cm. 3 When the isolation layer 4 is doped with p-type or n-type dopant atoms, the doping type of the isolation layer 4 is the same as that of the first doped layer 2 or the second doped layer 3. That is, the doping type of the isolation layer 4 is the same as that of the first doped layer 2, or the doping type of the isolation layer 4 is the same as that of the second doped layer 3. Specifically, both the isolation layer 4 and the first doped layer 2 are doped with p-type dopant atoms, and the second doped layer 3 is doped with n-type dopant atoms; or, both the isolation layer 4 and the first doped layer 2 are doped with n-type dopant atoms, and the second doped layer 3 is doped with p-type dopant atoms.

[0067] In this embodiment of the invention, the doping concentration of the isolation layer 4 is the concentration of doped atoms in the active state in the isolation layer 4, the doping concentration of the first doped layer 2 is the concentration of doped atoms in the active state in the first doped layer 2, and the doping concentration of the second doped layer 3 is the concentration of doped atoms in the active state in the second doped layer 3.

[0068] Specifically, when the doping type of the isolation layer 4 is P-type, the doping concentration of the isolation layer 4 is the concentration of the active P-type doped atoms in the isolation layer 4; conversely, when the doping type of the isolation layer 4 is N-type, the doping concentration of the isolation layer 4 is the concentration of the active N-type doped atoms in the isolation layer 4.

[0069] When the doping type of the first doped layer 2 is P-type, the doping concentration of the first doped layer 2 is the concentration of P-type doped atoms in the active state in the first doped layer 2; when the doping type of the first doped layer 2 is N-type, the doping concentration of the first doped layer 2 is the concentration of N-type doped atoms in the active state in the first doped layer 2.

[0070] When the doping type of the second doped layer 3 is P-type, the doping concentration of the second doped layer 3 is the concentration of P-type doped atoms in the active state in the second doped layer 3; when the doping type of the second doped layer 3 is N-type, the doping concentration of the second doped layer 3 is the concentration of N-type doped atoms in the active state in the second doped layer 3.

[0071] In this embodiment of the invention, the doping concentration of the isolation layer 4 is less than that of the first doping layer 2 and the second doping layer 3. This can be understood as the concentration of active doped atoms in the isolation layer 4 being less than that of active doped atoms in the first doping layer 2, and the concentration of active doped atoms in the isolation layer 4 being less than that of active doped atoms in the second doping layer 3.

[0072] The doping concentration of the isolation layer 4 is less than or equal to 1E18 / cm³. 3This can be understood as the concentration of doped atoms in the active state in isolation layer 4 being less than or equal to 1E18 / cm³. 3 For example, if the doped atom in isolation layer 4 is a phosphorus atom, then the concentration of activated phosphorus atoms in isolation layer 4 is less than or equal to 1E18 / cm³. 3 If the doped atom in isolation layer 4 is boron atom, then the concentration of active boron atom in isolation layer 4 is less than or equal to 1E18 / cm³. 3 .

[0073] In this embodiment of the invention, the doping concentration of the isolation layer 4 can be less than or equal to 1E18 / cm². 3 Any value in the range. For example, the doping concentration of the isolation layer 4 can be 0 / cm. 3 1E3 / cm 3 1E4 / cm 3 1E5 / cm 3 1E6 / cm 3 1E8 / cm 3 1E9 / cm 3 1E10 / cm 3 1E11 / cm 3 1E12 / cm 3 1E13 / cm 3 1E14 / cm 3 1E15 / cm 3 1E16 / cm 3 1E17 / cm 3 2E17 / cm 3 3E17 / cm 3 4E17 / cm 3 5E17 / cm 3 1E18 / cm 3 Any value in the range.

[0074] As an embodiment of the present invention, the isolation layer 4 is an intrinsic semiconductor layer or a doped semiconductor layer.

[0075] In this embodiment of the invention, the isolation layer 4 can be made of the same material as the first doped layer 2 and the second doped layer 3, or it can be different. When the isolation layer 4 is an intrinsic semiconductor layer or a doped semiconductor layer, the current transport capability of the isolation layer 4 is relatively weak, which can achieve good isolation between the first doped layer 2 and the second doped layer 3. Of course, in some embodiments, the isolation layer 4 can also be an insulating material. For example, the isolation layer 4 can be one or more of silicon oxide, silicon nitride, and silicon oxynitride layers, and the doping concentration of the isolation layer 4 is less than or equal to 1E18 / cm³. 3 .

[0076] As an embodiment of the present invention, the intrinsic semiconductor layer is at least one of an intrinsic polycrystalline silicon layer, an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, and an intrinsic nanocrystalline silicon layer. It can be understood that the isolation layer 4 can be one or a stack of at least two of the intrinsic polycrystalline silicon layer, intrinsic amorphous silicon layer, intrinsic microcrystalline silicon layer, and intrinsic nanocrystalline silicon layer. Preferably, the isolation layer 4 is an intrinsic amorphous silicon layer or an intrinsic polycrystalline silicon layer.

[0077] In one embodiment of the present invention, the doped semiconductor layer is at least one of a doped polycrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer. Preferably, the isolation layer 4 and the first doped layer 2 are integrally formed, which facilitates the integral molding and fabrication of the isolation layer 4 and the first doped layer 2. Specifically, the first doped layer 2, the second doped layer 3, and the isolation layer 4 are doped polycrystalline silicon layers, and the doping type of the isolation layer 4 is the same as the doping type of the first doped layer 2 or the second doped layer 3.

[0078] In one embodiment of the present invention, the doping concentration of the isolation layer 4 is less than 2E17 / cm. 3 .

[0079] In this embodiment, the doping concentration of the isolation layer 4 is controlled to be less than 2E17 / cm. 3 This further reduces the doping concentration of isolation layer 4, which helps to ensure the good electrical isolation effect of isolation layer 4.

[0080] As an embodiment of the present invention, the doping concentration of the isolation layer 4 is less than 1E17 / cm. 3 .

[0081] In this embodiment, the doping concentration of the isolation layer 4 is controlled to be less than 1E17 / cm. 3 This further reduces the doping concentration of isolation layer 4, which helps to ensure the good isolation effect of isolation layer 4.

[0082] In one embodiment of the present invention, both the first doped layer 2 and the isolation layer 4 are doped with group VA elements, the second doped layer 3 is doped with group IIIA elements, and the doping concentration of the isolation layer 4 is less than 3E17 / cm³. 3 .

[0083] In this embodiment, both the first doped layer 2 and the isolation layer 4 are doped with group VA elements from the periodic table, and the second doped layer 3 is doped with group IIIA elements from the periodic table. The doping concentration of the isolation layer 4 is controlled to be less than 3E17 / cm³. 3 This ensures good isolation effect of isolation layer 4, while also facilitating the control of doping concentration and processing.

[0084] In one embodiment of the present invention, both the first doped layer 2 and the isolation layer 4 are doped with group IIIA elements, the second doped layer 3 is doped with group VA elements, and the doping concentration of the isolation layer 4 is less than 1E17 / cm³. 3 .

[0085] In this embodiment, both the first doped layer 2 and the isolation layer 4 are doped with Group IIIA elements from the periodic table, and the second doped layer 3 is doped with Group VA elements from the periodic table. The doping concentration of the isolation layer 4 is controlled to be less than 1E17 / cm³. 3 This ensures good isolation effect of isolation layer 4, while also facilitating the control of doping concentration and processing.

[0086] In one embodiment of the present invention, the doping concentrations of both the second doped layer 3 and the first doped layer 2 are greater than 1E19 / cm². 3 .

[0087] In this embodiment, the doping concentrations of both the second doped layer 3 and the first doped layer 2 are controlled to be greater than 1E19 / cm. 3 This ensures lower contact resistance between the first doped layer 2 and the first transparent conductive film 16, and between the second doped layer 3 and the second metal electrode 6, which is more conducive to improving battery efficiency.

[0088] In this embodiment of the invention, a first transparent conductive film 16 is disposed between the first metal electrode 5 and the first doped layer 2, and the first metal electrode 5 is electrically connected to the first doped layer 2 through the first transparent conductive film 16. Since the first doped layer 2 is at least one of amorphous silicon, microcrystalline silicon, or nanocrystalline silicon, and these layers have poor lateral conductivity, the first metal electrode 5 is electrically connected to the first doped layer 2 through the first transparent conductive film 16. This creates a good ohmic contact between the first transparent conductive film 16 and the first doped layer 2, which improves the lateral transport efficiency of charge carriers. Furthermore, the first transparent conductive film 16 can serve as an anti-reflection layer, effectively reducing the reflection loss of incident light on the back of the battery and increasing sunlight utilization. Specifically, the first transparent conductive film 16 is a TCO (Transparent Conductive Oxide) thin film. The material of the first transparent conductive film 16 can be at least one of indium tin oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, and tungsten-doped indium oxide.

[0089] As an embodiment of the present invention, the back contact battery 100 further includes: The second transparent conductive film 17 is disposed on the surface of the second doped layer 3 away from the silicon substrate 1. The second metal electrode 6 is in contact with the second transparent conductive film 17. The second metal electrode 6 forms an electrical connection with the second doped layer 3 through the second transparent conductive film 17. The first transparent conductive film 16 and the second transparent conductive film 17 are spaced apart.

[0090] In this embodiment, the back contact battery 100 is simultaneously provided with a first transparent conductive film 16 and a second transparent conductive film 17. An insulating opening 18 is provided between the first transparent conductive film 16 and the second transparent conductive film 17 to insulate and isolate the first transparent conductive film 16 and the second transparent conductive film 17, preventing short circuits and leakage between them. The second transparent conductive film 17 is a TCO (Transparent Conductive Oxide) film. The material of the second transparent conductive film 17 can be at least one of indium tin oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, and tungsten-doped indium oxide.

[0091] When the second doped layer 3 is at least one of amorphous silicon, microcrystalline silicon, or nanocrystalline silicon, the second metal electrode 6 is electrically connected to the second doped layer 3 through the second transparent conductive film 17, which improves the lateral transport efficiency of charge carriers, as these layers have poor lateral conductivity. Furthermore, the second transparent conductive film 17 can serve as an anti-reflection layer, effectively reducing the reflection loss of incident light on the back of the battery and increasing sunlight utilization. Alternatively, when the second doped layer 3 is a polycrystalline silicon doped layer, the second transparent conductive film 17 can be disposed on the second doped layer 3 for ease of processing. The second transparent conductive film 17 and the first transparent conductive film 16 can be fabricated in one step, and an insulating opening 18 can be provided between them, facilitating the processing of the back contact battery 100.

[0092] As an embodiment of the present invention, the first transparent conductive film 16 and the second transparent conductive film 17 extend simultaneously onto the protrusion 13, and the insulating opening 18 is located on the protrusion 13, which facilitates the processing of the insulating opening 18.

[0093] In another embodiment of the present invention, the second doped layer 3 is a doped polycrystalline silicon layer, and the second metal electrode 6 is in direct contact with the second doped layer 3 to form an electrical connection.

[0094] In this embodiment, when the second doped layer 3 is a doped polysilicon layer, the second metal electrode 6 can directly contact the second doped layer 3 to form an electrical connection. That is, when the second doped layer 3 is a doped polysilicon layer, it is not necessary to provide a second transparent conductive film 17, yet good ohmic contact between the second metal electrode 6 and the second doped layer 3 can still be maintained. Furthermore, the material usage of the transparent conductive film can be reduced, which helps to lower costs. In some embodiments, when the second doped layer 3 is a doped polysilicon layer, the second transparent conductive film 17 can also be replaced by a passivation layer, with the second metal electrode 6 passing through the passivation layer to contact the second doped layer 3 and form an electrical connection. Exemplarily, the passivation layer can be a silicon nitride layer or a silicon oxynitride layer.

[0095] Refer again Figures 1-3 As one embodiment of the present invention, it further includes: The first dielectric layer 8 is disposed in the first region 111, located between the silicon substrate 1 and the first doped layer 2; and The second dielectric layer 9 is located in the second region 112 between the silicon substrate 1 and the second doped layer 3.

[0096] In this embodiment, the first dielectric layer 8 is disposed between the first doped layer 2 and the silicon substrate 1, and the second dielectric layer 9 is disposed between the second doped layer 3 and the silicon substrate 1. The first dielectric layer 8 and the second dielectric layer 9 passivate the surface of the silicon substrate 1 and allow carriers to pass through efficiently. The materials of the first dielectric layer 8 and the second dielectric layer 9 can be the same or different.

[0097] As an embodiment of the present invention, the first dielectric layer 8 is an intrinsic amorphous silicon layer.

[0098] In this embodiment, since the first doped layer 2 is at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon, and the first dielectric layer 8 is set as an intrinsic amorphous silicon layer, the first dielectric layer 8 can passivate the dangling bonds on the surface of the silicon substrate 1, reducing recombination losses. Simultaneously, the first dielectric layer 8 acts as a tunneling barrier layer, enabling selective transport of charge carriers. In some embodiments, the first dielectric layer 8 may also be a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0099] In one embodiment of the present invention, the second dielectric layer 9 is a tunneling layer and the second doped layer 3 is a doped polycrystalline silicon layer; or, the second dielectric layer 9 is an intrinsic amorphous silicon layer and the second doped layer 3 is at least one of a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer.

[0100] In this embodiment, when the second dielectric layer 9 is a tunneling layer, the second doped layer 3 is a doped polycrystalline silicon layer. The second dielectric layer 9 achieves good interfacial chemical passivation and utilizes the quantum tunneling effect to allow majority carriers to pass through, thereby achieving efficient selective carrier transport. When the second dielectric layer 9 is an intrinsic amorphous silicon layer, the second doped layer 3 is at least one of a doped amorphous silicon layer, a doped microcrystalline silicon layer, or a doped nanocrystalline silicon layer. The second dielectric layer 9 can passivate the dangling bonds on the surface of the silicon substrate 1, reducing recombination losses. At the same time, the second dielectric layer 9 acts as a tunneling barrier layer, achieving selective carrier transport.

[0101] As an embodiment of the present invention, the tunneling layer is one or a combination of at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, and silicon carbide layer.

[0102] In this embodiment, when the second dielectric layer 9 is a tunneling layer, the tunneling layer can be a stacked structure of one or more of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, and silicon carbide layer. This can achieve a good passivation effect of the tunneling layer and achieve efficient selective carrier transport.

[0103] Please refer to the reference. Figures 5-8 As an embodiment of the present invention, the isolation layer 4 has a trench 40, which partially or completely penetrates the isolation layer 4 along the thickness direction Z of the silicon substrate 1.

[0104] In this embodiment, the isolation layer 4 has trenches 40. This can be understood as all isolation layers 4 of the back contact battery 100 having trenches 40, or only a portion of the isolation layers 4 of the back contact battery 100 having trenches 40. In this embodiment, the isolation layer 4 is disposed on the protrusion 13, and the trenches 40 are located on the protrusion 13. The depth direction of the trenches 40 is the same as the thickness direction Z of the silicon substrate 1, which facilitates the processing of the trenches 40. Preferably, the trenches 40 are located on the top surface 130 of the protrusion 13, which further facilitates the processing of the trenches 40.

[0105] In this embodiment, the trench 40 can completely penetrate the isolation layer 4 along the thickness direction Z of the silicon substrate 1, or it can partially penetrate the isolation layer 4. By creating the trench 40 in the isolation layer 4, the conductivity of the isolation layer 4 can be reduced, thereby improving the electrical isolation effect of the isolation layer 4 on the second doped layer 3 and the first doped layer 2.

[0106] Please refer to Figure 5 and Figure 7As an embodiment of the present invention, the trench 40 completely penetrates the isolation layer 4 along the thickness direction Z of the silicon substrate 1. Taking the center plane P on the thickness direction Z of the silicon substrate 1 as the reference plane, the distance H3 from the bottom surface of the trench 40 to the center plane P is greater than the distance H1 from the plane where the first region 111 is located to the center plane P and the distance H2 from the plane where the second region 112 is located to the center plane P.

[0107] In this embodiment, the trench 40 completely penetrates the isolation layer 4 along the thickness direction Z of the silicon substrate 1. That is, the depth H5 of the trench 40 is greater than the thickness D6 of the isolation layer 4. The trench 40 extends into the protrusion 13 along the thickness direction Z of the silicon substrate 1. The position of the trench 40 exposes the silicon substrate 1, so that the isolation layer 4 is at least partially blocked, which can further improve the electrical isolation effect of the isolation layer 4 on the second doped layer 3 and the first doped layer 2.

[0108] Wherein, the central plane P in the thickness direction Z of the silicon substrate 1 is parallel to the plane containing the front surface 12 and the first region 111, and the central plane P in the thickness direction Z of the silicon substrate 1 is located between the plane containing the front surface 12 and the first region 111, and the central plane P in the thickness direction Z of the silicon substrate 1 can be located at the center position or a non-center position between the plane containing the front surface 12 and the first region 111; or, the central plane P in the thickness direction Z of the silicon substrate 1 is parallel to the plane containing the front surface 12 and the second region 112, and the central plane P in the thickness direction Z of the silicon substrate 1 is located between the plane containing the front surface 12 and the second region 112, and the central plane P in the thickness direction Z of the silicon substrate 1 can be located at the center position or a non-center position between the plane containing the front surface 12 and the second region 112.

[0109] Wherein, the distance H3 from the bottom surface of trench 40 to the central plane P is the average distance from the bottom surface of trench 40 along the thickness direction Z of silicon substrate 1 to the central plane P. For example, 5 to 10 measurement points are selected on the bottom surface of trench 40, and the arithmetic mean of the distances from these measurement points along the thickness direction Z of silicon substrate 1 to the central plane P is calculated as the distance H3 from the bottom surface of trench 40 to the central plane P. Similarly, the distance H1 from the plane containing the first region 111 to the central plane P is the average distance from the plane containing the first region 111 along the thickness direction Z of silicon substrate 1 to the central plane P. For example, 5 to 10 measurement points are selected on the plane containing the first region 111, and the arithmetic mean of the distances from these measurement points along the thickness direction Z of silicon substrate 1 to the central plane P is calculated as the distance H1 from the plane containing the first region 111 to the central plane P. The distance H2 from the plane containing the second region 112 to the central plane P is the average distance from the plane containing the second region 112 to the central plane P along the thickness direction Z of the silicon substrate 1. For example, 5 to 10 measurement points are selected on the plane containing the second region 112, and the arithmetic mean of the distances from these measurement points to the central plane P along the thickness direction Z of the silicon substrate 1 is calculated as the distance H2 from the plane containing the second region 112 to the central plane P.

[0110] In this embodiment, the distance H3 from the bottom surface of the trench 40 to the center plane P in the thickness direction Z of the silicon substrate 1 is controlled to be greater than the distance H1 from the plane where the first region 111 is located to the center plane P and the distance H2 from the plane where the second region 112 is located to the center plane P. This avoids the trench 40 from being too deep and exceeding the plane where the first region 111 is located and the plane where the second region 112 is located, thereby reducing the risk of the cell bending or cracking due to the trench 40 being too deep, and also avoiding large recombination losses caused by the trench 40 being too deep.

[0111] Please refer to the reference. Figure 6 As an embodiment of the present invention, at least a portion of the trench 40 penetrates the isolation layer 4 along the second direction Y.

[0112] In this embodiment, at least a portion of the trenches 40 penetrate the isolation layer 4 along the second direction Y, such that the isolation layer 4 is divided into two completely isolated parts by the trenches 40. The two isolated parts are not connected to each other, thereby achieving good insulation between the two parts. This further reduces the conductivity of the isolation layer 4 and greatly improves the electrical isolation effect of the isolation layer 4 on the second doped layer 3 and the first doped layer 2. Preferably, each trench 40 penetrates the corresponding isolation layer 4 along the second direction Y.

[0113] In some embodiments, at least some of the trenches 40 do not completely penetrate the isolation layer 4 along the second direction Y, that is, at least a portion of the trenches 40 have dimensions along the second direction Y that are smaller than the dimensions of the isolation layer 4 along the second direction Y.

[0114] For example, the ratio of the dimension of the trench 40 along the first direction X to the dimension of the separator 4 along the first direction X can be 10% to 70%, and the ratio of the dimension of the trench 40 along the second direction Y to the dimension of the separator 4 along the second direction Y can be 0.05% to 5%. In this case, during the metal electrode printing process, the trench 40 can be used as a mark point, and the position of the trench 40 can be identified by a vision system to adjust the position of the battery or screen, ensuring battery alignment accuracy and improving the printing accuracy of the metal electrode. In some embodiments, some of the trenches 40 penetrate the separator 4 along the second direction Y, while some of the trenches 40 do not completely penetrate the separator 4 along the second direction Y. This can better improve the isolation effect of a portion of the separator 4, and the trenches 40 on a portion of the separator 4 can be used as mark points to facilitate battery positioning and improve the printing accuracy of the metal electrode.

[0115] Please refer to the reference. Figure 7 As an embodiment of the present invention, the insulating opening 18 is located at the position of the groove 40. The insulating opening 18 can be formed at the same time as the groove 40 is opened. The laser can simultaneously form the groove 40 and the insulating opening 18, which can simplify the process and reduce production costs.

[0116] As an embodiment of the present invention, the width W4 of the groove 40 along the first direction X is 10~200 micrometers.

[0117] In this embodiment, the width W4 of the trench 40 along the first direction X is controlled to be 10~200 micrometers. This ensures the good isolation effect of the isolation layer 4 while avoiding excessive composite loss due to an excessively large width W4 of the trench 40 along the first direction X. For example, the width W4 of the trench 40 along the first direction X can be any value among 10 micrometers, 15 micrometers, 20 micrometers, 25 micrometers, 32 micrometers, 35 micrometers, 40 micrometers, 45 micrometers, 50 micrometers, 60 micrometers, 70 micrometers, 80 micrometers, 90 micrometers, 95 micrometers, 100 micrometers, 120 micrometers, 125 micrometers, 130 micrometers, 140 micrometers, 150 micrometers, 160 micrometers, 170 micrometers, 180 micrometers, 190 micrometers, and 200 micrometers.

[0118] Please refer to the reference. Figure 8 In another embodiment of the present invention, the trench 40 extends through the isolation layer 4 along the thickness direction Z of the silicon substrate 1, and the ratio of the depth H5 of the trench 40 to the thickness D6 of the isolation layer 4 is 0.5 to 0.9.

[0119] In this embodiment, the trench 40 partially penetrates the isolation layer 4 along the thickness direction Z of the silicon substrate 1. This can be understood as at least a portion of the trenches 40 penetrating the isolation layer 4 along the thickness direction Z of the silicon substrate 1. The depth H5 of the trench 40 is less than the thickness D6 of the isolation layer 4, and the isolation layer 4 is thinned at the trench 40 location. Due to the presence of the trench 40, the conductivity of the isolation layer 4 can be reduced, thereby improving the electrical isolation effect of the isolation layer 4 on the second doped layer 3 and the first doped layer 2. Moreover, since the trench 40 penetrates at least a portion of the thickness of the isolation layer 4, in this case, the trench 40 does not completely penetrate the isolation layer 4 along the thickness direction Z of the silicon substrate 1. By controlling the ratio of the trench depth H5 to the thickness D6 of the isolation layer 4 to be 0.5~0.9, damage to the interior of the silicon substrate 1 during laser trenching 40 can be avoided, thus preventing the formation of recombination centers and minimizing recombination losses in the solar cell. Therefore, this embodiment can improve the electrical isolation effect of the isolation layer 4 on the second doped layer 3 and the first doped layer 2, and avoid the trench 40 being too deep. This prevents the isolation layer 4 from being damaged by excessive recombination when the trench 40 is opened by laser, thus ensuring low battery recombination loss and ensuring battery efficiency.

[0120] Please refer to Figures 5-7 As an embodiment of the present invention, the first region 111 is provided with a first velvet structure 1111.

[0121] In this embodiment, the first doped layer 2 is at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon. A first textured structure 1111 is provided in the first region 111, so that each film layer in the first region 111 also forms a textured surface with the same morphology as the first textured structure 1111. This can reduce the reflection of sunlight incident on the back side 11, improve the absorption of sunlight incident on the back side 11 by the first region 111, and improve the power generation efficiency of the back side of the battery. Moreover, it is beneficial to improve the bonding force between the film layers in the first region 111 and improve the structural stability of the battery.

[0122] In one embodiment of the present invention, the second doped layer 3 is a doped polysilicon layer, and the second region 112 is set as a polished surface.

[0123] In this embodiment, when the second doped layer 3 is a doped polycrystalline silicon layer, the second region 112 is set as a polished surface, which is conducive to the more uniform and dense growth of the second dielectric layer 9 in the second region 112, with fewer defects, which can reduce the recombination loss in the second region 112 and improve the battery efficiency.

[0124] Please refer to Figure 9 As an embodiment of the present invention, the second doped layer 3 is at least one of amorphous silicon layer, microcrystalline silicon layer, and nanocrystalline silicon layer, and the second region 112 is provided with a second textured structure 1121.

[0125] In this embodiment, when the second doped layer 3 is at least one of amorphous silicon, microcrystalline silicon, or nanocrystalline silicon, a second textured structure 1121 is formed in the second region 112, so that each film layer in the second region 112 also forms a textured surface with the same morphology as the second region 112. This can reduce the reflection of sunlight incident on the back side 11, improve the absorption of sunlight incident on the back side 11 by the second region 112, and improve the power generation efficiency of the back side of the battery. Moreover, it is beneficial to improve the bonding force between the film layers in the second region 112 and improve the structural stability of the battery. The second textured structure 1121 may include at least one of upright pyramid, inverted pyramid, nanopillar, or nanopore, and the first textured structure 1111 and the second textured structure 1121 may be the same or different.

[0126] Please refer to the reference. Figure 7 As an embodiment of the present invention, the trench 40 completely penetrates the isolation layer 4 along the thickness direction Z of the silicon substrate 1, and the protrusion 13 is provided with a third textured structure 1311 on the surface of the trench 40.

[0127] In this embodiment, the groove 40 is located at the position of the protrusion 13. The protrusion 13 has a third textured surface structure 1311 on the surface corresponding to the groove 40. Due to the presence of the third textured surface structure 1311, the absorption of incident sunlight on the back side 11 can be increased, which is beneficial to improving the utilization rate of sunlight and thus improving the battery efficiency. The third textured surface structure 1311 can be provided on both the bottom surface and the inner wall surface of the groove 40.

[0128] As an embodiment of the present invention, the third textured structure 1311 includes at least one of a regular pyramid, an inverted pyramid, a nanopillar, and a nanopore.

[0129] In this embodiment, the specific structure of the third textured structure 1311 is not limited. The third textured structure 1311 can be one of a regular pyramid, an inverted pyramid, a nanopillar, or a nanopore. The third textured structure 1311 can also be a combination of at least two of the following: a regular pyramid, an inverted pyramid, a nanopillar, and a nanopore. Setting the third textured structure 1311 to include at least one of the following can achieve a good light-trapping effect, which is beneficial to improving the absorption of incident sunlight on the back side 11 and improving the power generation efficiency of the back side 11 of the battery.

[0130] For example, when the third textured structure 1311 is a right-side-up pyramid, the height of the third textured structure 1311 can be greater than or equal to 0.1 μm and less than or equal to 4 μm. For instance, the height of the third textured structure 1311 can be 0.1 μm, 0.5 μm, 0.9 μm, 1 μm, 1.2 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.8 μm, 2 μm, 2.2 μm, 2.5 μm, 3 μm, 3.5 μm, or 4 μm, etc. In this case, the height of the third textured structure 1311 is within the above range, which helps to prevent the specific surface area of ​​the textured morphology region from being too small due to the height of the third textured structure 1311 being too small, further enabling the third textured structure 1311 to have a higher light-trapping effect.

[0131] Please refer to the reference. Figure 10 As an embodiment of the present invention, the trench 40 is filled with polymer insulating material 7.

[0132] In this embodiment, the polymer insulating material 7 can be one or a combination of at least two of the following: parylene, fluorinated polymer, epoxy resin, acrylate, polyimide, and phenolic resin. Using these materials in the polymer insulating material 7 ensures good insulation performance, which is beneficial for improving the insulation effect at the trench 40 location. It also ensures good stress relief at the trench 40 location, reducing the risk of microcracks or warping in the back contact battery 100. Of course, the specific material of the polymer insulating material 7 is not limited to these; it can also be other polymer insulating materials.

[0133] Please refer to this again. Figure 1 and Figure 3 As an embodiment of the present invention, the height H0 of the protrusion 13 is 2 to 15 micrometers.

[0134] In this embodiment, the height H0 of the protrusion 13 is the greater of the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing the first region 111, and the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing the second region 112. Specifically, if the plane containing the first region 111 and the plane containing the second region 112 are coplanar, that is, the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing the first region 111 and the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing the second region 112 are the same, then the height H0 of the protrusion 13 is the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing either the first region 111 or the second region 112; if the plane containing the first region 111 and the plane containing the second region 112 are not coplanar, the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing either the first region 111 or the second region 112 is the same. If the distance to the plane containing the first region 111 is greater than the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing the second region 112, then the height H0 of the protrusion 13 is the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing the first region 111; conversely, if the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing the second region 112 is greater than the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing the first region 111, then the height H0 of the protrusion 13 is the distance from the top surface 130 of the protrusion 13 along the thickness direction Z of the silicon substrate 1 to the plane containing the second region 112.

[0135] In this embodiment, the height of the protrusion 13 is controlled to be 2~15 micrometers, which can achieve good electrical isolation between the second doped layer 3 and the first doped layer 2, and facilitate the processing of the protrusion 13. At the same time, it avoids the protrusion 13 being too high and excessively affecting the thickness of the first region 111 and the second region 112, ensuring good structural strength of the battery and reducing the risk of battery cell cracking or bending.

[0136] For example, the height H0 of protrusion 13 can be any value among 2 micrometers, 2.2 micrometers, 2.5 micrometers, 2.8 micrometers, 3 micrometers, 3.5 micrometers, 4 micrometers, 4.5 micrometers, 5 micrometers, 5.6 micrometers, 6 micrometers, 6.5 micrometers, 7 micrometers, 7.5 micrometers, 8 micrometers, 8.6 micrometers, 9 micrometers, 9.5 micrometers, 10 micrometers, 10.5 micrometers, 11 micrometers, 11.5 micrometers, 12 micrometers, 12.5 micrometers, 13 micrometers, 13.5 micrometers, 14 micrometers, 14.5 micrometers, and 15 micrometers.

[0137] Please refer to the reference. Figure 3 and Figure 7 As an embodiment of the present invention, the width W0 of the protrusion 13 along the first direction X is 20 to 350 micrometers.

[0138] In this embodiment, the width W0 of the protrusion 13 along the first direction X is the width of a single protrusion 13 along the first direction X. Controlling the width W0 of the protrusion 13 along the first direction X to 20-350 micrometers allows for lower precision requirements in laser etching within this width range, making it easier to achieve through modifications to existing process equipment. Simultaneously, the protrusion 13 achieves good insulation. If the width of the protrusion 13 is too small, it will be difficult to form the trench 40; if the width of the protrusion 13 is too large, it will result in excessive sacrifice of laser production capacity, and the area ratio of the first region 111 and the second region 112 will decrease, reducing the separation capability of photogenerated carriers. Therefore, setting the width of the protrusion 13 along the first direction X to 20-350 micrometers is beneficial for the processing of the protrusion 13 while maintaining good battery efficiency.

[0139] For example, the width W0 of the protrusion 13 along the first direction X can be any value among 20 micrometers, 22 micrometers, 25 micrometers, 30 micrometers, 32 micrometers, 35 micrometers, 40 micrometers, 45 micrometers, 50 micrometers, 60 micrometers, 70 micrometers, 80 micrometers, 90 micrometers, 100 micrometers, 110 micrometers, 120 micrometers, 130 micrometers, 140 micrometers, 160 micrometers, 185 micrometers, 190 micrometers, 200 micrometers, 210 micrometers, 230 micrometers, 240 micrometers, 250 micrometers, 270 micrometers, 280 micrometers, 300 micrometers, 320 micrometers, 340 micrometers, and 350 micrometers.

[0140] Please refer to this again. Figure 7 As an embodiment of the present invention, the difference between the width W0 of the protrusion 13 along the first direction X and the width W4 of the groove 40 along the first direction X is greater than 20 micrometers.

[0141] In this embodiment, the width W0 of the protrusion 13 along the first direction X is the width of a single protrusion 13 along the first direction X, and the width W4 of the groove 40 along the first direction X is the width of a single groove 40 along the first direction X. The width W0 of the protrusion 13 along the first direction X is greater than the width W4 of the groove 40 along the first direction X, and the difference between the two is greater than 20 micrometers. This avoids the difference between the width of the protrusion 13 and the width of the groove 40 being too small, which facilitates the processing and formation of the groove 40 and ensures a good isolation effect of the protrusion 13.

[0142] As one embodiment of the present invention, it also includes: A third dielectric layer 10 is disposed between the surface of the isolation layer 4 and the protrusion 13, and a trench 40 penetrates the third dielectric layer 10 along the thickness direction Z of the silicon substrate 1.

[0143] In this embodiment, a third dielectric layer 10 is disposed between the isolation layer 4 and the surface of the protrusion 13. The third dielectric layer 10 can passivate the surface of the protrusion 13, which can further improve the battery efficiency. The third dielectric layer 10 can be one or a combination of at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, silicon carbide layer, and intrinsic amorphous silicon layer.

[0144] As an embodiment of the present invention, the isolation layer 4 is doped with at least one of oxygen, nitrogen and carbon elements; The oxygen concentration in isolation layer 4 is 1×10⁻⁶. 16 ~2×10 22 atoms / cm 3 And / or, the nitrogen concentration in isolation layer 4 is 1×10 16 ~2×10 22 atoms / cm 3 And / or, the carbon concentration in isolation layer 4 is 1×10 16 ~2×10 22 atoms / cm 3 .

[0145] In this embodiment, at least one of oxygen, nitrogen, and carbon is doped into the isolation layer 4. Specifically, one of oxygen, nitrogen, and carbon can be doped into the isolation layer 4, or at least two of oxygen, nitrogen, and carbon can be doped simultaneously. Moreover, when oxygen is doped into the isolation layer 4, the concentration of oxygen in the isolation layer 4 is controlled to be 1 × 10⁻⁶. 16 ~2×10 22 atoms / cm 3 When nitrogen is doped into the isolation layer 4, the concentration of nitrogen in the isolation layer 4 is controlled to be 1×10⁻⁶. 16 ~2×10 22 atoms / cm 3 When carbon is doped into the isolation layer 4, the concentration of carbon in the isolation layer 4 is controlled to be 1×10⁻⁶. 16 ~2×10 22 atoms / cm 3 This can increase the resistivity of the isolation layer 4, thereby further enhancing the electrical isolation effect of the isolation layer 4.

[0146] Please refer to the reference. Figure 1 , Figure 3 and Figure 7 As an embodiment of the present invention, the isolation layer 4 further includes: A first extension 41 extends to the first region 111, the first extension 41 covers a portion of the first region 111, and the first extension 41 is connected to the first doped layer 2 along the first direction X. The second extension 42 extends to the second region 112, and the second extension 42 covers a portion of the second region 112. The second extension 42 is connected to the second doped layer 3 along the first direction X.

[0147] In this embodiment, the isolation layer 4 is partially disposed on the surface of the protrusion 13, and the isolation layer 4 forms a first extension 41 and a second extension 42. The first extension 41 extends to the first region 111, and the second extension 42 extends to the second region 112. This can further increase the unfolded length of the isolation layer 4, increase the distance between the first doped layer 2 and the second doped layer 3 along the surface of the silicon substrate 1, thereby increasing the creepage distance between the first doped layer 2 and the second doped layer 3, and further improving the electrical isolation effect between the first doped layer 2 and the second doped layer 3.

[0148] Please refer to the reference. Figure 11 As another embodiment of the present invention, along the thickness direction Z of the silicon substrate 1, the protrusion 13 includes a first end far from the front surface 12 and a second end close to the front surface 12, wherein the width W1 of the first end along the first direction X is greater than the width W2 of the second end along the first direction X.

[0149] In this embodiment, while the protrusion 13 provides electrical isolation between the first doped layer 2 and the second doped layer 3, the width W1 of the first end of the protrusion 13 along the first direction X is greater than the width W2 of the second end of the protrusion 13 along the first direction X, making the second end of the protrusion 13 have a "brim structure". This facilitates the light-trapping effect of the protrusion 13. Sunlight incident from the front side 12 is emitted from the back side 11 onto the side of the protrusion 13, and the sunlight emitted from the back side 11 can be better reflected back into the silicon substrate 1 by the side of the protrusion 13, thereby increasing the secondary absorption of sunlight and improving the utilization rate of sunlight. Moreover, the width W1 of the first end of the protrusion 13 along the first direction X is greater than the width W2 of the second end of the protrusion 13 along the first direction X, making the side of the isolation layer 4 inclined. This facilitates increasing the length of the isolation layer 4 on the protrusion 13, which can further improve the electrical isolation effect of the isolation layer 4. Preferably, along the thickness direction Z of the silicon substrate 1, the width of the protrusion 13 along the first direction X gradually increases from the second end to the first end.

[0150] As an embodiment of the present invention, at least one of the top surface 130, the first side surface 131, and the second side surface 132 is provided with a textured structure (not shown).

[0151] In this embodiment, the texture structure can be a plurality of strip-shaped convex structures or a porous structure. At least one of the top surface 130, the first side surface 131, and the second side surface 132 is provided with a texture structure. The texture structure can further enhance the light-trapping effect of the protrusion 13 and further improve the absorption rate of sunlight on the back surface 11, thereby improving battery efficiency.

[0152] In this embodiment of the invention, the first metal electrode 5 and the second metal electrode 6 have opposite polarities, and the first metal electrode 5 and the second metal electrode 6 are alternately spaced along a first direction X. Both the first metal electrode 5 and the second metal electrode 6 can be silver electrodes or aluminum electrodes.

[0153] Please refer to the reference. Figure 5 As an embodiment of the present invention, the height D1 of the first metal electrode 5 and the height D2 of the second metal electrode 6 are both greater than the height H0 of the protrusion 13.

[0154] In this embodiment, the height D1 of the first metal electrode 5 is the vertical distance from the side of the first metal electrode 5 facing away from the silicon substrate 1 to the side of the first metal electrode 5 close to the silicon substrate 1; the height D2 of the second metal electrode 6 is the vertical distance from the side of the second metal electrode 6 facing away from the silicon substrate 1 to the side of the second metal electrode 6 close to the silicon substrate 1. The height H0 of the protrusion 13 has been described above and will not be repeated here. Controlling the heights D1 of the first metal electrode 5 and D2 of the second metal electrode 6 to be greater than the height H0 of the protrusion 13 facilitates the first metal electrode 5 and the second metal electrode 6 to protrude from the protrusion 13 on the back surface 11, which is convenient for welding the first metal electrode 5 and the second metal electrode 6 to the solder ribbon.

[0155] This invention also provides a battery assembly, which includes the back contact battery 100 described in the above embodiments. It should be noted that this battery assembly has the same or similar beneficial effects as the back contact battery 100, and the related aspects between the two can be referred to each other; to avoid repetition, they will not be repeated here.

[0156] In this embodiment, multiple back-contact batteries 100 in the battery assembly are connected in series by solder strips to form a battery string, thereby achieving series current collection and output.

[0157] It is understood that in such embodiments, the battery assembly may also include a metal frame, a backsheet, photovoltaic glass, and an encapsulating film. The encapsulating film may be filled between the front and back sides of the back contact battery 100, the photovoltaic glass, adjacent battery cells, etc. As a filler, it may be a transparent colloid with good light transmittance and aging resistance. For example, the encapsulating film may be an EVA film or a POE film, and the specific choice can be made according to the actual situation, without limitation.

[0158] Photovoltaic glass can be applied to the encapsulating film on the front side of the back contact cell 100. The photovoltaic glass can be ultra-clear glass, which has high light transmittance, high transparency, and superior physical, mechanical, and optical properties. For example, ultra-clear glass can achieve a light transmittance of over 92%. It can protect the back contact cell 100 while minimizing impact on its efficiency. Simultaneously, the encapsulating film bonds the photovoltaic glass and the back contact cell 100 together, providing sealing, insulation, and waterproofing / moisture protection for the back contact cell 100.

[0159] The backsheet can be attached to the adhesive film on the back side of the back contact cell 100. The backsheet provides protection and support for the back contact cell 100, and offers reliable insulation, water resistance, and aging resistance. Multiple options are available for the backsheet, typically tempered glass, acrylic glass, or aluminum alloy TPT composite adhesive film, etc., and the specific choice is determined based on the specific circumstances and is not limited here. The backsheet, back contact cell 100, adhesive film, and photovoltaic glass can be mounted on a metal frame. The metal frame serves as the main external support structure for the entire battery module, providing stable support and installation. For example, the battery module can be installed at the desired location using the metal frame.

[0160] This invention also provides a photovoltaic system, which includes the battery module described in the above embodiments. It should be noted that this photovoltaic system has the same or similar beneficial effects as the back-contact battery 100 described above, and the related aspects between the two can be referred to each other; to avoid repetition, they will not be repeated here.

[0161] In this embodiment, the photovoltaic system can be applied in photovoltaic power plants, such as ground-mounted power plants, rooftop power plants, and floating power plants. It can also be applied to equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it is understood that the application scenarios of the photovoltaic system are not limited to these; that is, the photovoltaic system can be applied in all fields that require solar energy to generate electricity. Taking a photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a combiner box, and an inverter. The photovoltaic array may be an array combination of multiple battery modules; for example, multiple battery modules can form multiple photovoltaic arrays. The photovoltaic array is connected to the combiner box, which can collect the current generated by the photovoltaic array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to achieve solar power supply.

[0162] In the description of this specification, references to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0163] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A back-contact battery, characterized in that, include: A silicon substrate, the silicon substrate including a back side and a front side disposed opposite to each other, the back side having a first region and a second region disposed alternately at intervals along a first direction, the first region and the second region respectively extending along a second direction, the second direction intersecting the first direction; The silicon substrate has at least one protrusion formed between adjacent first and second regions; A first doped layer is disposed in the first region, wherein the first doped layer is at least one of amorphous silicon doped layer, microcrystalline silicon doped layer, and nanocrystalline silicon doped layer. A second doped layer is disposed in the second region, wherein the second doped layer is at least one of a doped polycrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer; An isolation layer is disposed on the back side and between the first doped layer and the second doped layer. The doping concentration of the isolation layer is less than that of the first doped layer and the second doped layer, and the doping concentration of the isolation layer is less than or equal to 1E18 / cm. 3 ; A first transparent conductive film is disposed on the surface of the first doped layer opposite to the silicon substrate; A first metal electrode in contact with the first transparent conductive film, wherein the first metal electrode forms an electrical connection with the first doped layer through the first transparent conductive film; and A second metal electrode electrically connected to the second doped layer.

2. The back contact battery according to claim 1, characterized in that, include: A second transparent conductive film is disposed on the surface of the second doped layer away from the silicon substrate. The second metal electrode is in contact with the second transparent conductive film. The second metal electrode forms an electrical connection with the second doped layer through the second transparent conductive film. The first transparent conductive film and the second transparent conductive film are spaced apart.

3. The back contact battery according to claim 1, characterized in that, The second doped layer is a doped polycrystalline silicon layer, and the second metal electrode is in direct contact with the second doped layer to form an electrical connection.

4. The back contact battery according to claim 1, characterized in that, Also includes: A first dielectric layer is disposed in the first region, located between the silicon substrate and the first doped layer; and The second dielectric layer is disposed in the second region and is located between the silicon substrate and the second doped layer.

5. The back contact battery according to claim 4, characterized in that, The first dielectric layer is an intrinsic amorphous silicon layer.

6. The back contact battery according to claim 4 or 5, characterized in that, The second dielectric layer is a tunneling layer, and the second doped layer is a doped polycrystalline silicon layer; or, the second dielectric layer is an intrinsic amorphous silicon layer, and the second doped layer is at least one of a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer.

7. The back contact battery according to claim 6, characterized in that, The tunneling layer is one or a combination of at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, and silicon carbide layer.

8. The back contact battery according to claim 1, characterized in that, The first region is provided with a first velvet structure.

9. The back contact battery according to claim 1 or 8, characterized in that, The second doped layer is a doped polysilicon layer, and the second region is set as a polished surface.

10. The back contact battery according to claim 1 or 8, characterized in that, The second doped layer is at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon, and the second region is provided with a second textured surface structure.

11. The back contact battery according to claim 1, characterized in that, The isolation layer is at least partially disposed on the protrusion.

12. The back contact battery according to claim 11, characterized in that, The isolation layer has trenches that partially or completely penetrate the isolation layer along the thickness direction of the silicon substrate.

13. The back contact battery according to claim 12, characterized in that, The trench extends through the isolation layer along the thickness direction of the silicon substrate, and the ratio of the depth of the trench to the thickness of the isolation layer is 0.5 to 0.

9.

14. The back contact battery according to claim 12, characterized in that, The trench completely penetrates the isolation layer along the thickness direction of the silicon substrate. With the center plane along the thickness direction of the silicon substrate as the reference plane, the distance from the bottom surface of the trench to the center plane is greater than the distance from the plane containing the first region to the center plane and the distance from the plane containing the second region to the center plane.

15. The back contact battery according to any one of claims 12 to 14, characterized in that, At least a portion of the trench penetrates the isolation layer along the second direction.

16. The back contact battery according to claim 12, characterized in that, The trench completely penetrates the isolation layer along the thickness direction of the silicon substrate, and the protrusion has a third textured structure corresponding to the position of the trench.

17. The back contact battery according to claim 16, characterized in that, The third textured structure includes at least one of the following: upright pyramid, inverted pyramid, nanopillar, and nanopore.

18. The back contact battery according to claim 12, characterized in that, The width of the groove along the first direction is 10 to 200 micrometers.

19. The back contact battery according to claim 1, characterized in that, The height of the protrusion is 2 to 15 micrometers.

20. The back contact battery according to claim 1, characterized in that, The width of the protrusion along the first direction is 20 to 350 micrometers.

21. The back contact battery according to claim 12, characterized in that, The difference between the width of the protrusion along the first direction and the width of the groove along the first direction is greater than 20 micrometers.

22. The back contact battery according to claim 12, characterized in that, The trench is filled with a polymer insulating material.

23. The back contact battery according to claim 12, characterized in that, Also includes: A third dielectric layer is disposed between the isolation layer and the raised surface, and the trench penetrates the third dielectric layer.

24. The back contact battery according to claim 1, characterized in that, The isolation layer is doped with at least one of oxygen, nitrogen and carbon elements; The oxygen concentration in the isolation layer is 1×10⁻⁶. 16 ~2×10 22 atoms / cm 3 And / or, the nitrogen concentration in the isolation layer is 1×10⁻⁶. 16 ~2×10 22 atoms / cm 3 And / or, the concentration of carbon in the isolation layer is 1×10⁻⁶. 16 ~2×10 22 atoms / cm 3 .

25. The back contact battery according to claim 1, characterized in that, The number of protrusions between adjacent first and second regions is 1 to 3.

26. The back contact battery according to claim 11, characterized in that, The isolation layer also includes: A first extension extending to the first region, the first extension covering a portion of the first region, the first extension being connected to the first doped layer along the first direction; A second extension extending into the second region, the second extension covering a portion of the second region, the second extension being connected to the second doped layer along the first direction.

27. The back contact battery according to claim 1, characterized in that, Along the thickness direction of the silicon substrate, the protrusion includes a first end portion away from the front surface and a second end portion near the front surface, wherein the width of the first end portion along the first direction is greater than the width of the second end portion along the first direction.

28. The back contact battery according to claim 1, characterized in that, The height of the first metal electrode and the height of the second metal electrode are both greater than the height of the protrusion.

29. The back contact battery according to claim 1, characterized in that, The isolation layer is an intrinsic semiconductor layer or a doped semiconductor layer.

30. The back contact battery according to claim 29, characterized in that, The intrinsic semiconductor layer is at least one of intrinsic polycrystalline silicon layer, intrinsic amorphous silicon layer, intrinsic microcrystalline silicon layer, and intrinsic nanocrystalline silicon layer.

31. The back contact battery according to claim 30, characterized in that, The doped semiconductor layer is at least one of the following: a doped polycrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer.

32. The back contact battery according to claim 1, characterized in that, The doping concentration of the isolation layer is less than 2E17 / cm. 3 .

33. The back contact battery according to claim 1, characterized in that, The doping concentration of the isolation layer is less than 1E17 / cm. 3 .

34. The back contact battery according to claim 1, characterized in that, The doping concentrations of both the second doped layer and the first doped layer are greater than 1E19 / cm. 3 .

35. A battery assembly, characterized in that, Including the back contact battery as described in any one of claims 1 to 34.

36. A photovoltaic system, characterized in that, Includes the battery assembly as described in claim 35.

Images