Photovoltaic cell and preparation method thereof
By using a microcrystalline silicon layer instead of a polycrystalline silicon layer in photovoltaic cells, combined with laser doping and PECVD film fabrication, the energy consumption and efficiency problems caused by high-temperature processing were solved, resulting in higher cell conversion efficiency and conductivity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TRINA SOLAR CO LTD
- Filing Date
- 2024-11-19
- Publication Date
- 2026-05-19
AI Technical Summary
The high-temperature formation process of polycrystalline silicon layers in existing photovoltaic cells leads to problems such as high energy consumption, uneven growth of polycrystalline silicon grains, damage to the tunneling oxide layer, and parasitic absorption, which affect the cell conversion efficiency.
A microcrystalline silicon layer is used to replace the polycrystalline silicon layer. A first tunneling layer, a first microcrystalline silicon layer and a first passivation antireflection layer are sequentially disposed on the back side of the substrate. The front side of the substrate is in contact with the substrate through a second microcrystalline silicon layer. Combined with laser doping process and PECVD film formation, high-temperature processing is avoided.
It reduces long-wavelength parasitic absorption, improves battery conductivity and carrier transport efficiency, reduces energy consumption, maintains substrate purity, and enhances battery conversion efficiency.
Smart Images
Figure CN122069833A_ABST
Abstract
Description
Technical Field
[0001] This invention relates primarily to the field of photovoltaic cell technology, and more particularly to a photovoltaic cell and its preparation method. Background Technology
[0002] A photovoltaic (PV) cell (also known as a solar cell) is a device that converts solar energy into electrical energy using the photoelectric effect. It is made of semiconductor materials. When sunlight shines on the surface of a PV cell, photons strike the semiconductor material, exciting electrons within the semiconductor and causing them to transition from the valence band to the conduction band, creating free electrons and holes. Under the influence of an electric field, the free electrons move along the interior of the semiconductor, forming an electric current. Holes also move within the semiconductor, but in the opposite direction, forming another type of current. When connected to an external circuit, a current is generated in the circuit, resulting in the output of electrical energy.
[0003] Photovoltaic cells generally include PERC cells, TOPCon cells, HJT cells, and IBC cells, etc., and different cells have different structures and manufacturing processes. For example, the manufacturing process of PERC cells mainly includes: texturing, which uses alkaline texturing to form pyramid and light-trapping structures on the surface; phosphorus diffusion to form PN junctions; PSG removal and single-sided polishing to remove edge PN junctions and form a polished surface; back-side passivation film deposition, which forms an oxide layer of about 2nm on the front side, followed by the deposition of an aluminum oxide film of about 10nm using ALD technology; front and back antireflection film deposition, which uses PECVD to deposit silicon nitride films on the front and back sides; back-side laser grooving, which uses lasers to create grooves with specific patterns on the back side; back-side printing of aluminum grid lines, front-side printing of silver grid lines, and high-temperature sintering, etc.
[0004] Photovoltaic cells, such as PERC and TOPcon, typically have a polycrystalline silicon layer. This layer not only performs the basic photoelectric conversion function but also exhibits strong stability and reliability. However, the formation of polycrystalline silicon requires amorphous silicon to undergo high-temperature annealing (>900℃), which negatively impacts cell efficiency. Furthermore, the polycrystalline silicon layer exhibits a significant absorption effect. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to provide a photovoltaic cell and its preparation method, which facilitates carrier transport and thus improves cell conversion efficiency.
[0006] To address the aforementioned technical problems, in a first aspect, the present invention provides a photovoltaic cell, comprising a substrate having a front side and a back side; on the back side of the substrate, a first tunneling layer, a first microcrystalline silicon layer, and a first passivation antireflection layer are sequentially provided along a direction away from the substrate, the first passivation antireflection layer having a first metal gate line; the front side of the substrate includes a first region and a second region, in the first region, the substrate has a second microcrystalline silicon layer, the second microcrystalline silicon layer has a second metal gate line, and in the second region, the substrate has a second passivation antireflection layer.
[0007] Optionally, a third microcrystalline silicon layer and a second tunneling layer are further provided between the first tunneling layer and the first microcrystalline silicon layer, wherein the third microcrystalline silicon layer is close to the first tunneling layer and the second tunneling layer is close to the first microcrystalline silicon layer.
[0008] Optionally, the substrate is a p-type silicon substrate, and the first microcrystalline silicon layer, the second microcrystalline silicon layer, and the third microcrystalline silicon layer are n-type doped microcrystalline silicon layers.
[0009] Optionally, the doping concentration of the first microcrystalline silicon layer and / or the second microcrystalline silicon layer is 1E20 to 1E21 atoms / cm³, and the doping concentration of the third microcrystalline silicon layer is 1E19 to 5E20 atoms / cm³.
[0010] Optionally, the first tunneling layer and / or the second tunneling layer are SiO2 tunneling layers.
[0011] Optionally, the first passivation antireflection layer and / or the second passivation antireflection layer are SiNx layers.
[0012] In a second aspect, the present invention provides a method for fabricating a photovoltaic cell, comprising: providing a substrate having a front side and a back side, the front side including a first region and a second region; sequentially fabricating a first tunneling layer, a first microcrystalline silicon layer and a first passivation antireflection layer on the back side of the substrate, and fabricating a first metal gate line on the first passivation antireflection layer; fabricating a second microcrystalline silicon layer on the substrate in the first region, and fabricating a second passivation antireflection layer on the substrate in the second region; and fabricating a second metal gate line on the second microcrystalline silicon layer.
[0013] Optionally, it further includes: after preparing the first microcrystalline silicon layer, a mask layer is further prepared on the first microcrystalline silicon layer; preparing the first passivation antireflection layer includes: removing the mask layer and then preparing the first passivation antireflection layer.
[0014] Optionally, the preparation of the second microcrystalline silicon layer includes: preparing a microcrystalline silicon layer on the front side of the substrate, removing the microcrystalline silicon layer outside the first region, and the remaining microcrystalline silicon layer being the second microcrystalline silicon layer.
[0015] Optionally, when preparing the second microcrystalline silicon layer, the portion of the second microcrystalline silicon layer in contact with the substrate is prepared using a laser doping process.
[0016] Optionally, it further includes: after preparing the first tunneling layer and before preparing the first microcrystalline silicon layer, sequentially preparing a third microcrystalline silicon layer and a second tunneling layer on the first tunneling layer; preparing the first microcrystalline silicon layer includes: preparing the first microcrystalline silicon layer on the second tunneling layer.
[0017] Optionally, the substrate is a p-type silicon substrate, and the first microcrystalline silicon layer, the second microcrystalline silicon layer, and the third microcrystalline silicon layer are n-type doped microcrystalline silicon layers.
[0018] Optionally, the doping concentration of the first microcrystalline silicon layer and / or the second microcrystalline silicon layer is 1E20 to 1E21 atoms / cm³, and the doping concentration of the third microcrystalline silicon layer is 1E19 to 5E20 atoms / cm³.
[0019] Compared with the prior art, the present invention has the following advantages: a first tunneling layer, a first microcrystalline silicon layer, and a first passivation antireflection layer are sequentially disposed on the back side of the battery substrate. The second microcrystalline silicon layer contacts the substrate on the front side. Through the first and second microcrystalline silicon layers, long-wavelength parasitic absorption is reduced, the battery conductivity is improved, and the first and second microcrystalline silicon layers have fewer internal defects, which is conducive to carrier transport and improves the battery conversion efficiency. Attached Figure Description
[0020] The accompanying drawings are included to provide a further understanding of this application; they are incorporated into and constitute a part of this application. The drawings illustrate embodiments of this application and, together with this specification, serve to explain the principles of this application. In the drawings:
[0021] Figure 1 This is a schematic diagram of a photovoltaic cell according to an embodiment of the present invention;
[0022] Figure 2 This is a schematic diagram of another structure of a photovoltaic cell according to an embodiment of the present invention;
[0023] Figure 3 This is a schematic flowchart of a photovoltaic cell preparation method according to an embodiment of the present invention.
[0024] In the picture:
[0025] 110-substrate;
[0026] 121 - First tunnel layer, 122 - Second tunnel layer;
[0027] 131 - First microcrystalline silicon layer, 132 - Second microcrystalline silicon layer, 133 - Third microcrystalline silicon layer;
[0028] 141 - First passivation and anti-reflection layer; 142 - Second passivation and anti-reflection layer;
[0029] 151 - First metal grid line, 152 - Second metal grid line. Detailed Implementation
[0030] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of this application. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.
[0031] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.
[0032] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application. In addition, although the terminology used in this application is selected from commonly known and used terms, some terms mentioned in this application's specification may have been chosen by the applicant according to his or her judgment, and their detailed meanings are explained in the relevant sections of this description. Moreover, this application should be understood not only through the actual terms used, but also through the meaning implied by each term.
[0033] Flowcharts are used in this application to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations may be added to these processes, or one or more steps may be removed from these processes.
[0034] Figure 1 This is a schematic diagram of a photovoltaic cell according to an embodiment of the present invention, for reference. Figure 1As shown, the photovoltaic cell structure of this embodiment includes a substrate 110, which has a front side and a back side. On the back side of the substrate, a first tunneling layer 121, a first microcrystalline silicon layer 131, and a first passivation antireflection layer 141 are sequentially provided along a direction away from the substrate 110. A first metal gate line 151 is provided on the first passivation antireflection layer 141. The front side of the substrate includes a first region and a second region. In the first region, a second microcrystalline silicon layer 132 is provided on the substrate 110, and a second metal gate line 152 is provided on the second microcrystalline silicon layer 132. In the second region, a second passivation antireflection layer 142 is provided on the substrate 110.
[0035] Conventional TOPcon cells fabricate a polycrystalline silicon layer on top of a tunneling layer. However, the large absorption effect of the polycrystalline silicon layer negatively impacts the conversion efficiency of the photovoltaic cell. Furthermore, the formation of polycrystalline silicon requires high-temperature annealing (>900℃) of amorphous silicon. This high-temperature process has several drawbacks, including: 1. High energy consumption; 2. Uneven growth of polycrystalline silicon grains due to high temperatures, affecting contact with the slurry and thus reducing conversion efficiency; 3. Damage to the tunneling oxide layer due to high temperatures, easily leading to pinholes, which hinders carrier transport and results in more phosphorus atoms in the silicon substrate and polycrystalline silicon layer, causing parasitic absorption; 4. High temperatures affect hydrogen passivation. Polycrystalline silicon requires high temperatures to maintain crystallinity, but excessively high temperatures can cause the breakage of Si-H bonds, creating recombination centers and affecting efficiency.
[0036] This embodiment improves the battery structure and enhances battery performance through a microcrystalline silicon layer. A first microcrystalline silicon layer 131 is disposed on the back side of the substrate, on the first tunneling layer 121. On the front side of the substrate, a second microcrystalline silicon layer 132 contacts the substrate 110. Both the first and second microcrystalline silicon layers 131 and 132 can be deposited by controlling the flow ratio of silane and hydrogen, and high crystallinity can be achieved without high-temperature annealing at around 600°C. The use of microcrystalline silicon layers on both sides of the substrate 110 reduces parasitic absorption effects in the long wavelength range. Furthermore, the microcrystalline silicon layer has lower contact resistance, good conductivity, and a larger window, allowing for control of optical and electrical properties by controlling the oxygen content. The grains of the microcrystalline silicon layer are denser than those of polycrystalline silicon layers, with fewer internal defects, which is beneficial for carrier transport.
[0037] In this embodiment, the second microcrystalline silicon layer 132 serves as a transition layer between the second metal gate line 152 and the substrate 110, helping to improve the interface quality between the two. Because the second microcrystalline silicon layer 132 has a certain degree of crystallinity, its surface roughness and the number of dangling bonds may be lower than those of the amorphous silicon layer, thereby reducing the formation of interface state defects and recombination centers, and improving the contact quality between the second metal gate line 152 and the substrate 110. In some cases, the second microcrystalline silicon layer 132 can block the diffusion of impurities (such as metal ions) from the second metal gate line 152 into the substrate 110, helping to maintain the purity of the substrate 110 and avoiding performance degradation caused by impurities.
[0038] In one example, a third microcrystalline silicon layer 133 and a second tunneling layer 122 are also present between the first tunneling layer 121 and the first microcrystalline silicon layer 131, wherein the third microcrystalline silicon layer 133 is close to the first tunneling layer 121 and the second tunneling layer 122 is close to the first microcrystalline silicon layer 131.
[0039] refer to Figure 2 As shown, the following structure is formed on the back side of the substrate through the above method: sequentially including a first tunneling layer 121, a third microcrystalline silicon layer 133, a second tunneling layer 122, the first tunneling layer 121, and a first passivation antireflection layer 141. Since the microcrystalline silicon layer requires a high doping concentration to facilitate carrier transport, it is also necessary to consider that because the microcrystalline silicon layer is too close to the substrate 110, the dopant in the microcrystalline silicon layer can easily enter the substrate 110 during the doping process, affecting the performance of the photovoltaic cell. Therefore, in this embodiment, the microcrystalline silicon layer on the back side of the substrate is designed as two layers, namely a first microcrystalline silicon layer 131 and a third microcrystalline silicon layer 133. In this way, the third microcrystalline silicon layer 133, which is close to the substrate 110, can be lightly doped to avoid adverse effects on the substrate 110, while the first microcrystalline silicon layer 131, which is close to the first metal gate line 151, can be heavily doped, improving the carrier transport efficiency.
[0040] In one example, the substrate 110 is a p-type silicon substrate, and the first microcrystalline silicon layer 131, the second microcrystalline silicon layer 132, and the third microcrystalline silicon layer 133 are n-type doped microcrystalline silicon layers. Further, the doping concentration of the first microcrystalline silicon layer 131 and / or the second microcrystalline silicon layer 132 is 1E20 to 1E21 atoms / cm³, and the doping concentration of the third microcrystalline silicon layer 133 is 1E19 to 5E20 atoms / cm³.
[0041] Photovoltaic cells are mainly classified into P-type silicon substrate cells and N-type silicon substrate cells according to the type of silicon substrate. These two types of cells differ in structure, but their power generation principle is based on the separation of photogenerated carriers through a PN junction. The fabrication process of P-type silicon substrate cells is relatively simple and the cost is lower. In this embodiment, the cost of P-type silicon substrates is cheaper than that of N-type silicon substrates, and they do not require high-temperature treatment above 900°C, resulting in lower energy consumption.
[0042] In one example, the first tunneling layer 121 and / or the second tunneling layer 122 are SiO2 tunneling layers. The SiO2 tunneling layer can significantly reduce the recombination rate at the battery surface because it forms a highly stable dielectric film on the silicon substrate surface, reducing the surface electron concentration and lowering the electron-hole recombination rate. In one implementation, the thickness of the SiO2 tunneling layer is in the range of 1 nm to 1.5 nm.
[0043] In one example, the first passivation anti-reflection layer 141 and / or the second passivation anti-reflection layer 142 are SiN. x Layer. SiN x Layer 143 effectively blocks the battery surface from contacting harmful substances such as oxygen and water molecules in the air, reduces the number of interface state defects and dangling bonds, reduces the reflection loss of incident light on the battery surface, and improves the light absorption rate.
[0044] Furthermore, SiN x The layer can be replaced with a SiON layer or an ITO (transparent conductive film). In one implementation, the thickness of the first passivation antireflection layer 141 or the second passivation antireflection layer 142 can reach 80 nm. The thickness of 80 nm is sufficient to block the corrosion of the slurry and form a good contact.
[0045] In this embodiment, the photovoltaic cell has a first tunneling layer 121, a first microcrystalline silicon layer 131, and a first passivation antireflection layer 141 sequentially disposed on the back side of the substrate. On the front side of the substrate, a second microcrystalline silicon layer 132 contacts the substrate 110. The first and second microcrystalline silicon layers 131 and 132 reduce long-wavelength parasitic absorption, improving the cell's conductivity. Furthermore, the first and second microcrystalline silicon layers 131 and 132 have fewer internal defects, facilitating carrier transport and improving the cell's conversion efficiency. In addition, a third microcrystalline silicon layer 133 can be added to the back side of the substrate, thereby effectively controlling the doping concentration of each microcrystalline silicon layer on the back side of the substrate to achieve better carrier transport performance.
[0046] Another embodiment of the present invention provides a method for preparing a photovoltaic cell, referring to... Figure 3 As shown, method 300 includes: S310, providing a substrate having a front side and a back side, the front side including a first region and a second region; S320, sequentially fabricating a first tunneling layer, a first microcrystalline silicon layer, and a first passivation antireflection layer on the back side of the substrate, and fabricating a first metal gate line on the first passivation antireflection layer; S330, fabricating a second microcrystalline silicon layer on the substrate in the first region, and fabricating a second passivation antireflection layer on the substrate in the second region; and fabricating a second metal gate line on the second microcrystalline silicon layer.
[0047] In this embodiment, PECVD (Plasma Enhanced Chemical Vapor Deposition) can be used to prepare the film. PECVD is a process in which reactive gases are ionized in a deposition chamber using glow discharge or microwaves to produce chemically active ionic gases. These ionized gases then undergo a series of chemical reactions to form a stable thin film on the substrate surface. PECVD offers advantages such as low material costs, fast film formation speed, and minimal diffusion.
[0048] In one example, after fabricating the first microcrystalline silicon layer, a mask layer is also fabricated on the first microcrystalline silicon layer. Therefore, fabricating the first passivation antireflection layer specifically involves removing the mask layer and then fabricating the first passivation antireflection layer.
[0049] After the first microcrystalline silicon layer is prepared, a waiting period is required before the preparation of subsequent films (such as the first passivation antireflection layer). Therefore, to avoid the formation of an oxide layer on the surface of the first microcrystalline silicon layer, this embodiment can prepare a mask layer after the first microcrystalline silicon layer is prepared. When performing the next film preparation process, this mask layer is removed before the preparation of subsequent films.
[0050] In one example, the preparation of the second microcrystalline silicon layer includes: preparing a microcrystalline silicon layer on the front side of the substrate, removing the microcrystalline silicon layer outside the first region, and the remaining microcrystalline silicon layer being the second microcrystalline silicon layer.
[0051] In one example, during the fabrication of the second microcrystalline silicon layer, the portion of the second microcrystalline silicon layer in contact with the substrate is processed using laser doping. Using laser doping can reduce the effects of high temperatures and improve the contact effect between the second microcrystalline silicon layer and the substrate.
[0052] In one example, method 300 further includes: after the preparation of the first tunneling layer and before the preparation of the first microcrystalline silicon layer, sequentially preparing the third microcrystalline silicon layer and the second tunneling layer on the first tunneling layer; specifically, preparing the first microcrystalline silicon layer is done on the second tunneling layer. Therefore, a stacked structure of the first tunneling layer, the third microcrystalline silicon layer, the second tunneling layer, and the first microcrystalline silicon layer can be formed on the back side of the substrate.
[0053] In one example, the substrate is a p-type silicon substrate, and the first, second, and third microcrystalline silicon layers are n-type doped microcrystalline silicon layers. Further, the doping concentration of the first and / or second microcrystalline silicon layers is 1E20–1E21 atoms / cm³, and the doping concentration of the third microcrystalline silicon layer is 1E19–5E20 atoms / cm³.
[0054] The photovoltaic cell fabricated by the method described in this embodiment has a substrate with a first tunneling layer, a first microcrystalline silicon layer, and a first passivation antireflection layer sequentially disposed on the back side. A second microcrystalline silicon layer contacts the substrate on the front side. The first and second microcrystalline silicon layers reduce long-wavelength parasitic absorption, improving cell conductivity. Furthermore, the first and second microcrystalline silicon layers have fewer internal defects, facilitating carrier transport and improving cell conversion efficiency. Adding a third microcrystalline silicon layer on the back side of the substrate effectively controls the doping concentration of each microcrystalline silicon layer on the back side, achieving even better carrier transport performance.
[0055] The basic concepts have been described above. Obviously, for those skilled in the art, the above disclosure is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.
[0056] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic related to at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.
[0057] Although this application has been described with reference to specific embodiments, those skilled in the art should recognize that the above embodiments are only used to illustrate this application, and various equivalent changes or substitutions can be made without departing from the spirit of this application. Therefore, any changes or modifications to the above embodiments within the essential spirit of this application will fall within the scope of the claims of this application.
Claims
1. A photovoltaic cell, characterized in that, Includes a substrate, the substrate having a front side and a back side; On the back side of the substrate, a first tunneling layer, a first microcrystalline silicon layer, and a first passivation antireflection layer are sequentially provided along a direction away from the substrate, and a first metal gate line is provided on the first passivation antireflection layer; The front side of the substrate includes a first region and a second region. In the first region, the substrate has a second microcrystalline silicon layer and a second metal gate line. In the second region, the substrate has a second passivation antireflection layer.
2. The photovoltaic cell as described in claim 1, characterized in that, A third microcrystalline silicon layer and a second tunneling layer are further provided between the first tunneling layer and the first microcrystalline silicon layer, wherein the third microcrystalline silicon layer is close to the first tunneling layer and the second tunneling layer is close to the first microcrystalline silicon layer.
3. The photovoltaic cell as described in claim 2, characterized in that, The substrate is a p-type silicon substrate, and the first microcrystalline silicon layer, the second microcrystalline silicon layer and the third microcrystalline silicon layer are n-type doped microcrystalline silicon layers.
4. The photovoltaic cell as described in claim 3, characterized in that, The doping concentration of the first microcrystalline silicon layer and / or the second microcrystalline silicon layer is 1E20 to 1E21 atoms / cm³, and the doping concentration of the third microcrystalline silicon layer is 1E19 to 5E20 atoms / cm³.
5. The photovoltaic cell as described in claim 2, characterized in that, The first tunneling layer and / or the second tunneling layer are SiO2 tunneling layers.
6. The photovoltaic cell as described in claim 1, characterized in that, The first passivation anti-reflection layer and / or the second passivation anti-reflection layer are SiN x layer.
7. A method for preparing a photovoltaic cell, characterized in that, include: A substrate is provided, the substrate having a front side and a back side, the front side including a first region and a second region; A first tunneling layer, a first microcrystalline silicon layer, and a first passivation antireflection layer are sequentially fabricated on the back side of the substrate, and a first metal gate line is fabricated on the first passivation antireflection layer. In the first region, a second microcrystalline silicon layer is formed on the substrate; in the second region, a second passivation antireflection layer is formed on the substrate; and a second metal gate line is formed on the second microcrystalline silicon layer.
8. The method for preparing a photovoltaic cell as described in claim 7, characterized in that, Also includes: After the first microcrystalline silicon layer is prepared, a mask layer is also prepared on the first microcrystalline silicon layer; The preparation of the first passivation antireflection layer includes: removing the mask layer and then preparing the first passivation antireflection layer.
9. The method for preparing a photovoltaic cell as described in claim 7, characterized in that, The preparation of the second microcrystalline silicon layer includes: preparing a microcrystalline silicon layer on the front side of the substrate, removing the microcrystalline silicon layer outside the first region, and the remaining microcrystalline silicon layer being the second microcrystalline silicon layer.
10. The method for preparing a photovoltaic cell as described in claim 7, characterized in that, When preparing the second microcrystalline silicon layer, the portion of the second microcrystalline silicon layer in contact with the substrate is prepared using a laser doping process.
11. The method for preparing a photovoltaic cell as described in claim 7, characterized in that, Also includes: After the first tunneling layer is prepared and before the first microcrystalline silicon layer is prepared, a third microcrystalline silicon layer and a second tunneling layer are sequentially prepared on the first tunneling layer. The preparation of the first microcrystalline silicon layer includes: preparing the first microcrystalline silicon layer on the second tunneling layer.
12. The method for preparing a photovoltaic cell as described in claim 11, characterized in that, The substrate is a p-type silicon substrate, and the first microcrystalline silicon layer, the second microcrystalline silicon layer and the third microcrystalline silicon layer are n-type doped microcrystalline silicon layers.
13. The method for preparing a photovoltaic cell as described in claim 12, characterized in that, The doping concentration of the first microcrystalline silicon layer and / or the second microcrystalline silicon layer is 1E20 to 1E21 atoms / cm³, and the doping concentration of the third microcrystalline silicon layer is 1E19 to 5E20 atoms / cm³.