Capacitive sensor detection circuit

Abstract

A capacitive sensor detection circuit is used in a sensor element (10). The sensor element is provided with: a movable electrode (100) that can be displaced; a first electrode (121) that outputs a signal corresponding to a change in a first capacitance (Cs1) that changes in accordance with the displacement of the movable electrode; and a second electrode (122) that outputs a signal corresponding to a change in a second capacitance (Cs2) that changes in accordance with the displacement of the movable electrode. The capacitive sensor detection circuit (20) is provided with a control unit that acquires a first input signal (Vin1) and a second input signal (Vin2). A signal having a frequency corresponding to the frequency of the modulation signal and a phase opposite to the phase of the modulation signal is output to the first capacitor and the second capacitor, said signal having a feedback amplitude Vcnt at which the amplitudes of a first input signal Vin1 and a second input signal Vin2, which correspond to the frequency and the phase of the modulation signal S, approach zero.

Description

Technical Field

[0001] This disclosure relates to a detection circuit for a capacitive sensor. Background Technology

[0002] Conventionally, as described in Non-Patent Document 1, there are known detection circuits for capacitive sensors that detect acceleration based on changes in electrostatic capacitance due to electrode displacement. These detection circuits include: a fully differential amplifier that outputs a signal corresponding to the change in electrostatic capacitance; and a feedback amplifier that controls the input voltage of the fully differential amplifier to a predetermined voltage.

[0003] Existing technical documents Patent documents Non-patent document 1: A Three-Axis Micromachined Accelerometer with a CMOSPosition-Sense Interface and Digital Offset-Trim Electronics IEEE JOURNAL OFSOLID-STATE CIRCUITS, VOL.34, NO.4, APRIL 1999 Summary of the Invention

[0004] The problem that the invention aims to solve In the detection circuit described in Non-Patent Document 1, the feedback amplifier sets the input voltage of the fully differential amplifier to a predetermined voltage, thus resetting the input voltage of the fully differential amplifier. During the period when the input voltage of the fully differential amplifier is reset, the signal output from the fully differential amplifier does not contain a signal corresponding to acceleration, and therefore becomes a signal that is discontinuous in time.

[0005] The purpose of this disclosure is to provide a capacitive sensor detection circuit that makes the output signal corresponding to the change in electrostatic capacitance a signal that is continuous with respect to time.

[0006] Solution for solving the problem The capacitive sensor detection circuit according to the first aspect of this disclosure is used for a sensor element, the sensor element comprising: a displaceable movable electrode; a first electrode that outputs a signal corresponding to a change in a first electrostatic capacitance between the first electrode and the movable electrode, which varies according to the displacement of the movable electrode; and a second electrode that outputs a signal corresponding to a change in a second electrostatic capacitance between the second electrode and the movable electrode, which varies according to the displacement of the movable electrode. The capacitive sensor detection circuit comprises: a signal generation unit that outputs a signal having an input amplitude, frequency, and phase, i.e., a modulation signal, to the movable electrode; a fully differential amplifier having a first input terminal connected to the first electrode, a second input terminal connected to the second electrode, a first output terminal outputting a signal corresponding to the signal input to the first input terminal (i.e., a first input signal) and the signal input to the second input terminal (i.e., a second input signal), and a second output terminal outputting a signal corresponding to the first input signal and the second input signal; a first feedback capacitor connected to the first input terminal and the first output terminal; a second feedback capacitor connected to the second input terminal and the second output terminal; and a calculation unit that calculates a signal based on the change in capacitance between the first electrode and the second electrode. The system comprises: a first output signal output from an output terminal and a second output signal output from a second output terminal; a value related to the displacement of a movable electrode; a first capacitor connected to a node between the first electrode and the first input terminal; a second capacitor connected to a node between the second electrode and the second input terminal; and a control unit that acquires the first input signal and the second input signal, and outputs a signal to the first capacitor and the second capacitor such that the amplitude of the first input signal and the second input signal, whose frequency and phase correspond to the frequency and phase of the modulation signal, are close to zero, the frequency of the signal corresponds to the frequency of the modulation signal, and the phase of the signal is opposite to the phase of the modulation signal.

[0007] Furthermore, the capacitive sensor detection circuit according to the second aspect of this disclosure is used for a sensor element, which includes: a displaceable movable electrode; a first electrode that outputs a signal corresponding to a change in a first electrostatic capacitance between the first electrode and the movable electrode, which varies according to the displacement of the movable electrode; and a second electrode that outputs a signal corresponding to a change in a second electrostatic capacitance between the second electrode and the movable electrode, which varies according to the displacement of the movable electrode. The capacitive sensor detection circuit includes: a signal generation unit that outputs a signal having an input amplitude, frequency, and phase, i.e., a modulation signal, to the movable electrode; a fully differential amplifier having a first input terminal connected to the first electrode, a second input terminal connected to the second electrode, a first output terminal outputting a signal corresponding to the signal input to the first input terminal (i.e., a first input signal) and the signal input to the second input terminal (i.e., a second input signal), and a second output terminal outputting a signal corresponding to the first input signal and the second input signal; a first feedback capacitor connected to the first input terminal and the first output terminal; a second feedback capacitor connected to the second input terminal and the second output terminal; and a calculation unit that calculates a signal based on the change in capacitance between the first electrode and the second electrode. The system comprises: a first output signal output from an output terminal and a second output signal output from a second output terminal; a value related to the displacement of a movable electrode; a first capacitor connected to a node between the first electrode and the first input terminal; a second capacitor connected to a node between the second electrode and the second input terminal; and a control unit that acquires the first output signal and the second output signal and outputs a signal to the first capacitor and the second capacitor such that the signal has a feedback amplitude that makes the amplitude of the first output signal and the second output signal, whose frequency and phase correspond to the frequency and phase of the modulation signal, approach zero; the frequency of the signal corresponds to the frequency of the modulation signal; and the phase of the signal is opposite to the phase of the modulation signal.

[0008] Therefore, the frequency and phase of the first input signal and the amplitude of the second input signal, corresponding to the frequency and phase of the modulated signal, continuously approach zero. Thus, there is no need to set a reset period for the first and second input signals. Therefore, the output signal from the fully differential amplifier, corresponding to the changes in the first and second electrostatic capacitances, becomes a signal that is continuous with respect to time.

[0009] Furthermore, the bracketed reference numerals used to indicate each constituent element, etc., represent an example of the correspondence between that constituent element, etc., and the specific constituent elements, etc., described in the embodiments described later. Attached Figure Description

[0010] Figure 1 This is a configuration diagram of the sensor element using the capacitive sensor detection circuit of the first embodiment.

[0011] Figure 2This is a circuit diagram of a capacitive sensor detection circuit.

[0012] Figure 3 This is a diagram representing the modulation signal from the signal generation section of the detection circuit of a capacitive sensor.

[0013] Figure 4 This is a diagram showing the common-mode feedback circuit of the output of a fully differential amplifier in a capacitive sensor detection circuit.

[0014] Figure 5 This is a block diagram of the control section of the capacitive sensor detection circuit.

[0015] Figure 6 This is the circuit diagram of the control unit.

[0016] Figure 7 A diagram showing the signals output from the control unit.

[0017] Figure 8 This is a circuit diagram of the control unit in the capacitive sensor detection circuit of the second embodiment.

[0018] Figure 9 This is a circuit diagram of the capacitive sensor detection circuit according to the third embodiment.

[0019] Figure 10 This is a diagram showing the input common-mode feedback circuit of the fully differential amplifier in the capacitive sensor detection circuit of the fourth embodiment.

[0020] Figure 11 This is a circuit diagram of a capacitive sensor detection circuit.

[0021] Figure 12 This is a circuit diagram of the control section of the capacitive sensor detection circuit.

[0022] Figure 13 This is a circuit diagram of the control unit in the capacitive sensor detection circuit of the fifth embodiment.

[0023] Figure 14 This is a circuit diagram of the capacitive sensor detection circuit according to the sixth embodiment. Detailed Implementation

[0024] Hereinafter, embodiments will be described with reference to the accompanying drawings. Furthermore, in the following embodiments, the same reference numerals are used to label the same or equivalent parts, and their descriptions are omitted.

[0025] (First Implementation) The capacitive sensor detection circuit of this embodiment is used for Figure 1The sensor element 10 shown is configured to output a signal that is continuous with respect to time, corresponding to changes in electrostatic capacitance. First, the sensor element 10 will be described.

[0026] The sensor element 10 includes a movable electrode 100, a first elastic part 101, a first fixed part 111, a second elastic part 102, a second fixed part 112, a first electrode 121, and a second electrode 122.

[0027] The movable electrode 100 is displaced by acceleration or pressure. One end of the first elastic part 101 is connected to the movable electrode 100 in the direction of displacement. The other end of the first elastic part 101 is connected to the first fixed part 111 in the direction of displacement. The first fixed part 111 is fixed to a housing or the like (not shown). One end of the second elastic part 102 is connected to the side of the movable electrode 100 opposite to the first elastic part 101 in the direction of displacement. The other end of the second elastic part 102 is connected to the second fixed part 112 in the direction of displacement. The second fixed part 112 is fixed to a housing or the like (not shown). Therefore, if the movable electrode 100 is displaced, the first elastic part 101 and the second elastic part 102 generate a restoring force through elastic deformation. Through this restoring force, the displaced movable electrode 100 returns to its original position.

[0028] The first electrode 121 and the portion of the movable electrode 100 connected to the first elastic part 101 are opposite each other in the direction of displacement of the movable electrode 100. Furthermore, when the movable electrode 100 is displaced, the distance between the first electrode 121 and the movable electrode 100 changes, thus changing the first electrostatic capacitance Cs1. Therefore, as... Figure 2 As shown, the first electrode 121 and the movable electrode 100 function as variable capacitors. Furthermore, the first electrostatic capacitance Cs1 is the electrostatic capacitance between the first electrode 121 and the movable electrode 100.

[0029] return Figure 1 For example, when the movable electrode 100 moves toward the first electrode 121, the distance between the first electrode 121 and the movable electrode 100 decreases, thus increasing the first electrostatic capacitance Cs1. Furthermore, the first electrode 121 outputs a signal corresponding to the change in the first electrostatic capacitance Cs1.

[0030] The second electrode 122 is opposite to the portion of the movable electrode 100 connected to the second elastic part 102 in the direction of displacement of the movable electrode 100. Therefore, the second electrode 122 is opposite to the side of the movable electrode 100 opposite to the first electrode 121. Furthermore, when the movable electrode 100 is displaced, the distance between the second electrode 122 and the movable electrode 100 changes, thus changing the second electrostatic capacitance Cs2. Therefore, as... Figure 2 As shown, the second electrode 122 and the movable electrode 100 function as variable capacitors. Furthermore, the second electrostatic capacitance Cs2 is the electrostatic capacitance between the second electrode 122 and the movable electrode 100.

[0031] return Figure 1 For example, when the movable electrode 100 moves toward the first electrode 121, the distance between the second electrode 122 and the movable electrode 100 increases, thus decreasing the second electrostatic capacitance Cs2. Therefore, when the movable electrode 100 moves, the change in the second electrostatic capacitance Cs2 is opposite to the change in the first electrostatic capacitance Cs1. Furthermore, the second electrode 122 outputs a signal corresponding to the change in the second electrostatic capacitance Cs2.

[0032] Furthermore, here, the first electrostatic capacitance Cs1 when the movable electrode 100 is not displaced is the same as the second electrostatic capacitance Cs2 when the movable electrode 100 is not displaced, and is designated as Cs0. Additionally, the sameness includes the manufacturing tolerance range.

[0033] The sensor element 10 is configured as described above. Next, the structure of the capacitive sensor detection circuit for the sensor element 10 will be described.

[0034] like Figure 2 As shown, the capacitive sensor detection circuit 20 is an ASIC, comprising a signal generation unit 22, a fully differential amplifier 24, a first feedback capacitor 31, a first feedback resistor 41, a second feedback capacitor 32, and a second feedback resistor 42. Furthermore, the capacitive sensor detection circuit 20 includes a calculation unit 50, a first parasitic capacitor 51, a second parasitic capacitor 52, a first capacitor 61, a second capacitor 62, and a control unit 70. Additionally, ASIC is an abbreviation for Application Specific Integrated Circuit.

[0035] The signal generation unit 22 modulates the signal by including a modulator. Furthermore, the signal generation unit 22 outputs the modulated signal to the movable electrode 100. The signal output by the signal generation unit 22 is a signal having an input amplitude Vm, frequency, and phase, for example, such as... Figure 3 The image shown is a rectangular wave. However, the signal output by the signal generation unit 22 is not limited to a rectangular wave; it can also be a triangular wave, a sawtooth wave, or a sine wave, etc.

[0036] Here, the signal output from the signal generation unit 22 to the movable electrode 100 is designated as the modulation signal S. The signal with an amplitude equal to the input amplitude Vm, a frequency the same as the frequency of the modulation signal S, and a phase opposite to the phase of the modulation signal S is designated as the inverting signal Sinv.

[0037] Then, return Figure 2The signal generation unit 22 outputs the modulation signal S and the inverting signal Sinv to the control unit 70, which will be described later.

[0038] The fully differential amplifier 24 has a first input terminal 241, a second input terminal 242, a first output terminal 251, and a second output terminal 252.

[0039] The first input terminal 241 is a non-inverting input terminal and is connected to the first electrode 121. A signal from the first electrode 121 is input to the first input terminal 241.

[0040] The second input terminal 242 is an inverting input terminal and is connected to the second electrode 122. Additionally, a signal from the second electrode 122 is input to the second input terminal 242.

[0041] Here, the signal input to the first input terminal 241 is designated as the first input signal Vin1. The signal input to the second input terminal 242 is designated as the second input signal Vin2.

[0042] The first output terminal 251 outputs a signal corresponding to the first input signal Vin1 and the second input signal Vin2.

[0043] The second output terminal 252 outputs a signal corresponding to the first input signal Vin1 and the second input signal Vin2.

[0044] Furthermore, the signal output from the first output terminal 251 is designated as the first output signal Vout1. The signal output from the second output terminal 252 is designated as the second output signal Vout2.

[0045] Furthermore, the fully differential amplifier 24 includes Figure 4 The output common-mode feedback circuit 260 is shown. Therefore, half of the voltage associated with the sum of the first output signal Vout1 and the second output signal Vout2, i.e., (Vout1+Vout2) / 2, is controlled to be a predetermined voltage. Furthermore, the predetermined voltage is set through experiments, simulations, etc.

[0046] return Figure 2 One end of the first feedback capacitor 31 is connected to the first input terminal 241. The other end of the first feedback capacitor 31 is connected to the first output terminal 251.

[0047] One end of the second feedback capacitor 32 is connected to the second input terminal 242. The other end of the second feedback capacitor 32 is connected to the second output terminal 252.

[0048] One end of the first feedback resistor 41 is connected to the first input terminal 241 and one end of the first feedback capacitor 31. The other end of the first feedback resistor 41 is connected to the first output terminal 251 and the other end of the first feedback capacitor 31.

[0049] One end of the second feedback resistor 42 is connected to the second input terminal 242 and one end of the second feedback capacitor 32. The other end of the second feedback resistor 42 is connected to the second output terminal 252 and the other end of the second feedback capacitor 32.

[0050] Here, the electrostatic capacitance of the first feedback capacitor 31 is designated as the first feedback capacitor Cf1. The electrostatic capacitance of the second feedback capacitor 32 is designated as the second feedback capacitor Cf2. The resistance of the first feedback resistor 41 is designated as the first resistance Rf1. The resistance of the second feedback resistor 42 is designated as the second resistance Rf2.

[0051] Furthermore, the first feedback capacitor Cf1 and the second feedback capacitor Cf2 are set to the same value, Cf. Therefore, Cf1 = Cf2 = Cf. Additionally, the first resistor Rf1 and the second resistor Rf2 are set to the same value, Rf. Therefore, Rf1 = Rf2 = Rf.

[0052] The calculation unit 50 acquires a first output signal Vout1 and a second output signal Vout2. Based on these acquired first output signals Vout1 and second output signals Vout2, the calculation unit 50 calculates the displacement of the movable electrode 100. Furthermore, the calculation unit 50 calculates the acceleration, pressure, etc., of the movable electrode 100 based on the calculated displacement. Thus, the calculation unit 50 calculates the acceleration, pressure, etc., of a detection object (not shown) that moves along with the movable electrode 100. Moreover, the acceleration, pressure, etc., of the movable electrode 100 correspond to values ​​related to the displacement of the movable electrode 100.

[0053] One end of the first parasitic capacitor 51 is connected between the first electrode 121 and the first input terminal 241. The other end of the first parasitic capacitor 51 is grounded.

[0054] One end of the second parasitic capacitor 52 is connected between the second electrode 122 and the second input terminal 242. The other end of the second parasitic capacitor 52 is grounded.

[0055] One end of the first capacitor 61 is connected between the first electrode 121 and the first input terminal 241. The other end of the first capacitor 61 is connected to the control unit 70, which will be described later.

[0056] One end of the second capacitor 62 is connected between the second electrode 122 and the second input terminal 242. The other end of the second capacitor 62 is connected to the control unit 70, which will be described later.

[0057] Here, the electrostatic capacitance of the first capacitor 61 is designated as the first capacitor capacitance Ct1. The electrostatic capacitance of the second capacitor 62 is designated as the second capacitor capacitance Ct2.

[0058] Furthermore, the capacitance of the first capacitor Ct1 and the capacitance of the second capacitor Ct2 are set to be the same, which is set to Ct0. Therefore, Ct1 = Ct2 = Ct0.

[0059] like Figure 5 As shown, the control unit 70 includes an adder 75, a synchronous detector 80, a controller 85, a first adjustment switch 91, and a second adjustment switch 92.

[0060] like Figure 6 As shown, the adder 75 includes, for example, a first voltage follower circuit 751, a first power supply 761, a first constant current power supply 771, a second voltage follower circuit 752, a second power supply 762, and a second constant current power supply 772. Furthermore, the adder 75 includes a first filter capacitor 781, a second filter capacitor 782, a confluencer 785, a filter resistor 787, a high-pass filter 790, and a reference power supply 795.

[0061] The first voltage follower circuit 751 acquires a first input signal Vin1 and outputs a signal corresponding to the acquired first input signal Vin1. Specifically, the first voltage follower circuit 751 includes at least one transistor. Here, the number of transistors in the first voltage follower circuit 751 is one. Moreover, the transistor in the first voltage follower circuit 751 is, for example, a MOSFET. The drain electrode of the MOSFET in the first voltage follower circuit 751 is connected to the first power supply 761. The gate electrode of the MOSFET in the first voltage follower circuit 751 corresponds to the input terminal of the first voltage follower circuit 751 and is connected between the first electrode 121 and the first input terminal 241. The source electrode of the MOSFET in the first voltage follower circuit 751 corresponds to the output terminal of the first voltage follower circuit 751 and is grounded via the first constant current power supply 771. Therefore, the first voltage follower circuit 751 acquires the first input signal Vin1 and outputs a signal equal to Vin1-Vgs1, which is the voltage obtained by subtracting the first gate-source voltage Vgs1 from the voltage of the first input signal Vin1. MOSFET is an abbreviation for Metal-Oxide-Semiconductor Field-Effect Transistor. The first gate-source voltage Vgs1 is the voltage between the gate electrode and the source electrode in the MOSFET of the first voltage follower circuit 751.

[0062] The second voltage follower circuit 752 acquires the second input signal Vin2 and outputs a signal corresponding to the acquired second input signal Vin2. Specifically, the second voltage follower circuit 752 includes at least one transistor. Here, the number of transistors in the second voltage follower circuit 752 is one. Furthermore, the transistor in the second voltage follower circuit 752 is, for example, a MOSFET. The drain electrode of the MOSFET in the second voltage follower circuit 752 is connected to the second power supply 762. The gate electrode of the MOSFET in the second voltage follower circuit 752 is equivalent to the input terminal of the second voltage follower circuit 752 and is connected between the second electrode 122 and the second input terminal 242. The source electrode of the MOSFET in the second voltage follower circuit 752 is equivalent to the output terminal of the second voltage follower circuit 752 and is grounded via the second constant current power supply 772. Therefore, the second voltage follower circuit 752 acquires the second input signal Vin2 and outputs a signal obtained by subtracting the second gate-source voltage Vgs2 from the voltage of the second input signal Vin2, i.e., the Vin2-Vgs2 voltage. In addition, the second gate-source voltage Vgs2 is the voltage between the gate electrode and the source electrode in the MOSFET of the second voltage follower circuit 752.

[0063] One end of the first filter capacitor 781 is connected to the source electrode of the MOSFET of the first voltage follower circuit 751. Therefore, the first filter capacitor 781 outputs the signal from the first voltage follower circuit 751.

[0064] One end of the second filter capacitor 782 is connected to the source electrode of the MOSFET in the second voltage follower circuit 752. Therefore, the second filter capacitor 782 outputs the signal from the second voltage follower circuit 752.

[0065] The merging section 785 is connected to the other end of the first filter capacitor 781 and the other end of the second filter capacitor 782. Therefore, the signal of the merging section 785 is the sum of the signals output from the first filter capacitor 781 and the signals output from the second filter capacitor 782. The signal output from the first filter capacitor 781 is a signal related to the first input signal Vin1, and the signal output from the second filter capacitor 782 is a signal related to the second input signal Vin2. Therefore, in the adding section 75, the signal related to the sum of the first input signal Vin1 and the second input signal Vin2 is acquired.

[0066] One end of the filter resistor 787 is connected to the other end of the first filter capacitor 781 and the other end of the second filter capacitor 782 via the confluence section 785.

[0067] The high-pass filter 790 includes a first filter capacitor 781, a second filter capacitor 782, and a filter resistor 787. Furthermore, the high-pass filter 790 removes low-frequency components from the signal in the confluence section 785. Thus, the high-pass filter 790 removes the DC component from the signal in the confluence section 785. Therefore, the high-pass filter 790 removes the DC component from the signal related to the sum of the first input signal Vin1 and the second input signal Vin2.

[0068] The positive terminal of the reference power supply 795 is connected to the confluence section 785 via a filter resistor 787. The negative terminal of the reference power supply 795 is grounded. The voltage of the reference power supply 795 is, for example, half of the output voltage of the first power supply 761 or the second power supply 762.

[0069] The synchronous detector 80 demodulates the signal related to the sum of the first input signal Vin1 and the second input signal Vin2 in accordance with the frequency and phase of the modulation signal S. For example, the synchronous detector 80 includes a first switch 801, a second switch 802, a third switch 803, and a fourth switch 804.

[0070] One end of the first switch 801 is connected to the confluence section 785. Furthermore, the first switch 801 is switched on and off according to the modulation signal S. One end of the second switch 802 is connected to the confluence section 785. Additionally, the second switch 802 is switched on and off according to the inverting signal Sinv. One end of the third switch 803 is connected to the other end of the filter resistor 787 and the positive terminal of the reference power supply 795. Furthermore, the third switch 803 is switched on and off according to the modulation signal S. One end of the fourth switch 804 is connected to the other end of the filter resistor 787 and the positive terminal of the reference power supply 795. Additionally, the fourth switch 804 is switched on and off according to the inverting signal Sinv.

[0071] Therefore, through the modulation signal S and the inverting signal Sinv, the first switch 801, the second switch 802, the third switch 803, and the fourth switch 804 are turned on and off. This demodulates the signal in the confluence section 785 according to the frequency and phase of the modulation signal S. Therefore, the signal related to the sum of the first input signal Vin1 and the second input signal Vin2 is demodulated according to the frequency and phase of the modulation signal S.

[0072] The controller 85 includes a transconductance amplifier 850 for the controller and a capacitor 852 for the controller.

[0073] The non-inverting input terminal of the transconductance amplifier 850 is connected to the other end of the second switch 802 and the other end of the third switch 803. Furthermore, the non-inverting input terminal of the transconductance amplifier 850 is connected to the positive terminal of the reference power supply 795 via the third switch 803. The inverting input terminal of the transconductance amplifier 850 is connected to the other end of the first switch 801 and the other end of the fourth switch 804. Additionally, the inverting input terminal of the transconductance amplifier 850 is connected to the positive terminal of the reference power supply 795 via the fourth switch 804. Therefore, the transconductance amplifier 850 compares the signal related to the sum of the first input signal Vin1 and the second input signal Vin2, which are demodulated by the synchronous detector 80, with the signal from the reference power supply 795.

[0074] One end of the controller capacitor 852 is connected to the output terminal of the controller transconductance amplifier 850. The other end of the controller capacitor 852 is grounded. Therefore, the controller 85 becomes a gm-c integrator through the controller transconductance amplifier 850 and the controller capacitor 852.

[0075] Furthermore, the controller 85 uses the signal demodulated by the synchronous detector 80 related to the sum of the first input signal Vin1 and the second input signal Vin2, the signal from the reference power supply 795, the transconductance amplifier 850 for the controller, and the capacitor 852 for the controller. Thus, the controller 85 calculates a feedback amplitude Vcnt that makes the amplitude of the signal demodulated by the synchronous detector 80 related to the sum of the first input signal Vin1 and the second input signal Vin2 zero. Additionally, the controller 85 outputs a signal having the calculated feedback amplitude Vcnt to the first adjustment switch 91.

[0076] One end of the first adjustment switch 91 is connected to the output terminal of the transconductance amplifier 850 for the controller and one end of the capacitor 852 for the controller. Thus, a signal with a feedback amplitude Vcnt is input to the first adjustment switch 91. Furthermore, the other end of the first adjustment switch 91 is connected to the other end of the first capacitor 61 and the other end of the second capacitor 62. Additionally, the first adjustment switch 91 is turned on and off according to the inverted signal Sinv.

[0077] One end of the second adjustment switch 92 is grounded. The other end of the second adjustment switch 92 is connected to the other ends of the first capacitor 61, the second capacitor 62, and the first adjustment switch 91. Furthermore, the second adjustment switch 92 is switched on and off according to the modulation signal S.

[0078] Furthermore, the first adjustment switch 91 and the second adjustment switch 92 are turned on and off according to the modulation signal S and the inverting signal Sinv. Thus, as... Figure 7As shown, the frequency of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 is adjusted to the frequency of the modulation signal S. Furthermore, the phase of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 is adjusted to be opposite to the phase of the modulation signal S, i.e., the phase of the inverted signal Sinv. Figure 2 As shown, a signal with a feedback amplitude Vcnt that has its frequency and phase adjusted is output to the first capacitor 61 and the second capacitor 62.

[0079] The capacitive sensor detection circuit 20 of the first embodiment is configured as described above. Next, the operation of the capacitive sensor detection circuit 20 will be explained.

[0080] The signal generation unit 22 outputs a modulated signal S having an input amplitude Vm, frequency, and phase to the movable electrode 100 and the control unit 70. Furthermore, the signal generation unit 22 outputs an inverted signal Sinv to the control unit 70. Additionally, the movable electrode 100 moves toward the first electrode 121. At this time, the first electrostatic capacitance Cs1 increases, and the second electrostatic capacitance Cs2 decreases. The change in the first electrostatic capacitance Cs1 and the second electrostatic capacitance Cs2 is defined as ΔCs. The first electrostatic capacitance Cs1 is expressed as shown in equation (1-1). The second electrostatic capacitance Cs2 is expressed as shown in equation (1-2). Furthermore, as described above, Cs0 represents the first electrostatic capacitance Cs1 and the second electrostatic capacitance Cs2 when the movable electrode 100 is not moved.

[0081] Cs1=Cs0+ΔCs ……(1-1) Cs2=Cs0-ΔCs ……(1-2) Then, the first electrode 121 outputs a signal corresponding to ΔCs to the first input terminal 241. Thus, a signal from the first electrode 121 is input to the first input terminal 241. Additionally, the second electrode 122 outputs a signal corresponding to ΔCs to the second input terminal 242. Thus, a signal from the second electrode 122 is input to the second input terminal 242. At this time, the first output terminal 251 outputs a first output signal Vout1 corresponding to the first input signal Vin1 and the second input signal Vin2 to the calculation unit 50. The second output terminal 252 outputs a second output signal Vout2 corresponding to the first input signal Vin1 and the second input signal Vin2 to the calculation unit 50.

[0082] At this time, the amplitude of the difference between the first output signal Vout1 and the second output signal Vout2 is expressed using the input amplitude Vm, ΔCs, and Cf as shown in the following equation (1-3). Furthermore, as mentioned above, Cf is the electrostatic capacitance of the first feedback capacitor 31 and the second feedback capacitor 32. Additionally, Vout1 in the following equation (1-3) is the amplitude of the first output signal Vout1. Vout2 in the following equation (1-3) is the amplitude of the second output signal Vout2.

[0083] Vout1-Vout2=2×Vm×ΔCs / Cf……(1-3) Therefore, the calculation unit 50 acquires a first output signal Vout1 from the first output terminal 251. Furthermore, the calculation unit 50 acquires a second output signal Vout2 from the second output terminal 252. In addition, using these acquired first output signals Vout1 and Vout2, a preset input amplitude Vm and Cf, and the aforementioned relationships (1-3), the calculation unit 50 calculates ΔCs. Furthermore, the calculation unit 50 calculates the displacement of the movable electrode 100 based on the calculated ΔCs. Additionally, the calculation unit 50 calculates the acceleration, pressure, etc., of the movable electrode 100 based on the calculated displacement. Thus, the calculation unit 50 calculates the acceleration, pressure, etc., of a detection object (not shown) that moves along with the movable electrode 100.

[0084] Here, the absolute value of the difference between Cs0 and the capacitances of the first capacitor Ct1 and the second capacitor Ct2 is defined as ΔCe. Furthermore, it is assumed that the amplitude of the signal output from the control unit 70 to the first capacitor 61 and the second capacitor 62 is the same as the input amplitude Vm.

[0085] At this point, the amplitude of the first input signal Vin1, whose frequency and phase correspond to the frequency and phase of the modulation signal S, is expressed using input amplitudes Vm, ΔCe, and Cf as shown in equation (1-4). The amplitude of the second input signal Vin2, whose frequency and phase correspond to the frequency and phase of the modulation signal S, is expressed using input amplitudes Vm, ΔCe, and Cf as shown in equation (1-5). Furthermore, Vin1 in equation (1-4) is the amplitude of the first input signal Vin1. Vin2 in equation (1-5) is the amplitude of the second input signal Vin2.

[0086] Vin1=Vm×ΔCe×Cf……(1-4) Vin2=Vm×ΔCe×Cf……(1-5) Furthermore, let's assume that the first input signal Vin1, represented by the above equation (1-4), is input to the first input terminal 241. Let's assume that the second input signal Vin2, represented by the above equation (1-5), is input to the second input terminal 242. At this time, the fully differential amplifier 24 includes an output common-mode feedback circuit 260, thereby making the first input signal Vin1 and the second input signal Vin2 in phase. Therefore, the first input signal Vin1, represented by the above equation (1-4), and the second input signal Vin2, represented by the above equation (1-5), have little effect on the difference between the first output signal Vout1 and the second output signal Vout2, i.e., Vout1-Vout2.

[0087] However, here, as described above, the capacitive sensor detection circuit 20 includes a first parasitic capacitor 51 and a second parasitic capacitor 52. Furthermore, the electrostatic capacitance of the first parasitic capacitor 51 is designated as the first parasitic capacitance Cp1. The electrostatic capacitance of the second parasitic capacitor 52 is designated as the second parasitic capacitance Cp2. The absolute value of the difference between the first parasitic capacitance Cp1 and the second parasitic capacitance Cp2 is designated as ΔCp.

[0088] Furthermore, the amplitude of the in-phase signal of the first input signal Vin1 and the second input signal Vin2 is a value related to Vm×ΔCe / Cf. Additionally, the amplitude of the difference between the first output signal Vout1 and the second output signal Vout2, using this and ΔCp, is expressed using the input amplitudes Vm, ΔCe, Cf, and ΔCp as shown in equation (1-6) below. Moreover, Vout1 in equation (1-6) below is the amplitude of the first output signal Vout1. Vout2 in equation (1-6) below is the amplitude of the second output signal Vout2.

[0089] Vout1-Vout2=Vm×ΔCe / Cf×ΔCp / Cf……(1-6) Therefore, the amplitude of the difference between the first output signal Vout1 and the second output signal Vout2 includes the value represented by the right-hand side of the above-mentioned relation (1-6). Therefore, the amplitude of the difference between the first output signal Vout1 and the second output signal Vout2, as represented by the above-mentioned relation (1-6), becomes the offset component of the detected values ​​of acceleration, pressure, etc., calculated according to the above-mentioned relation (1-3).

[0090] Furthermore, here, the amplitude of the first input signal Vin1, whose frequency and phase correspond to the frequency and phase of the modulation signal S, is expressed using the input amplitude Vm, feedback amplitude Vcnt, Cs0, Ct0, and Cf as shown in equation (1-7). The amplitude of the second input signal Vin2, whose frequency and phase correspond to the frequency and phase of the modulation signal S, is expressed using the input amplitude Vm, feedback amplitude Vcnt, Cs0, Ct0, and Cf as shown in equation (1-8). Additionally, as mentioned above, Ct0 is the electrostatic capacitance of the first capacitor 61 and the second capacitor 62. Furthermore, Vin1 in equation (1-7) is the amplitude of the first input signal Vin1. Vin2 in equation (1-8) is the amplitude of the second input signal Vin2.

[0091] Vin1=(Vm×Cs0-Vcnt×Ct0) / Cf……(1-7) Vin2=(Vm×Cs0-Vcnt×Ct0) / Cf……(1-8) Therefore, when Vm×Cs0-Vcnt×Ct0 is zero, the amplitudes of the first input signal Vin1 and the second input signal Vin2, corresponding to the frequency and phase of the modulation signal S, become zero. Therefore, even if there is a difference between Cs0 and Ct0, the offset component becomes zero. Therefore, even if there exists an absolute value ΔCe between Cs0 and the capacitances of the first capacitor Ct1 and the second capacitor Ct2, the offset component also becomes zero.

[0092] Therefore, the control unit 70 calculates the feedback amplitude Vcnt that makes Vm×Cs0-Vcnt×Ct0 zero. For this purpose, the control unit 70 includes, for example, an adder 75, a synchronous detector 80, a controller 85, a first adjustment switch 91, and a second adjustment switch 92.

[0093] Here, as described above, the first input terminal 241 is connected to the first electrode 121 and the first capacitor 61. The second input terminal 242 is connected to the second electrode 122 and the second capacitor 62. Therefore, the first input signal Vin1 and the second input signal Vin2 are signals related to the input amplitude Vm, the feedback amplitude Vcnt, Cs0, and Ct0.

[0094] Therefore, the adder 75 acquires the first input signal Vin1 and the second input signal Vin2. Furthermore, the adder 75 includes a first voltage follower circuit 751, a second voltage follower circuit 752, and a confluence section 785. Thus, the adder 75 obtains a signal related to the sum of the first input signal Vin1 and the second input signal Vin2 from the acquired first input signal Vin1 and second input signal Vin2.

[0095] Furthermore, the high-pass filter 790 of the adder 75 removes low-frequency components from the signal acquired by the adder 75 that is related to the sum of the first input signal Vin1 and the second input signal Vin2. Thus, the high-pass filter 790 removes the DC component from the signal acquired by the adder 75 that is related to the sum of the first input signal Vin1 and the second input signal Vin2.

[0096] The synchronous detector 80 demodulates the signal, which is the sum of the first input signal Vin1 and the second input signal Vin2 after the DC component has been removed by the high-pass filter 790, in accordance with the frequency and phase of the modulation signal S.

[0097] The controller 85 uses the signal demodulated by the synchronous detector 80 related to the sum of the first input signal Vin1 and the second input signal Vin2, as well as the signal from the reference power supply 795. Therefore, the controller 85 calculates the feedback amplitude Vcnt that makes the amplitude of the signal demodulated by the synchronous detector 80 related to the sum of the first input signal Vin1 and the second input signal Vin2 zero. Thus, the controller 85 calculates the feedback amplitude Vcnt that makes Vm×Cs0-Vcnt×Ct0 zero. Furthermore, the controller 85 outputs a signal having the calculated feedback amplitude Vcnt to the first adjustment switch 91.

[0098] Furthermore, the first adjustment switch 91 and the second adjustment switch 92 are turned on and off according to the modulation signal S and the inverting signal Sinv. Therefore, the frequency of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 becomes the frequency of the modulation signal S. Additionally, the phase of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 becomes the phase opposite to that of the modulation signal S, i.e., the phase of the inverting signal Sinv. A signal with an amplitude set to the feedback amplitude Vcnt, a frequency set to the same frequency as the modulation signal S, and a phase set to the opposite phase of the modulation signal S is output to the first capacitor 61 and the second capacitor 62. Therefore, the amplitudes of the first input signal Vin1 and the second input signal Vin2, whose frequencies and phases correspond to the frequency and phase of the modulation signal S, are close to zero. Thus, the offset component becomes zero.

[0099] The capacitive sensor detection circuit 20 operates as described above. Next, it will be explained that the output signal in the capacitive sensor detection circuit 20, which corresponds to the change in electrostatic capacitance, is a continuous signal with respect to time.

[0100] As described in Non-Patent Document 1, a detection circuit for a capacitive sensor that detects acceleration based on changes in electrostatic capacitance due to electrode displacement is known. Furthermore, as described in U.S. Patent No. 10,591,318, a detection circuit for a capacitive sensor that detects changes in electrostatic capacitance due to electrode displacement is known. In the detection circuits described in Non-Patent Document 1 and U.S. Patent No. 10,591,318, the input voltage of the fully differential amplifier is reset. However, during the period when the input voltage of the fully differential amplifier is reset, the signal output from the fully differential amplifier does not contain a signal corresponding to acceleration, and therefore becomes a signal discontinuous with respect to time.

[0101] The capacitive sensor detection circuit 20 of this embodiment includes a control unit 70. The control unit 70 acquires signals related to the input amplitudes Vm, Cs0, and Ct0, namely the first input signal Vin1 and the second input signal Vin2. Furthermore, the control unit 70 outputs a signal with a feedback amplitude Vcnt to the first capacitor 61 and the second capacitor 62. The feedback amplitude Vcnt makes the amplitudes of the first input signal Vin1 and the second input signal Vin2, whose frequencies and phases correspond to the frequency and phase of the modulation signal S, approach zero. Additionally, the frequency of the signal with the feedback amplitude Vcnt is set to be the same as or corresponding to the frequency of the modulation signal S. Furthermore, the phase of the signal with the feedback amplitude Vcnt is set to be opposite to the phase of the modulation signal S.

[0102] Therefore, the amplitudes of the first input signal Vin1 and the second input signal Vin2, whose frequencies and phases correspond to the frequency and phase of the modulation signal S, continuously approach zero. Thus, there is no need to set a reset period for the first input signal Vin1 and the second input signal Vin2. Therefore, the output signal from the fully differential amplifier 24, that is, the output signal corresponding to the changes in the first electrostatic capacitance Cs1 and the second electrostatic capacitance Cs2, becomes a signal that is continuous with respect to time.

[0103] Furthermore, in the detection circuit described in Non-Patent Document 1, U.S. Patent No. 10,591,318, noise is retained in each capacitor upon reset. Therefore, the detection accuracy of changes in electrostatic capacitance is reduced in the detection circuit described in Non-Patent Document 1, U.S. Patent No. 10,591,318.

[0104] In the capacitive sensor detection circuit 20 of this embodiment, the output signal corresponding to the changes in the first electrostatic capacitance Cs1 and the second electrostatic capacitance Cs2 becomes a signal that is continuous with respect to time, thus suppressing the noise held in each capacitor. Therefore, the detection accuracy of suppressing changes in electrostatic capacitance is reduced.

[0105] Furthermore, the capacitive sensor detection circuit 20 of the first embodiment also exhibits the following effects.

[0106] [1-1] The control unit 70 includes an adder 75, a synchronous detector 80, and a controller 85. As a result, the control unit 70 can easily calculate the feedback amplitude Vcnt.

[0107] [1-2] The control unit 70 has a high-pass filter 790. The high-pass filter 790 removes the DC component contained in the signal related to the sum of the first input signal Vin1 and the second input signal Vin2.

[0108] The gain adjustment of the controller 85 becomes easy through the high-pass filter 790. Therefore, the feedback amplitude Vcnt oscillation is suppressed by the controller 85.

[0109] [1-3] The addition unit 75 includes a first voltage follower circuit 751, a first filter capacitor 781, a second voltage follower circuit 752, a second filter capacitor 782, and a current confluence unit 785.

[0110] The first voltage follower circuit 751 suppresses the flow of current from the first electrode 121 to the first input terminal 241 to the control unit 70. Furthermore, the second voltage follower circuit 752 suppresses the flow of current from the second electrode 122 to the second input terminal 242 to the control unit 70. Therefore, the situation where the control unit 70 interferes with the operation of the fully differential amplifier 24 is suppressed.

[0111] [1-4] The synchronous detector 80 includes a first switch 801, a second switch 802, a third switch 803, and a fourth switch 804. The controller 85 includes a transconductance amplifier 850 for the controller and a capacitor 852 for the controller.

[0112] Therefore, it is easy to demodulate the signal related to the sum of the first input signal Vin1 and the second input signal Vin2, corresponding to the frequency and phase of the modulation signal S. Furthermore, it is easy to calculate the feedback amplitude Vcnt.

[0113] (Second Implementation) In the second embodiment, the synchronous detector 80 and the controller 85 are configured differently from those in the first embodiment. Otherwise, they are the same as in the first embodiment.

[0114] Specifically, such as Figure 8 As shown, the synchronous detector 80 includes a first switch 801 and a second switch 802, but does not include a third switch 803 and a fourth switch 804.

[0115] Furthermore, one end of the first switch 801 is connected to the confluence section 785. The first switch 801 is then switched on and off according to the inverting signal Sinv. Additionally, one end of the second switch 802 is connected to the other end of the filter resistor 787 and the positive terminal of the reference power supply 795. The second switch 802 is also switched on and off according to the modulation signal S.

[0116] Therefore, the first switch 801 and the second switch 802 are turned on and off according to the modulation signal S and the inverting signal Sinv. Thus, the signal in the confluence section 785 is demodulated in accordance with the frequency and phase of the modulation signal S. Therefore, the signal related to the sum of the first input signal Vin1 and the second input signal Vin2 is demodulated in accordance with the frequency and phase of the modulation signal S.

[0117] The controller 85 includes an operational amplifier 854 instead of a transconductance amplifier 850. In addition to a capacitor 852, the controller 85 also includes a resistor 856. The non-inverting input terminal of the operational amplifier 854 is connected to one end of the second switch 802, the other end of the filter resistor 787, and the positive terminal of the reference power supply 795. The inverting input terminal of the operational amplifier 854 is connected to the other ends of the first switch 801 and the second switch 802 via the resistor 856. Therefore, the operational amplifier 854 compares the signal, demodulated by the synchronous detector 80 and related to the sum of the first input signal Vin1 and the second input signal Vin2, with the signal from the reference power supply 795.

[0118] Furthermore, one end of the controller capacitor 852 is connected to the inverting input terminal of the controller operational amplifier 854. The other end of the controller capacitor 852 is connected to the output terminal of the controller operational amplifier 854. Therefore, the controller 85, through the controller operational amplifier 854 and the controller capacitor 852, becomes an integrator with capacitor-based feedback implemented.

[0119] Additionally, the controller 85 uses the signal demodulated by the synchronous detector 80 related to the sum of the first input signal Vin1 and the second input signal Vin2, the signal from the reference power supply 795, the controller operational amplifier 854, the controller capacitor 852, and the controller resistor 856. Therefore, the controller 85 calculates a feedback amplitude Vcnt that makes the amplitude of the signal demodulated by the synchronous detector 80 related to the sum of the first input signal Vin1 and the second input signal Vin2 zero. The controller 85 then outputs a signal having the calculated feedback amplitude Vcnt to the first adjustment switch 91.

[0120] Furthermore, the first adjustment switch 91 and the second adjustment switch 92 are turned on and off according to the modulation signal S and the inverting signal Sinv. The frequency of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 becomes the frequency of the modulation signal S. Furthermore, the phase of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 becomes the phase opposite to that of the modulation signal S, i.e., the phase of the inverting signal Sinv. A signal with amplitude set to the feedback amplitude Vcnt, frequency set to the same frequency as the modulation signal S, and phase set to the opposite phase of the modulation signal S is output to the first capacitor 61 and the second capacitor 62. Therefore, the amplitudes of the first input signal Vin1 and the second input signal Vin2, whose frequencies and phases correspond to the frequency and phase of the modulation signal S, are close to zero. Thus, the offset component becomes zero.

[0121] The capacitive sensor detection circuit 20 of the second embodiment is configured as described above. In this second embodiment, it also achieves the same effect as the first embodiment.

[0122] (Third Implementation) In the third embodiment, such as Figure 9 As shown, the capacitive sensor detection circuit 20 also includes a first adjustment capacitor 611 and a second adjustment capacitor 622. Otherwise, it is the same as in the first embodiment.

[0123] One end of the first adjusting capacitor 611 is connected between the first electrode 121 and the first input terminal 241. The other end of the first adjusting capacitor 611 is connected to the signal generation unit 22.

[0124] One end of the second adjusting capacitor 622 is connected between the second electrode 122 and the second input terminal 242. The other end of the second adjusting capacitor 622 is connected to the signal generation unit 22.

[0125] In addition, the signal generation unit 22 outputs the inverted signal Sinv to the first adjustment capacitor 611 and the second adjustment capacitor 622.

[0126] The capacitive sensor detection circuit 20 of the third embodiment is configured as described above. In this third embodiment, it achieves the same effects as the first embodiment. Furthermore, the third embodiment also achieves the effects described below.

[0127] [2] The capacitive sensor detection circuit 20 also includes a first adjustment capacitor 611 and a second adjustment capacitor 622. In addition, the signal generation unit 22 outputs an inverted signal Sinv to the first adjustment capacitor 611 and the second adjustment capacitor 622.

[0128] The current between the first electrode 121 and the first input terminal 241 is adjusted via the first adjusting capacitor 611. Therefore, when the control unit 70 outputs a signal with feedback amplitude Vcnt to the first capacitor 61, the increase in current flowing from the control unit 70 to the first capacitor 61 is suppressed. Similarly, the current between the second electrode 122 and the second input terminal 242 is adjusted via the second adjusting capacitor 622. Therefore, when the control unit 70 outputs a signal with feedback amplitude Vcnt to the first capacitor 61, the increase in current flowing from the control unit 70 to the first capacitor 61 is suppressed. Thus, the current consumption of the control unit 70 is suppressed.

[0129] (Fourth Implementation) In the fourth embodiment, the configuration of the fully differential amplifier 24 and the processing of the control unit 70 differ from those in the first embodiment. Otherwise, they are the same as in the first embodiment.

[0130] The fully differential amplifier 24 includes Figure 10 The input common-mode feedback circuit 270 shown is used instead of the output common-mode feedback circuit 260. Therefore, the voltage controlled to be half of the voltage related to the sum of the first input signal Vin1 and the second input signal Vin2, i.e., (Vin1+Vin2) / 2, becomes the predetermined voltage. Furthermore, the predetermined voltage is set through experiments, simulations, etc.

[0131] The fully differential amplifier 24 includes an input common-mode feedback circuit 270. Therefore, in the fourth embodiment, unlike the first embodiment, the first input signal Vin1, whose frequency and phase correspond to the frequency and phase of the modulation signal S, is not expressed as the above-described relationship (1-7). Furthermore, the second input signal Vin2, whose frequency and phase correspond to the frequency and phase of the modulation signal S, is not expressed as the above-described relationship (1-8).

[0132] In contrast, the first output signal Vout1, whose frequency and phase correspond to the frequency and phase of the modulated signal S, is represented by the input amplitude Vm, feedback amplitude Vcnt, Cs0, Ct0, and Cf as shown in Equation (2-1). Furthermore, the second output signal Vout2, whose frequency and phase correspond to the frequency and phase of the modulated signal S, is represented by the input amplitude Vm, feedback amplitude Vcnt, Cs0, Ct0, and Cf as shown in Equation (2-2).

[0133] Vout1=(Vm×Cs0-Vcnt×Ct0) / Cf……(2-1) Vout2=(Vm×Cs0-Vcnt×Ct0) / Cf……(2-2) Therefore, when Vm×Cs0-Vcnt×Ct0 is zero, the first output signal Vout1 and the second output signal Vout2, which correspond to the frequency and phase of the modulation signal S, become zero, and thus the offset component becomes zero.

[0134] Therefore, the control unit 70 calculates Vcnt that makes Vm×Cs0-Vcnt×Ct0 zero. For this purpose, for example, as... Figure 11 and Figure 12 As shown, the control unit 70 includes an adder 75, a synchronous detector 80, a controller 85, a first adjustment switch 91, and a second adjustment switch 92.

[0135] Here, as described above, the first input terminal 241 is connected to the first electrode 121 and the first capacitor 61. The second input terminal 242 is connected to the second electrode 122 and the second capacitor 62. Therefore, the first input signal Vin1 and the second input signal Vin2 are signals related to the input amplitude Vm, the feedback amplitude Vcnt, Cs0, and Ct0. Furthermore, the first output terminal 251 outputs signals corresponding to the first input signal Vin1 and the second input signal Vin2. The second output terminal 252 outputs signals corresponding to the first input signal Vin1 and the second input signal Vin2. Therefore, the first output signal Vout1 and the second output signal Vout2 are signals related to the input amplitude Vm, the feedback amplitude Vcnt, Cs0, and Ct0.

[0136] Therefore, the adder 75 acquires the first output signal Vout1 and the second output signal Vout2. Furthermore, the adder 75 includes a first voltage follower circuit 751, a second voltage follower circuit 752, and a confluencer 785. Thus, the adder 75 acquires a signal related to the sum of the first output signal Vout1 and the second output signal Vout2 from the acquired first output signal Vout1 and second output signal Vout2.

[0137] Furthermore, the high-pass filter 790 of the adder 75 removes low-frequency components from the signal acquired by the adder 75 that is related to the sum of the first output signal Vout1 and the second output signal Vout2. Thus, the high-pass filter 790 removes the DC component from the signal acquired by the adder 75 that is related to the sum of the first output signal Vout1 and the second output signal Vout2.

[0138] The synchronous detector 80 demodulates the signal, which has had its DC component removed by the high-pass filter 790 and is related to the sum of the first output signal Vout1 and the second output signal Vout2, in accordance with the frequency and phase of the modulation signal S.

[0139] The controller 85 uses the signal demodulated by the synchronous detector 80 related to the sum of the first output signal Vout1 and the second output signal Vout2, as well as the signal from the reference power supply 795. Therefore, the controller 85 calculates the feedback amplitude Vcnt that makes the amplitude of the signal demodulated by the synchronous detector 80 related to the sum of the first output signal Vout1 and the second output signal Vout2 zero. Thus, it calculates the feedback amplitude Vcnt that makes Vm×Cs0-Vcnt×Ct0 zero. Furthermore, the controller 85 outputs a signal having the calculated feedback amplitude Vcnt to the first adjustment switch 91.

[0140] Furthermore, the first adjustment switch 91 and the second adjustment switch 92 are turned on and off according to the modulation signal S and the inverting signal Sinv. Therefore, the frequency of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 becomes the frequency of the modulation signal S. Additionally, the phase of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 becomes the phase opposite to that of the modulation signal S, i.e., the phase of the inverting signal Sinv. A signal with amplitude set to the feedback amplitude Vcnt, frequency set to the same frequency as the modulation signal S, and phase set to the opposite phase of the modulation signal S is output to the first capacitor 61 and the second capacitor 62. Therefore, the amplitudes of the first output signal Vout1 and the second output signal Vout2, whose frequencies and phases correspond to those of the modulation signal S, are close to zero. Thus, the offset component becomes zero.

[0141] The capacitive sensor detection circuit 20 of the fourth embodiment is configured as described above, and the control unit 70 performs the processing. In this fourth embodiment, it also achieves the same effect as the first embodiment.

[0142] (Fifth implementation method) In the fifth embodiment, the synchronous detector 80 and the controller 85 are configured differently from those in the fourth embodiment. Otherwise, they are the same as in the fourth embodiment.

[0143] The fifth embodiment is a combination of the second and fourth embodiments. Specifically, as follows: Figure 13 As shown, the synchronous detector 80 includes a first switch 801 and a second switch 802, but does not include a third switch 803 and a fourth switch 804.

[0144] Furthermore, one end of the first switch 801 is connected to the confluence section 785. The first switch 801 is then switched on and off according to the inverting signal Sinv. Additionally, one end of the second switch 802 is connected to the other end of the filter resistor 787 and the positive terminal of the reference power supply 795. The second switch 802 is also switched on and off according to the modulation signal S.

[0145] Therefore, the first switch 801 and the second switch 802 are turned on and off according to the modulation signal S and the inverting signal Sinv. Thus, the signal in the confluence section 785 is demodulated in accordance with the frequency and phase of the modulation signal S. Therefore, the signal related to the sum of the first output signal Vout1 and the second output signal Vout2 is demodulated in accordance with the frequency and phase of the modulation signal S.

[0146] The controller 85 includes an operational amplifier 854 instead of a transconductance amplifier 850. In addition to a capacitor 852, the controller 85 also includes a resistor 856. The non-inverting input terminal of the operational amplifier 854 is connected to one end of the second switch 802, the other end of the filter resistor 787, and the positive terminal of the reference power supply 795. The inverting input terminal of the operational amplifier 854 is connected to the other ends of the first switch 801 and the second switch 802 via the resistor 856. Therefore, the operational amplifier 854 compares the signal demodulated by the synchronous detector 80, which is related to the sum of the first output signal Vout1 and the second output signal Vout2, with the signal from the reference power supply 795.

[0147] Furthermore, one end of the controller capacitor 852 is connected to the inverting input terminal of the controller operational amplifier 854. The other end of the controller capacitor 852 is connected to the output terminal of the controller operational amplifier 854. Therefore, the controller 85, through the controller operational amplifier 854 and the controller capacitor 852, becomes an integrator with capacitor-based feedback implemented.

[0148] Additionally, the controller 85 uses the signal related to the sum of the first output signal Vout1 and the second output signal Vout2, which is demodulated by the synchronous detector 80; a signal from the reference power supply 795; a controller operational amplifier 854; a controller capacitor 852; and a controller resistor 856. Therefore, the controller 85 calculates a feedback amplitude Vcnt that makes the amplitude of the signal demodulated by the synchronous detector 80 related to the sum of the first output signal Vout1 and the second output signal Vout2 zero. The controller 85 then outputs a signal having the calculated feedback amplitude Vcnt to the first adjustment switch 91.

[0149] Furthermore, the first adjustment switch 91 and the second adjustment switch 92 are turned on and off according to the modulation signal S and the inverting signal Sinv. The frequency of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 becomes the frequency of the modulation signal S. Furthermore, the phase of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 becomes the phase opposite to that of the modulation signal S, i.e., the phase of the inverting signal Sinv. A signal with amplitude set to the feedback amplitude Vcnt, frequency set to the same frequency as the modulation signal S, and phase set to the opposite phase of the modulation signal S is output to the first capacitor 61 and the second capacitor 62. Therefore, the amplitudes of the first output signal Vout1 and the second output signal Vout2, whose frequencies and phases correspond to those of the modulation signal S, are close to zero. Thus, the offset component becomes zero.

[0150] The capacitive sensor detection circuit 20 of the fifth embodiment is configured as described above. In this fifth embodiment, it also achieves the same effect as in the fourth embodiment.

[0151] (Sixth Implementation Method) In the sixth embodiment, such as Figure 14 As shown, the capacitive sensor detection circuit 20 also includes a first adjustment capacitor 611 and a second adjustment capacitor 622. Otherwise, it is the same as in the fourth embodiment.

[0152] The sixth embodiment is a combination of the third and fourth embodiments. Specifically, one end of the first adjusting capacitor 611 is connected between the first electrode 121 and the first input terminal 241. The other end of the first adjusting capacitor 611 is connected to the signal generation unit 22.

[0153] One end of the second adjusting capacitor 622 is connected between the second electrode 122 and the second input terminal 242. The other end of the second adjusting capacitor 622 is connected to the signal generation unit 22. In addition, the signal generation unit 22 outputs an inverted signal Sinv to the first adjusting capacitor 611 and the second adjusting capacitor 622.

[0154] The capacitive sensor detection circuit 20 of the sixth embodiment is configured as described above. In this sixth embodiment, it also has the same effect as in the fourth embodiment. Furthermore, in the sixth embodiment, it has the same effect as described above [2] in the third embodiment.

[0155] (Other implementation methods) This disclosure is not limited to the above-described embodiments, and appropriate modifications can be made to the above-described embodiments. In addition, in each of the above embodiments, the elements constituting the embodiments are not necessarily essential, except where they are specifically stated to be necessary or are clearly considered to be necessary in principle.

[0156] The control unit and method described in this disclosure can also be implemented by a dedicated computer, which is provided by a processor and memory programmed to perform one or more functions embodied in a computer program. Alternatively, the control unit and method described in this disclosure can also be implemented by a dedicated computer provided by a processor composed of one or more dedicated hardware logic circuits. Alternatively, the control unit and method described in this disclosure can also be implemented by one or more dedicated computers composed of a combination of a processor and memory programmed to perform one or more functions and a processor composed of one or more hardware logic circuits. In addition, the computer program can also be stored as instructions executed by the computer on a computer-readable non-transferable tangible recording medium.

[0157] In each of the embodiments, the first voltage follower circuit 751 has one transistor. However, the number of transistors in the first voltage follower circuit 751 is not limited to one, and may be two or more. Furthermore, the second voltage follower circuit 752 has one transistor. However, the number of transistors in the second voltage follower circuit 752 is not limited to one, and may be two or more.

[0158] In each of the embodiments, the transistors of the first voltage follower circuit 751 and the second voltage follower circuit 752 are MOSFETs. However, the transistors of the first voltage follower circuit 751 and the second voltage follower circuit 752 are not limited to MOSFETs; for example, they can also be bipolar transistors.

[0159] In each of the embodiments, the first electrostatic capacitance Cs1 when the movable electrode 100 is not displaced is the same as the second electrostatic capacitance Cs2 when the movable electrode 100 is not displaced, which is Cs0. However, the first electrostatic capacitance Cs1 when the movable electrode 100 is not limited to being the same as the second electrostatic capacitance Cs2 when the movable electrode 100 is not displaced. The first electrostatic capacitance Cs1 when the movable electrode 100 is not displaced can also be different from the second electrostatic capacitance Cs2 when the movable electrode 100 is not displaced.

[0160] In each of the embodiments described, the first feedback capacitor Cf1 is the same as the second feedback capacitor Cf2, which is Cf. However, the first feedback capacitor Cf1 is not limited to being the same as the second feedback capacitor Cf2. The first feedback capacitor Cf1 can also be different from the second feedback capacitor Cf2.

[0161] In each of the embodiments described, the first resistor Rf1 and the second resistor Rf2 are the same, which is Rf. However, the first resistor Rf1 is not limited to being the same as the second resistor Rf2. The first resistor Rf1 can also be different from the second resistor Rf2.

[0162] In each of the embodiments, the high-pass filter 790 includes a filter resistor 787. The high-pass filter 790 may also include a switched capacitor instead of the filter resistor 787.

[0163] In each embodiment, the first adjustment switch 91 is turned on and off according to the inverted signal Sinv. The second adjustment switch 92 is turned on and off according to the modulation signal S. The signal that turns the first adjustment switch 91 on and off only needs to be a signal whose frequency is the same as the frequency of the modulation signal S and the inverted signal Sinv, and whose phase is the same as the phase of the inverted signal Sinv. Similarly, the signal that turns the second adjustment switch 92 on and off only needs to be a signal whose frequency is the same as the frequency of the modulation signal S and the inverted signal Sinv, and whose phase is the same as the phase of the modulation signal S.

[0164] In the first, third, fourth, and sixth embodiments, the first switch 801 is turned on and off according to the modulation signal S. The second switch 802 is turned on and off according to the inverted signal Sinv. The third switch 803 is turned on and off according to the modulation signal S. The fourth switch 804 is turned on and off according to the inverted signal Sinv. The signal that turns the first switch 801 on and off can be any signal whose frequency is the same as the frequency of the modulation signal S and the inverted signal Sinv, and whose phase is the same as the phase of the modulation signal S. The signal that turns the second switch 802 on and off can be any signal whose frequency is the same as the frequency of the modulation signal S and the inverted signal Sinv, and whose phase is the same as the phase of the inverted signal Sinv. The signal that turns the third switch 803 on and off can be any signal whose frequency is the same as the frequency of the modulation signal S and the inverted signal Sinv, and whose phase is the same as the phase of the modulation signal S and the inverted signal Sinv. The signal that turns the fourth switch 804 on and off can be any signal whose frequency is the same as the frequency of the modulation signal S and the inverted signal Sinv, and whose phase is the same as the phase of the inverted signal Sinv.

[0165] In the second and fifth embodiments, the first switch 801 is turned on and off according to the inverted signal Sinv. The second switch 802 is turned on and off according to the modulation signal S. The signal that turns the first switch 801 on and off only needs to be a signal whose frequency is the same as the frequency of the modulation signal S and the inverted signal Sinv, and whose phase is the same as the phase of the inverted signal Sinv. Similarly, the signal that turns the second switch 802 on and off only needs to be a signal whose frequency is the same as the frequency of the modulation signal S and the inverted signal Sinv, and whose phase is the same as the phase of the modulation signal S.

[0166] In the second and fifth embodiments, the controller 85 includes a controller resistor 856. The controller 85 may also include a switched capacitor instead of the controller resistor 856.

[0167] The various implementation methods described can also be combined appropriately.

Claims

1. A capacitive sensor detection circuit used in a sensor element, the sensor element comprising: a displaceable movable electrode; a first electrode that outputs a signal corresponding to a change in a first electrostatic capacitance between the first electrode and the movable electrode, which varies according to the displacement of the movable electrode; and a second electrode that outputs a signal corresponding to a change in a second electrostatic capacitance between the second electrode and the movable electrode, which varies according to the displacement of the movable electrode, the capacitive sensor detection circuit being characterized in that it comprises: The signal generation unit outputs a modulated signal to the movable electrode, which has an input amplitude, frequency and phase. A fully differential amplifier has a first input terminal connected to the first electrode, a second input terminal connected to the second electrode, a first output terminal that outputs a signal corresponding to the signal input to the first input terminal (i.e., a first input signal) and the signal input to the second input terminal (i.e., a second input signal), and a second output terminal that outputs a signal corresponding to the first input signal and the second input signal. A first feedback capacitor is connected to the first input terminal and the first output terminal; The second feedback capacitor is connected to the second input terminal and the second output terminal; The calculation unit calculates a value related to the displacement of the movable electrode based on the signal output from the first output terminal (i.e., the first output signal) and the signal output from the second output terminal (i.e., the second output signal). A first capacitor is connected to the node between the first electrode and the first input terminal; A second capacitor is connected to the node between the second electrode and the second input terminal; as well as The control unit acquires the first input signal and the second input signal, and outputs the following signal to the first capacitor and the second capacitor: the signal has a feedback amplitude that makes the amplitude of the first input signal and the second input signal, whose frequency and phase correspond to the frequency and phase of the modulation signal, close to zero; the frequency of the signal corresponds to the frequency of the modulation signal; and the phase of the signal is opposite to the phase of the modulation signal.

2. The capacitive sensor detection circuit according to claim 1, characterized in that, The control unit has: The adder acquires a signal related to the sum of the first input signal and the second input signal; The synchronous detector demodulates the signal related to the sum of the first input signal and the second input signal in accordance with the frequency and phase of the modulated signal; as well as The controller calculates the feedback amplitude based on a signal related to the sum of the first input signal and the second input signal after demodulation by the synchronous detector, and a signal from the reference power supply.

3. The capacitive sensor detection circuit according to claim 2, characterized in that, The control unit includes a high-pass filter that removes the DC component from the signal related to the sum of the first input signal and the second input signal. The synchronous detector demodulates the signal related to the sum of the first input signal and the second input signal, after the DC component has been removed by the high-pass filter.

4. The capacitive sensor detection circuit according to claim 2, characterized in that, The addition unit includes: A first voltage follower circuit acquires the first input signal and outputs a signal corresponding to the first input signal; The first filter capacitor is connected to the output terminal of the first voltage follower circuit; The second voltage follower circuit acquires the second input signal and outputs a signal corresponding to the second input signal; The second filter capacitor is connected to the output terminal of the second voltage follower circuit. as well as The confluence section, connected to the first filter capacitor and the second filter capacitor, makes the signal the sum of the first input signal and the second input signal.

5. The capacitive sensor detection circuit according to claim 2, characterized in that, The synchronous detector includes: The first switch is turned on and off according to a signal whose frequency is the same as the frequency of the modulation signal and whose phase is the same as the phase of the modulation signal; The second switch is turned on and off based on a signal whose frequency is the same as the frequency of the modulation signal and whose phase is opposite to the phase of the modulation signal. The third switch is turned on and off based on a signal whose frequency and phase are the same as the modulation signal; and The fourth switch is turned on and off based on a signal whose frequency is the same as the frequency of the modulation signal but whose phase is opposite to the phase of the modulation signal. The controller includes: A transconductance amplifier, wherein its non-inverting input terminal is connected to the second switch and the third switch, and its inverting input terminal is connected to the first switch, the fourth switch, and the reference power supply; and A capacitor is connected to the output terminal of the transconductance amplifier and to ground.

6. The capacitive sensor detection circuit according to claim 2, characterized in that, The synchronous detector includes: A first switch, which is turned on and off according to a signal whose frequency is the same as the frequency of the modulation signal and whose phase is opposite to the phase of the modulation signal; and The second switch is turned on and off based on a signal whose frequency and phase are the same as the modulation signal. The controller includes: A resistor, which is connected to the first switch and the second switch; An operational amplifier, wherein its inverting input terminal is connected to the resistor and its non-inverting input terminal is connected to the reference power supply; and A capacitor is connected to the inverting input terminal and the output terminal of the operational amplifier.

7. The capacitive sensor detection circuit according to claim 1, characterized in that, The capacitive sensor detection circuit includes: A first adjusting capacitor is connected to the node between the first electrode and the first input terminal; as well as A second adjusting capacitor is connected at the node between the second electrode and the second input terminal. The signal generation unit outputs a signal to the first adjustment capacitor and the second adjustment capacitor. The signal has the same amplitude as the input amplitude, the same frequency as the modulation signal, and the opposite phase to the modulation signal.

8. The capacitive sensor detection circuit according to any one of claims 1 to 7, characterized in that, The fully differential amplifier includes an output common-mode feedback circuit that makes half of the voltage associated with the sum of the first output signal and the second output signal close to a predetermined voltage.

9. A capacitive sensor detection circuit used in a sensor element comprising: a displaceable movable electrode; a first electrode outputting a signal corresponding to a change in a first electrostatic capacitance between the first electrode and the movable electrode, which varies according to the displacement of the movable electrode; and a second electrode outputting a signal corresponding to a change in a second electrostatic capacitance between the second electrode and the movable electrode, which varies according to the displacement of the movable electrode, wherein the capacitive sensor detection circuit is characterized by comprising: The signal generation unit outputs a modulated signal to the movable electrode, which has an input amplitude, frequency and phase. A fully differential amplifier has a first input terminal connected to the first electrode, a second input terminal connected to the second electrode, a first output terminal that outputs a signal corresponding to the signal input to the first input terminal (i.e., a first input signal) and the signal input to the second input terminal (i.e., a second input signal), and a second output terminal that outputs a signal corresponding to the first input signal and the second input signal. A first feedback capacitor is connected to the first input terminal and the first output terminal; The second feedback capacitor is connected to the second input terminal and the second output terminal; The calculation unit calculates a value related to the displacement of the movable electrode based on the signal output from the first output terminal (i.e., the first output signal) and the signal output from the second output terminal (i.e., the second output signal). A first capacitor is connected to the node between the first electrode and the first input terminal; A second capacitor is connected to the node between the second electrode and the second input terminal; as well as The control unit acquires the first output signal and the second output signal, and outputs the following signal to the first capacitor and the second capacitor: the signal has a feedback amplitude that makes the amplitude of the first output signal and the second output signal, whose frequency and phase correspond to the frequency and phase of the modulation signal, close to zero; the frequency of the signal corresponds to the frequency of the modulation signal; and the phase of the signal is opposite to the phase of the modulation signal.

10. The capacitive sensor detection circuit according to claim 9, characterized in that, The control unit has: The adder acquires a signal related to the sum of the first output signal and the second output signal; The synchronous detector demodulates the signal related to the sum of the first output signal and the second output signal in accordance with the frequency and phase of the modulated signal; as well as The controller calculates the feedback amplitude based on a signal related to the sum of the first output signal and the second output signal after demodulation by the synchronous detector, and a signal from the reference power supply.

11. The capacitive sensor detection circuit according to claim 10, characterized in that, The control unit includes a high-pass filter that removes the DC component from the signal related to the sum of the first output signal and the second output signal. The synchronous detector demodulates the signal related to the sum of the first output signal and the second output signal after the DC component has been removed by the high-pass filter.

12. The capacitive sensor detection circuit according to claim 10, characterized in that, The addition unit includes: A first voltage follower circuit acquires the first output signal and outputs a signal corresponding to the first output signal; The first filter capacitor is connected to the output terminal of the first voltage follower circuit; The second voltage follower circuit acquires the second output signal and outputs a signal corresponding to the second output signal; The second filter capacitor is connected to the output terminal of the second voltage follower circuit. as well as The confluence section, connected to the first filter capacitor and the second filter capacitor, makes the signal the sum of the first output signal and the second output signal.

13. The capacitive sensor detection circuit according to claim 10, characterized in that, The synchronous detector includes: The first switch is turned on and off according to a signal whose frequency is the same as the frequency of the modulation signal and whose phase is the same as the phase of the modulation signal; The second switch is turned on and off based on a signal whose frequency is the same as the frequency of the modulation signal and whose phase is opposite to the phase of the modulation signal. The third switch is turned on and off based on a signal whose frequency and phase are the same as the modulation signal; and The fourth switch is turned on and off based on a signal whose frequency is the same as the frequency of the modulation signal but whose phase is opposite to the phase of the modulation signal. The controller includes: A transconductance amplifier, wherein its non-inverting input terminal is connected to the second switch and the third switch, and its inverting input terminal is connected to the first switch, the fourth switch, and the reference power supply; and A capacitor is connected to the output terminal of the transconductance amplifier and to ground.

14. The capacitive sensor detection circuit according to claim 10, characterized in that, The synchronous detector includes: A first switch, which is turned on and off according to a signal whose frequency is the same as the frequency of the modulation signal and whose phase is opposite to the phase of the modulation signal; and The second switch is turned on and off based on a signal whose frequency and phase are the same as the modulation signal. The controller includes: A resistor, which is connected to the first switch and the second switch; An operational amplifier, wherein its inverting input terminal is connected to the resistor and its non-inverting input terminal is connected to the reference power supply; and A capacitor is connected to the inverting input terminal and the output terminal of the operational amplifier.

15. The capacitive sensor detection circuit according to claim 9, characterized in that, The capacitive sensor detection circuit includes: A first adjusting capacitor is connected to the node between the first electrode and the first input terminal; as well as A second adjusting capacitor is connected at the node between the second electrode and the second input terminal. The signal generation unit outputs a signal to the first adjustment capacitor and the second adjustment capacitor. The signal has the same amplitude as the input amplitude, the same frequency as the modulation signal, and the opposite phase to the modulation signal.

16. The capacitive sensor detection circuit according to any one of claims 9 to 15, characterized in that, The fully differential amplifier includes an input common-mode feedback circuit that makes half of the voltage associated with the sum of the first input signal and the second input signal close to a predetermined voltage.

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