Analog-to-digital conversion device and analog-to-digital conversion method
By resetting multiple capacitors in the capacitor array separately, the problem of instantaneous high current during the reset of the cyclic asymptotic analog-to-digital converter is solved, thereby improving the stability and performance of the converter.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- REALTEK SEMICON CORP
- Filing Date
- 2024-11-20
- Publication Date
- 2026-05-22
AI Technical Summary
Existing cyclic asymptotic analog-to-digital converters generate a large instantaneous current when resetting the capacitor array, which affects the converter's performance.
By resetting multiple capacitors in the capacitor array of the analog-to-digital converter separately, the simultaneous resetting of multiple capacitors is avoided, thereby reducing instantaneous high current.
This effectively avoids the generation of instantaneous high current, improving the stability and performance of the analog-to-digital converter.
Smart Images
Figure CN122073473A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to an analog-to-digital conversion apparatus and an analog-to-digital conversion method, and more particularly to an analog-to-digital conversion apparatus and an analog-to-digital conversion method for avoiding instantaneous high current. Background Technology
[0002] Analog-to-digital converters (ADCs) are commonly used in electronic devices to convert analog signals into digital signals that the devices can process. A successful approximation register analog-to-digital converter (SAR ADC) is a common type of ADC. In a SAR ADC, the capacitor array is used to store the input signal, and then the digital signal is generated through the coordinated operation of its comparator and logic control circuitry.
[0003] After the conversion process is complete, the cyclic asymptotic analog-to-digital converter (CBADC) needs to reset the capacitor array in order to execute the next conversion process. However, the existing CBADC reset method resets multiple capacitors in the capacitor array simultaneously, which may cause a large instantaneous current, thereby affecting the CBADC. Summary of the Invention
[0004] In view of the shortcomings of the prior art, one of the objectives of this disclosure is to provide an analog-to-digital conversion apparatus and an analog-to-digital conversion method to improve the shortcomings of the prior art.
[0005] In some embodiments, the analog-to-digital converter includes a switch, a capacitor array, a comparator, and logic control circuitry. The switch is configured to sample at least one input signal based on a sampled signal. The capacitor array includes multiple capacitors for storing at least one input signal. The comparator is configured to generate a comparison result based on the at least one input signal stored in the multiple capacitors of the capacitor array. The logic control circuitry is configured to reset the multiple capacitors respectively based on a conversion end signal or a sampled signal.
[0006] In some implementations, the analog-to-digital conversion method includes the following steps: a switch samples at least one input signal based on a sampling signal; a plurality of capacitors in a capacitor array store at least one input signal; a comparator generates a comparison result based on the at least one input signal stored in the plurality of capacitors in the capacitor array; and a logic control circuit resets the plurality of capacitors respectively based on a conversion end signal or a sampling signal.
[0007] The technical means embodied in the embodiments of this disclosure can improve at least one of the shortcomings of the prior art. The analog-to-digital conversion apparatus and analog-to-digital conversion method of this disclosure can avoid the instantaneous large current caused by resetting multiple capacitors simultaneously by resetting multiple capacitors of the capacitor array separately.
[0008] The features, implementation, and effects of this disclosure are described in detail below with reference to the accompanying drawings. Attached Figure Description
[0009] Figure 1 A schematic diagram of an analog-to-digital converter is provided according to some embodiments of this disclosure;
[0010] Figure 2 A flowchart illustrating an analog-to-digital conversion method according to some embodiments of this disclosure is provided.
[0011] Figure 3 A timing diagram of an analog-to-digital converter is shown according to some embodiments of this disclosure;
[0012] Figure 4 A timing diagram of an analog-to-digital converter is shown according to some embodiments of this disclosure;
[0013] Figure 5 A timing diagram of an analog-to-digital converter is shown according to some embodiments of this disclosure;
[0014] Figure 6 A timing diagram of an analog-to-digital converter is shown according to some embodiments of this disclosure;
[0015] Figure 7 A timing diagram of an analog-to-digital converter is shown according to some embodiments of this disclosure;
[0016] Figure 8 A timing diagram of an analog-to-digital converter is shown according to some embodiments of this disclosure;
[0017] Figure 9 A timing diagram of an analog-to-digital converter is shown according to some embodiments of this disclosure;
[0018] Figure 10 A timing diagram of an analog-to-digital converter is shown according to some embodiments of this disclosure;
[0019] Figure 11 A schematic diagram of an analog-to-digital converter is provided according to some embodiments of this disclosure;
[0020] Figure 12 To illustrate a method according to some embodiments of this disclosure, such as Figure 11A schematic diagram of the asynchronous controller of the analog-to-digital converter shown; and
[0021] Figure 13 A timing diagram of an asynchronous controller is drawn according to some embodiments of this disclosure. Detailed Implementation
[0022] All terms used herein have their ordinary meanings. The definitions of the terms above in commonly used dictionaries, and examples of the use of any term discussed herein, are merely illustrative and should not be construed as limiting the scope or meaning of this disclosure. Similarly, this disclosure is not limited to the various embodiments shown in this specification.
[0023] As used herein, “coupled” or “connected” can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or acting on each other. As used herein, the term “circuit” can be a device consisting of at least one transistor and / or at least one active or passive component connected in a certain manner to process signals.
[0024] As used herein, the term "and / or" includes any combination of one or more of the listed related items. The terms first, second, third, etc., are used herein to describe and distinguish the individual components. Therefore, a first component may also be referred to as a second component without departing from the intent of this disclosure. For ease of understanding, similar components in the figures will be designated with the same reference numerals.
[0025] To address the problem of instantaneous high current caused by simultaneously resetting multiple capacitors in a capacitor array in the prior art, this disclosure proposes an analog-to-digital conversion device and an analog-to-digital conversion method, which are detailed below.
[0026] Figure 1 A schematic diagram of an analog-to-digital converter 100 is provided according to some embodiments of this disclosure. As shown, the analog-to-digital converter 100 includes a switch 110, a capacitor array 120, a comparator 130, a logic control circuit 140, a switch 150, and a switch 160. Switch 110 is coupled to the capacitor array 120 and the logic control circuit 140. The capacitor array 120 is coupled to the comparator 130. The comparator 130 is coupled to the logic control circuit 140. The logic control circuit 140 is coupled to switches 150 and 160.
[0027] To make the operation of the analog-to-digital converter 100 easier to understand, please refer to the following: Figure 2 and Figure 3 , Figure 2 A flowchart of an analog-to-digital conversion method 200 is provided according to some embodiments of this disclosure. Figure 3A timing diagram of an analog-to-digital converter 100 is provided according to some embodiments of this disclosure.
[0028] Please see Figure 2 Step 210 involves the switch sampling at least one input signal based on the sampling signal. For example, please refer to... Figure 1 , 3 Switch 110 samples at least one input signal Vip and Vin based on the high-level sampling signal Clks.
[0029] Please see Figure 2 Step 220 involves storing at least one input signal using multiple capacitors in the capacitor array. For example, please refer to... Figure 1 , 3 The capacitor array 120 has multiple capacitors C1 to C10 that store at least one input signal Vip and Vin. In some embodiments, each of the multiple capacitors C1 to C10 may include a pair of capacitors used to store one bit of the input signal Vip and Vin. For example, capacitor C1 includes a pair of capacitors used to store one bit of the input signal Vip and Vin.
[0030] Please see Figure 2 Step 230 involves the comparator generating a comparison result based on at least one input signal stored in the capacitor array's plurality of capacitors. For example, please refer to... Figure 1 , 3 The comparator 130 compares at least one input signal Vip and Vin stored in the capacitors C1 to C10 of the capacitor array 120 according to the enable signal Clkc, thereby generating a comparison result. Subsequently, the comparison result is transmitted to the logic control circuit 140, which generates data B1 to B10 based on the comparison result and transmits the data B1 to B10 to the digital signal processing device (not shown) for subsequent signal processing.
[0031] Please see Figure 2 In step 240, the logic control circuit resets multiple capacitors individually based on the conversion end signal or the sampling signal. For example, please refer to... Figure 1 , 3The logic control circuit 140 resets multiple capacitors C1 to C10 respectively based on the high-level transition end signal EOFh. Specifically, capacitor C1 in the capacitor array 120 is used to store at least one bit of the input signals Vip and Vin (e.g., bit signal Vcap_p / n). <1> Capacitor C2 is used to store at least one input signal Vip and Vin, and another signal (such as the bit signal Vcap_p / n). <2> And so on. Overall, the logic control circuit 140 resets capacitor C1 at reset time Treset1, capacitor C2 at reset time Treset2, and so on, based on the high-level transition end signal EOFh. Finally, the logic control circuit 140 resets capacitor C10 at reset time Treset10. It should be noted that the bit signal Vcap_p / n stored in capacitor C1 after the reset is... <1> It can be 0 or 1, depending on the design requirements of the analog-to-digital converter 100. Similarly, the bit signal Vcap_p / n stored in the reset capacitor C2... <2> It can be 0 or 1, and so on.
[0032] In another embodiment, please refer to Figure 1 , 4 The logic control circuit 140 resets multiple capacitors C1 to C10 respectively based on the high-level sampling signal Clksh. Specifically, capacitor C1 in the capacitor array 120 is used to store at least one bit of the input signals Vip and Vin (e.g., the bit signal Vcap_p / n). <1> Capacitor C2 is used to store at least one input signal Vip and Vin, and another signal (such as the bit signal Vcap_p / n). <2> And so on. Overall, the logic control circuit 140 resets capacitor C1 at reset time Treset1 based on the high-level sampling signal Clksh, resets capacitor C2 at reset time Treset2, and so on, finally resetting capacitor C10 at reset time Treset10.
[0033] It should be noted that, in Figure 4 In the embodiment, the bit signal Vcap_p / n stored in the reset capacitor C1 <1> It can be 0 or 1, depending on the design requirements of the analog-to-digital converter 100. Similarly, the bit signal Vcap_p / n stored in the reset capacitor C2... <2> It can be 0 or 1, and so on. Furthermore, the logic control circuit 140 is used to reset the sampling signal Clksh of the multiple capacitors C1 to C10 to be the sampling signal Clksh for the next conversion procedure. For example, in Figure 2In step 210, switch 110 samples at least one input signal Vip and Vin according to the sampling signal Clks of the current conversion program. When the current conversion program ends and the next conversion program begins, the sampling signal Clksh of the next conversion program is used as the reset trigger signal, and the logic control circuit 140 resets multiple capacitors C1 to C10 respectively according to the sampling signal Clksh of the next conversion program.
[0034] like Figures 1-4 According to the embodiments described herein, the analog-to-digital conversion device 100 and analog-to-digital conversion method 200 of this disclosure can avoid the instantaneous large current caused by resetting multiple capacitors C1 to C10 simultaneously by resetting multiple capacitors C1 to C10 of the capacitor array 120 respectively.
[0035] In some embodiments, the logic control circuit 140 resets the plurality of capacitors C1 to C10 one by one according to the conversion end signal or the sampling signal. See also Figure 1 , 3 The logic control circuit 140 resets multiple capacitors C1 to C10 one by one during the reset times Treset1 to Treset10 based on the high-level transition end signal EOFh. (See also...) Figure 1 , 4 The logic control circuit 140 resets multiple capacitors C1 to C10 one by one during the reset time Treset1 to Treset10 according to the high-level sampling signal Clksh.
[0036] In some embodiments, the logic control circuit 140, based on a conversion end signal or a sampling signal, sequentially resets the first capacitor (corresponding to the most significant bit (MSB) among the plurality of capacitors C1 to C10) to the second capacitor (corresponding to the least significant bit (LSB) among the plurality of capacitors C1 to C10). See also... Figure 1 , 3 The logic control circuit 140, based on the high-level transition end signal EOFh, sequentially resets the capacitor C1 corresponding to the most significant bit among the multiple capacitors C1 to C10 to the capacitor C10 corresponding to the least significant bit. Specifically, the logic control circuit 140 resets the capacitor C1 corresponding to the most significant bit at reset time Treset1 based on the high-level transition end signal EOFh. Subsequently, the logic control circuit 140 resets capacitor C2 at reset time Treset2, and so on, finally resetting the capacitor C10 corresponding to the least significant bit at reset time Treset10.
[0037] Please see Figure 1 , 4The logic control circuit 140, based on the high-level sampling signal Clksh, sequentially resets the capacitor C1 corresponding to the most significant bit among the multiple capacitors C1 to C10 to the capacitor C10 corresponding to the least significant bit. Specifically, the logic control circuit 140 resets the capacitor C1 corresponding to the most significant bit at reset time Treset1 based on the high-level sampling signal Clksh. Subsequently, the logic control circuit 140 resets capacitor C2 at reset time Treset2, and so on, finally resetting the capacitor C10 corresponding to the least significant bit at reset time Treset10.
[0038] The analog-to-digital converter 100 disclosed herein is not limited to only employing Figure 3 and Figure 4 The embodiments described above are used to reset the multiple capacitors C1 to C10 of the capacitor array 120 respectively. Other different embodiments will be described one by one later.
[0039] In some embodiments, the logic control circuit 140 simultaneously resets at least two of the plurality of capacitors C1 to C10 based on a conversion end signal or a sampling signal. The at least two capacitors correspond to different bits of at least one input signal, Vip, and Vin, respectively. For example, please refer to... Figure 1 , 5 The logic control circuit 140 resets capacitors C1 and C2 among multiple capacitors C1 to C10 at the same reset time Treset1 and Treset2 according to the high-level transition end signal EOFh. As described in the previous embodiment, capacitors C1 and C2 correspond to different bits of at least one input signal Vip and Vin, respectively. In another embodiment, please refer to... Figure 1 , 6 The logic control circuit 140 resets capacitors C1 and C2 among multiple capacitors C1 to C10 at the same reset time Treset1 and Treset2 according to the high-level sampling signal Clksh. As described in the previous embodiment, capacitors C1 and C2 correspond to different bits of at least one input signal Vip and Vin, respectively.
[0040] In some embodiments, the logic control circuit 140 resets the first and second capacitors among the plurality of capacitors C1 to C10 at a first reset time based on a conversion end signal or a sampling signal, and resets the third and fourth capacitors among the plurality of capacitors C1 to C10 at a second reset time. For example, please refer to... Figure 1 , 5The logic control circuit 140, based on the high-level transition end signal EOFh, resets capacitors C1 and C2 of multiple capacitors C1 to C10 at the same reset times Treset1 and Treset2, resets capacitors C3 and C4 of multiple capacitors C1 to C10 at the same reset times Treset3 and Treset4, and so on, finally resetting capacitors C9 and C10 of multiple capacitors C1 to C10 at the same reset times Treset9 and Treset10. Please refer to... Figure 1 , 6 The logic control circuit 140 resets capacitors C1 and C2 of multiple capacitors C1 to C10 at the same reset time Treset1 and Treset2 according to the high-level sampling signal Clksh, and resets capacitors C3 and C4 of multiple capacitors C1 to C10 at the same reset time Treset3 and Treset4, and so on, and finally resets capacitors C9 and C10 of multiple capacitors C1 to C10 at the same reset time Treset9 and Treset10.
[0041] In some embodiments, the logic control circuit 140, based on a conversion end signal or a sampling signal, sequentially resets the first capacitor (corresponding to the least significant bit among the plurality of capacitors C1 to C10) to the second capacitor (corresponding to the most significant bit among the plurality of capacitors C1 to C10). For example, please refer to... Figure 1 , 7 The logic control circuit 140, based on the high-level transition end signal EOFh, sequentially resets the capacitor C10 corresponding to the least significant bit among the multiple capacitors C1 to C10 to the capacitor C1 corresponding to the most significant bit among the multiple capacitors C1 to C10. Specifically, the logic control circuit 140 resets the capacitor C10 corresponding to the least significant bit at reset time Treset1 based on the high-level transition end signal EOFh. Subsequently, the logic control circuit 140 resets capacitor C9 at reset time Treset2, and so on, finally resetting the capacitor C1 corresponding to the most significant bit at reset time Treset10.
[0042] Please see Figure 1 , 8The logic control circuit 140, based on the high-level sampling signal Clksh, sequentially resets the capacitor C10 corresponding to the least significant bit among the multiple capacitors C1 to C10 to the capacitor C1 corresponding to the most significant bit among the multiple capacitors C1 to C10. Specifically, the logic control circuit 140 resets the capacitor C10 corresponding to the least significant bit at reset time Treset1 based on the high-level sampling signal Clksh. Subsequently, the logic control circuit 140 resets capacitor C9 at reset time Treset2, and so on, finally resetting the capacitor C1 corresponding to the most significant bit at reset time Treset10.
[0043] In some embodiments, the logic control circuit 140 simultaneously resets at least two of the plurality of capacitors C1 to C10 based on a conversion end signal or a sampling signal, wherein the at least two capacitors correspond to different bits. For example, please refer to... Figure 1 , 9 The logic control circuit 140 resets capacitors C9 and C10 among multiple capacitors C1 to C10 at the same reset time Treset1 and Treset2 according to the high-level transition end signal EOFh. As described in the previous embodiment, capacitor C9 and capacitor C10 respectively correspond to different bits of at least one input signal Vip and Vin. In another embodiment, please refer to... Figure 1 , 10 The logic control circuit 140 resets capacitors C9 and C10 among multiple capacitors C1 to C10 at the same reset time Treset1 and Treset2 according to the high-level sampling signal Clksh. As described in the previous embodiment, capacitors C9 and C10 correspond to different bits of at least one input signal Vip and Vin, respectively.
[0044] It should be noted that the method by which the analog-to-digital converter 100 resets the multiple capacitors C1 to C10 is not based on... Figures 3 to 10 Limited to the embodiments described herein, in other embodiments, the analog-to-digital converter 100 of this disclosure can simultaneously reset three capacitors, or the analog-to-digital converter 100 of this disclosure can simultaneously reset more than three capacitors. In another embodiment, the analog-to-digital converter 100 of this disclosure can simultaneously reset two non-contiguous capacitors (e.g., simultaneously reset capacitors C1 and C3), or the analog-to-digital converter 100 of this disclosure can simultaneously reset three non-contiguous capacitors (e.g., simultaneously reset capacitors C1, C3, and C6), or even the analog-to-digital converter 100 of this disclosure can simultaneously reset more than three non-contiguous capacitors. The method by which the analog-to-digital converter 100 of this disclosure resets multiple capacitors C1 to C10 can be determined according to actual needs. As long as the multiple capacitors C1 to C10 are reset separately, or as long as not all capacitors C1 to C10 are reset simultaneously, they all fall under the concept protected by the analog-to-digital converter 100 of this disclosure.
[0045] Figure 11 A schematic diagram of an analog-to-digital converter 100 is provided according to some embodiments of this disclosure. Compared to Figure 1 , Figure 11 The analog-to-digital converter 100 further draws the components inside the logic control circuit 140.
[0046] As shown in the figure, the logic control circuit 140 includes an asynchronous controller 141, a latch 142, and a buffer 143. The asynchronous controller 141 outputs multiple frequency signals Clk1 to C10, at least two of which are asynchronous. The latch 142 is configured to reset multiple capacitors C1 to C10 respectively via switches 150 and 160 based on the multiple frequency signals Clk1 to C10. Furthermore, the latch 142 can store the comparison result of the comparator 130. The buffer 143 reads the comparison result stored in the latch 142 and outputs data B1 to B10 to a digital signal processing device (not shown) for subsequent signal processing based on the comparison result.
[0047] Figure 12 To illustrate a method according to some embodiments of this disclosure, such as Figure 11 This is a schematic diagram of the asynchronous controller 141 of the analog-to-digital converter 100. As shown, the asynchronous controller 141 includes a delay line 1411 and multiple flip-flops DFF1 to DFF11.
[0048] To facilitate understanding Figure 12 For instructions on operating the asynchronous controller 141, please refer to [link / reference needed]. Figure 13 A timing diagram of the asynchronous controller 141 is drawn. Delay line 1411 is used to delay the sampled signal Clks to generate multiple reset signals Reset[1] to Reset[5]. Multiple flip-flops DFF1 to DFF10 are configured to generate multiple frequency signals Clk1 to Clk10 based on the multiple reset signals Reset[1] to Reset[5], and transmit the multiple frequency signals Clk1 to Clk10 to Figure 11 The latch 142 then resets multiple capacitors C1 to C10 respectively based on multiple frequency signals Clk1 to Clk10. As described above, the sampling signal Clks is delayed by the delay line 1411 to generate Figure 13 The multiple reset signals Reset[1] to Reset[5] with time differences are shown. The flip-flops DFF1 to DFF10 then generate [the signal] based on the reset signals Reset[1] to Reset[5] with time differences. Figure 13The frequency signals Clk1 to Clk10 shown have time differences, so the latch 142 can reset the multiple capacitors C1 to C10 respectively according to the frequency signals Clk1 to Clk10 with time differences.
[0049] In some embodiments, Figure 12 The delay line 1411 includes delayers D1 to D5. Delayer D1 is used to delay the sampled signal Clks to generate a reset signal Reset[1], delayer D2 is used to delay the reset signal Reset[1] to generate a reset signal Reset[2], and so on, until finally delayer D5 is used to delay the reset signal Reset[4] to generate a reset signal Reset[5]. In summary, Figure 12 The delay line 1411 was indeed generated. Figure 13 The multiple reset signals Reset[1] to Reset[5] with time differences are shown.
[0050] It should be noted that this disclosure is not limited to the embodiments shown in Figures 1 to 13, but is merely illustrative of one implementation of this disclosure to facilitate understanding of the technology. The patent scope of this disclosure shall be determined by the scope of the invention application. Modifications and refinements made by those skilled in the art to the embodiments of this disclosure without departing from the spirit of this disclosure still fall within the scope of the invention application.
[0051] In summary, the technical means embodied in the embodiments of this disclosure can improve at least one of the shortcomings of the prior art. The analog-to-digital conversion apparatus and analog-to-digital conversion method of this disclosure can avoid the instantaneous large current caused by resetting multiple capacitors simultaneously by resetting multiple capacitors of the capacitor array separately.
[0052] Although the embodiments of this disclosure are described above, these embodiments are not intended to limit this disclosure. Those skilled in the art can make changes to the technical features of this disclosure based on its express or implied content. All such changes may fall within the scope of patent protection sought by this disclosure. In other words, the scope of patent protection of this disclosure shall be determined by the scope of the patent application in this specification.
[0053] [Symbol Explanation]
[0054] 100: Analog-to-digital converter
[0055] 110: Switch
[0056] 120: Capacitor Array
[0057] 130: Comparator
[0058] 140: Logic control circuit
[0059] 141: Asynchronous controller
[0060] 1411: Delay line
[0061] 142: Latch
[0062] 143: Buffer
[0063] 150: Switch
[0064] 160: Switch
[0065] 200: Method
[0066] 210~240: Steps
[0067] B1~B10: Data
[0068] C1~C10: Capacitors
[0069] Clks: Sampling signal
[0070] Clksh: High-level sampling signal
[0071] Clkc: Enable signal
[0072] Clkin: Frequency input
[0073] Clk1~10: Frequency signals
[0074] D1~D5: Delayers
[0075] DFF1~DFF11: Flip-flops
[0076] EOF: End-of-conversion signal
[0077] EOFh: High-level end-of-conversion signal
[0078] Outp、Outn: Outputs
[0079] Reset[1]~Reset[5]: Reset signals
[0080] Treset1~Treset10: Reset times
[0081] Vip、Vin: Input signals
[0082] Vref: Reference signal
[0083] Vcap_p<1:10>、Vcap_n<1:10>: Bit signals
[0084] Vcap_p / n<1>~Vcap_p / n<10>: Bit signals
[0085] Valid: Valid signal
[0086] VDD: Power supply voltage
Claims
1. An analog-to-digital converter, comprising: A switch is configured to sample at least one input signal based on a sampled signal; A capacitor array, comprising a plurality of capacitors, wherein the plurality of capacitors are used to store the at least one input signal; A comparator that uses the at least one input signal configured to store a comparison result based on the plurality of capacitors in the capacitor array; as well as A logic control circuit is configured to reset the plurality of capacitors respectively based on a conversion end signal or the sampling signal.
2. The analog-to-digital converter according to claim 1, wherein the logic control circuit resets the plurality of capacitors one by one according to the conversion end signal or the sampling signal.
3. The analog-to-digital converter according to claim 1, wherein the logic control circuit is sequentially reset from the first capacitor corresponding to the most significant bit (MSB) to the second capacitor corresponding to the least significant bit (LSB) of the plurality of capacitors according to the conversion end signal or the sampling signal.
4. The analog-to-digital converter according to claim 1, wherein the logic control circuit simultaneously resets at least two of the plurality of capacitors according to the conversion end signal or the sampling signal, wherein the at least two capacitors respectively correspond to different bits of the at least one input signal.
5. The analog-to-digital converter according to claim 1, wherein the logic control circuit resets the first capacitor and the second capacitor among the plurality of capacitors at a first reset time according to the conversion end signal or the sampling signal, and resets the third capacitor and the fourth capacitor among the plurality of capacitors at a second reset time.
6. The analog-to-digital converter according to claim 1, wherein the logic control circuit is sequentially reset from the first capacitor corresponding to the least significant bit among the plurality of capacitors to the second capacitor corresponding to the most significant bit among the plurality of capacitors according to the conversion end signal or the sampling signal.
7. The analog-to-digital conversion circuit according to claim 1, wherein the logic control circuit comprises: An asynchronous controller for outputting multiple frequency signals, wherein at least two of the multiple frequency signals are asynchronous; as well as A latch, which resets the plurality of capacitors respectively based on the plurality of frequency signals.
8. The analog-to-digital converter according to claim 7, wherein the asynchronous controller comprises: A delay line is used to delay the sampled signal to generate multiple reset signals; as well as Multiple flip-flops are configured to generate multiple frequency signals according to the multiple reset signals and transmit the multiple frequency signals to the latch.
9. The analog-to-digital converter according to claim 8, wherein the delay line comprises: A first delayer is used to delay the sampled signal to generate a first reset signal among the plurality of reset signals; as well as A second delayer is used to delay the first reset signal to generate a second reset signal among the plurality of reset signals.
10. An analog-to-digital conversion method, comprising: The switch samples at least one input signal based on the sampling signal. The at least one input signal is stored by multiple capacitors in a capacitor array; The comparator generates a comparison result based on the at least one input signal stored in the plurality of capacitors of the capacitor array; as well as The logic control circuit resets the plurality of capacitors respectively based on the conversion end signal or the sampling signal.