Network equipment, networking method and device

Abstract

The invention discloses network equipment and a networking method and device, relates to the technical field of cluster networks, and is used for solving the problem that the network equipment cannot change network topology. According to the scheme provided by the invention, the switching board is replaced, so that the network equipment supports mesh networking and also supports clos networking. According to the scheme provided by the embodiment of the invention, a plurality of SW boards are consistent or normalized under clos networking and mesh networking, and convenience can be provided for deployment, so that the network equipment is suitable for a small-scale networking scene and is also suitable for a large-scale networking scene.

Description

Technical Field

[0001] This application relates to the field of trunking network technology, and in particular to a network device, networking method and apparatus. Background Technology

[0002] A star topology (Clos) is a simple network topology where all devices are connected to a central device (such as a switch or router). A mesh topology, on the other hand, is where all nodes are directly connected to each other, forming a network structure. In a mesh topology, each node can communicate with every other node without needing to go through intermediate nodes.

[0003] In some scenarios, such as AI scenarios, the choice of network topology depends on many factors, such as network size, complexity, data transmission requirements, and security requirements. However, currently, AI devices only support one network topology. If a change in network topology is needed, the hardware architecture and devices must be redesigned, resulting in poor flexibility and high time costs. Summary of the Invention

[0004] This application provides a network device, networking method, and apparatus to solve the problem of being unable to change the network topology.

[0005] In a first aspect, embodiments of this application provide a network device, which includes a service board array. The service board array includes N service boards; each of the N service boards includes L processing chips, and the L processing chips are meshed together on the service boards; N and L are both positive integers greater than 1.

[0006] The network device supports both mesh networking and CLOS networking.

[0007] In one possible implementation, the network device, in a mesh network configuration, further includes a first switching board array, wherein the service board array is vertically pluggable to the first switching board array; the first switching board array is used to implement mesh connections between N processing chips belonging to different service boards.

[0008] In another possible implementation, the network device in a CLOS network also includes a second switching board array, wherein the service board array is vertically pluggable to the second switching board array; the second switching board array includes M switching chips, each of the M switching chips is connected to N*L processing chips included in the second switching board array, where M is a positive integer.

[0009] The solution described in this application allows the service board array to connect with different switching board arrays, enabling different network topologies for the service board array through a pluggable switching board array approach. This eliminates the need to redesign the hardware architecture for the service board array, saving time and reducing implementation complexity.

[0010] In one possible implementation, a chassis is also included, with the service board array and the first switching board array perpendicularly inserted on both sides of the chassis, or the service board array and the second switching board array perpendicularly inserted on both sides of the chassis.

[0011] In the above method, the switch board array and the service board array are pluggable and connected through the chassis, which is easy to implement.

[0012] In one possible implementation, the connection between the service board array and the first switching board array is a backplane-free orthogonal connection; or, the connection between the service board array and the second switching board array is a backplane-free orthogonal connection.

[0013] In the above implementation method, the connection between the service board and the switching board is achieved by using a backplane-free orthogonal connection. The service board and the switching board do not need to be connected by cables, that is, they are directly connected, which avoids the problems of high connection error rate and cable wear caused by too many cables.

[0014] In one possible implementation, the number of connections between N processing chips belonging to different service boards is (N-1)*N*L / 2; the first switching board array includes L first switching boards, each of which is used to implement (N-1)*N / 2 connections.

[0015] In the above method, under mesh networking, each first switching board achieves the same number of connections, which can reduce the design difficulty of the first switching board and the difficulty of wiring on different switching boards.

[0016] In one possible implementation, the (N-1)*N*L / 2 connections are divided into L connection groups. The k-th connection group includes connections between the k-th processing chips on N service boards. The k-th connection group is further divided into L sub-connection groups, where k is less than or equal to L. A third switching board is used to implement the connections included in the L sub-connection groups. The third switching board is any one of the L first switching boards. The L sub-connection groups to which the connections implemented by the third switching board belong are different connection groups.

[0017] By employing the above methods, the wiring patterns on different first switching boards are made consistent. This consistency or normalization of the first switching boards reduces the difficulty of deploying mesh networks. Furthermore, the consistency across different first switching boards eliminates the need to design multiple first switching boards, thus reducing design complexity and making it easier to use and deploy.

[0018] In one possible implementation, the kth sub-connection group in different connection groups contains the same number of connections.

[0019] In one possible implementation, the ports of the third switching board are divided into N port groups. The third switching board is any one of the L first switching boards. The N port groups are connected one-to-one with the ports on the N service boards. The first port group includes L sub-port groups. The first port group is any one of the N port groups. The ports in the j-th sub-port group of the N port groups are interconnected on the third switching board. The value of j is a positive integer less than or equal to L.

[0020] By using the aforementioned port grouping method to achieve consistency and normalization of the first switching board, the deployment difficulty of mesh networking can be further reduced.

[0021] In one possible implementation, the service board array is provided with a plurality of first connectors, and the first switching board array is provided with a plurality of second connectors, wherein the plurality of first connectors of the service board array are connected one-to-one with the plurality of second connector arrays of the second switching board array.

[0022] For example, the first connector and the second connector can form an orthogonal connection to achieve a backplane-free orthogonal connection between the service board array and the switching board array. No cables are needed between the service boards and the switching boards; a direct connection method is used, avoiding the problems of high connection error rates and cable wear caused by excessive cables.

[0023] In one possible implementation, the first service board includes L first connectors, and the first service board is any one of the N service boards; the third switching board includes N second connectors, and the third switching board is any one of the L first switching boards; one of the first connectors includes N-1 ports corresponding to a processing chip on the first service board, and the second connector includes N-1 ports;

[0024] Each of the N second connectors in the third switching board includes L groups of ports. The processing chips corresponding to the first connectors to which the ports connected to the first port group belong are different from those corresponding to the first connectors to which the ports connected to the second port group belong. The first port group and the second port group are any one of the L groups of ports. The pairs of ports on the N second connectors that correspond to the j-th group are interconnected on the third switching board, where j is a positive integer less than or equal to L.

[0025] By employing the above methods, while achieving backplane-free orthogonal architecture, the wiring patterns on different first switching boards are made consistent. This consistency or normalization of the first switching boards reduces the deployment complexity of mesh networks. Furthermore, the consistency across different first switching boards eliminates the need to design multiple first switching boards, thus reducing design complexity and making the network easier to use and deploy.

[0026] In one possible implementation, the j-th group of any two second connectors belonging to different first switching boards includes the same number of ports.

[0027] In one possible implementation, the first connector to which the port connected to the j-th group of ports on the third connector belongs corresponds to the first processing chip, and the third connector is a second connector of the third switching board. The first connector to which the port connected to the j-th group of ports on the fourth connector belongs corresponds to the second processing chip, and the fourth connector is a second connector of the fourth switching board. The first processing chip and the second processing chip are two processing chips on the same service board, and the third switching board and the fourth switching board are two switching boards among L first switching boards.

[0028] The position of the third connector on the third switching board can be the same as the position of the third connector on the fourth switching board.

[0029] For example, connectors, processing chips, and service boards can be numbered. All switch boards use the same numbering method. Connectors in the same location have the same number. For connectors with the same number on different switch boards, the first connector belonging to the pluggable port of the j-th group corresponds to two unnumbered processing chips on the same service board.

[0030] Secondly, embodiments of this application provide a networking method, comprising: in a mesh networking scenario, vertically pluggable connecting a service board array to a first switching board array; and when switching from a mesh networking scenario to a CLOS networking scenario, replacing the first switching board array with a second switching board array and pluggable connecting it to the service board array; wherein, the service board array includes N service boards; each of the N service boards includes L processing chips, and the L processing chips are meshed on the service boards; N and L are both positive integers greater than 1; the first switching board array is used to implement mesh connections between the N processing chips belonging to different service boards; the second switching board array includes M switching chips, each of the M switching chips is connected to the N*L processing chips included in the second switching board array, and M is a positive integer;

[0031] Alternatively, in a CLOS networking scenario, the service board array and the second switch board array can be vertically pluggable; and when switching from a CLOS networking scenario to a mesh networking scenario, the second switch board array can be replaced by the first switch board array and pluggable connected to the service board array.

[0032] In a mesh networking scenario, data transmission between the N*L processing chips on the service board array is achieved through a first switching board array. In a CLOS networking scenario, any one of the N*L processing chips on the service board array transmits data with any one of the M switching chips.

[0033] In one possible implementation, the service board array is vertically pluggable connected to the first switching board array, including: vertically pluggable connecting the service board array to the first switching board array via a chassis;

[0034] or,

[0035] The method of making the service board array and the second switching board array vertically pluggable includes: making the service board array and the second switching board array vertically pluggable through the chassis.

[0036] In one possible implementation, the connection between the service board array and the first switching board array is a backplane-free orthogonal connection; or, the connection between the service board array and the second switching board array is a backplane-free orthogonal connection.

[0037] The connection method between the aforementioned service board array and the first switching board array can be found in the relevant description in the first aspect, and will not be repeated here. The connection method between the service board array and the second switching board array can be found in the relevant description in the first aspect, and will not be repeated here.

[0038] Thirdly, embodiments of this application provide a networking device, including a first connection unit and a second connection unit. The first connection unit is used to vertically pluggable connect a service board array to a first switching board array in a mesh networking scenario; the second connection unit is used for...

[0039] When switching from a mesh networking scenario to a CLOOS networking scenario, the first switching board array is replaced by a second switching board array that is pluggably connected to the service board array. The service board array comprises N service boards; each of the N service boards comprises L processing chips, which are meshed together on the service boards; N and L are both positive integers greater than 1. The first switching board array is used to implement mesh connections between the N processing chips belonging to different service boards; the second switching array comprises M switching chips, each of which is connected to the N*L processing chips included in the second switching board array, where M is a positive integer.

[0040] Alternatively, the first connection unit is used to vertically pluggable connect the service board array and the second switch board array in a CLOS networking scenario; the second connection unit is used to replace the second switch board array with the first switch board array and pluggable connect them to the service board array when switching from a CLOS networking scenario to a mesh networking scenario.

[0041] The connection method between the aforementioned service board array and the first switching board array can be found in the relevant description in the first aspect, and will not be repeated here. The connection method between the service board array and the second switching board array can be found in the relevant description in the first aspect, and will not be repeated here.

[0042] Fourthly, embodiments of this application provide a networking device, including a processor and a memory; the memory is used to store a computer program; the processor is used to execute the computer program stored in the memory, so that the networking device performs the method described in the second aspect.

[0043] Fifthly, embodiments of this application provide a computer-readable storage medium including a program and instructions, wherein the method described in the second aspect is executed when the program or instructions are run on a processor.

[0044] In a sixth aspect, embodiments of this application provide a computer program product, including a computer program, which, when run by an electronic device, causes the electronic device to perform the method described in the second aspect.

[0045] Based on the above-mentioned implementation methods, this application can be further combined to provide more implementations. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of a possible mesh network topology;

[0047] Figure 2 This is a schematic diagram of a possible CLOS network topology;

[0048] Figure 3 A schematic diagram of a network device structure provided in an embodiment of this application;

[0049] Figure 4 This application provides a schematic diagram of a connector arrangement.

[0050] Figure 5A A schematic diagram of a mesh network topology with 32 NPU chips is provided for an embodiment of this application;

[0051] Figure 5B A schematic diagram of a CLOS network topology for 32 NPU chips is provided in this embodiment of the application;

[0052] Figure 6 This is a schematic diagram illustrating the orthogonal connection between the SPU array and the SW1 array provided in an embodiment of this application.

[0053] Figure 7 This is a schematic diagram illustrating the connection between the SPU array and the SW2 array provided in an embodiment of this application.

[0054] Figure 8 A schematic diagram showing the arrangement of the front-view connectors of the AI ​​server provided in an embodiment of this application;

[0055] Figure 9 A pin mapping diagram of a first connector and a second connector provided in an embodiment of this application;

[0056] Figure 10 A pin mapping diagram of the first connector and the second connector under a combined grouping method provided in this application embodiment;

[0057] Figure 11 A schematic diagram of chip connection mapping implemented by the first switching board provided in the embodiments of this application;

[0058] Figure 12 Another pin mapping diagram of the first connector and the second connector provided for embodiments of this application;

[0059] Figure 13A A pin mapping diagram of the first connector and the second connector provided in an embodiment of this application;

[0060] Figure 13B A pin mapping diagram of the first connector and the second connector provided in an embodiment of this application;

[0061] Figure 14AThis is a schematic diagram of a networking method provided in an embodiment of this application;

[0062] Figure 14B This is a schematic diagram of another networking method provided in an embodiment of this application;

[0063] Figure 15 This is a schematic diagram of the networking device structure provided in the embodiments of this application;

[0064] Figure 16 This is a schematic diagram of the structure of the electronic device 1600 provided in an embodiment of this application. Detailed Implementation

[0065] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0066] In the description of this application, unless otherwise stated, "multiple" refers to two or more. Additionally, " / " indicates that the related objects are in an "or" relationship; for example, A / B can represent A or B. "And / or" in this application merely describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. Furthermore, to facilitate a clear description of the technical solutions of the embodiments of this application, the terms "first" and "second" are used in the embodiments to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" are not necessarily different. It should also be noted that, unless specifically stated, the specific description of some technical features in one embodiment can also be used to explain the corresponding technical features mentioned in other embodiments.

[0067] The technical terms involved in the embodiments of this application will be described below.

[0068] Mesh networking:

[0069] See Figure 1 The diagram shown is a possible mesh network topology. Figure 1 Taking a 6-node example, all nodes are directly connected, eliminating the need for data exchange between other nodes. This mesh topology is suitable for small to medium-sized networks, allowing data exchange between two nodes without traversing other nodes. Mesh topologies offer advantages such as low latency, low cost, and low power consumption.

[0070] CLOS networking:

[0071] See Figure 2 The diagram shows a possible CLOS network topology. Data exchange between nodes is performed via switching chips. CLOS networking is a large-scale network composed of multiple planes and levels. CLOS networking is suitable for large-scale networking, offering advantages such as non-blocking, reconfigurability, and scalability. However, compared to mesh networking, CLOS networking has higher switch costs, greater latency, and higher power consumption.

[0072] veneer:

[0073] A single board refers to a circuit unit with a specific function, composed of components such as printed circuit boards (PCBs), components, and connectors. Different functional units in communication equipment can be called single boards, such as line processing units (LPUs), switch fabric units (SFUs), main processing units (MPUs), and service processing units (SPUs).

[0074] Switching board: It should be understood that the switching board mentioned in this application refers to a switching board, such as an SFU (Switching Unit). A switching board is a hardware structure on a communication device that can be used to achieve high-speed point-to-point connections between various service boards for data forwarding on the service boards.

[0075] Service board: It should be understood that the service board described in this application may also be called a line card board, such as an LPU. A service board is a hardware structure on a communication device that can be used for service processing or service forwarding.

[0076] To ensure compatibility with both mesh and CLOS networking, this application provides a network system, network device, networking method, and apparatus that supports replacing circuit boards to accommodate different network topologies. The network system provided in this application can be applied to scenarios such as AI servers, AI cluster systems, general-purpose computing systems, supercomputing centers, or routing.

[0077] See Figure 3 The diagram shown is a schematic representation of a network device structure according to an embodiment of this application. The network device includes a service board array, which comprises multiple service boards, taking N service boards as an example. Each of the N service boards includes L processing chips.

[0078] The processing chip can be a chip that performs processing tasks in a network system cluster, such as a central processing unit (CPU), graphics processing unit (GPU), neural network processing unit (NPU), data processing unit (DPU), etc., and this application does not impose specific limitations. The processing chip can be a computing chip used in high-performance computing (HPC), artificial intelligence (AI), and other application scenarios to process business within the cluster, or it can be a storage chip used by storage nodes in a distributed storage scenario, and this application does not impose specific limitations.

[0079] In one possible implementation, the network device also includes a switching board array. The switching board array is used to enable communication connections between processing chips on N service boards.

[0080] In this embodiment, different network topologies can be achieved by updating the switching board array. The switching board array includes multiple switching boards. Each switching board contains internal wiring and various connectors, supporting the insertion of other service boards onto the first switching board. Connectors, also known as plugs, sockets, and connectors, generally refer to electrical connectors, i.e., devices that connect two active devices to transmit current or signals. Furthermore, the network device may also include physical entities composed of subracks, slots, cooling and power supply modules, providing space for the placement and interconnection of various components and protecting them. The service board array and the switching board array are vertically pluggable.

[0081] For example, network devices can be orthogonal architecture devices. This can be understood as: service board arrays and switching board arrays can be orthogonally connected without a backplane. A backplane (or backplane system) is a set of parallel electrical connectors used to connect multiple printed circuit boards together to form the backbone of a complete computer system. Orthogonal architecture devices are devices that use a backplane-less orthogonal architecture, where the service boards and switching boards are orthogonal.

[0082] In one possible implementation, the network device can be any device in the network cluster, such as a chassis-based device. The network device may also include a chassis. Service board arrays and switch board arrays are vertically inserted into both sides (or two sides) of the chassis. In one example, the service board array can be horizontally inserted at the front of the chassis, and the switch array can be vertically inserted at the rear of the chassis. In another example, the service board array can be vertically inserted at the front of the chassis, and the switch array can be horizontally inserted at the rear of the chassis. Of course, in some scenarios, the service board array can also be inserted at the rear of the chassis, and the switch array at the front of the chassis.

[0083] For ease of distinction, the switchboard array under mesh networking will be referred to as the first switchboard array, and the switchboard array under CLOS networking will be referred to as the second switchboard array.

[0084] The following sections describe the solutions for mesh networking and CLOS networking respectively.

[0085] Mesh networking:

[0086] The network equipment includes a service board array, which comprises N service boards. Each of the N service boards includes L processing chips. The L processing chips in a first service board are meshed together. The first service board can be any one of the N service boards. The mesh connection here can be understood as each of the L processing chips being connected to all the other processing chips. It should be noted that, in addition to the L processing chips, the service board may also include other processing chips for purposes such as expanding the network scale or providing backup for other processing chips.

[0087] The network equipment also includes a first switching board array. The first switching board array may include one or more first switching boards. The first switching board has internal wiring, and when the service board array is vertically pluggable and detachable from the first switching board array, the first switching board array can achieve mesh connectivity between N processing chips belonging to different service boards. For example, the N*L processing chips on the service board array can be divided into L processing chip groups, each processing chip group including N processing chips. The processing chips in a processing chip group belong to different service boards. The processing chips in different processing chip groups are different. The first switching board array can achieve mesh connectivity between the N processing chips in each processing chip group.

[0088] The number of connections within each processing chipset is (N-1)*N / 2. Therefore, the number of connections across L processing chipsets is (N-1)*N*L / 2. In other words, the number of mesh connections between N service boards is (N-1)*N*L / 2. The first switching board array can include multiple first switching boards. Each first switching board is responsible for a portion of the mesh connections. N is greater than L.

[0089] In one possible implementation, (N-1)*N*L / 2 mesh connections are evenly distributed across multiple first switching boards. For example, the number of first switching boards in the first switching board array can be L, with each first switching board responsible for (N-1)*N / 2 mesh connections.

[0090] In one possible implementation, to achieve consistency (or normalization) among the L first switching boards, the connections can be assigned to each first switching board in a grouped manner. Consistency of the first switching boards can be understood as the internal wiring of the first switching boards being identical. For example, (N-1)*N*L / 2 connections can be divided into L connection groups, with each connection group containing connections corresponding to a processing chip on each of the N service boards. This can be understood as grouping the (N-1)*N*L / 2 connections according to processing chip groups; therefore, (N-1)*N*L / 2 connections are divided into L connection groups. Each connection group includes (N-1)*N / 2 connections. Different connection groups correspond to different processing chips on the same service board. For example, the k-th connection group includes connections between the k-th processing chips on the N service boards.

[0091] Furthermore, each connection group can be divided into L sub-connection groups. Each of the L sub-connection groups in a connection group is assigned one-to-one to L first switching boards. Taking one of the L first switching boards as an example (or, for ease of description, the third switching board, which is one of the L first switching boards), as an example, the third switching board implements the connections included in the L sub-connection groups. The L sub-connection groups to which the connections implemented by the third switching board belong belong to different connection groups. The division method for each connection group is the same. Alternatively, it can be understood that the L sub-connection groups to which the connections implemented by the first switching boards belong correspond to different processing chipsets.

[0092] In one possible implementation, the sub-connection groups of each connection group can be sequentially assigned to multiple first switching boards in a "round-robin" manner.

[0093] The "rotation" method is described below.

[0094] The connections in each sub-connection group of the L connection groups are sequentially assigned to the L switches according to the round-robin allocation principle. In the i-th round, starting from the i-th sub-connection group of the i-th connection group, the connections within the i-th sub-connection group of the L connection groups are sequentially assigned to the L switches. i is a positive integer less than or equal to L. The above round-robin method is only an example; reverse round-robin or other allocation methods can also be used.

[0095] Taking L as 4 as an example, the first round starts at the first sub-connection group of the first connection group, the second round starts at the second sub-connection group of the second connection group, the third round starts at the third sub-connection group of the third connection group, and the fourth round starts at the fourth sub-connection group of the fourth connection group.

[0096] Optionally, the number of connections in each sub-connection group can be a multiple of L. Different sub-connection groups can have the same or different numbers of connections.

[0097] For example, consider four service boards, each with two processing chips (N=4, L=2). The number of first switching boards is two. The number of processing chipsets is two. Each of the two connection groups includes three connections. These three connections are divided into two sub-connection groups; for example, the first sub-connection group includes two connections, and the second sub-connection group includes one connection. The first switching board implements the connections included in the first sub-connection group of the first connection group and the connections included in the second sub-connection group of the second connection group. The second switching board implements the connections included in the first sub-connection group of the second connection group and the connections included in the second sub-connection group of the first connection group. See Table 1, assuming each service board has two processing chips, D1 and D2. In Table 1, the first chip on all four service boards is referred to as D1, and the second chip as D2.

[0098] Table 1

[0099]

[0100] For example, taking 8 service boards as an example, each service board includes 4 processing chips, i.e., N=8, L=4. The number of first switching boards is 4. The number of processing chipsets is 4. Each of the 4 connection groups includes 28 connections. The 28 connections in each connection group are divided into 4 sub-connection groups, for example, the first sub-connection group includes 16 connections, the second sub-connection group includes 4 connections, the third sub-connection group includes 4 connections, and the fourth sub-connection group includes 4 connections. The first switching board is used to implement the connections included in the first sub-connection group of the first connection group, the connections included in the second sub-connection group of the second connection group, the connections included in the third sub-connection group of the third connection group, and the connections included in the fourth sub-connection group. The second switch board is used to implement the connections included in the first sub-connection group of the second connection group, the connections included in the second sub-connection group of the third connection group, the connections included in the third sub-connection group of the fourth connection group, and the connections included in the fourth sub-connection group of the first connection group.

[0101] Referring to Table 2, taking four processing chips on each service board, designated as D1-D4, as an example. In Table 2, the first chip on each of the eight service boards is referred to as D1, the second chip as D2, the third chip as D3, and the fourth chip as D4. Table 2 illustrates several possible grouping methods, but is not limited to these.

[0102] Table 2

[0103]

[0104]

[0105] In another possible implementation, each service board includes L processing chips, each with a unique number. Different service boards can use the same numbering method. For example, the L processing chips on each service board can be numbered D1 to DL. The L processing chips with the same number belong to one processing chip group.

[0106] During polling, the (N-1)*N*L / 2 connections can be grouped, for example, by processing chip number. Connections with the same processing chip number are grouped into one connection group, resulting in (N-1)*N*L / 2 connections divided into L connection groups. Each connection group contains (N-1)*N / 2 connections. Then, the connections within each connection group are divided into L sub-connection groups. Each connection group is divided in the same way. Following the round-robin allocation principle, the connections in each sub-connection group of the L connection groups are sequentially assigned to the L switches. In the i-th poll, starting from the i-th sub-connection group of the i-th connection group, the connections in the i-th sub-connection group of the L connection groups are sequentially assigned to the L switch boards. The value of i is a positive integer less than or equal to L.

[0107] In one possible implementation, each service board has (N-1)*L ports for connecting to the switching board array. Each port can include multiple lanes. For example, a serializer / deserializer (SerDes) constitutes a lane. The serializer is also called the SerDes transmitter (Tx), and the deserializer is also called the receiver (Rx). The serializer converts parallel signals into serial signals. The deserializer converts serial signals into parallel signals. Each port can consist of 1, 2, or 4 lanes. The (N-1)*L ports correspond to L processing chips. Each processing chip includes N-1 ports. For ease of distinction, the N-1 ports of each processing chip are referred to as external ports. Each processing chip also includes L-1 internal ports, which are used for mesh connections with other processing chips on the service board. It is understood that external ports and internal ports are distinguished relative to the functions of the service board. This is merely a naming convention; other naming methods can also be used, such as L-1 first ports and N-1 second ports. This application does not limit this. In some embodiments, to facilitate vertical connection between the service board and the switching board, each service board has (N-1)*L ports, which correspond one-to-one with the (N-1)*L ports of the L processing chips on the service board. In some possible implementation scenarios, the ports of the service board can also be the ports of the processing chips.

[0108] Each first switching board may include N*(N-1) ports. N service boards are connected to L first switching boards, meaning that the N*(N-1)*L ports on the N service boards are connected one-to-one with the N*(N-1)*L ports on the L first switching boards. The N*(N-1) ports on each first switching board are connected via internal wiring, thus enabling connections between processing chips belonging to different service boards.

[0109] In some possible implementation scenarios, each processing chip on the service board may include N-1 ports for connecting to the first switching board, as well as other spare ports, such as ports for network expansion.

[0110] In some embodiments, each connection in the above-described rotation is mapped to two ports on each first switching board, thus forming the internal wiring on the first switching board. Ports on each first switching board are grouped according to the implemented connections. It should be understood that each first switching board includes N port groups, and each of the N port groups corresponds one-to-one with the N service boards. Ports within the same port group cannot be connected. Then, each port group is divided into L sub-port groups. Each of the L sub-port groups corresponds one-to-one with the L sub-connection groups. Ports within the same sub-port group in different port groups are interconnected on the first switching board.

[0111] For example, taking 8 service boards as an example, each service board includes 4 processing chips, i.e., N=8, L=4. The number of first switching boards is 4. The number of processing chip groups is 4. Each of the 4 connection groups includes 28 connections. The 28 connections in each connection group are divided into 4 sub-connection groups, using Method 1 in Table 2 as an example. As shown in Table 3, each port group includes 7 ports, namely port 1 to port 7. The 7 ports in each port group are not interconnected. In each column of Table 3, the same number indicates that two ports in the same sub-port group within two port groups are interconnected on the first switching board. For example, port 1 in port group 1 and port 1 in port group 2 are interconnected. Port 3 in port group 3 is interconnected with port 1 in port group 7. It should be understood that Table 3 is only an example; there are other connection methods, but it is necessary to ensure that ports in different sub-port groups are not interconnected.

[0112] Table 3

[0113]

[0114]

[0115] For example, taking four service boards as an example, each service board includes two processing chips, i.e., N=4, L=2. The number of first switching boards is 2. The number of processing chip sets is 2. Each of the two connection groups includes 6 connections. The 6 connections in each connection group are divided into 2 sub-connection groups, as shown in Table 1. Referring to Table 4, each port group includes 3 ports, namely port 1 to port 3. The 3 ports in each port group are not interconnected. In each column of Table 3, the same number indicates that two ports in the same sub-port group within two port groups are interconnected on the first switching board. For example, port 1 in port group 1 and port 1 in port group 2 are interconnected. Port 3 in port group 2 is interconnected with port 3 in port group 3.

[0116] Table 4

[0117]

[0118] In one possible implementation, the connection between the service board and the switching board is an electrical connection. This electrical connection is primarily achieved through electrical connectors, specifically backplane-less orthogonal connectors. These backplane-less orthogonal connectors allow the service board and switching board to be directly orthogonally connected without cables or optical fibers, thus avoiding the problems of high cable connection error rates and high cable or optical fiber losses caused by an excessive number of cables or optical fibers.

[0119] Alternatively, electrical connections can also be achieved between service boards and switching boards using a combination of electrical connectors and cables. The electrical connectors here can be high-speed connectors with a backplane. This connection method requires a small number of cables. First, flexible connections are established between the service boards, switching boards, and high-speed connectors using cables. Then, the high-speed connectors are rotated 90 degrees to achieve an orthogonal connection between the switching boards and service boards, making them nearly directly orthogonal. Because the number of cables is reduced, the problems of high cable connection error rates and high cable or fiber loss caused by an excessive number of cables or optical fibers can be mitigated.

[0120] Based on this, the aforementioned ports can be implemented using connectors. The connectors referred to here are electrical connectors, and for ease of description, they are simply called connectors. For clarity, the connectors on the service board are referred to as the first connector, and the connectors on the switching board are referred to as the second connector. If the first connector is a male connector, the second connector can be a female connector corresponding to the male connector. If the first connector is a female connector, the second connector can be a male connector corresponding to the female connector. Each service board has one or more connectors, and each connector has one or more sub-connectors. The number of sub-connectors is related to the number of ports included in the connector.

[0121] In one possible implementation, the service board array includes a first connector array for implementing the aforementioned L*(N-1)*N ports. The first switching board array also includes a second connector array for implementing the same L*(N-1)*N ports. The ports of the first connector array are directly connected to the ports of the second connector array in a one-to-one correspondence. The L*(N-1)*N ports of the second connector array are also directly connected in pairs to the first switching board array, enabling mesh connectivity of the processing chips on different service boards. The specific port connection method is as described above.

[0122] Exemplarily, a first connector array includes a plurality of first connectors, and a second connector array includes a plurality of second connectors. In one example, the specifications of the plurality of first connectors may be the same or different. The specifications of the plurality of second connectors may be the same or different. In another example, the first connectors and second connectors have the same specifications, both using N-1 port connectors. Optionally, the N-1 port connector can also be implemented using multiple smaller specification connectors; for example, a 7-port connector can be implemented using one 4-port connector and one 3-port connector. For ease of description, the smaller specification connectors used to form the N-1 port connector are referred to as sub-connectors. That is, a 7-port connector includes one 4-port sub-connector and one 3-port sub-connector.

[0123] For example, both the first connector and the second connector have N-1 ports. Each service board has L first connectors, so the service board array has L*N first connectors. Each first switching board has N second connectors, so the first switching board array has N*L second connectors. The L*N first connectors and N*L second connectors are connected in a one-to-one correspondence. For example, see... Figure 4 As shown, taking N=8 and L=4 as an example. Figure 4 In the middle, the overlapping position between the service board and the switching board is a pair of 7-port connectors, namely a 7-port first connector and a 7-port second connector.

[0124] Each of the N second connectors on the first switching board includes L groups of ports. Ports within the same group on different second connectors are interconnected on the first switching board. Taking one of the L first switching boards as an example (for ease of distinction, this first switching board is referred to as the third switching board), the third switching board is any one of the L first switching boards. Each of the N second connectors on the third switching board includes L groups of ports. The first connector to which a port connected to a first port group belongs corresponds to a different processing chip than the first connector to which a port connected to a second port group belongs. The first port group and the second port group are any one of the L groups of ports. Ports on the N second connectors corresponding to the j-th group are interconnected on the third switching board, where j is a positive integer less than or equal to L. Alternatively, the first connector can also be divided into L groups of ports. The grouping method for the first connector is the same as that for the second connector. For example, the first group of ports on the first connector and the first group of ports on the second connector are pluggable. Different groups of ports on the first connector correspond to different processing chips. For example, the first group of ports, the second group of ports, ..., the Lth group of ports of the first connector are respectively connected to (or correspond to) the first processing chip, the second processing chip, ..., the Lth processing chip of the same service board.

[0125] In some embodiments, the j-th group of any two second connectors belonging to different first switching boards includes the same number of ports. For example, if the first group of the second connectors on the first first switching board includes 8 ports, then the first group of the second connectors on the second first switching board also includes 8 ports.

[0126] In some possible implementations, the first connectors to which the ports connected to the j-th group of ports of the second connectors at the same position on different first switching boards belong to different processing chips on the same service board. For example, the first connector to which the port connected to the j-th group of ports on the third connector belongs corresponds to the first processing chip, and the third connector is a second connector on the third switching board. The first connector to which the port connected to the j-th group of ports on the fourth connector belongs to the second processing chip, and the fourth connector is a second connector on the fourth switching board. The first processing chip and the second processing chip are two processing chips on the same service board, and the third switching board and the fourth switching board are two switching boards out of L first switching boards. The position of the third connector on the third switching board is the same as the position of the fourth connector on the fourth switching board.

[0127] Combining the port groups and sub-port groups mentioned above, a second connector comprising N-1 ports constitutes a port group. The L groups of ports mentioned above can be understood as L sub-port groups. Taking N=8 and L=4 as an example, as shown in Table 4, each second connector includes 7 ports, namely port 1 through port 7. In each column of Table 4, the same number indicates that two ports within the same sub-port group of two port groups are interconnected on the first switch board. For example, port 1 of port group 1 is interconnected with port 1 of port group 2. Port 3 of port group 3 is interconnected with port 1 of port group 7. It should be understood that Table 6 is only one example; there are other connection methods, but it is necessary to ensure that ports from different sub-port groups are not interconnected.

[0128] Table 4

[0129]

[0130] The following describes the Clos networking topology.

[0131] Clos networking:

[0132] In a CLOS network topology, the network equipment also includes a second switching board array. The second switching board array is vertically pluggable to the service board array. It should be noted that currently, the service board array on the network device is connected to the first switching board array (i.e., a mesh network). If a switch to a CLOS network is needed, the first switching board array can be unplugged from the network device, and the second switching board array can be vertically connected to the service board array. Conversely, if the service board array on the network device is currently connected to the second switching board array (i.e., a CLOS network), and a switch to a mesh network is needed, the second switching board array can be unplugged from the network device, and the first switching board array can be vertically connected to the service board array.

[0133] The second switching board array may include one or more second switching boards. Each second switching board may include one or more switching chips. Each processing chip in the service board array needs to be connected to each switching chip on the second switching board. The second switching board array includes M switching chips, where M is a positive integer. The value of M is related to service requirements and / or the number of ports on the processing chips. In some possible implementation scenarios, each processing chip has N-1 external ports, in which case M is a positive integer less than or equal to N-1. In other possible implementation scenarios, each processing chip has multiple spare ports, in which case the number of switching chips can be increased according to the number of spare ports and service requirements. Each of the M switching chips is connected to the N*L processing chips in the second switching board array to achieve CLOS networking.

[0134] The switching chip can have the function of transmitting electrical signals and transmitting data based on rules, and can provide a dedicated electrical signal path for any two processing chips connected to the switching chip. This application does not make any specific limitations.

[0135] The switching chip can store a routing table or a media access control (MAC) address table. This routing table or MAC address table can include multiple entries, each of which can represent a forwarding path. Each entry can include at least the source address, the destination address, and the corresponding next-hop address. After receiving a data packet sent by the processing chip, the switching chip can look up the routing table or MAC address table based on the source address and destination address carried in the data packet to obtain the forwarding path of the data packet, determine the next-hop address, and then forward the data packet to the next-hop address.

[0136] In specific implementations, if the switching chip is a Layer 2 switch (link layer switch), a MAC address table can be generated using switch forwarding algorithms such as Address Resolution Protocol (ARP), and the source and destination addresses can be MAC addresses. If the switching chip is a Layer 3 switch (network layer switch), a routing table can be generated using routing algorithms such as Routing Information Protocol (RIP) and Border Gateway Protocol (BGP), and the aforementioned source and destination addresses can be IP addresses; this application does not impose specific limitations on this.

[0137] In one possible implementation, the service board array can be deployed on a first housing, and the switching board array (either a first switching board array or a second switching board array) can be deployed on a second housing. The service board array and the switching board array are vertically pluggable connected through the first and second housings.

[0138] The box can refer to a chassis or other enclosure that serves to house and secure accessories, and to support and protect the various accessories inside the chassis. The box may include the outer shell, brackets, various switches and indicator lights on the panel, etc. The box may be made of a combination of steel plate and plastic, and this application does not make any specific limitation.

[0139] The solution provided in this application enables network devices to support both mesh and CLOS networking by replacing the switchboard (SW). Furthermore, through the aforementioned rotational deployment method, multiple SW boards maintain consistency or normalization in both CLOS and mesh networking, facilitating deployment. Using different SW boards on the network device provides greater application flexibility. It is suitable for both small-scale and large-scale networking scenarios. The network device provided in this application can also be applied to mixed mesh and CLOS networking scenarios.

[0140] The solution provided in this application embodiment is described below with specific examples. Taking an AI server as an example, with an SFU as the service board and an NPU as the processing chip, the following example is used.

[0141] The AI ​​server comprises 32 NPUs. Taking N=8 and L=4 as an example, the 32 NPUs form a 4x8 array. These 32 NPUs are deployed on 8 SPU boards. For ease of description, these 8 SPUs are referred to as SPU-1 to SPU-8. Each SPU board deploys 4 NPUs. Each NPU chip has 10 ports.

[0142] The AI ​​server includes four Switching Unit (SW) chips. Each SW chip has 32 ports. The NPUs between the SPU boards can be networked in either Mesh or Clos configurations. The AI ​​server can be equipped with interchangeable SW boards to support both Clos and Mesh networking.

[0143] See Figure 5A The diagram shows a mesh network topology diagram with 32 NPU chips. The 32 NPUs are arranged in a 4x8 array, with 4 NPUs horizontally (numbered D1 to D4) connected by mesh (each NPU provides 3 ports) and 8 NPUs vertically connected by mesh (each NPU provides 7 ports), forming a 4x8 mesh network.

[0144] See Figure 5B The diagram shows a CLOS network topology with 32 NPU chips. CLOS switching is performed by a Switching Module (SW) chip, and all 32 NPUs are connected to a single SW chip (for simplicity, the horizontal thick black lines represent one port from each NPU connected to the SW chip). One SW chip can be deployed on one SW board. In some possible implementation scenarios, multiple SW chips can be deployed on different SW boards. The number of SW chips on different SW boards can be the same or different. In some scenarios, to ensure consistency, the same number of SW chips can be deployed on different SW boards. Figure 5BAs an example, let's consider four Switching Module (SW) chips. Based on the number of ports on the NPU, it supports connecting at least seven SW chips. That is, the NPU has seven ports vertically that can be externally connected, thus supporting the connection of seven SW chips. Of course, the number of SW chips that can be connected can be selected according to needs. Each SW chip can include 32 ports for connecting to 32 NPUs.

[0145] Taking both mesh networking and clos networking as examples, where four switch boards are used, for easy distinction, the switch board in mesh networking is called SW1, and the switch board in clos networking is called SW2.

[0146] In a mesh network, eight SPU boards are connected to four SW1s via orthogonal connectors. See also Figure 6 As shown, in a mesh network, NPU chips with the same reference number on different SPU boards are connected via wires on orthogonal connectors on each SW board. Figure 6 In this configuration, the four SW1s are designated SW1-1, SW1-2, SW1-3, and SW1-4. The orthogonal connector comprises a pair of connectors: a first connector mounted on the SPU board and a second connector mounted on the SW1 board.

[0147] In a CLOS network, eight SPU boards are connected to four SW2 boards via orthogonal connectors. See also... Figure 7 As shown, in a CLOS network, all 32 NPU chips are connected to a single SW2 via orthogonal connectors. That is, each SW2 is connected to all 32 NPUs. Figure 7 In this configuration, the four SW2s are designated SW2-1, SW2-2, SW2-3, and SW2-4. The orthogonal connector comprises a pair of connectors: a first connector mounted on the SPU board and a third connector mounted on the SW2 board.

[0148] For example, Figure 8 This is a schematic diagram of the front-view connector layout for the AI ​​server. The AI ​​server is a chassis-type server. The SPU is horizontally inserted at the front of the chassis, and the SW board is vertically inserted at the rear of the chassis. The SPU board and SW board are connected orthogonally. Figure 8 In the example shown, both the first and second connectors have 7 ports. Each SPU includes 4 first connectors, and each first connector includes 7 ports. An SPU array consisting of 8 SPUs includes 32 first connectors. Each SW1 includes 8 second connectors with 7 ports each. Figure 8 In this configuration, each 7-port connector corresponds to one orthogonal connector, namely one 7-port first connector and one 7-port second connector.

[0149] The port connections of each orthogonal connector for the corresponding NPU can be configured using the rotation method described above. The four first connectors on each SPU are connected one-to-one with the four second connectors on the four SW boards. To ensure consistency across SWs, meaning the insertion positions of each SW are unrestricted, the ports on different first switching boards are connected in the same way. On each SPU board, the seven ports of the first connectors connected to the second connectors on the first switching board belong to the four NPUs.

[0150] During polling, the 112 connections (8-1)*8*4 / 2 = 112 can be grouped, for example, by NPU number (or processing chipset). Connections to NPUs with the same number are grouped into one connection group, resulting in 4 connection groups for the 112 connections. Each connection group contains 28 connections. Then, the connections within each connection group are further divided into 4 sub-connection groups. Each connection group is divided in the same way. Following the round-robin allocation principle, the connections in each sub-connection group of the 4 connection groups are sequentially assigned to the 4 switches. In the i-th poll, starting from the i-th sub-connection group of the i-th connection group, the connections in the i-th sub-connection group of the 4 connection groups are sequentially assigned to the 4 first switching boards. The value of i is a positive integer less than or equal to L.

[0151] As an example, see Figure 9 The diagram shown is a pin mapping diagram of a first connector and a second connector provided in this application, which can also be called a pin map. Figure 9 In the example, sub-connection group 1 includes 16 connections and sub-connection groups 2-4 each include 4 connections.

[0152] Figure 9 In the diagram, each row represents the pin map of four connectors for one SPU, and the pin maps for all eight SPU boards are identical. The intersection of the vertical columns SW1-1, SW1-2, SW1-3, and SW1-4 with the horizontal column represents a connector containing seven ports. Each empty space represents the number of an NPU chip; that is, the port corresponds to the NPU with the number specified within the empty space. Alternatively, each empty space can be understood as an NPU port number. However, it should be noted that different NPUs can have different port numbers. Figure 9 For ease of description, ports of the same NPU are assigned the same number. Using this method, port connections between NPUs with the same number on different SPUs are allocated to four SW1s.

[0153] Furthermore, combining the above groupings, it can be seen that ports 1-4 on SW1-1 implement 16 connections between the 8 SPU boards numbered D1, which can be understood as sub-connection group 1 in connection group 1. Figure 10 (referred to as Group 1 in Chinese), see [link / reference]. Figure 10 As shown. Port 5 on SW1-1 enables four connections between the eight SPU boards numbered D2, which can be understood as sub-connection group 2 within connection group 2. Port 6 on SW1-1 enables four connections between the eight SPU boards numbered D3, which can be understood as sub-connection group 3 within connection group 3. Port 7 on SW1-1 enables four connections between the eight SPU boards numbered D4, which can be understood as sub-connection group 4 within connection group 4. Ports 1-7 on SW1, as mentioned here, refer to ports 1-7 of the eight second connectors on SW1. For example, port 1 refers to port 1 of each of the eight second connectors on SW1.

[0154] Ports 1-4 on SW1-2 enable 16 connections between the eight SPU boards numbered D2, which can be understood as sub-connection group 1 in connection group 2. Port 5 on SW1-2 enables 4 connections between the eight SPU boards numbered D3, which can be understood as sub-connection group 2 in connection group 3. Port 6 on SW1-2 enables 4 connections between the eight SPU boards numbered D4, which can be understood as sub-connection group 3 in connection group 4. Port 7 on SW1-2 enables 4 connections between the eight SPU boards numbered D1, which can be understood as sub-connection group 4 in connection group 1.

[0155] Ports 1-4 on SW1-3 enable 16 connections between the eight SPU boards numbered D3, which can be understood as sub-connection group 1 in connection group 3. Port 5 on SW1-3 enables 4 connections between the eight SPU boards numbered D4, which can be understood as sub-connection group 2 in connection group 4. Port 6 on SW1-3 enables 4 connections between the eight SPU boards numbered D1, which can be understood as sub-connection group 3 in connection group 2. Port 7 on SW1-3 enables 4 connections between the eight SPU boards numbered D2, which can be understood as sub-connection group 4 in connection group 2.

[0156] Ports 1-4 on SW1-4 enable 16 connections between the eight SPU boards with chip number D4, which can be understood as sub-connection group 1 in connection group 4. Port 5 on SW1-4 enables 4 connections between the eight SPU boards with chip number D1, which can be understood as sub-connection group 2 in connection group 1. Port 6 on SW1-4 enables 4 connections between the eight SPU boards with chip number D2, which can be understood as sub-connection group 3 in connection group 2. Port 7 on SW1-4 enables 4 connections between the eight SPU boards with chip number D3, which can be understood as sub-connection group 4 in connection group 3.

[0157] Understandably, after the above-described rotational allocation, each SW1 completes 1 / 4 of the mesh connections on the AI ​​server. Four SW1s stacked together can complete the mesh connections for all 32 NPUs within the AI ​​server. To ensure complete consistency across all SW1 boards, the differences in connections need to be addressed using different pin map connectors on the SW1 boards.

[0158] The different connection methods on the connectors of each SW are called "rotation," meaning SW1-1 starts with D1, SW1-2 starts with D2, SW1-3 starts with D3, and SW1-4 starts with D4. The connectors of SW1-1 are connected with 4 D1 + 1 D2 + 1 D3 + 1 D4; the connectors of SW1-2 are connected with 4 D2 + 1 D3 + 1 D4 + 1 D1; the connectors of SW1-3 are connected with 4 D3 + 1 D4 + 1 D1 + 1 D2; and the connectors of SW1-4 are connected with 4 D4 + 1 D1 + 1 D2 + 1 D3.

[0159] See Figure 11 As shown, the mesh connection can be considered as a 360-degree disk, with each SW board occupying a 90-degree area. SW1 to SW4 are rotated 90 degrees each, perfectly covering the 360-degree disk. This rotation method achieves consistency or uniformity among the four SW1s. In other words, the internal wiring of the four SW1s is identical; their different placements result in different connection relationships. It should be understood that when the positions of the SW1s are swapped, the internal wiring of the repositioned SW1s enables connections to different NPU chips.

[0160] The following example illustrates the connection relationships between the ports included in each SW1.

[0161] Each of the eight second connectors on SW1 includes four groups of ports. For distinction, the eight second connectors are numbered second connectors 1-8. Ports within the same group on different second connectors are interconnected on SW1. Combining the port groups and sub-port groups mentioned above, a second connector includes seven ports, forming a port group. These seven port groups can be understood as seven sub-port groups. Referring to Table 6, each second connector includes seven ports, designated as port 1 through port 7. In each column of Table 6, the same number indicates that two ports within the same sub-port group of two second connectors are interconnected on SW1. For example, port 1 of second connector 1 is interconnected with port 1 of second connector 8. Port 3 of second connector 3 is interconnected with port 3 of second connector 5. It should be understood that Table 6 is only an example; other connection methods exist, such as those shown in Tables 3 and 5. Of course, besides the connection relationships in Tables 3, 5, and 6, there are other connection methods, which will not be illustrated in detail in this application.

[0162] Table 6

[0163]

[0164] In a CLOS network, each SW2 chip connects to four ports on each of the eight SPU boards, in order to... Figure 9 Taking the pin map shown as an example, each SW2 can connect to ports 4, 5, 6, and 7 of the SPU board to ensure that each NPU chip is connected to SW2. Alternatively, each SW2 can also connect to ports 1, 5, 6, and 7 of the SPU board to ensure that each NPU chip is connected to SW2. Alternatively, each SW2 can also connect to ports 2, 5, 6, and 7 of the SPU board to ensure that each NPU chip is connected to SW2. Alternatively, each SW2 can also connect to ports 3, 5, 6, and 7 of the SPU board to ensure that each NPU chip is connected to SW2.

[0165] As another example, see Figure 12 The diagram shown is a pin mapping relationship between another first connector and a second connector provided in this application. Figure 12 In the example, sub-connection group 1 includes 12 connections, sub-connection group 2 includes 8 connections, and sub-connection groups 3-4 include 4 connections.

[0166] Figure 12In the diagram, each row represents the pin map of four connectors for one SPU, and the pin maps for all eight SPU boards are identical. The intersection of the vertical columns SW1-1, SW1-2, SW1-3, and SW1-4 with the horizontal column represents a connector containing seven ports. Each empty space represents the number of an NPU chip, meaning that the port connected to that empty space is the port numbered within it. Alternatively, each empty space can be understood as an NPU port number. Using this method, port connections between NPUs with the same number on different SPUs are assigned to the four SW1 blocks.

[0167] Furthermore, combining the above groupings, it can be seen that ports 1, 2, and 4 on SW1-1 implement 12 connections between the 8 SPU boards numbered D1, which can be understood as sub-connection group 1 in connection group 1. Figure 12 (referred to as Group 1) is implemented by ports 1, 2, and 4. See [link / reference]. Figure 12 As shown. Ports 3 and 5 on SW1-1 enable 8 connections between the 8 chips numbered D2 on the 8 SPU boards. This can be understood as sub-connection group 2 in connection group 2 being implemented by ports 3 and 5. Port 6 on SW1-1 enables 4 connections between the 8 chips numbered D3 on the 8 SPU boards. This can be understood as sub-connection group 3 in connection group 3 being implemented by port 6. Port 7 on SW1-1 enables 4 connections between the 8 chips numbered D4 on the 8 SPU boards. This can be understood as sub-connection group 4 in connection group 4 being implemented by port 7.

[0168] Ports 1, 2, and 4 on SW1-2 enable 12 connections between the 8 SPUs numbered D2. This can be understood as sub-connection group 1 in connection group 2 being implemented by ports 1, 2, and 4. Ports 3 and 5 on SW1-2 enable 8 connections between the 8 SPUs numbered D3. This can be understood as sub-connection group 2 in connection group 3 being implemented by ports 3 and 5. Port 6 on SW1-2 enables 4 connections between the 8 SPUs numbered D4. This can be understood as sub-connection group 3 in connection group 4 being implemented by port 6. Port 7 on SW1-2 enables 4 connections between the 8 SPUs numbered D1. This can be understood as sub-connection group 4 in connection group 1 being implemented by port 7.

[0169] Ports 1, 2, and 4 on SW1-3 establish 12 connections between the eight SPUs numbered D3. This can be understood as sub-connection group 1 within connection group 3 being implemented by ports 1, 2, and 4. Ports 3 and 5 on SW1-3 establish 8 connections between the eight SPUs numbered D4. This can be understood as sub-connection group 2 within connection group 4 being implemented by ports 3 and 5. Port 6 on SW1-3 establishes 4 connections between the eight SPUs numbered D1. This can be understood as sub-connection group 3 within connection group 2 being implemented by port 6. Port 7 on SW1-3 establishes 4 connections between the eight SPUs numbered D2. This can be understood as sub-connection group 4 within connection group 2 being implemented by port 7.

[0170] Ports 1, 2, and 4 on SW1-4 enable 12 connections between the eight SPUs numbered D4. This can be understood as sub-connection group 1 within connection group 4 being implemented by ports 1, 2, and 4. Ports 3 and 5 on SW1-4 enable 4 connections between the eight SPUs numbered D1. This can be understood as sub-connection group 2 within connection group 1 being implemented by ports 3 and 5. Port 6 on SW1-4 enables 4 connections between the eight SPUs numbered D2. This can be understood as sub-connection group 3 within connection group 2 being implemented by port 6. Port 7 on SW1-4 enables 4 connections between the eight SPUs numbered D3. This can be understood as sub-connection group 4 within connection group 3 being implemented by port 7.

[0171] It should be noted that this application embodiment does not limit the port allocation method for different connections, but connections within the same sub-connection group must be assigned the same ports. When connections within the same sub-connection group require multiple ports on the same first connector, these ports may or may not be adjacent. For example, Figure 12 In this embodiment, the ports configured for the sub-connection group 1 on each of the first switching boards are 1, 2, and 4. Of course, ports 1-3 or other ports can also be configured, and this application does not limit this.

[0172] The following example illustrates the connection relationships between the ports included in each SW1.

[0173] Each of the eight second connectors on SW1 includes four groups of ports. For distinction, the eight second connectors are numbered second connectors 1-8. Ports within the same group on different second connectors are interconnected on SW1. Combining the port groups and sub-port groups mentioned above, a second connector includes seven ports, forming a port group. These seven groups of ports can be understood as seven sub-port groups. Referring to Table 7, each second connector includes seven ports, designated as port 1-port 7. In each column of Tables 7 and 8, the same number indicates that two ports within the same sub-port group of two port groups (or two second connectors) are interconnected on SW1. For example, in Table 7, port 1 of second connector 1 is interconnected with port 1 of second connector 2. Port 3 of second connector 3 is interconnected with port 1 of second connector 2. It should be understood that Tables 7 and 8 are merely examples; other connection methods exist, which will not be illustrated here. For example, combining Table 7 and... Figure 12 For example, port 1 of the second connector 1 and port 1 of the second connector 2 are connected to enable the connection between D1 on SPU-1 and D1 on SPU-2. Port 3 of the second connector 2 and port 3 of the second connector 3 are connected to enable the connection between D2 on SPU-2 and D2 on SPU-3. Furthermore, referring to Table 8 and... Figure 12 For example, port 1 of the second connector 1 and the second connector 8 are connected to enable the connection between D1 on SPU-1 and D1 on SPU-8. Port 3 of the second connector 2 and the second connector 5 are connected to enable the connection between D2 on SPU-2 and D2 on SPU-5.

[0174] Table 7

[0175]

[0176] Table 8

[0177]

[0178] In a CLOS network, each SW2 chip connects to four ports on each of the eight SPU boards, in order to... Figure 12 The pin map shown is an example. Each SW2 can connect to ports 4 (or 1 or 2), 5 (or 3), 6, and 7 of the SPU board, so that each NPU chip is connected to SW2.

[0179] As yet another example, see Figure 13A and Figure 13B The diagram shown illustrates the pin mapping relationship between a first connector and a second connector provided in this application. Figure 13A and Figure 14BIn the example, sub-connection group 1 includes 8 connections, sub-connection group 2 includes 8 connections, sub-connection group 3 includes 8 connections, and sub-connection group 4 includes 4 connections.

[0180] Figure 13A and Figure 13B In the diagram, each row represents the pin map of four connectors for one SPU, and the pin maps for all eight SPU boards are identical. The intersection of the vertical columns SW1-1, SW1-2, SW1-3, and SW1-4 with the horizontal column represents a connector containing seven ports. Each empty space represents the number of an NPU chip, meaning that the port connected to that empty space is the port numbered within it. Alternatively, each empty space can be understood as an NPU port number. Using this method, port connections between NPUs with the same number on different SPUs are assigned to the four SW1 blocks.

[0181] Furthermore, combining the above groupings, it can be seen that ports 1 and 4 on SW1-1 implement 8 connections between the 8 chips numbered D1 on the 8 SPU boards, which can be understood as sub-connection group 1 in connection group 1. Figure 13A (referred to as Group 1) is implemented by ports 1 and 4, see [link / reference]. Figure 13A As shown. Ports 2 and 5 on SW1-1 enable 8 connections between the 8 chips numbered D2 on the 8 SPU boards. This can be understood as sub-connection group 2 in connection group 2 being implemented by ports 3 and 5. Ports 3 and 6 on SW1-1 enable 8 connections between the 8 chips numbered D3 on the 8 SPU boards. This can be understood as sub-connection group 3 in connection group 3 being implemented by ports 3 and 6. Port 7 on SW1-1 enables 4 connections between the 8 chips numbered D4 on the 8 SPU boards. This can be understood as sub-connection group 4 in connection group 4 being implemented by port 7.

[0182] Ports 1 and 4 on SW1-2 establish eight connections between eight chips numbered D2 on the eight SPU boards. This can be understood as sub-connection group 1 in connection group 2 being implemented by ports 1 and 4. Ports 2 and 5 on SW1-2 establish eight connections between eight chips numbered D3 on the eight SPU boards. This can be understood as sub-connection group 2 in connection group 3 being implemented by ports 2 and 5. Ports 3 and 6 on SW1-2 establish eight connections between eight chips numbered D4 on the eight SPU boards. This can be understood as sub-connection group 3 in connection group 4 being implemented by ports 3 and 6. Port 7 on SW1-2 establishes four connections between eight chips numbered D1 on the eight SPU boards. This can be understood as sub-connection group 4 in connection group 1 being implemented by port 7.

[0183] Ports 1 and 4 on SW1-3 establish eight connections between eight chips numbered D3 on the eight SPU boards. This can be understood as sub-connection group 1 within connection group 3 being implemented by ports 1 and 4. Ports 2 and 5 on SW1-3 establish eight connections between eight chips numbered D4 on the eight SPU boards. This can be understood as sub-connection group 2 within connection group 4 being implemented by ports 2 and 5. Ports 3 and 6 on SW1-3 establish eight connections between eight chips numbered D1 on the eight SPU boards. This can be understood as sub-connection group 3 within connection group 2 being implemented by ports 3 and 6. Port 7 on SW1-3 establishes four connections between eight chips numbered D2 on the eight SPU boards. This can be understood as sub-connection group 4 within connection group 2 being implemented by port 7.

[0184] Ports 1 and 4 on SW1-4 establish eight connections between eight chips numbered D4 on the eight SPU boards. This can be understood as sub-connection group 1 within connection group 4 being implemented by ports 1 and 4. Ports 2 and 5 on SW1-4 establish eight connections between eight chips numbered D1 on the eight SPU boards. This can be understood as sub-connection group 2 within connection group 1 being implemented by ports 2 and 5. Ports 3 and 6 on SW1-4 establish eight connections between eight chips numbered D2 on the eight SPU boards. This can be understood as sub-connection group 3 within connection group 2 being implemented by ports 3 and 6. Port 7 on SW1-4 establishes four connections between eight chips numbered D3 on the eight SPU boards. This can be understood as sub-connection group 4 within connection group 3 being implemented by port 7.

[0185] It should be noted that the embodiments of this application do not limit the allocation method of different connections on the port, but the connections in the same sub-connection group need to be allocated the same port.

[0186] Figure 13B and Figure 13A The difference is that, Figure 13B The ports of the second connector used to implement the same sub-connection group are adjacent.

[0187] The following example illustrates the connection relationships between the ports included in each SW1.

[0188] Each of the eight second connectors on SW1 comprises four groups of ports. For distinction, the eight second connectors are numbered Second Connector 1-8. Ports within the same group on different second connectors are interconnected on SW1. Combining the port groups and sub-port groups mentioned above, a second connector comprising seven ports constitutes a port group. These seven port groups can be understood as seven sub-port groups. Referring to Tables 9 and 10, each second connector includes seven ports, designated as Port 1 through Port 7. Table 9... Figure 13A The grouping method shown in Table 10 is an example. Figure 13BTaking the grouping method shown as an example, in each column of Tables 9 and 10, the same number indicates that two ports in the same sub-port group within two port groups (or two second connectors) are interconnected on SW1. For example, in Table 9, port 1 of second connector 1 and port 1 of second connector 2 are interconnected. Port 3 of second connector 3 is interconnected with port 1 of second connector 2. It should be understood that Tables 9 and 10 are only examples, and there are other connection methods, which will not be illustrated in this application. For example, combining Table 9 and... Figure 13A For example, port 1 of the second connector 1 and port 1 of the second connector 2 are connected to enable the connection between D1 on SPU-1 and D1 on SPU-2. Port 3 of the second connector 2 and port 3 of the second connector 3 are connected to enable the connection between D3 on SPU-2 and D3 on SPU-3. Furthermore, referring to Table 10 and... Figure 13B For example, port 1 of the second connector 1 and port 1 of the second connector 2 are connected to enable the connection between D1 on SPU-1 and D1 on SPU-2. Port 3 of the second connector 2 and port 3 of the second connector 3 are connected to enable the connection between D2 on SPU-2 and D2 on SPU-5.

[0189] Table 9

[0190]

[0191] Table 10

[0192]

[0193] In a CLOS network, each SW2 chip connects to four ports on each of the eight SPU boards. Figure 13A Taking the pin map shown as an example, each SW2 can connect to ports 4 (or 1 or 2), 5 (or 2), 6 (or 3), and 7 of the SPU board, ensuring that each NPU chip is connected to an SW2. Figure 13B Taking the pin map shown as an example, each SW2 can connect to port 1 (or port 2), 3 (or port 4), 5 (or port 6) and 7 of the SPU board to ensure that each NPU chip is connected to SW2.

[0194] It should be understood that the above embodiment takes N=8 and L=4 as an example. The quantities of N and L can be increased or decreased, and can be designed according to requirements. In some possible implementation scenarios, N can be an even number, and L can be either an odd or even number.

[0195] The solution provided in this application enables network devices to support both mesh and CLOS networking by replacing the switch (SW) board. Furthermore, the solution provided in this application ensures consistency or normalization among multiple SW boards in both CLOS and mesh networking, facilitating deployment. Using different SW boards on the network device provides greater application flexibility. It is suitable for both small-scale and large-scale networking scenarios. The network device provided in this application can also be applied to mixed mesh and CLOS networking scenarios.

[0196] Based on the above embodiments, this application also provides a networking method, see [link to relevant documentation]. Figure 14A and Figure 14B As shown. This networking method can be implemented by a networking device or by electronic devices that deploy the networking device. Electronic devices can be, for example, industrial robots or other devices capable of networking.

[0197] In a mesh networking scenario, the S1401a allows for a vertically pluggable connection between the service board array and the first switching board array.

[0198] S1402a, when switching from a mesh networking scenario to a CLOS networking scenario, the first switching board array is replaced by a second switching board array and connected to the service board array in a pluggable manner.

[0199] The service board array comprises N service boards; each of the N service boards comprises L processing chips, which are meshed together on the service boards; N and L are both positive integers greater than 1; the first switching board array is used to implement mesh connections between the N processing chips belonging to different service boards; the second switching board array comprises M switching chips, each of the M switching chips is connected to the N*L processing chips included in the second switching board array, where M is a positive integer.

[0200] S1401b, in a CLOS networking scenario, the service board array and the second switching board array are vertically pluggable connected.

[0201] S1402b, when switching from CLOS networking to mesh networking, the second switching board array is replaced by the first switching board array, which is pluggably connected to the service board array.

[0202] In one possible implementation, the service board array is vertically pluggable connected to the first switching board array, which includes: vertically pluggable connecting the service board array to the first switching board array via a chassis.

[0203] In one possible implementation, vertically pluggable connection of the service board array to the second switching board array includes: vertically pluggable connection of the service board array to the second switching board array via a chassis.

[0204] The connection method between the service board array and the first switching board array has been described previously and will not be repeated here. The connection method between the service board array and the second switching board array has been described previously and will not be repeated here.

[0205] The methods of the embodiments of this application have been described in detail above, and the apparatus of the embodiments of this application is provided below.

[0206] Please see Figure 15 , Figure 15 This is a schematic diagram of a networking device provided in an embodiment of this application. The device has the functions described above. Figure 14A or Figure 14B The networking method shown has the following functions. These functions can be implemented through hardware or through hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0207] In one possible implementation, the device includes a first connection unit 1501 and a second connection unit 1502.

[0208] The first connection unit 1501 is used to vertically plug and play the service board array with the first switching board array in a mesh networking scenario; the second connection unit 1502 is used to replace the first switching board array with the second switching board array and plug and play the service board array when switching from a mesh networking scenario to a CLOS networking scenario.

[0209] Alternatively, the first connection unit 1501 is used to vertically pluggable connect the service board array and the second switch board array in a CLOS networking scenario; the second connection unit 1502 is used to replace the second switch board array with the first switch board array and pluggable connect them to the service board array when switching from a CLOS networking scenario to a mesh networking scenario.

[0210] The connection method between the service board array and the first switching board array has been described previously and will not be repeated here. The connection method between the service board array and the second switching board array has been described previously and will not be repeated here.

[0211] Please see Figure 16 , Figure 16This is a schematic diagram of the structure of an electronic device 1600 provided in an embodiment of this application. The electronic device 1600 includes a processor 1601, a memory 1602, and a communication interface 1603, which are interconnected via a bus 1604.

[0212] The memory 1602 includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or compact disc read-only memory (CD-ROM), and is used to store related computer programs and data. The communication interface 1603 is used to receive and transmit data.

[0213] Processor 1601 can be one or more central processing units (CPUs). When processor 1601 is a CPU, the CPU can be a single-core CPU or a multi-core CPU.

[0214] This electronic device can be a computer, virtual machine, server, cloud device, etc. The processor 1601 in this electronic device 1600 is used to read the computer program code stored in the aforementioned memory 1602 and execute it. Figure 14A and Figure 14B The method of any of the embodiments shown.

[0215] It should be noted that, Figure 16 The implementation of each operation of the described electronic device 1600 can also be referred to accordingly. Figures 2 to 6 The corresponding description of the illustrated embodiments. Furthermore, Figure 16 The beneficial effects of the described electronic device 1600 can be referred to Figures 2 to 6 The corresponding descriptions of the embodiments shown will not be repeated here.

[0216] This application embodiment also provides a chip, including: a processor, configured to retrieve and run a computer program from a memory, causing a device equipped with the chip to perform actions such as... Figure 14A and Figure 14B The method of any of the embodiments shown.

[0217] This application also provides a computer-readable storage medium storing programs and instructions for execution by a device, which, when run on an electronic device, Figure 14A and Figure 14B The method and flow shown are thus implemented.

[0218] This application also provides a computer program product, including a computer program, which, when run by an electronic device... Figure 14A and Figure 14B The method and flow shown are thus implemented.

[0219] It should be understood that the processor mentioned in the embodiments of this application can be a CPU, or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0220] It should also be understood that the memory mentioned in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0221] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) is integrated into the processor.

[0222] It should be noted that the memories described herein are intended to include, but are not limited to, these and any other suitable types of memories.

[0223] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0224] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0225] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0226] In addition, the functional units in the various embodiments of this application can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0227] The steps in the method of this application embodiment can be adjusted, combined, or deleted according to actual needs. The modules in the device of this application embodiment can be combined, divided, or deleted according to actual needs.

[0228] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A network device, characterized in that, Including service board arrays; The service board array includes N service boards; each of the N service boards includes L processing chips, and the L processing chips are meshed together on the service boards; N and L are both positive integers greater than 1. The network device further includes a first switching board array, and the service board array is vertically pluggable to the first switching board array; the first switching board array is used to realize mesh connection between N processing chips belonging to different service boards; or, The network device further includes a second switching board array, and the service board array is vertically pluggable connected to the second switching board array; the second switching board array includes M switching chips, and each of the M switching chips is connected to N*L processing chips included in the second switching board array, where M is a positive integer.

2. The network device as described in claim 1, characterized in that, It also includes a chassis, with the service board array and the first switching board array vertically inserted on both sides of the chassis, or the service board array and the second switching board array vertically inserted on both sides of the chassis.

3. The network device as described in claim 1 or 2, characterized in that, The connection between the service board array and the first switching board array is a backplane-less orthogonal connection; or... The connection between the service board array and the second switching board array is a backplane-less orthogonal connection.

4. The network device according to any one of claims 1-3, characterized in that, The number of connections between N processing chips belonging to different service boards is (N-1)*N*L / 2; the first switching board array includes L first switching boards, and each first switching board is used to implement (N-1)*N / 2 connections.

5. The network device as described in claim 4, characterized in that, The (N-1)*N*L / 2 connections are divided into L connection groups. The kth connection group includes connections between the kth processing chips on the N service boards. The kth connection group is further divided into L sub-connection groups, where k is less than or equal to L. The third switching board is used to implement the connections included in the L sub-connection groups. The third switching board is any one of the L first switching boards. The L sub-connection groups to which the connections implemented by the third switching board belong are different connection groups.

6. The network device as described in claim 5, characterized in that, The kth sub-connection group in different connection groups contains the same number of connections.

7. The network device as described in claim 5 or 6, characterized in that, The ports of the third switching board are divided into N port groups. The third switching board is any one of the L first switching boards. The N port groups are connected one-to-one with the ports on the N service boards. The first port group includes L sub-port groups. The first port group is any one of the N port groups. The ports in the j-th sub-port group of the N port groups are interconnected on the third switching board. The value of j is a positive integer less than or equal to L.

8. The network device according to any one of claims 1-7, characterized in that, The service board array is provided with multiple first connectors, and the first switching board array is provided with multiple second connectors. The multiple first connectors of the service board array are connected one-to-one with the multiple second connector arrays of the second switching board array.

9. The network device as described in claim 8, characterized in that, The first service board includes L first connectors, and the first service board is any one of the N service boards; the third switching board includes N second connectors, and the third switching board is any one of the L first switching boards; one first connector includes N-1 ports corresponding to a processing chip on the first service board, and the second connector includes N-1 ports; Each of the N second connectors in the third switching board includes L groups of ports. The processing chips corresponding to the first connectors to which the ports connected to the first port group belong are different from those corresponding to the first connectors to which the ports connected to the second port group belong. The first port group and the second port group are any one of the L groups of ports. The pairs of ports on the N second connectors that correspond to the j-th group are interconnected on the third switching board, where j is a positive integer less than or equal to L.

10. The network device as described in claim 9, characterized in that, The j-th group of any two second connectors belonging to different first switching boards includes the same number of ports.

11. The network device as described in claim 9 or 10, characterized in that, The first connector to which the port connected to the j-th group of ports on the third connector belongs corresponds to the first processing chip. The third connector is a second connector of the third switching board. The first connector to which the port connected to the j-th group of ports on the fourth connector belongs corresponds to the second processing chip. The fourth connector is a second connector of the fourth switching board. The first processing chip and the second processing chip are two processing chips on the same service board. The third switching board and the fourth switching board are two switching boards among L first switching boards.

12. A networking method, characterized in that, The method includes: In a mesh networking scenario, the service board array is vertically pluggable connected to the first switching board array; and when switching from a mesh networking scenario to a CLOS networking scenario, the first switching board array is replaced by a second switching board array that is pluggable connected to the service board array; wherein, the service board array includes N service boards; each of the N service boards includes L processing chips, and the L processing chips are meshed on the service boards; N and L are both positive integers greater than 1; the first switching board array is used to realize the mesh connection between the N processing chips belonging to different service boards; the second switching array includes M switching chips, and each of the M switching chips is connected to the N*L processing chips included in the second switching board array, where M is a positive integer; or, In a CLOS networking scenario, the service board array is vertically pluggable connected to the second switch board array; and when switching from a CLOS networking scenario to a mesh networking scenario, the second switch board array is replaced by the first switch board array, which is pluggable connected to the service board array.

13. The method as described in claim 12, characterized in that, The service board array is vertically pluggable connected to the first switching board array, including: vertically pluggable connecting the service board array to the first switching board array via a chassis; or, Connecting the service board array to the second switching board array in a vertically pluggable manner includes: connecting the service board array to the second switching board array in a vertically pluggable manner via a chassis.

14. The method as described in claim 12 or 13, characterized in that, The connection between the service board array and the first switching board array is a backplane-less orthogonal connection; or... The connection between the service board array and the second switching board array is a backplane-less orthogonal connection.

15. The method according to any one of claims 12-14, characterized in that, The number of connections between N processing chips belonging to different service boards is (N-1)*N*L / 2; the first switching board array includes L first switching boards, and each first switching board is used to implement (N-1)*N / 2 connections.

16. The method as described in claim 15, characterized in that, The (N-1)*N*L / 2 connections are divided into L connection groups. The kth connection group includes connections between the kth processing chips on the N service boards. The kth connection group is further divided into L sub-connection groups, where k is less than or equal to L. The third switching board is used to implement the connections included in the L sub-connection groups. The third switching board is any one of the L first switching boards. The L sub-connection groups to which the connections implemented by the third switching board belong are different connection groups.

17. The method as described in claim 16, characterized in that, The kth sub-connection group in different connection groups contains the same number of connections.

18. The method as described in claim 16 or 17, characterized in that, The ports of the third switching board are divided into N port groups. The third switching board is any one of the L first switching boards. The N port groups are connected one-to-one with the ports on the N service boards. The first port group includes L sub-port groups. The first port group is any one of the N port groups. The ports in the j-th sub-port group of the N port groups are interconnected on the third switching board. The value of j is a positive integer less than or equal to L.

19. The method according to any one of claims 12-18, characterized in that, The service board array is provided with multiple first connectors, and the first switching board array is provided with multiple second connectors. The multiple first connectors of the service board array are connected one-to-one with the multiple second connector arrays of the second switching board array.

20. The method as described in claim 19, characterized in that, The first service board includes L first connectors, and the first service board is any one of the N service boards; the third switching board includes N second connectors, and the third switching board is any one of the L first switching boards; one first connector includes N-1 ports corresponding to a processing chip on the first service board, and the second connector includes N-1 ports; Each of the N second connectors in the third switching board includes L groups of ports. The processing chips corresponding to the first connectors to which the ports connected to the first port group belong are different from those corresponding to the first connectors to which the ports connected to the second port group belong. The first port group and the second port group are any one of the L groups of ports. The pairs of ports on the N second connectors that correspond to the j-th group are interconnected on the third switching board, where j is a positive integer less than or equal to L.

21. The method as described in claim 20, characterized in that, The j-th group of any two second connectors belonging to different first switching boards includes the same number of ports.

22. The method as described in claim 20 or 21, characterized in that, The first connector to which the port connected to the j-th group of ports on the third connector belongs corresponds to the first processing chip. The third connector is a second connector of the third switching board. The first connector to which the port connected to the j-th group of ports on the fourth connector belongs corresponds to the second processing chip. The fourth connector is a second connector of the fourth switching board. The first processing chip and the second processing chip are two processing chips on the same service board. The third switching board and the fourth switching board are two switching boards among L first switching boards.

23. A networking device, characterized in that, Including processor and memory; The memory is used to store computer programs; The processor is configured to execute a computer program stored in the memory, so that the networking device performs the method as described in any one of claims 12-22.

24. A computer-readable storage medium, characterized in that, It includes programs and instructions, which, when run on a processor, execute the method as described in any one of claims 12-22.

25. A computer program product, characterized in that, It includes a computer program, which, when run by an electronic device, causes the electronic device to perform the method as described in any one of claims 12-22.

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