Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention relates to a solar cell, a preparation method thereof and a photovoltaic module. The solar cell comprises a substrate, a first doped conductive layer and a first grid line, the first doped conductive layer and the first grid line are sequentially arranged on the backlight face of the substrate, the first doped conductive layer comprises a first area in the middle and a second area outside the first area, and the first area comprises an edge area close to the second area and a middle area away from the second area. The second area, the edge area and the middle area are arranged in the first direction, the middle area comprises a first middle sub-area and a second middle sub-area, the first middle sub-area is configured to be an area corresponding to the first grid line in position, the two sub-areas are alternately arranged in the second direction, and the first direction intersects with the second direction; the edge region is provided with a convex microstructure, and the roughness Ra1 of the edge region, the roughness Ra2 of the second middle sub-region and the roughness Ra3 of the second region meet Ra1gt; ra1, Ra2, Ra1gt; and Ra3. The solar cell can improve the power generation efficiency of the backlight surface and improve the double-sided rate.

Description

Technical Field

[0001] This application relates to the field of solar cells, and in particular to solar cells and their preparation methods, and photovoltaic modules. Background Technology

[0002] In solar cells, when light shines on the back surface, there is a problem of light escape, which makes it difficult to improve the bifaciality of the solar cell and ultimately affects the photoelectric performance of the solar cell. Summary of the Invention

[0003] This application discloses a solar cell and its fabrication method, as well as a photovoltaic module, to solve the problem of light escape from the back of a solar cell.

[0004] To achieve the above objectives, in a first aspect, this application discloses a solar cell, said solar cell comprising: A substrate with a backlight, a patterned first doped conductive layer, and a first gate line, wherein the first gate line is in electrical contact with a portion of the first doped conductive layer; The first doped conductive layer is disposed on the backlight surface of the substrate. The first doped conductive layer includes a first region located in the middle and a second region located outside the first region. The first region includes an edge region adjacent to the second region and a middle region away from the second region. The middle region includes a first middle sub-region and a second middle sub-region located outside the first middle sub-region. The first middle sub-region is configured to correspond to the region of the first gate line. The second region, the edge region, and the middle region are arranged along a first direction. The first middle sub-region and the second middle sub-region are arranged alternately along a second direction. The first direction and the second direction intersect. In the edge region, the surface of the first doped conductive layer is provided with a plurality of protruding microstructures; the surface roughness of the first doped conductive layer in the edge region is Ra1, the surface roughness of the first doped conductive layer in the second intermediate sub-region is Ra2, and the surface roughness of the first doped conductive layer in the second region is Ra3, where Ra1>Ra3 and Ra1>Ra2.

[0005] Furthermore, the protruding microstructure includes one or more of a hemispherical structure, a columnar structure, or an island structure; and / or, The maximum distance between any two points on the outer contour of the protruding microstructure is 0.05 μm to 0.5 μm.

[0006] Further, the surface reflectivity of the first doped conductive layer in the edge region is R1, the surface reflectivity of the first doped conductive layer in the second intermediate sub-region is R2, and the surface reflectivity of the first doped conductive layer in the second region is R3, where R1 < R3 and R1 < R2.

[0007] Further, in the first intermediate sub-region, a plurality of the convex microstructures are provided on the surface of the first doped conductive layer facing away from the substrate, and the first intermediate sub-region satisfies at least one of the following conditions: (1) The roughness Ra4 of the surface of the first doped conductive layer in the first intermediate sub-region facing away from the substrate satisfies Ra4 > Ra1 > Ra3 and Ra4 > Ra1 > Ra2; (2) The density of the convex microstructures in the first intermediate sub-region is greater than the density of the convex microstructures in the edge region; (3) The reflectivity of the first intermediate sub-region is R4, where R4 < R1 < R3 and R4 < R1 < R2.

[0008] Further, the density of the convex microstructures in the first intermediate sub-region is 10 per μm 2 ~30 per μm 2 and the density of the convex microstructures in the edge region is 1 per μm 2 ~10 per μm 2 .

[0009] Further, an intrinsic layer and a second doped conductive layer are sequentially provided on the surface of the first doped conductive layer in the second region facing away from the substrate, and the first doped conductive layer and the second doped conductive layer have different conductivity types.

[0010] Further, the convex microstructures are the remaining structures of the intrinsic layer in the edge region; the crystallization rate of the edge region is X1, the crystallization rate of the second intermediate sub-region is X2, the crystallization rate of the second region is X3, and the crystallization rate of the first intermediate sub-region is X4, where X2 > X4 > X1 > X3; and / or, The reflectivity R3' of the surface of the second doped conductive layer in the second region facing away from the substrate satisfies R3' < R3, and R4 < R1 < R3' < R2.

[0011] Further, X1 is 91.5% - 92.5%, X2 is 92.5% - 93.5%, X3 is 91.0% - 92.0%, and X4 is 92.0% - 93.0%; and / or, R1 is 25% - 30%, R2 is 30% - 35%, R3' is 30% - 35%, and R4 is 15% - 25%.

[0012] Furthermore, a transparent conductive layer is provided on the surface of the second doped conductive layer facing away from the substrate, on the protruding microstructure in the edge region, on the protruding microstructure in the first intermediate sub-region, and on the surface of the first doped conductive layer in the second intermediate sub-region facing away from the substrate; and / or, The thickness of the intrinsic layer is 1 nm to 10 nm, the thickness of the second doped conductive layer is 2 nm to 15 nm, and the thickness ratio of the intrinsic layer to the second doped conductive layer is 1:(1.4 to 1.8).

[0013] Furthermore, the length of the first gate line along the first direction is less than or equal to the length of the first intermediate sub-region along the first direction.

[0014] Further, the ratio of the length of the first intermediate sub-region along the first direction to the length of the first gate line along the first direction is greater than or equal to 2; and / or, The length of the first intermediate sub-region along the first direction is 50 μm to 100 μm; and / or, The length of the first gate line along the first direction is 5 μm to 30 μm.

[0015] Furthermore, the height of the first gate line is 7.5 μm to 45 μm; and / or, The length of the edge region along the first direction is 2 μm to 10 μm; and / or, The length of the first intermediate sub-region along the second direction is 15 μm to 30 μm.

[0016] Furthermore, the solar cell also includes: A patterned second doped conductive layer is disposed in a third region on the backlight surface of the substrate, and the patterned second doped conductive layer and the patterned first doped conductive layer are interdigitated. A transparent conductive layer and a second gate line are sequentially disposed on the patterned second doped conductive layer opposite to the surface of the substrate. The solar cell further includes an intrinsic layer disposed between the substrate and the patterned second doped conductive layer, and a dielectric layer disposed between the substrate and the patterned first doped conductive layer; The substrate has a light-receiving surface, and a first passivation layer and an anti-reflection layer are sequentially disposed on the light-receiving surface of the substrate.

[0017] Further, the height difference between the surface of the transparent conductive layer in the third region facing away from the substrate and the light-receiving surface of the substrate is h1, and the height difference between the adjacent interface of the dielectric layer and the substrate and the light-receiving surface of the substrate is h2, where h1 < h2; and there is a gap between the transparent conductive layer in the second region and the transparent conductive layer in the third region; and / or, The dielectric layer has micropores that open along the thickness direction of the dielectric layer, and the pore size of the micropores is 0.5 nm to 2 nm.

[0018] Secondly, this application provides a method for fabricating a solar cell, wherein the solar cell is the solar cell described in the first aspect, and the fabrication method includes the following steps: Patterning Processing: The first doped conductive layer disposed on the backlight surface of the substrate is patterned to obtain a patterned first doped conductive layer; wherein, the patterned first doped conductive layer includes a first region located in the middle and a second region located outside the first region, the first region includes an edge region adjacent to the second region and a middle region away from the second region, the middle region includes a first middle sub-region and a second middle sub-region located outside the first middle sub-region, the first middle sub-region is configured to be a region whose position corresponds to the first gate line; the second region, the edge region, and the middle region are arranged along a first direction, the first middle sub-region and the second middle sub-region are arranged alternately along a second direction, and the first direction and the second direction intersect; Surface treatment: A plurality of raised microstructures are formed on the surface of the first doped conductive layer located in the edge region, so that the surface roughness of the first doped conductive layer in the edge region is Ra1, the surface roughness of the first doped conductive layer in the second intermediate sub-region is Ra2, and the surface roughness of the first doped conductive layer in the second region is Ra3, where Ra1>Ra3 and Ra1>Ra2. Fabricating the first gate line: The first gate line is disposed on the first intermediate sub-region.

[0019] Furthermore, the surface treatment steps include: The first doped conductive layer after patterning is laser-grooved. The laser grooving process parameters include: laser wavelength of 266 nm to 532 nm, laser spot overlap rate of -10% to 0%, and relative power of 20% to 60%.

[0020] Furthermore, after laser grooving, the raised microstructure is obtained in the first intermediate sub-region, and the density of the raised microstructure in the first intermediate sub-region is greater than the density of the raised microstructure in the edge region.

[0021] Furthermore, prior to the patterning process, the preparation method further includes: Preparation of dielectric layer: The dielectric layer is prepared on the substrate; Preparation of the first doped conductive layer: The first doped conductive layer is prepared on the surface of the dielectric layer, and a doped glass layer is also formed on the first doped conductive layer; A mask layer is prepared on the surface of the doped glass layer.

[0022] Furthermore, the graphical processing steps include: Remove the mask layer and the doped glass layer in the third region, which is the region outside the first and second regions; First wet cleaning: Remove the first doped conductive layer and the dielectric layer in the third region, remove the film layers on the side surface and the light-receiving surface of the substrate, remove the mask layer and the doped glass layer in the first region and the second region, so that the light-receiving surface of the substrate and the backlight surface of the third region form a textured structure.

[0023] Furthermore, after the first wet cleaning and before the surface treatment, the preparation method further includes: Preparation of passivation layer: depositing a first passivation layer on the light-receiving surface of the substrate, and depositing a second passivation layer on the first doped conductive layer on the back-light surface of the substrate; Preparation of antireflection layer: Deposit the antireflection layer on the surface of the first passivation layer opposite to the substrate to obtain a first semi-finished product; Sintering: The first semi-finished product is processed at 730℃~750℃ for 30 s~90 s to obtain the second semi-finished product; Photoinjection: The second semi-finished product is processed at 600℃~700℃ for 10 s~60 s to obtain the third semi-finished product; The second passivation layer and the anti-reflection layer on the second passivation layer are removed from the third semi-finished product to obtain the fourth semi-finished product; Preparation of intrinsic layer: The intrinsic layer is prepared on the back side of the fourth semi-finished product, wherein the back side is the backlight side of the substrate; Preparation of a second doped conductive layer: The second doped conductive layer is prepared on the surface of the intrinsic layer.

[0024] Further, the surface treatment steps include: laser grooving to remove the second doped conductive layer and the intrinsic layer located in the second intermediate sub-region until the substrate is exposed; removing the second doped conductive layer located in the edge region and the first intermediate sub-region to obtain a patterned second doped conductive layer; removing a portion of the intrinsic layer in the edge region and the first intermediate sub-region, leaving a retained structure formed by the remaining intrinsic layer, the retained structure being the protruding microstructure; and / or, Following the surface treatment step, the preparation method further includes a second wet cleaning to remove laser residue from the first intermediate sub-region and the edge region.

[0025] Furthermore, after the second wet cleaning step, the preparation method further includes: Fabrication of a transparent conductive layer: Depositing the transparent conductive layer on the backlight surface of the substrate having a patterned first doped conductive layer and a patterned second doped conductive layer; A designated area of ​​the transparent conductive layer is locally etched to expose the surfaces of a portion of the first doped conductive layer and a portion of the second doped conductive layer. The designated area corresponds to the region where the transparent conductive layer located at the junction of the third region and the second region is disconnected. Fabrication of the first gate line and the second gate line: The first gate line is fabricated on the transparent conductive layer in the first intermediate sub-region, and the second gate line is fabricated on the transparent conductive layer in the third region.

[0026] Thirdly, embodiments of this application provide a photovoltaic module, the photovoltaic module comprising the solar cell as described in the first aspect, or the photovoltaic module comprising the solar cell prepared by the preparation method of the second aspect.

[0027] Compared with the prior art, the beneficial effects of this application are as follows: The solar cell of this application can improve the light utilization rate of the back surface, improve the light escape phenomenon of the back surface, help improve the power generation efficiency of the back surface, and thus effectively improve the bifaciality of the solar cell.

[0028] The first doped conductive layer is a patterned structure disposed on the back surface of the substrate. This layer has a first region and a second region located outside the first region. In this application, the first region is configured such that it includes an edge region near the second region and a middle region away from the second region. The second region, the edge region, and the middle region are arranged along a first direction. The middle region includes alternating first and second intermediate sub-regions arranged along a second direction, where the first and second directions intersect. The first intermediate sub-region is configured to contact the first gate line, and the second intermediate sub-region is configured not to contact the first gate line; therefore, the second intermediate sub-region occupies a larger proportion of the middle region. The surface of the first doped conductive layer located in the edge region has a surface structure with several raised microstructures. The surface roughness of the first doped conductive layer in the edge region away from the substrate is Ra1; the surface roughness of the first doped conductive layer in the second intermediate sub-region away from the substrate is Ra2; and the surface roughness of the first doped conductive layer in the second region away from the substrate is Ra3, where Ra1>Ra3 and Ra1>Ra2. This allows the first doped conductive layer in the edge region to effectively reduce reflectivity compared to the first doped conductive layer in the second intermediate sub-region and the first doped conductive layer in the second region. With this configuration, when the back surface of the solar cell is illuminated, the edge region can utilize its rougher surface and lower reflectivity to capture more light, improve light utilization, and mitigate light escape from the back surface of the solar cell. This increases the number of charge carriers generated on the back surface, improves the power generation efficiency of the back surface, and ultimately effectively enhances the bifaciality of the solar cell. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a cross-sectional schematic diagram of the first type of solar cell provided in the embodiments of this application; Figure 2 yes Figure 1 Top view of the first doped conductive layer in region I; Figure 3 yes Figure 2 Exploded view; Figure 4 yes Figure 3 Exploded view of the first area in the middle; Figure 5 yes Figure 4 Exploded view of the central area; Figure 6This is a schematic diagram of the protruding microstructure of the solar cell provided in the embodiments of this application; Figure 7 This is a top view of the first doped conductive layer of the second type of solar cell provided in this application embodiment; Figure 8 This is a cross-sectional schematic diagram of the second type of solar cell provided in the embodiments of this application; Figure 9 yes Figure 8 A magnified view of a portion of region II; Figure 10 This is a schematic diagram showing the positional relationship between the first doped conductive layer and the first grid line of the second type of solar cell provided in this application embodiment (transparent conductive layer omitted). Figure 11 yes Figure 10 A magnified view of a portion of region III; Figure 12 This is a process flow diagram of the solar cell fabrication method provided in the embodiments of this application; Figure 13 This is a schematic diagram illustrating the process from preparing the dielectric layer to preparing the mask layer, as provided in the embodiments of this application. Figure 14 This is a schematic diagram of the graphical processing provided in the embodiments of this application; Figure 15 This is a schematic diagram of the preparation of the passivation layer to the removal of the second passivation layer in the third semi-finished product and the anti-reflection layer on the second passivation layer, provided in the embodiments of this application; Figure 16 This is a schematic diagram of the preparation of the intrinsic layer and the second doped conductive layer according to an embodiment of this application; Figure 17 This is a schematic diagram of the surface treatment in an embodiment of this application; Figure 18 This is a schematic diagram of the preparation of the transparent conductive layer and local etching in an embodiment of this application; Figure 19 This is a schematic diagram of the fabrication of the gate lines according to an embodiment of this application; Figures 20-23 This is a topographic image of the first doped conductive layer away from the substrate surface in Embodiment 1 of this application.

[0031] Explanation of reference numerals in the attached figures: A. First region; A1. Edge region; A2. Middle region; A21. First middle sub-region; A22. Second middle sub-region; B. Second region; C. Third region; 1. Substrate; 2. First doped conductive layer; 21. Doped glass layer; 22. Mask layer; 31. First gate line; 32. Second gate line; 40. Protruding microstructure; 4. Intrinsic layer; 5. Second doped conductive layer; 6. Transparent conductive layer; 7. Dielectric layer; 8. Passivation layer; 81. First passivation layer; 82. Second passivation layer; 9. Anti-reflection layer. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0034] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0035] Furthermore, the terms "installation," "setup," "equipped with," "connection," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0036] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, components, or parts (which may be the same or different in specific type and construction), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, components, or parts. Unless otherwise stated, "a plurality of" means two or more.

[0037] In solar cells, the flat structure of the back surface lacks microstructures capable of diffuse reflection or light scattering. This results in high reflectivity but unidirectional reflection, making it difficult for incident light to undergo effective multiple reflections within the solar cell. Consequently, most of the incident light is directly reflected out of the cell, leading to significant light escape loss. Furthermore, the back surface of the solar cell contains grid lines made of metallic materials, which further enhance reflection and reduce light utilization. This is especially pronounced in back-contact solar cells, where all grid lines are located on the back surface. Due to this light escape problem, the low light utilization of incident light on the back surface affects its photoelectric conversion efficiency, ultimately limiting the bifaciality of the solar cell.

[0038] Based on the analysis of the causes of the above-mentioned technical problems, the embodiments of this application provide a solar cell and its preparation method, as well as a photovoltaic module. By optimizing the structure of the back surface of the solar cell, the above-mentioned technical problems are solved, the utilization rate of light on the back surface is improved, the light escape phenomenon on the back surface is reduced, and the power generation efficiency of the back surface is improved, thereby effectively improving the bifaciality of the solar cell.

[0039] The technical solutions provided in this application will be further described below with reference to the embodiments and accompanying drawings.

[0040] Combination Figures 1 to 5 As shown, Figure 1 This is a schematic cross-sectional view of a solar cell according to an embodiment of this application, wherein the cross-section is a cross-section along the thickness direction of the solar cell. Figure 2 This is a top view of the first doped conductive layer 2 in the solar cell region I of this application embodiment, specifically a schematic diagram of the first doped conductive layer 2 viewed from the side facing away from the substrate. Figure 3 yes Figure 2 Explosion diagram, Figure 4 yes Figure 3 Exploded view of region A in the first part. Figure 5 yes Figure 4 Exploded view of the central area A2.

[0041] This application provides a solar cell, such as... Figure 1 As shown, the solar cell includes: a substrate 1 with a backlight surface, a patterned first doped conductive layer 2, and a first grid line 31, wherein the first grid line 31 is in contact with a portion of the first doped conductive layer 2.

[0042] like Figures 1-3 As shown, a first doped conductive layer 2 is disposed on the backlight surface of the substrate 1. The first doped conductive layer 2 includes a first region A located in the center and a second region B located outside the first region A. Figure 3 and Figure 4, the first region A includes an edge region A1 adjacent to the second region B and an intermediate region A2 far from the second region B, as Figure 5 shown, the intermediate region A2 includes: a first intermediate sub-region A21 and a second intermediate sub-region A22 located outside the first intermediate sub-region. The first intermediate sub-region A21 is configured as a region corresponding to the position of the first gate line 31, and the second intermediate sub-region A22 is configured as a region where the first gate line 31 is not provided. As Figures 2-5 shown, the second region B, the edge region A1, and the intermediate region A2 are arranged along the first direction ( Figure 3 the X direction in Figure 5 ), and the first intermediate sub-region A21 and the second intermediate sub-region A22 are alternately arranged along the second direction (

[0043] the Y direction in

[0044] ); the first direction and the second direction intersect. In addition, the first direction is the length extension direction of the first gate line 31, and the second direction is a direction different from the first direction. Preferably, the first direction and the second direction are perpendicular to each other. Figure 1 It can be understood that the patterned first doped conductive layer 2 means that the first doped conductive layer 2 does not cover the backlight surface of the substrate 1 as a complete whole film layer, but the first doped conductive layer 2 is provided in a part of the backlight surface of the substrate 1 and not provided in other regions, so that the first doped conductive layer 2 located on the substrate forms a patterned structure. Figure 3 shown, in the first direction, the first region A is located in the middle, and on both sides of the first region A are the second regions B.

[0045] Here, adjacent and far refer to the relationship of the physical distance between the centers of the regions in the first region and the center of the second region in the first direction. As Figure 2 shown, the distance between the center of the edge region A1 and the center of the second region B is d1, and the distance between the center of the intermediate region A2 and the center of the second region B is d2, d1 < d2, so the edge region A1 is the region adjacent to the second region B, and the intermediate region A2 is the region far from the second region B.

[0046] Here, as Figure 5As shown, the first intermediate sub-region A21 is configured to correspond to the region of the first gate line 31, and the first intermediate sub-region A21 and the second intermediate sub-region A22 are arranged alternately along the second direction (i.e., the Y direction). The proportion of the first intermediate sub-region A21 in the intermediate region A2 is greater than the proportion of the second intermediate sub-region A22 in the intermediate region A2. It is understood that, in the embodiments of this application, the first gate line 31 can be directly or indirectly disposed on the first intermediate sub-region A21 in the first doped conductive layer 2, that is, it can be directly contacted, or a transparent conductive layer 6 can be disposed on the first doped conductive layer 2, and the first gate line 31 can be disposed on the transparent conductive layer 6, so as to realize the electrical connection between the first doped conductive layer 2 and the first gate line 31 through the transparent conductive layer 6. This application does not limit this.

[0047] Combination Figures 2-4 As shown, in the edge region A1 of the first doped conductive layer 2, a plurality of protruding microstructures 40 are provided on the surface of the first doped conductive layer 2. The surface roughness of the first doped conductive layer 2 in the edge region A1 is Ra1, the surface roughness of the first doped conductive layer 2 in the second intermediate sub-region A22 is Ra2, and the surface roughness of the first doped conductive layer 2 in the second region B is Ra3. Ra1>Ra3, Ra1>Ra2.

[0048] The solar cells of this application embodiment can improve the light utilization rate of the back surface, improve the light escape phenomenon of the back surface, help improve the power generation efficiency of the back surface, and thus effectively improve the bifaciality of the solar cells.

[0049] The surface roughness of the first doped conductive layer 2 in the edge region A1 is Ra1, the surface roughness of the first doped conductive layer 2 in the second intermediate sub-region A22 is Ra2, and the surface roughness of the first doped conductive layer 2 in the second region B is Ra3. Since Ra1>Ra3 and Ra1>Ra2, the first doped conductive layer in the edge region A1 can effectively reduce reflectivity compared to the first doped conductive layer 2 in the second intermediate sub-region A22 and the second region B. With this configuration, when the back surface of the solar cell is illuminated, the edge region A1 can utilize its rougher surface and lower reflectivity to capture more light, improve light utilization, mitigate light escape from the back surface of the solar cell, increase the number of charge carriers generated on the back surface, improve the power generation efficiency of the back surface, and thus effectively improve the bifaciality of the solar cell.

[0050] Furthermore, the protruding microstructures 40 include hemispherical structures, columnar structures, or island structures (such as...). Figure 6 One or more of the following (as shown in Figure 40c). The hemispherical structure is as follows: Figure 6As shown in Figure 40a, this refers to a structure with a relatively smooth arc-shaped profile. From the contact surface with the first doped conductive layer 2 to the apex of the raised microstructure 40, the cross-sectional area gradually decreases. It can be a standard hemispherical geometry (i.e., a circular cross-section, with the ratio of the height of the raised microstructure 40 to the diameter of the bottom circle being 0.5), or an approximately hemispherical shape (i.e., a circular or elliptical cross-section, with the ratio of the height of the raised microstructure 40 to the width of the bottom being less than 0.5). Figure 6 As shown in Figure 40b, the cross-section is circular or elliptical, and the cross-sectional area of ​​the contact surface with the first doped conductive layer 2 is equal to the cross-sectional area of ​​the top of the protruding microstructure 40. This structure is a columnar structure. An island structure refers to a structure formed by connecting several protruding structures together. Its cross-sectional shape is irregular, and the cross-sectional area of ​​the contact surface with the first doped conductive layer 2 can be equal to the cross-sectional area of ​​the top of the protruding microstructure 40 (e.g., ...). Figure 6 As shown in 40c), the cross-sectional area can also gradually decrease along the direction from the contact surface to the top (e.g. Figure 6 (As shown in Figure 40d). In this embodiment, the hemispherical structure, columnar structure, or island structure increases the roughness of the edge region A1, reduces the reflectivity of the region, and reduces light escape.

[0051] Furthermore, the maximum distance between any two points on the outer contour of the protruding microstructure 40 is 0.05 μm to 0.5 μm. The outer contour refers to the contour of the contact surface between the protruding microstructure 40 and the first doped conductive layer 2. The dimensions of the protruding microstructure 40 are obtained by scanning electron microscopy. For example, as shown... Figure 6 As shown in Figure 40a, when the protruding microstructure 40 is a regular hemispherical structure, the size of the protruding microstructure 40 is the diameter D of the hemispherical structure. For example, the maximum distance between any two points on the outer contour of the protruding microstructure 40 is 0.05 μm, 0.2 μm, 0.3 μm, 0.4 μm, or 0.5 μm. Preferably, the size of the protruding microstructure 40 is 0.3 μm. In this embodiment, when the size of the protruding microstructure 40 is 0.05 μm to 0.5 μm, the phenomenon of light escape in the edge region A1 can be further improved.

[0052] Further, the surface reflectivity of the first doped conductive layer 2 in the edge region A1 is R1, the surface reflectivity of the first doped conductive layer 2 in the second intermediate sub-region A22 is R2, and the surface reflectivity of the first doped conductive layer 2 in the second region B is R3, where R1 < R3 and R1 < R2. Here, the surface reflectivity is obtained by testing with a reflectivity tester. In the embodiments of the present application, corresponding to the roughness of each region, the greater the roughness, the smaller the reflectivity and the more light is absorbed. Therefore, in addition to absorbing the same amount of light as the second region B, the edge region A1 and the second intermediate sub-region A22 can further absorb more light, further improving the phenomenon of light escape.

[0053] Further, as Figure 7 shown, it is a top view of the first doped conductive layer of the second solar cell provided by the embodiments of the present application. In the first intermediate sub-region A21, a plurality of protruding microstructures 40 are provided on the surface of the first doped conductive layer 2 facing away from the substrate 1; the first intermediate sub-region A21 satisfies at least one of the following conditions: (1) The roughness Ra4 of the surface of the first doped conductive layer 2 in the first intermediate sub-region A21 facing away from the substrate 1, where Ra4 > Ra1 > Ra3 and Ra4 > Ra1 > Ra2; (2) The density of the protruding microstructures 40 in the first intermediate sub-region A21 is greater than the density of the protruding microstructures 40 in the edge region A1; (3) The reflectivity of the first intermediate sub-region A21 is R4, where R4 < R1 < R3 and R4 < R1 < R2.

[0054] In the embodiments of the present application, the protruding microstructures 40 in the first intermediate sub-region A21 increase the roughness of other film layers on the first doped conductive layer 2, improve the bonding force of the first grid line 31, enhance the contact performance of the first grid line 31, reduce the contact resistance, and improve the optoelectronic performance of the solar cell. At the same time, the risk of grid line detachment is reduced, and the stability of the battery is improved. When the first intermediate sub-region A21 satisfies condition (1) or condition (2), the first intermediate sub-region A21 is the region with the highest roughness on the surface of the first doped conductive layer 2 facing away from the substrate 1, and the roughness of other film layers on the first doped conductive layer 2 is correspondingly increased. When the first grid line 31 is provided in this region, the bonding force is further enhanced, the risk of the first grid line 31 detaching is lower, the contact performance is better, and the optoelectronic performance of the solar cell is more excellent. When the first intermediate sub-region A21 satisfies condition (3), it can increase the further light absorption amount on the backlight surface of the solar cell, improve the light escape phenomenon on the backlight surface of the solar cell, and at the same time, reduce the offset of the first grid line 31, ensuring the yield rate of the solar cell.

[0055] Further, the density of the protruding microstructures 40 in the first intermediate sub-region A21 is 10 per μm 2 ~30 per μm2 The density of the protruding microstructures 40 in the edge region A1 is 1 per μm. 2 ~10 cells / μm 2 For example, the density of the protrusion microstructures 40 in the first intermediate sub-region A21 is 10 per μm. 2 13 cells / μm 2 15 cells / μm 2 18 cells / μm 2 21 cells / μm 2 24 cells / μm 2 27 cells / μm 2 29 cells / μm 2 Or 30 / μm 2 Preferably, the density of the protruding microstructures 40 in the first intermediate sub-region A21 is 20 per μm. 2 For example, the density of the protruding microstructures 40 in the second intermediate sub-region A22 is 1 per μm. 2 13 cells / μm 2 5 per μm 2 8 per μm 2 Or 10 / μm 2 Preferably, the density of the protruding microstructures 40 in the second intermediate sub-region A22 is 5 per μm. 2 In this embodiment, when the density of the protruding microstructures 40 in the first intermediate sub-region A21 is within the above-mentioned range, the bonding strength of the first grid line 31 can be further improved, thereby enhancing the stability and photoelectric performance of the solar cell; when the density of the protruding microstructures 40 in the edge region A1 is within the above-mentioned range, the light utilization rate of the back surface of the solar cell can be further improved, the light escape phenomenon can be reduced, and the bifaciality of the solar cell can be improved.

[0056] Furthermore, combined Figures 8 to 9 As shown, Figure 8 This is a cross-sectional schematic diagram of another solar cell provided in an embodiment of this application, wherein the cross-section is in the thickness direction (i.e., the Z direction) of the solar cell. Figure 9 yes Figure 8 A magnified view of a portion of region II. An intrinsic layer 4 and a second doped conductive layer 5 are sequentially disposed on the surface of the first doped conductive layer 2 in region B. The first doped conductive layer 2 and the second doped conductive layer 5 have different conductivity types.

[0057] In this embodiment, the intrinsic layer 4 is a film layer without N-type dopant atoms and / or P-type dopant atoms, and this film layer has insulating properties. One of the first doped conductive layer 2 and the second doped conductive layer 5 is an N-type doped conductive layer, with doping atoms including at least one of phosphorus, antimony, or arsenic; the other is a P-type doped conductive layer, with doping atoms including at least one of boron, gallium, or indium. In this embodiment, the intrinsic layer 4 disposed between the first doped conductive layer 2 and the second doped conductive layer 5 can passivate defects at the interface between the first doped conductive layer 2 and the second doped conductive layer 5. More importantly, the insulating properties of the intrinsic layer 4 can prevent direct contact between the first doped conductive layer 2 and the second doped conductive layer 5, reducing the possibility of leakage in this area.

[0058] Furthermore, the protruding microstructure 40 is the retained structure of the intrinsic layer 4 in the edge region A1; the crystallization rate of the edge region A1 is X1, the crystallization rate of the second intermediate sub-region A22 is X2, the crystallization rate of the second region B is X3, and the crystallization rate of the first intermediate sub-region A21 is X4, X2>X4>X1>X3.

[0059] The retained structure refers to the structure preserved during the removal of intrinsic layer 4 in the fabrication process of the solar cell; that is, it is not a structure formed by adding more process steps. The formation process of the protruding microstructure 40 inevitably results in the protruding microstructure 40 and intrinsic layer 4 being made of the same material.

[0060] In this embodiment, the crystallinity of the edge region A1 corresponds to the crystallinity of the raised microstructure 40 and the first doped conductive layer 2 as a whole; the crystallinity of the second intermediate sub-region A22 corresponds to the crystallinity of the first doped conductive layer 2; the crystallinity of the second region B corresponds to the crystallinity of the second doped conductive layer 5; and the crystallinity of the first intermediate sub-region A21 corresponds to the crystallinity of the raised microstructure 40 and the first doped conductive layer 2 as a whole. In this embodiment, the relationship between the crystallinity of each region is X2>X4>X1>X3. The crystallinity of the first region A is greater than that of the second region B, resulting in higher crystallinity and lower contact resistance. The first intermediate sub-region A21 within the first region A simultaneously possesses both high crystallinity and roughness. Therefore, the first gate line 31 is disposed within the first intermediate sub-region A21. While ensuring the bonding strength of the first gate line 31, the photoelectric performance of the solar cell can be further improved.

[0061] Further, X1 is 91.5% - 92.5%, X2 is 92.5% - 93.5%, X3 is 91.0% - 92.0%, and X4 is 92.0% - 93.0%. Among them, the crystallization rate X is obtained by testing with a Raman spectrometer. Exemplarily, X1 is 91.5%, 92.0% or 92.5%, X2 is 92.5%, 93.0% or 93.5%, X3 is 91.0%, 91.5% or 92.0%, X4 is 92.0%, 92.5% or 93.0%. In the embodiments of the present application, when the crystallization rate X4 of the protruding microstructures 40 in the first intermediate sub-region A21 is within the above range, the contact resistance of the solar cell can be further reduced, the carrier transport efficiency can be improved, and it has more excellent optoelectronic properties.

[0062] Further, the surface reflectivity R3' of the second doped conductive layer 5 in the second region B satisfies R3' < R3, and R4 < R1 < R3' < R2. In the embodiments of the present application, after the intrinsic layer 4 and the second doped conductive layer 5 are provided on the surface of the first doped conductive layer 2, the reflectivity of the backlight surface of the second region B is the surface reflectivity of the second doped conductive layer 5, and the reflectivity of this region is further reduced, so that the absorption effect of the backlight surface of the solar cell on light is better, the light escape phenomenon is improved, which helps to improve the backlight surface power generation efficiency, and thus effectively improves the bifaciality of the solar cell.

[0063] Further, R1 is 25% - 30%, R2 is 30% - 35%, R3' is 30% - 35%, and R4 is 15% - 25%. Exemplarily, R1 is 25%, 27% or 30%, R2 is 30%, 33% or 35%, R3' is 30%, 33% or 35%, R4 is 15%, 20% or 25%. In the embodiments of the present application, when the surface reflectivity R1 of the first doped conductive layer 2 in the edge region A1 is within the above range, the absorption of light by the backlight surface of the solar cell can be further enhanced, and the bifaciality of the solar cell can be improved.

[0064] Further, as Figure 8As shown, a transparent conductive layer 6 is disposed on the surface of the second doped conductive layer 5 facing away from the substrate 1, on the raised microstructure 40, on the raised microstructure 40 of the first intermediate sub-region A21, and on the surface of the first doped conductive layer 2 facing away from the substrate 1 of the second intermediate sub-region A22. A dielectric layer 7 is disposed between the substrate 1 and the patterned first doped conductive layer 2. The transparent conductive layer 6 is made of one or more of indium tin oxide, indium zinc oxide, and indium tungsten oxide. The dielectric layer 7 can be made of a variety of dielectric materials, such as at least one of silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. In this embodiment, the transparent conductive layer 6 has good light transmittance, retains the roughness and reflectivity of each patterned region, and can improve the light absorption rate of the back surface of the solar cell. The dielectric layer 7 has excellent passivation performance, which can reduce carrier recombination loss. The solar cell in this embodiment can be a passivated contact solar cell, a heterojunction cell, or a back contact cell.

[0065] Further, the thickness of the intrinsic layer 4 is 1 nm to 10 nm, the thickness of the second doped conductive layer 5 is 2 nm to 15 nm, and the thickness ratio of the intrinsic layer 4 to the second doped conductive layer 5 is 1:(1.4 to 1.8). For example, the thickness of the intrinsic layer 4 is 1 nm, 3 nm, 5 nm, 7 nm, 9 nm, or 10 nm, the thickness of the second doped conductive layer 5 is 2 nm, 3 nm, 5 nm, 7 nm, 9 nm, 11 nm, 13 nm, or 15 nm, and the thickness ratio of the intrinsic layer 4 to the second doped conductive layer 5 is 1:1.4, 1:1.5, 1:1.6, 1:1.7, or 1:1.8. In this embodiment, the intrinsic layer 4 has a certain thickness, thus reducing the possibility of contact between the first doped conductive layer 2 and the second doped conductive layer 5 located on both sides of the intrinsic layer 4 due to defects in the intrinsic layer 4 itself, and reducing leakage in the second region B of the solar cell. Preferably, the intrinsic layer 4 has a thickness of 7 nm, the second doped conductive layer 5 has a thickness of 11 nm, and the thickness ratio of the intrinsic layer 4 to the second doped conductive layer 5 is 1:1.6.

[0066] The first grid line 31 in the solar cell of the present application embodiment will be further described below.

[0067] The length of the first gate line 31 along the first direction is less than or equal to the length of the first intermediate sub-region A21 along the first direction. For example... Figure 10 and Figure 11As shown, the length of the first gate line 31 along the first direction (i.e., the X direction) is less than L1, and the length of the first intermediate sub-region A21 along the first direction is L2. In this embodiment, the length of the first gate line 31 along the first direction is less than or equal to the length of the first intermediate sub-region A21 along the first direction, and the area in the first intermediate sub-region A21 without gate lines can further capture more light. The reflectivity R4 of this area is the smallest in the region of the first doped conductive layer 2 of the solar cell, thus increasing the amount of light absorbed by the back surface of the solar cell, improving the light escape phenomenon of the back surface of the solar cell, and reducing the offset of the first gate line 31, ensuring the yield of the solar cell. It is understood that... Figure 10 and Figure 11 To clearly illustrate the positional relationship between the first intermediate sub-region A21 and the first gate line 31 in the first doped conductive layer 2, other films that can be disposed between the first doped conductive layer 2 and the first gate line 31 are omitted. This should not be construed as excluding the disposal of other films. For example, a transparent conductive layer 6 can also be disposed. That is, the first gate line 31 can be directly in contact with the first intermediate sub-region A21 in the first doped conductive layer 2, or a transparent conductive layer 6 can be disposed on the first doped conductive layer 2, and the first gate line 31 can be disposed on the transparent conductive layer 6, so that the electrical connection between the first doped conductive layer 2 and the first gate line 31 can be achieved through the transparent conductive layer 6. This application does not impose any restrictions on this.

[0068] Further, the ratio of the length of the first intermediate sub-region A21 along the first direction to the length of the first gate line 31 along the first direction is greater than or equal to 2. For example, the ratio of the length of the first intermediate sub-region A21 along the first direction to the length of the first gate line 31 along the first direction is 2, 3, 5, or 7. In this embodiment, the ratio of the length of the first intermediate sub-region A21 along the first direction to the length of the first gate line 31 along the first direction is greater than or equal to 2, which better avoids contact between the first gate line 31 and the second doped conductive layer 5 of the second region B, reducing the possibility of leakage. Preferably, the ratio of the length of the first intermediate sub-region A21 along the first direction to the length of the first gate line 31 along the first direction is 3.

[0069] Further, the length of the first intermediate sub-region A21 along the first direction is 50 μm to 100 μm. For example, the length of the first intermediate sub-region A21 along the first direction is 50 μm, 65 μm, 80 μm, 90 μm, or 100 μm; the length of the first gate line 31 along the first direction is 5 μm to 30 μm. For example, the length of the first gate line 31 along the first direction is 5 μm, 11 μm, 17 μm, 23 μm, or 30 μm. In this embodiment, when the lengths of the first intermediate sub-region A21 and the first gate line 31 along the first direction are within the above ranges, the light escape phenomenon of the solar cell back surface can be further improved, thereby increasing the bifaciality of the solar cell. Preferably, the length of the first intermediate sub-region A21 along the first direction is 75 μm, and the length of the first gate line 31 along the first direction is 25 μm.

[0070] Further, the height of the first gate line 31 is 7.5 μm to 45 μm. For example, the height of the first gate line 31 is 7.5 μm, 15 μm, 23 μm, 29 μm, 37 μm, or 45 μm. In this embodiment, when the height of the first gate line 31 is within the above range, the aspect ratio of the first gate line 31 can improve the bifaciality of the solar cell while further ensuring the current transmission effect. Preferably, the height of the first gate line 31 is 40 μm.

[0071] Further, the length of the edge region A1 along the first direction is 2 μm to 10 μm. For example, the length of the edge region A1 along the first direction is 2 μm, 4 μm, 7 μm, or 10 μm. In this embodiment, when the length of the edge region A1 along the first direction is within the above range, it can further ensure the light absorption rate of the back surface of the solar cell and improve the bifaciality of the solar cell. Preferably, the length of the edge region A1 along the first direction is 7 μm.

[0072] Further, the length of the first intermediate sub-region A21 along the second direction is 15 μm to 30 μm. For example, the length of the first intermediate sub-region A21 along the second direction is 15 μm, 19 μm, 22 μm, 26 μm, 28 μm, or 30 μm. Preferably, the length of the first intermediate sub-region A21 along the second direction is 22 μm.

[0073] The following provides further description of other structures of the solar cells in the embodiments of this application.

[0074] Furthermore, such as Figure 8 As shown, the solar cell also includes: The patterned second doped conductive layer 5 is disposed in the third region C on the backlight surface of the substrate 1, and the patterned second doped conductive layer 5 and the patterned first doped conductive layer 2 are interdigitated. A transparent conductive layer 6 and a second gate line 32 are sequentially disposed on the surface of the patterned second doped conductive layer 5 facing away from the substrate 1.

[0075] It is understandable that the patterned second doped conductive layer 5 means that the second doped conductive layer 5 does not cover the back surface of the substrate 1 as a complete film layer, but rather the second doped conductive layer 5 is provided in a part of the back surface of the substrate 1, and the second doped conductive layer 5 is not provided in other areas, so that the second doped conductive layer 5 on the substrate forms a patterned structure.

[0076] Among them, the first region A and the second region B are arranged as a whole, and the third region C is arranged alternately along the first direction (i.e. the X direction).

[0077] The interdigitated distribution refers to the patterned first doped conductive layer 2 and the patterned second doped conductive layer 5 both having a comb-like structure, with the two different doped conductive layers arranged in a parallel and alternating manner.

[0078] In this embodiment, the third region C serves as one type of doped conductive region of the solar cell, while the first region A and the second region B together constitute another type of doped conductive region. The two types of doped conductive regions have opposite conductivity types, ensuring the normal operation of the solar cell. The interdigitated distribution can shorten the carrier transport distance, reduce series resistance, and simultaneously prevent recombination caused by electrons and holes crossing each other during transport, reducing the risk of short circuits caused by direct contact between the two doped conductive layers and ensuring the purity of carrier separation. The solar cell in this embodiment is a heterojunction and tunneling oxygen passivation contact hybrid back contact solar cell (HTBC) or a passivated back contact solar cell (TBC).

[0079] Further, the first passivation layer 81 is made of aluminum oxide and has a thickness of 10 nm to 20 nm. The antireflection layer 9 is made of one or more of silicon nitride, silicon oxynitride, or silicon oxide and has a thickness of 70 nm to 100 nm. The thickness of the antireflection layer 9 is 70 nm, 80 nm, 90 nm, or 100 nm. For example, the thickness of the first passivation layer 81 is 10 nm, 13 nm, 17 nm, or 20 nm. In this embodiment, the hydrogen cutoff effect of the first passivation layer 81 reduces the diffusion of hydrogen atoms in the antireflection layer 9 into the solar cell, ensuring its antireflection effect.

[0080] Furthermore, the solar cell also includes an intrinsic layer 4 disposed between the substrate 1 and the patterned second doped conductive layer 5; the substrate 1 has a light-receiving surface, on which a first passivation layer 81 and an anti-reflection layer 9 are sequentially disposed. Preferably, the first doped conductive layer 2 is an N-type doped conductive layer, and the second doped conductive layer 5 is a P-type doped conductive layer. The solar cell of this embodiment is an HTBC. Compared with TBC, the solar cell of this embodiment further reduces the non-radiative recombination of the P-type doped conductive layer in the solar cell, improves the carrier transport rate of the solar cell, and enhances the photoelectric performance of the solar cell.

[0081] Furthermore, such as Figure 8 As shown, the height difference between the surface of the transparent conductive layer 6 in the third region C facing away from the substrate 1 and the light-receiving surface of the substrate 1 is h1, and the height difference between the interface between the dielectric layer 7 and the substrate 1 and the light-receiving surface of the substrate 1 is h2, where h1 < h2; there is a gap between the transparent conductive layer 6 in the second region B and the transparent conductive layer 6 in the third region C. In this embodiment, h1 < h2, and the gap between the transparent conductive layer 6 in the second region B and the third region C reduces the possibility of solar cell leakage.

[0082] Furthermore, the dielectric layer 7 has micropores opening along its thickness direction, with a pore size of 0.5 nm to 2 nm. For example, the pore size is 0.5 nm, 0.8 nm, 1.2 nm, 1.7 nm, or 2 nm. In this embodiment, the micropores in the dielectric layer 7 can further improve the carrier mobility in the solar cell, thereby enhancing the photoelectric performance of the solar cell. Preferably, the pore size is 1.2 nm.

[0083] Secondly, this application also provides a method for preparing the above-mentioned solar cell. It is understood that this preparation method is one way to obtain the solar cell described in this application, but it is not limited to the only method. That is, the solar cell in this application embodiment can also be prepared by other methods, and this application does not impose any limitations on this. Therefore, it should not be construed as a limitation on the solar cell provided in this application embodiment.

[0084] like Figure 12 As shown, the preparation method includes: Patterning process: The first doped conductive layer 2 disposed on the back surface of the substrate 1 is patterned to obtain a patterned first doped conductive layer 2; wherein, the patterned first doped conductive layer 2 includes a first region A located in the middle and a second region B located outside the first region A. The first region A includes an edge region A1 adjacent to the second region and a middle region A2 away from the second region. The middle region A2 includes a first middle sub-region A21 and a second middle sub-region A22 located outside the first middle sub-region A21. The first middle sub-region A21 is configured to correspond to the region of the first gate line 31. The second region B, the edge region A1, and the middle region A2 are arranged along a first direction, and the first middle sub-region A21 and the second middle sub-region A22 are arranged alternately along a second direction. The first direction and the second direction intersect. Surface treatment: Several raised microstructures 40 are made on the surface of the first doped conductive layer 2 located in the edge region A1, so that the surface roughness of the first doped conductive layer 2 in the edge region A1 is Ra1, the surface roughness of the first doped conductive layer 2 in the second intermediate sub-region A22 is Ra2, and the surface roughness of the first doped conductive layer 2 in the second region B is Ra3, Ra1>Ra3, Ra1>Ra2. Fabrication of the first gate line 31: The first gate line 31 is disposed on the first intermediate sub-region A21.

[0085] In this embodiment, the patterning process results in a first doped conductive layer 2 being formed on a portion of the back surface of the substrate 1, while another portion does not have the first doped conductive layer 2. This allows the areas without the first doped conductive layer 2 to be fitted with other doped conductive layers in subsequent processes. Then, surface treatment is performed on the different regions of the first doped conductive layer 2, which has become a patterned film layer, to form raised microstructures 40 on the surface of the first doped conductive layer 2 located in the edge region A1. These raised microstructures 40 increase the roughness of the edge region, improving the light absorption efficiency of the solar cell's back surface and increasing the bifaciality of the solar cell.

[0086] The following section provides further explanation of the relevant steps in graphical processing.

[0087] Furthermore, such as Figure 13 As shown, before patterning, the fabrication method further includes: fabricating a dielectric layer 7, fabricating a first doped conductive layer 2, and fabricating a mask layer 22.

[0088] Preparation of dielectric layer 7: Dielectric layer 7 is prepared on substrate 1.

[0089] Preparation of the first doped conductive layer 2: The first doped conductive layer 2 is prepared on the surface of the dielectric layer 7, and a doped glass layer 21 is also formed on the first doped conductive layer 2. The steps are as follows: (1) Propulsion: Nitrogen gas is introduced at a flow rate of 1 L / min to 2 L / min, oxygen gas is introduced at a flow rate of 0.3 L / min to 1 L / min, and a gas source containing the first doped atoms at a flow rate of 0.3 L / min to 1 L / min at 20℃ to 30℃ is introduced; (2) Deposition: Nitrogen gas is introduced at a flow rate of 10 L / min to 20 L / min at 830℃ to 870℃, and deposition is carried out for 15 min to 25 min to obtain the first doped conductive layer 2 on the dielectric layer 7. During this process, a doped glass layer 21 is also formed on the surface of the first doped conductive layer 2, wherein the doped glass layer 21 refers to silicon-containing glass doped with the first doped atoms. The gas source containing the first doped atom can be determined according to the conductivity type of the first doped conductive layer. When the first doped conductive layer 2 is an N-type doped conductive layer, the gas source containing the first doped atom is at least one of a phosphorus source, an antimony source, or an arsenic source. When the first doped conductive layer 2 is a P-type doped conductive layer, the doped atom includes at least one of a boron source, a gallium source, or an indium source.

[0090] The steps for preparing the mask layer 22 are as follows: at 200℃~400℃, the mask layer 22 is deposited on the surface of the doped glass layer 21.

[0091] In this embodiment, through the steps of preparing the dielectric layer 7 and the first doped conductive layer 2, a film of the first doped conductive layer 2 is formed on the back surface of the substrate 1. The first doped conductive layer 2 in this application is a doped conductive layer doped with N-type dopant atoms. Compared to a doped conductive layer doped with P-type dopant atoms, it has a lower processing temperature, better film formation effect, fewer carrier recombination centers, and better photoelectric performance of the solar cell. The solar cell with the preparation steps of this embodiment can be any of a heterojunction cell, a passivated contact cell, or a back contact cell.

[0092] Furthermore, such as Figure 14 As shown, the steps of graphical processing include: The mask layer 22 and the doped glass layer 21 of the third region C are removed. The third region C is the region other than the first region A and the second region B. The method for removing the mask layer 22 and the doped glass layer 21 of the third region C can be laser grooving, chemical grooving, etc. This application does not limit the removal method.

[0093] First wet cleaning: Remove the first doped conductive layer 2 and dielectric layer 7 of the third region C, remove the film layers on the side surface and light-receiving surface of the substrate 1, remove the mask layer 22 and doped glass layer 21 of the first region A and the second region B, so that the light-receiving surface of the substrate 1 and the back-light surface of the third region C form a textured structure. The first wet cleaning process includes the following steps: pre-cleaning (1%~3% NaOH, time 120 s~180 s), removal of mask layer 22 (10%~20% HF + 20%~30% HNO3), removal of doped glass layer 21 (mixed acid solution of 20%~30% HNO3 and 10%~20% H2SO4, temperature 22℃~28℃, time 60 s~120 s), alkaline polishing (1%~5% NaOH, 5%~10% H2O2, 1%~5% additives, temperature 70℃~80℃, time 480 s~720 s), texturing (1%~5% NaOH, 5%~10% additives, temperature 70℃~80℃, time 300 s~500 s), and alkaline washing (1%~5% NaOH, 5%~10% H2O2, time 120 s~180 s). The process consists of the following steps: first O3 wash (O3 flow rate of 10 ppm to 50 ppm, 0.1% HCl, time 120 s to 180 s), acid wash (1% to 10% HCl, 5% to 15% H2O2, time 120 s to 240 s), second O3 wash (O3 flow rate of 10 ppm to 50 ppm, 0.1% HCl, time 120 s to 180 s), and slow HF extraction (HF 10% to 20%, time 30 s to 60 s).

[0094] In this embodiment, during the patterning process, the mask layer 22 and the doped glass layer 21 are first removed, followed by a first wet cleaning process. This exposes the substrate 1 of the third region C, forming a patterned first doped conductive layer 2. The first wet cleaning process also removes the light-receiving surface and side film layers of the solar cell while simultaneously creating a textured surface on the light-receiving surface of the substrate 1 and the back surface of the third region C, thereby improving the solar cell's light absorption rate.

[0095] Preferably, the step of removing the mask layer 22 and the doped glass layer 21 in the third region C is performed using a laser grooving method. The laser process parameters include: wavelength of 266 nm to 532 nm, relative power of 40% to 60%, test power of 40 W to 60 W, frequency of 800 kHz, single pulse energy of 50 mJ to 100 mJ, and unit pulse energy density of 200 mJ / cm². 2 ~400 mJ / cm 2The laser spot width is 100 μm to 200 μm, the line spacing is 90 μm to 150 μm, the speed is 20 m / s to 80 m / s, the spacing direction overlap is 10% to 30%, the scanning overlap is 30% to 70%, the laser spot is rectangular, the spot width D is 100 μm to 250 μm, and the longitudinal length H of the spot is 100 μm to 300 μm.

[0096] Furthermore, such as Figures 15-16 As shown, after the first wet cleaning and before surface treatment, the preparation method also includes: preparing a passivation layer 8, preparing an antireflection layer 9, sintering, photoinjection, removing the second passivation layer 82 from the third semi-finished product and the antireflection layer 9 on the second passivation layer 82, preparing an intrinsic layer 4 and preparing a second doped conductive layer 5.

[0097] like Figure 15 As shown, the preparation steps of passivation layer 8 are as follows: depositing a first passivation layer 81 on the light-receiving surface of substrate 1, and depositing a second passivation layer 82 on the first doped conductive layer 2 on the back-light-receiving surface of substrate 1. The steps are as follows: trimethylaluminium (TMA) is introduced at a flow rate of 50 sccm to 200 sccm, and O2 or N2O is introduced at a flow rate of 300 sccm to 1000 sccm. The TMA pulse time is 0.1 s to 0.3 s, and the O2 or N2O pulse time is 0.2 s to 0.5 s. The system is purged at 180℃ to 220℃ and 0.5 Torr to 2 Torr for 3 s to 8 s, and the cycle is repeated 80 to 150 times. The deposition rate is 3 nm / min to 8 nm / min. The annealing temperature at the end of the deposition is 380℃ to 420℃, resulting in the first passivation layer 81 and the second passivation layer 82. In this embodiment, the second passivation layer 82 is a monolithic structure, meaning that the second passivation layer 82 is formed on the substrate 1 of the third region C, and on the first doped conductive layer 2 of the first region A and the second region B. In this embodiment, the materials of the first passivation layer 81 and the second passivation layer 82 are aluminum oxide. The material contains Al-H bonds and Al-OH bonds. Under high-temperature conditions, these chemical bonds in the film layer will break, achieving passivation at the interface. Simultaneously, aluminum oxide can also provide field passivation, suppressing the escape of hydrogen atoms from the antireflection layer 9, further improving the performance of the solar cell.

[0098] The preparation steps of the antireflection layer 9 are as follows: the antireflection layer 9 is deposited on the surface of the first passivation layer 81 to obtain the first semi-finished product. The steps are as follows: SiH4 is introduced at a flow rate of 300 sccm~600 sccm, NH3 is introduced at a flow rate of 1000 sccm~2500 sccm, and N2 is introduced at a flow rate of 2000 sccm~5000 sccm. The deposition time is 180 s~300 s at 400℃~450℃ and 0.2 Torr~1.5 Torr to obtain the antireflection layer 9.

[0099] The sintering step is as follows: the first semi-finished product is processed at 730℃~750℃ for 30 s~90 s to obtain the second semi-finished product. Exemplarily, the sintering temperature is 730℃, 735℃, 740℃, 745℃, or 750℃, and the time is 30 s, 50 s, 70 s, or 90 s. In this embodiment, the temperature and time of the sintering step activate hydrogen ions in the passivation layer 8 and the antireflection layer 9. The generated hydrogen ions can passivate defects in the substrate 1, the third region C, and the first doped conductive layer 2 in the first region A and the second region B, reducing carrier recombination centers and improving the performance of the solar cell. Preferably, the sintering temperature is 740℃ and the time is 60 s.

[0100] The light injection step is as follows: the second semi-finished product is processed at 600℃~700℃ for 10 s~60 s to obtain the third semi-finished product. For example, the light injection temperature is 600℃, 630℃, 650℃, 670℃, or 700℃, and the time is 10 s, 25 s, 40 s, 55 s, or 60 s. In this embodiment, light injection excites electron-hole pairs in the passivation layer 8 and the antireflection layer 9, activating hydrogen ions and forming a built-in electric field that causes hydrogen ions to move. This can passivate defects in the substrate 1, the third region C, and the first doped conductive layer 2 in the first region A and the second region B, reducing carrier recombination centers and improving the performance of the solar cell. Preferably, the light injection temperature is 650℃ and the time is 35 s.

[0101] The step of removing the second passivation layer 82 and the antireflection layer 9 on the second passivation layer 82 from the third semi-finished product is as follows: using 20%~60% HF, the third semi-finished product is treated at 23℃~27℃ for 60 s~120 s to obtain the fourth semi-finished product. In this embodiment, after the hydrogen atoms in the second passivation layer 82 on the backlight side passivate the first doped conductive layer 2, they are removed to ensure good contact between the subsequently formed intrinsic layer 4 and the first doped conductive layer 2.

[0102] After removing the second passivation layer 82 and the antireflection layer 9 from the third semi-finished product, the fabrication method further includes fabricating an intrinsic layer 4 and a second doped conductive layer 5 (such as...) on the back surface of the solar cell. Figure 16 As shown in the figure, different conductive doped layers of different conductivity types are formed in different areas of the back surface, thereby realizing the effective combination of back contact solar cells, heterojunction solar cells and passivated contact solar cells, and giving full play to the technical advantages of each type of cell.

[0103] The intrinsic layer 4 is prepared by: depositing the second passivation layer 82 and the antireflection layer 9 on the second passivation layer 82 around the back side of the fourth semi-finished product obtained by removing the second passivation layer 82 from the third semi-finished product, with the back side being the backlight side of the substrate 1. The preparation process of the intrinsic layer 4 is as follows: SiH4 is introduced at a flow rate of 30 sccm to 100 sccm at 180℃~220℃ and 100 Pa~200 Pa, and hydrogen gas is introduced at a flow rate of 150 sccm to 1000 sccm, with a hydrogen to silane ratio of 5:1~10:1, to obtain the intrinsic layer 4. The preparation method of the second doped conductive layer 5 is as follows: SiH4 is introduced at a flow rate of 30 sccm to 100 sccm, hydrogen gas is introduced at a flow rate of 150 sccm to 1000 sccm, and a gas source containing second doped conductive atoms is introduced at a flow rate of 200 sccm to 400 sccm. The deposition rate is 0.3 nm / min to 0.6 nm / min, thus obtaining the second doped conductive layer 5. The gas source containing the second doped atoms can be determined according to the conductivity type of the second doped conductive layer. When the second doped conductive layer 5 is an N-type doped conductive layer, the gas source containing the first doped atoms is at least one of a phosphorus source, an antimony source, or an arsenic source. When the second doped conductive layer 5 is a P-type doped conductive layer, the doped atoms include at least one of a boron source, a gallium source, or an indium source.

[0104] In this embodiment, the intrinsic layer 4 is a monolithic film layer, meaning that the intrinsic layer 4 is formed on the second doped conductive layer 5 in the first region A and the second region B, and on the substrate 1 in the third region C. The second doped conductive layer 5 is also a monolithic film layer, disposed on the surface of the intrinsic layer 4 in each region of the back surface of the entire solar cell. In this embodiment, the intrinsic layer 4 is an insulating film layer without doped atoms, thus avoiding direct contact between the first doped conductive layer 2 and the second doped conductive layer 5, reducing the possibility of leakage in this region, and improving the stability of the solar cell.

[0105] Preferably, the gas source containing the first doped conductive atoms is a phosphorus source, and the gas source containing the second doped conductive atoms is a boron source, that is, the first doped conductive layer 2 is an N-type doped conductive layer, and the second doped conductive layer 5 is a P-type doped conductive layer. The solar cell in this embodiment is a heterojunction and tunneling oxygen passivation contact hybrid back contact solar cell (HTBC). Compared to a passivated back contact solar cell (TBC), the solar cell in this embodiment further reduces the non-radiative recombination of the P-type doped conductive layer in the solar cell, improves the carrier transport rate of the solar cell, and enhances the photoelectric performance of the solar cell.

[0106] Preferably, the phosphorus source is phosphorus oxychloride, and the boron source is boron trichloride or trimethylboron.

[0107] The surface treatment steps are explained below. A schematic diagram of the solar cell structure during the surface treatment process is shown below. Figure 17 As shown.

[0108] The surface treatment steps include: laser grooving the patterned first doped conductive layer 2 to obtain a patterned first doped conductive layer 2. The laser grooving process parameters include: laser wavelength of 266 nm to 532 nm, laser spot overlap rate of -10% to 0%, and relative power of 20% to 60%. For example, the laser wavelength is 266 nm, 283 nm, 346 nm, 429 nm, or 532 nm, and the relative power is 20%, 30%, 40%, 50%, or 60%. In this embodiment, after laser grooving with these process parameters, a first region A and a second region B are formed in the area of ​​the first doped conductive layer 2. The first region A is the laser-grooved region, and the second region B is the region where the second doped conductive layer 5 and the intrinsic layer 4 are retained. During the laser grooving process, the central region A2 is the core area of ​​the laser beam, therefore the second doped conductive layer 5 and the intrinsic layer 4 are completely removed in this region, exposing the first doped conductive layer 2. The edge region A1 is the edge area of ​​the laser beam; due to insufficient energy, the intrinsic silicon removal in this region is incomplete, meaning that a residual structure of the intrinsic layer 4 exists in this region. This residual structure is the raised microstructure 40. The presence of the raised microstructure 40 increases the roughness of the surface of the first doped conductive layer 2 on the side facing away from the substrate 1, improving the utilization rate of light. Preferably, the laser wavelength is 350 nm, the laser spot overlap rate is -5%, and the relative power is 40%.

[0109] The laser spot overlap rate refers to the percentage of the overlapping area between two adjacent laser spots during laser scanning, relative to the area of ​​a single spot. Essentially, a laser spot overlap rate greater than 0% indicates that two adjacent laser spots overlap; a laser spot overlap rate less than 0% indicates that two adjacent laser spots do not overlap at all; and a laser spot overlap rate equal to 0% indicates that two adjacent laser spots are exactly adjacent but do not overlap. For example, the laser spot overlap rate can be -10%, -8%, -5%, -3%, or 0%. In this embodiment, by controlling the process parameters of the laser spot overlap rate, a laser spot overlap rate is formed as shown in the example. Figure 7In the structure shown, the two laser spots do not overlap. During the process, laser spillover causes alternating first intermediate sub-regions A21 and A22 to form in the middle region A2, with the first intermediate sub-region A21 being the overlapping area of ​​two adjacent laser spots. The second intermediate sub-region A22 is the central region of the laser beam, therefore the second doped conductive layer 5 and intrinsic layer 4 are completely removed in this region, exposing the first doped conductive layer 2. The first intermediate sub-region A21 is the edge region of the laser spot. Due to insufficient energy, the intrinsic silicon in this region is not completely removed, resulting in a residual structure of intrinsic layer 4 in this region, which is the protruding microstructure 40. In this embodiment, the protruding microstructure 40 can be formed simultaneously in the edge region A1 and the first intermediate sub-region A21. Since the first intermediate sub-region A21 is acted upon by two laser spots simultaneously, a raised microstructure 40 with a density greater than that of the edge region A1 is formed in this region. This increases the roughness of the first intermediate sub-region A21, resulting in a stronger bond between the first gate line 31 and the first doped conductive layer 2 on the first intermediate sub-region A21. This reduces the possibility of the first gate line 31 falling off during use and improves the stability of the solar cell.

[0110] Furthermore, after laser grooving, the preparation method also includes a second wet cleaning to remove laser residue from the first intermediate sub-region A21 and the edge region A1. The second wet cleaning steps include: alkaline cleaning (1%~2% NaOH, 5%~10% H2O2, time 50 s~70 s), O3 cleaning (O3 flow rate 10 ppm~50 ppm, 0.5%~1% HCl, time 50 s~70 s), acid washing (1%~5% HF, 5%~15% H2O2, time 50 s~70 s), and acid washing (1%~5% HF, time 30 s~90 s). In this embodiment, the second wet cleaning removes unstable impurities (e.g., silicon nitride) generated during the laser grooving step, retaining only the stable protruding microstructure 40.

[0111] The following describes the steps following the second wet cleaning process, such as... Figure 18 and Figure 19 As shown, these steps include, in sequence: Fabrication of the transparent conductive layer 6: The transparent conductive layer 6 is deposited on the back surface of a substrate 1 having a patterned first doped conductive layer 2 and a patterned second doped conductive layer 5. The steps are as follows: the transparent conductive layer 6 is fabricated at 160℃~190℃ and 0.7 Pa~1.0 Pa. In this embodiment, the transparent conductive layer 6 improves the light absorption efficiency of the back surface of the solar cell, further improving the bifaciality of the solar cell.

[0112] A designated area of ​​the transparent conductive layer 6 is locally etched to expose the surfaces of a portion of the first doped conductive layer 2 and a portion of the second doped conductive layer 5. The designated area refers to the region where the transparent conductive layer 6 is disconnected at the boundary between the third region C and the second region B. This step involves printing etching paste into the designated area of ​​the transparent conductive layer 6, removing the etching paste using a paste cleaning process, and cleaning away any residue at the etched area, thus exposing the film layer beneath the transparent conductive layer 6 in that designated area. In this embodiment, etching away the transparent conductive layer 6 at the boundary between the third region C and the second region B avoids the possibility of solar cell leakage and improves the safety and stability of the solar cell.

[0113] Preparation of grid lines: Print paste on the first intermediate sub-region A21 and cure to prepare the first grid line 31. Print paste on the grid line setting area of ​​the third region C and cure to prepare the second grid line 32.

[0114] The technical solution of this application will be further explained below with reference to more specific embodiments.

[0115] Example This embodiment provides an HTBC solar cell. Its fabrication steps are as follows: Clean the substrate; Preparation of dielectric layer: A 1.5 nm SiO2 dielectric layer was prepared on the surface of the substrate by low pressure chemical vapor deposition (LPCVD). Preparation of the first doped conductive layer: A 250 nm doped conductive layer with phosphorus atoms was deposited on the surface of the dielectric layer by LPCVD, with POCl3 as the phosphorus source; Fabrication of the mask layer: A 2 nm silicon nitride mask layer is fabricated on the surface of the first doped conductive layer; Graphical processing: Removal of mask layer and doped glass layer: Laser removal of the mask layer and doped glass layer in the third region exposes the first doped conductive layer in that region; First wet cleaning: Remove the first doped conductive layer and dielectric layer in the third region until the substrate in that region is exposed; remove the film layers on the side surface and light-receiving surface of the substrate; remove the mask layers and doped glass layers in the first and second regions, so that the light-receiving surface of the substrate and the back surface of the third region form a textured structure. Preparation of passivation layers: Al2O3 was deposited as the first passivation layer and the second passivation layer on the light-receiving surface and the back-light-receiving surface, respectively, by atomic layer deposition (ALD); the thickness of the first passivation layer and the second passivation layer was 15 nm. Preparation of antireflection layer: A silicon nitride antireflection layer with a thickness of 80 nm is deposited on the first passivation layer by plasma-enhanced chemical vapor deposition (PECVD). Sintering: Sinter at 740℃ for 60 s; Light injection: Light injection at 650℃ for 35 s; Remove the second passivation layer: Remove the second passivation layer to expose the first doped conductive layer in the first and second regions, and the silicon substrate in the third region; remove the anti-reflection layer on the second passivation layer and perform a wrap-around plating. Intrinsic layer preparation: An intrinsic layer is deposited on the back side by PECVD. The material of the intrinsic layer is amorphous silicon and the thickness of the intrinsic layer is 7 nm. Preparation of the second doped conductive layer: A second doped conductive layer doped with boron atoms is deposited on the intrinsic layer. The thickness of the second doped conductive layer is 11 nm, and the boron source is BCl3.

[0116] Surface treatment: Laser grooving: A laser acts on a first region to remove the second doped conductive layer and the intrinsic layer, forming a second intermediate sub-region where the second doped conductive layer and the intrinsic layer are completely removed, a first intermediate sub-region where the second doped conductive layer is completely removed and the intrinsic layer remains, and an edge region where the second doped conductive layer and the intrinsic layer are completely retained, forming a patterned second doped conductive layer, wherein the length of the first intermediate sub-region A21 along the first direction is 75 μm; Second wet cleaning: The second wet cleaning removes the laser residue from step twelve; Preparation of transparent conductive layer: An ITO layer with a thickness of 65 nm was deposited on the back side by PVD process; Local etching: Etching paste is printed in a designated area of ​​the transparent conductive layer, and then the etching paste is removed by a paste cleaning process; Preparation of the first and second grid lines: screen printing grid line paste, low temperature curing to form the first and second grid lines, the length of the first grid line is 25 μm and the height is 40 μm.

[0117] Comparative Example The difference between this comparative example and the embodiment is that, in the laser grooving step, the intrinsic layer and the second doped conductive layer are removed from the entire area of ​​the first doped conductive layer. That is, the first doped conductive layer in the second region does not have an intrinsic layer or a second doped conductive layer, and there are no protruding microstructures in the edge region.

[0118] Performance testing: 1. Morphology and size of the protruding microstructure The morphology and dimensions of the semi-finished product after step twelfth of the example were obtained by scanning electron microscopy. The test results are as follows: Figures 20-23 As shown, where Figures 20-22 This is a topographic map of the edge region. Figure 23 This is a topographic map of the first intermediate sub-region.

[0119] 2. Reflectivity The semi-finished product after step 12 of the embodiment and the comparative example were tested using a reflectance meter. The test results are shown in Table 1.

[0120] 3. Crystallization rate The semi-finished products after step 12 of the example were tested using Raman spectroscopy in both the embodiment and the comparative example. The test results are shown in Table 1.

[0121] 4. Photoelectric properties The HALAM test and sorting equipment was used to test the open-circuit voltage, fill factor, and photoelectric conversion efficiency of the examples and comparative examples. The HALAM equipment simulates sunlight and is equipped with electronic loads, data acquisition and calculation devices to test the electrical performance of photovoltaic devices (including solar cells). The calibrated light intensity of the solar cells under test was controlled at 1000±5 W / m². The test results are shown in Table 2.

[0122] Table 1. Test results of reflectivity and crystallinity for the examples and comparative examples.

[0123] Table 2. Photoelectric performance test results of the examples and comparative examples.

[0124] As shown in Tables 1 and 2, the patterned structure of the first doped conductive layer in this embodiment enables the back surface of the solar cell to have various reflectivities and crystallinity. After the transparent conductive layer is set, due to its high light transmittance, the reflectivity of the back surface of the solar cell in this embodiment can be indirectly reflected by R4, R1, R3', and R2. The overall reflectivity of the patterned first doped conductive layer in this embodiment is lower than that in the comparative example. Therefore, when the back surface of the solar cell is illuminated, this embodiment can utilize its rougher surface and lower reflectivity to further capture more light, improve light utilization, and mitigate light escape from the back surface of the solar cell. This increases the power generation efficiency of the back surface and effectively improves the bifaciality of the solar cell.

[0125] Meanwhile, in this embodiment, the crystallization rate of different regions of the first doped conductive layer is greater than that of the comparative example, especially the crystallization rate of the first intermediate sub-region. The transparent conductive layer has good conductivity. Therefore, the first gate line set in the first intermediate sub-region has a lower contact resistance while ensuring the bonding strength, which can further improve the photoelectric performance of the solar cell.

[0126] The technical solutions disclosed in the embodiments of this application have been described in detail above. Specific examples have been used in this article to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core inventive points of the embodiments of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A solar cell, characterized in that, The solar cell includes: a substrate having a backlight surface, a patterned first doped conductive layer, and a first grid line, wherein the first grid line is in electrical contact with a portion of the first doped conductive layer; The first doped conductive layer is disposed on the backlight surface of the substrate. The first doped conductive layer includes a first region located in the middle and a second region located outside the first region. The first region includes an edge region adjacent to the second region and a middle region away from the second region. The middle region includes a first middle sub-region and a second middle sub-region located outside the first middle sub-region. The first middle sub-region is configured to correspond to the region of the first gate line. The second region, the edge region, and the middle region are arranged along a first direction. The first middle sub-region and the second middle sub-region are arranged alternately along a second direction. The first direction and the second direction intersect. In the edge region, the surface of the first doped conductive layer is provided with a plurality of protruding microstructures; the surface roughness of the first doped conductive layer in the edge region is Ra1, the surface roughness of the first doped conductive layer in the second intermediate sub-region is Ra2, and the surface roughness of the first doped conductive layer in the second region is Ra3, where Ra1>Ra3 and Ra1>Ra2.

2. The solar cell according to claim 1, characterized in that, The protruding microstructures include one or more of hemispherical, columnar, or island-like structures; and / or, The maximum distance between any two points on the outer contour of the protruding microstructure is 0.05 μm to 0.5 μm.

3. The solar cell according to claim 1, characterized in that, The surface reflectance of the first doped conductive layer in the edge region is R1, the surface reflectance of the first doped conductive layer in the second intermediate sub-region is R2, and the surface reflectance of the first doped conductive layer in the second region is R3. <R3,R1<R2。 4. The solar cell according to claim 3, characterized in that, In the first intermediate sub-region, a plurality of protruding microstructures are disposed on the surface of the first doped conductive layer facing away from the substrate, and the first intermediate sub-region satisfies at least one of the following conditions: (1) The surface roughness of the first doped conductive layer of the first intermediate sub-region away from the substrate is Ra4, Ra4>Ra1>Ra3, Ra4>Ra1>Ra2; (2) The density of the protruding microstructures in the first intermediate sub-region is greater than the density of the protruding microstructures in the edge region; (3) The reflectance of the first intermediate sub-region is R4, R4 <R1<R3,R4<R1<R2。 5. The solar cell according to claim 4, characterized in that, The density of the protrusion microstructures in the first intermediate sub-region is 10 per μm. 2 ~30 cells / μm 2 The density of the protruding microstructures in the edge region is 1 per μm. 2 ~10 cells / μm 2 .

6. The solar cell according to claim 4, characterized in that, An intrinsic layer and a second doped conductive layer are sequentially disposed on the surface of the first doped conductive layer away from the substrate in the second region, wherein the first doped conductive layer and the second doped conductive layer have different conductivity types.

7. The solar cell according to claim 6, characterized in that, The protruding microstructure is a residual structure of the intrinsic layer in the edge region; the crystallinity of the edge region is X1, the crystallinity of the second intermediate sub-region is X2, the crystallinity of the second region is X3, and the crystallinity of the first intermediate sub-region is X4, where X2>X4>X1>X3; and / or, The reflectivity R3' of the surface of the second doped conductive layer in the second region facing away from the substrate satisfies R3' < R3, and R4 < R1 < R3' < R2.

8. The solar cell according to claim 7, characterized in that, X1 is 91.5% - 92.5%, X2 is 92.5% - 93.5%, X3 is 91.0% - 92.0%, X4 is 92.0% - 93.0%; and / or, R1 is 25% - 30%, R2 is 30% - 35%, R3' is 30% - 35%, R4 is 15% - 25%.

9. The solar cell according to claim 6, characterized in that, A transparent conductive layer is provided on the surface of the second doped conductive layer facing away from the substrate, on the protruding microstructures in the edge region, on the protruding microstructures in the first intermediate sub-region, and on the surface of the first doped conductive layer in the second intermediate sub-region facing away from the substrate; and / or, The thickness of the intrinsic layer is 1 nm - 10 nm, the thickness of the second doped conductive layer is 2 nm - 15 nm, and the thickness ratio of the intrinsic layer to the second doped conductive layer is 1:(1.4 - 1.8).

10. The solar cell according to claim 1, characterized in that, The length of the first gate line along the first direction is less than or equal to the length of the first intermediate sub-region along the first direction.

11. The solar cell according to claim 10, characterized in that, The ratio of the length of the first intermediate sub-region along the first direction to the length of the first gate line along the first direction is greater than or equal to 2; and / or, The length of the first intermediate sub-region along the first direction is 50 μm - 100 μm; and / or, The length of the first gate line along the first direction is 5 μm - 30 μm.

12. The solar cell according to claim 1, characterized in that, The height of the first gate line is 7.5 μm - 45 μm; and / or, The length of the edge region along the first direction is 2 μm - 10 μm; and / or, The length of the first intermediate sub-region along the second direction is 15 μm - 30 μm.

13. The solar cell according to any one of claims 1-12, characterized in that, The solar cell further includes: A patterned second doped conductive layer, provided in a third region on the backlight surface of the substrate, and the patterned second doped conductive layer and the patterned first doped conductive layer are in an interdigitated distribution; A transparent conductive layer and a second gate line are sequentially provided on the surface of the patterned second doped conductive layer facing away from the substrate; The solar cell further includes an intrinsic layer provided between the substrate and the patterned second doped conductive layer, and a dielectric layer provided between the substrate and the patterned first doped conductive layer; The substrate has a light-receiving surface, and a first passivation layer and an antireflection layer are sequentially provided on the light-receiving surface of the substrate.

14. The solar cell according to claim 13, characterized in that, The height difference between the surface of the transparent conductive layer in the third region facing away from the substrate and the light-receiving surface of the substrate is h1, and the height difference between the adjacent interface of the dielectric layer and the substrate and the light-receiving surface of the substrate is h2, with h1 < h2; there is a gap between the transparent conductive layer in the second region and the transparent conductive layer in the third region; and / or, The dielectric layer has micropores opened along the thickness direction of the dielectric layer, and the pore diameter of the micropores is 0.5 nm - 2 nm.

15. A method for fabricating a solar cell, characterized in that, The preparation method includes: Patterning Processing: A first doped conductive layer disposed on the backlight surface of the substrate is patterned to obtain a patterned first doped conductive layer; wherein, the patterned first doped conductive layer includes a first region located in the middle and a second region located outside the first region, the first region includes an edge region adjacent to the second region and a middle region away from the second region, the middle region includes a first middle sub-region and a second middle sub-region located outside the first middle sub-region, the first middle sub-region being configured to correspond to the region of the first gate line; the second region, the edge region, and the middle region are arranged along a first direction, the first middle sub-region and the second middle sub-region are arranged alternately along a second direction, and the first direction and the second direction intersect; Surface treatment: A plurality of raised microstructures are formed on the surface of the first doped conductive layer located in the edge region, so that the surface roughness of the first doped conductive layer in the edge region is Ra1, the surface roughness of the first doped conductive layer in the second intermediate sub-region is Ra2, and the surface roughness of the first doped conductive layer in the second region is Ra3, where Ra1>Ra3 and Ra1>Ra2. Fabricating the first gate line: The first gate line is disposed on the first intermediate sub-region.

16. The preparation method according to claim 15, characterized in that, The surface treatment steps include: The first doped conductive layer after patterning is laser-grooved. The laser grooving process parameters include: laser wavelength of 266 nm to 532 nm, laser spot overlap rate of -10% to 0%, and relative power of 20% to 60%.

17. The preparation method according to claim 16, characterized in that, After laser grooving, the raised microstructure is obtained in the first intermediate sub-region, and the density of the raised microstructure in the first intermediate sub-region is greater than the density of the raised microstructure in the edge region.

18. The preparation method according to claim 15, characterized in that, Prior to the patterning process, the preparation method further includes: Preparation of dielectric layer: The dielectric layer is prepared on the substrate; Preparation of the first doped conductive layer: The first doped conductive layer is prepared on the surface of the dielectric layer, and a doped glass layer is also formed on the first doped conductive layer; A mask layer is prepared on the surface of the doped glass layer.

19. The preparation method according to claim 18, characterized in that, The steps of the graphical processing include: Remove the mask layer and the doped glass layer in the third region, which is the region outside the first and second regions; First wet cleaning: Remove the first doped conductive layer and the dielectric layer in the third region, remove the film layers on the side surface and the light-receiving surface of the substrate, remove the mask layer and the doped glass layer in the first region and the second region, so that the light-receiving surface of the substrate and the backlight surface of the third region form a textured structure.

20. The preparation method according to claim 19, characterized in that, After the first wet cleaning and before the surface treatment, the preparation method further includes: Preparation of passivation layer: depositing a first passivation layer on the light-receiving surface of the substrate, and depositing a second passivation layer on the first doped conductive layer on the back-light surface of the substrate; Preparation of antireflection layer: Deposit the antireflection layer on the surface of the first passivation layer opposite to the substrate to obtain a first semi-finished product; Sintering: The first semi-finished product is processed at 730℃~750℃ for 30 s~90 s to obtain the second semi-finished product; Photoinjection: The second semi-finished product is processed at 600℃~700℃ for 10 s~60 s to obtain the third semi-finished product; The second passivation layer and the anti-reflection layer on the second passivation layer are removed from the third semi-finished product to obtain the fourth semi-finished product; Preparation of intrinsic layer: The intrinsic layer is prepared on the back side of the fourth semi-finished product, wherein the back side is the backlight side of the substrate; Preparation of a second doped conductive layer: The second doped conductive layer is prepared on the surface of the intrinsic layer.

21. The preparation method according to claim 20, characterized in that, The surface treatment steps include: laser grooving to remove the second doped conductive layer and the intrinsic layer located in the second intermediate sub-region until the substrate is exposed; removing the second doped conductive layer located in the edge region and the first intermediate sub-region to obtain a patterned second doped conductive layer; removing a portion of the intrinsic layer in the edge region and the first intermediate sub-region, leaving a retained structure formed by the remaining intrinsic layer, the retained structure being the protruding microstructure; and / or, Following the surface treatment step, the preparation method further includes a second wet cleaning to remove laser residue from the first intermediate sub-region and the edge region.

22. The preparation method according to claim 21, characterized in that, Following the second wet cleaning step, the preparation method further includes: Fabrication of a transparent conductive layer: Depositing the transparent conductive layer on the backlight surface of the substrate having a patterned first doped conductive layer and a patterned second doped conductive layer; A designated area of ​​the transparent conductive layer is locally etched to expose the surfaces of a portion of the first doped conductive layer and a portion of the second doped conductive layer. The designated area corresponds to the region where the transparent conductive layer located at the junction of the third region and the second region is disconnected. Fabrication of the first gate line and the second gate line: The first gate line is fabricated on the transparent conductive layer in the first intermediate sub-region, and the second gate line is fabricated on the transparent conductive layer in the third region.

23. A photovoltaic module, characterized in that, The photovoltaic module includes the solar cell as described in any one of claims 1 to 14 and the solar cell prepared by the preparation method described in any one of claims 15 to 22.

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