Mother battery piece, battery piece, preparation method of mother battery piece and preparation method of battery piece, and photovoltaic module

Abstract

The invention provides a mother battery piece, a battery piece, a preparation method of the mother battery piece and a photovoltaic module. The battery piece comprises a first semiconductor substrate; the first doped semiconductor layer is arranged in the central region; the isolation groove is formed in the first isolation area and surrounds the central area; wherein the side surface comprises a first sub-surface, and the first sub-surface is connected with the groove wall of the isolation groove; the tunneling passivation contact structure is at least arranged on the second surface; the first passivation layer at least covers the first doped semiconductor layer, the isolation groove and the first sub-surface; wherein the first sub-surface and the second surface are both provided with a plurality of square tower footing structures, the difference between the side length of the largest square tower footing structure on the first sub-surface and the side length of the largest square tower footing structure on the second surface is a first numerical value, and the first numerical value is smaller than or equal to 15 microns. The battery efficiency can be improved, and the manufacturing cost can be reduced.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and in particular to a mother cell, a cell and its preparation method, and a photovoltaic module. Background Technology

[0002] With the continuous development of solar cell technology, people have higher and higher requirements for the photoelectric conversion efficiency of cells. However, the improvement of industrialized cell efficiency still faces many challenges. Among them, contact recombination in the metal-silicon contact area and Auger recombination and deep-level recombination caused by diffusion in the silicon matrix are the main factors restricting the improvement of cell efficiency.

[0003] TOPcon (Tunnel Oxide Passivated Contact) solar cells have a tunnel oxide layer and a doped polycrystalline silicon layer fabricated on the second side of the cell. These two layers together form a passivated contact structure, which can reduce the recombination rate, extend minority carrier lifetime, and improve the cell's photoelectric conversion efficiency. Currently, how to improve the efficiency of TOPcon cells while reducing manufacturing costs has become a key research focus for those skilled in the art. Summary of the Invention

[0004] Therefore, it is necessary to provide a mother cell, a cell and its preparation method, and a photovoltaic module that can improve battery efficiency and reduce manufacturing costs.

[0005] In a first aspect, embodiments of this application provide a battery cell, comprising:

[0006] A first semiconductor substrate includes a first surface, a second surface, and a side surface connecting the first surface and the second surface, wherein the first surface includes a central region and a first isolation region disposed around the central region;

[0007] A first doped semiconductor layer is disposed in the central region; the first doped semiconductor layer is of a first doping type.

[0008] An isolation groove is disposed in the first isolation area and surrounds the central area; wherein, the side surface includes a first sub-surface, and the first sub-surface is connected to the groove wall of the isolation groove;

[0009] A tunneling passivation contact structure is provided at least on the second surface; the tunneling passivation contact structure is a second doping type, and the first doping type and the second doping type are opposite.

[0010] The first passivation layer at least covers the first doped semiconductor layer, the isolation trench, and the first sub-surface;

[0011] The first sub-face and the second face are provided with multiple square tower base structures. The difference between the side length of the largest square tower base structure on the first sub-face and the side length of the largest square tower base structure on the second face is a first value, which is less than or equal to 15 μm.

[0012] In the aforementioned battery cell, on the one hand, the isolation trench serves as an isolation layer, preventing short circuits caused by the connection between the first doped semiconductor layer on the first surface and the conductive doped layer on the side surface. On the other hand, during the etching of the isolation trench, the substrate doped layer (inner expansion layer) on the side surface is etched simultaneously. This arrangement facilitates control over the etching depth of the isolation trench and the side surface during the process. This not only results in a shallower isolation trench depth, reducing the impact of excessively deep trenches on battery efficiency, but also makes the side length of the square tower base structure on the first sub-surface smaller, meaning the etching depth of the etchant on the side surface is shallower, which helps reduce damage to the first semiconductor substrate. This not only facilitates carrier collection but also reduces the reflection of external light. Furthermore, compared to related technologies, the difference between the side length of the largest square tower base structure on the first sub-surface and the side length of the largest square tower base structure on the second surface in this application is smaller, also reflecting the shallower etching depth of the etchant on the side surface, which helps reduce damage to the first semiconductor substrate. In addition, this application can also reduce the etching time in the side surface area, reducing process time and etchant costs.

[0013] In one embodiment, the bottom wall of the isolation groove is provided with a plurality of square tower base structures, wherein the side length of the largest square tower base structure on the bottom wall is greater than the side length of the largest square tower base structure on the first sub-surface;

[0014] And / or, the first difference is less than or equal to 15 μm and greater than or equal to -2 μm.

[0015] In one embodiment, no substrate doping layer is disposed within the first semiconductor substrate connected to the first sub-surface.

[0016] In one embodiment, the solar cell includes a first substrate doped layer of a second doping type, the first substrate doped layer being disposed on at least a portion of the side surface.

[0017] In one embodiment, the first substrate doped layer is disposed on the first sub-surface.

[0018] In one embodiment, the tunneling passivation contact structure is also located on a portion of the side surface, and along a direction perpendicular to the side surface, the orthographic projection of the first substrate doped layer on the side surface does not overlap with the orthographic projection of the tunneling passivation contact structure on the side surface.

[0019] In one embodiment, the solar cell further includes a second substrate doped layer disposed on the side of the tunneling passivation contact structure close to the first semiconductor substrate; the second substrate doped layer is a second doping type.

[0020] In one embodiment, the thickness of the first substrate doped layer is less than the thickness of the second substrate doped layer.

[0021] In one embodiment, the surface peak doping concentration of the first substrate doped layer is less than the surface peak doping concentration of the second substrate doped layer;

[0022] And / or, the total doping amount of the first substrate doped layer is less than the total doping amount of the second substrate doped layer.

[0023] In one embodiment, the first substrate doped layer and the second substrate doped layer are connected together.

[0024] In one embodiment, the side surface further includes a second sub-surface, the first sub-surface being located between the second sub-surface and the first isolation region; the second substrate doped layer located on the side surface is disposed on the second sub-surface;

[0025] The second sub-surface is provided with multiple square tower base structures, and the side length of the largest square tower base structure on the first sub-surface is greater than the side length of the largest square tower base structure on the second sub-surface.

[0026] In one embodiment, the first sub-face and the second sub-face are parallel, or the first sub-face is inclined relative to the second sub-face.

[0027] In one embodiment, the bottom wall of the isolation groove is a polished surface or a pyramidal velvet surface;

[0028] And / or, the depth of the isolation groove is between 3μm and 15μm.

[0029] In one embodiment, the first semiconductor substrate further includes a diced surface, one end of which is connected to the bottom wall of the isolation trench on the first surface, and the other end of which is connected to the second surface.

[0030] In one embodiment, the tunneling passivation contact structure includes a tunneling layer and a second doped semiconductor layer stacked along a direction away from the first semiconductor substrate; the second doped semiconductor layer is of a second doping type; and / or

[0031] The battery cell also includes:

[0032] A second passivation layer at least covers the tunneling passivation contact structure;

[0033] The first electrode is disposed on the first surface and is in ohmic contact with the first doped semiconductor layer;

[0034] The second electrode is disposed on the second surface and is in ohmic contact with the tunneling passivation contact structure.

[0035] Secondly, embodiments of this application provide a mother battery cell, comprising:

[0036] The second semiconductor substrate includes a first surface, a second surface, and a side surface connecting the first surface and the second surface, which are disposed opposite to each other. The first surface includes a second isolation region, a plurality of central regions, and at least one dicing region. The plurality of central regions are spaced apart, and a dicing region is provided between two adjacent central regions. The second isolation region surrounds the periphery of the plurality of central regions and the at least one dicing region.

[0037] A first doped semiconductor layer is disposed in the central region; the first doped semiconductor layer is of a first doping type.

[0038] Multiple isolation grooves are provided, each of which is arranged around a corresponding central area and is located in the second isolation area and the cutting area; wherein, the side surface includes a first sub-surface, the first sub-surface being connected to the groove wall of the isolation groove in the second isolation area;

[0039] A tunneling passivation contact structure is provided at least on the second surface; the tunneling passivation contact structure is a second doping type, and the first doping type and the second doping type are opposite.

[0040] The first passivation layer at least covers the first doped semiconductor layer, the isolation trench, and the first sub-surface;

[0041] The first sub-face and the second face are provided with multiple square tower base structures. The difference between the side length of the largest square tower base structure on the first sub-face and the side length of the largest square tower base structure on the second face is a first value, which is less than or equal to 15 μm.

[0042] In the aforementioned mother cell, on the one hand, the isolation trench serves as an isolation layer, preventing short circuits caused by the connection between the first doped semiconductor layer on the first surface and the conductive doped layer on the side surface. On the other hand, during the etching of the isolation trench, the substrate doped layer (inner expansion layer) on the side surface is etched simultaneously. This arrangement facilitates control over the etching depth of the isolation trench and the side surface during the process. This not only results in a shallower isolation trench depth, reducing the impact of excessively deep trenches on cell efficiency, but also makes the side length of the square tower base structure on the first sub-surface smaller, meaning the etching depth of the etchant on the side surface is shallower, which helps reduce damage to the first semiconductor substrate. This not only facilitates carrier collection but also reduces the reflection of external light. Furthermore, compared to related technologies, the difference between the side length of the largest square tower base structure on the first sub-surface and the side length of the largest square tower base structure on the second surface in this application is smaller, also reflecting the shallower etching depth of the etchant on the side surface, which helps reduce damage to the first semiconductor substrate. In addition, this application can also reduce the etching time in the side surface area, reducing process time and etchant costs.

[0043] In one embodiment, the plurality of central regions are spaced apart along a first direction, which is perpendicular to the thickness direction of the second semiconductor substrate.

[0044] In one embodiment, the bottom wall of the isolation groove is provided with a plurality of square tower base structures, wherein the side length of the largest square tower base structure on the bottom wall is greater than the side length of the largest square tower base structure on the first sub-surface;

[0045] And / or, the first difference is less than or equal to 15 μm and greater than or equal to -2 μm.

[0046] In one embodiment, no substrate doping layer is disposed in the second semiconductor substrate connected to the first sub-surface.

[0047] In one embodiment, the isolation groove includes a first groove segment and a second groove segment, the first groove segment being located in the cutting area and the second groove segment being located in the second isolation area; the width of the first groove segment is greater than the width of the second groove segment;

[0048] In a direction perpendicular to the extension direction of the isolation groove, the size of the first groove segment is the width of the first groove segment; in a direction perpendicular to the extension direction of the isolation groove, the size of the second groove segment is the width of the second groove segment.

[0049] In one embodiment, the solar cell includes a first substrate doped layer of a second doping type, the first substrate doped layer being disposed on at least a portion of the side surface.

[0050] In one embodiment, the first substrate doped layer is disposed on the first sub-surface.

[0051] In one embodiment, the tunneling passivation contact structure is also located on a portion of the side surface, and along a direction perpendicular to the side surface, the orthographic projection of the first substrate doped layer on the side surface does not overlap with the orthographic projection of the tunneling passivation contact structure on the side surface.

[0052] In one embodiment, the mother cell further includes a second substrate doped layer, which is disposed on the side of the tunneling passivation contact structure near the second semiconductor substrate; the second substrate doped layer is a second doping type.

[0053] In one embodiment, the thickness of the first substrate doped layer is less than the thickness of the second substrate doped layer.

[0054] In one embodiment, the surface peak doping concentration of the first substrate doped layer is less than the surface peak doping concentration of the second substrate doped layer;

[0055] And / or, the total doping amount of the first substrate doped layer is less than the total doping amount of the second substrate doped layer.

[0056] In one embodiment, the first substrate doped layer and the second substrate doped layer are connected together.

[0057] In one embodiment, the side surface further includes a second sub-surface, the first sub-surface being located between the second sub-surface and the second isolation region; the second substrate doped layer located on the side surface is disposed on the second sub-surface;

[0058] The second sub-surface is provided with multiple square tower base structures, and the side length of the largest square tower base structure on the first sub-surface is greater than the side length of the largest square tower base structure on the second sub-surface.

[0059] In one embodiment, the first sub-face and the second sub-face are parallel, or the first sub-face is inclined relative to the second sub-face.

[0060] In one embodiment, the bottom wall of the isolation groove is a polished surface or a pyramidal velvet surface;

[0061] And / or, the depth of the isolation groove is between 3μm and 15μm.

[0062] In one embodiment, the tunneling passivation contact structure includes a tunneling layer and a second doped semiconductor layer stacked along a direction away from the second semiconductor substrate; the second doped semiconductor layer is of a second doping type; and / or

[0063] The mother battery also includes:

[0064] A second passivation layer at least covers the tunneling passivation contact structure;

[0065] The first electrode is disposed on the first surface and is in ohmic contact with the first doped semiconductor layer;

[0066] The second electrode is disposed on the second surface and is in ohmic contact with the tunneling passivation contact structure.

[0067] Thirdly, embodiments of this application provide a method for preparing a battery cell, comprising:

[0068] A second semiconductor substrate is provided; the second semiconductor substrate includes a first surface, a second surface, and a side surface connecting the first surface and the second surface, the first surface includes a second isolation region, a plurality of central regions, and at least one dicing region, the plurality of central regions are spaced apart, and a dicing region is provided between two adjacent central regions, the second isolation region surrounds the periphery of the plurality of central regions and the at least one dicing region;

[0069] A first doped semiconductor layer and a plurality of initial isolation trenches are formed on the first surface; the first doped semiconductor layer is disposed in the central region, and each of the initial isolation trenches is disposed around a corresponding central region and is located in the second isolation region and the dicing region;

[0070] A tunneling passivation contact material layer is formed on the second semiconductor substrate; the tunneling passivation contact material layer covers the second surface, the side surface, and the initial isolation trench;

[0071] The initial isolation trench and at least a portion of the tunneling passivation contact material layer on the side surface are etched, and the initial isolation trench is further etched to obtain the isolation trench. The exposed area on the side surface is etched to obtain the first sub-surface and the tunneling passivation contact structure. The first doped semiconductor layer is of a first doping type, and the tunneling passivation contact structure is of a second doping type, with the first doping type and the second doping type being opposite. Multiple square tower base structures are provided on both the first sub-surface and the second surface. The difference between the side length of the largest square tower base structure on the first sub-surface and the side length of the largest square tower base structure on the second surface is a first value, which is less than or equal to 15 μm.

[0072] A first passivation layer is formed on the second semiconductor substrate; the first passivation layer at least covers the first doped semiconductor layer, the isolation trench, and the first sub-surface;

[0073] The dicing region of the second semiconductor substrate is diced to form multiple battery cells.

[0074] The aforementioned method for fabricating the battery cell has several advantages. First, the isolation trench serves as a barrier, preventing short circuits caused by the connection between the first doped semiconductor layer on the first surface and the conductive doped layer on the side surface. Second, during the etching of the isolation trench, the substrate doped layer (inner expansion layer) on the side surface is etched simultaneously. This arrangement facilitates control over the etching depth of the isolation trench and the side surface during the process. This not only results in a shallower isolation trench, reducing the impact of excessively deep trenches on battery efficiency, but also minimizes the side length of the square tower base structure on the first sub-surface. In other words, the etching depth of the etchant on the side surface is shallower, which helps reduce damage to the first semiconductor substrate. This not only facilitates carrier collection but also reduces the reflection of external light. Furthermore, compared to related technologies, the difference between the side length of the largest square tower base structure on the first sub-surface and the side length of the largest square tower base structure on the second surface is smaller, further demonstrating the shallower etching depth of the etchant on the side surface, which helps reduce damage to the first semiconductor substrate. In addition, this application can reduce the etching time in the side surface region, thereby reducing process time and etchant costs.

[0075] In one embodiment, the step of forming a first doped semiconductor layer and a plurality of initial isolation trenches on the first surface includes:

[0076] A first doped semiconductor material layer and a first silicon-oxygen dielectric layer are formed on the second semiconductor substrate; the first doped semiconductor material layer and the first silicon-oxygen dielectric layer are both located on the first surface and the side surface.

[0077] Remove the first silicon-oxygen dielectric layer from the second isolation region and the cutting region;

[0078] Remove the first silicon-oxygen dielectric layer on the side;

[0079] The first doped semiconductor material layer exposed by the first silicon oxide dielectric layer is removed to obtain the first doped semiconductor layer and the plurality of the initial isolation trenches.

[0080] In one embodiment, the step of removing the first silicon oxide dielectric layer from the second isolation region and the dicing region includes:

[0081] The first silicon oxide dielectric layer in the second isolation region and the cutting region is removed using a laser process.

[0082] In one embodiment, in the steps of etching the initial isolation trench and at least part of the tunneling passivation contact material layer on the side surface, further etching the initial isolation trench to obtain the isolation trench, and etching the exposed area on the side surface to obtain the first sub-face and the tunneling passivation contact structure, a first alkaline solution is used for etching, and the etching time of the first alkaline solution is between 100s and 400s.

[0083] In one embodiment, the first alkaline solution comprises potassium hydroxide, and the volume concentration of the alkaline solution in the first alkaline solution is between 1% and 3%.

[0084] Fourthly, embodiments of this application provide a photovoltaic module, which includes the solar cells in any of the embodiments of the first aspect. Attached Figure Description

[0085] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0086] Figure 1A This is a schematic diagram of the cross-sectional structure of a battery cell provided in one embodiment of this application.

[0087] Figure 1B This is a schematic diagram of the cross-sectional structure of another battery cell provided in an embodiment of this application.

[0088] Figure 1C This is a schematic diagram of the cross-sectional structure of another type of battery cell provided in an embodiment of this application.

[0089] Figure 2 This is a schematic diagram of the tower base structure of the first sub-face and the second sub-face (or the second face) provided in an embodiment of this application.

[0090] Figure 3A This is a schematic diagram of the cross-sectional structure of a mother cell provided in an embodiment of this application.

[0091] Figure 3B This is a schematic diagram of the cross-sectional structure of another mother cell provided in an embodiment of this application.

[0092] Figure 3C This is a schematic diagram of the cross-sectional structure of another mother cell provided in an embodiment of this application.

[0093] Figure 4 for Figure 3A The diagram shows a top view of the mother cell.

[0094] Figure 5 This is a top view schematic diagram of another mother cell provided in an embodiment of this application.

[0095] Figure 6 This is a schematic flowchart of a method for preparing a battery cell according to an embodiment of this application.

[0096] Figure 7 for Figure 6 A schematic diagram of the structure of the second semiconductor substrate in the fabrication method shown.

[0097] Figure 8 for Figure 6 The diagram shows the structure after the formation of the first doped semiconductor material layer and the first silicon-oxygen dielectric layer in the preparation method shown.

[0098] Figure 9 for Figure 6 A schematic diagram of the structure after the first silicon-oxygen dielectric layer is removed from a local area of ​​the first surface in the preparation method shown.

[0099] Figure 10 for Figure 6 The schematic diagram shows the structure after the first silicon-oxygen dielectric layer on the side and the second side is removed in the preparation method shown.

[0100] Figure 11 for Figure 6 The diagram shows the structure after the initial isolation groove is formed in the preparation method shown.

[0101] Figure 12 for Figure 6 The diagram shows the structure after the tunneling material layer and the second doped semiconductor material layer are formed in the preparation method shown.

[0102] Figure 13 for Figure 6 A schematic diagram of the structure after the removal of the second silicon-oxygen dielectric layer in a local area in the preparation method shown.

[0103] Figure 14 for Figure 6 The diagram shows the structure after the isolation trench and the first substrate doped layer are formed in the preparation method shown.

[0104] Figure 15 for Figure 6 The diagram shows the structure after the first passivation layer and the second passivation layer are formed in the preparation method shown.

[0105] Explanation of icon numbers:

[0106] 1. Mother cell; 10. Second semiconductor substrate; 20. Cell; 21. First semiconductor substrate; 22. First doped semiconductor layer; 23. Isolation trench; 231. First trench segment; 232. Second trench segment; 24. Tunneling passivation contact structure; 241. Tunneling layer; 242. Second doped semiconductor layer; 25. First substrate doped layer; 26. Second substrate doped layer; 27. First passivation layer; 28. Second passivation layer; 291. First electrode; 292. Second electrode;

[0107] M1, First face; M2, Second face; M3, Side face; M3-1, First sub-face; M3-2, Second sub-face; M4, Cutting face; Q1, Central area; Q2, First isolation area; Q3, Second isolation area; Q4, Cutting area; T1, Square tower base structure;

[0108] 100, First doped semiconductor material layer; 200, First silicon oxide dielectric layer; 300, Tunneling material layer; 400, Second doped semiconductor material layer; 500, Second silicon oxide dielectric layer; 600, Initial isolation trench; 700, Initial substrate doped layer. Detailed Implementation

[0109] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0110] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0111] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0112] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0113] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0114] Embodiments of the application are described herein with reference to cross-sectional views illustrating preferred embodiments (and intermediate structures), thus allowing for the anticipation of variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shape of the area shown herein, but should include shape deviations due to, for example, manufacturing techniques.

[0115] Firstly, such as Figure 1A and Figure 1B As shown, this application embodiment provides a battery cell 20, which includes a first semiconductor substrate 21, a first doped semiconductor layer 22, an isolation trench 23, a tunneling passivation contact structure 24, and a first passivation layer 27.

[0116] The first semiconductor substrate 21 includes a first surface M1, a second surface M2, and a side surface M3 connecting the first surface M1 and the second surface M2, which are disposed opposite to each other. The first surface M1 includes a central region Q1 and a first isolation region Q2 surrounding the central region Q1. A first doped semiconductor layer 22 is disposed in the central region Q1. In this embodiment, the central region Q1 can be considered as the region where the first doped semiconductor layer 22 is disposed. An isolation trench 23 is disposed in the first isolation region Q2 and surrounds the central region Q1. In this embodiment, the first isolation region Q2 can be considered as the region where the isolation trench 23 is disposed. The side surface M3 includes a first sub-surface M3-1, which is connected to the trench wall of the isolation trench 23. A tunneling passivation contact structure 24 is disposed at least on the second surface M2. The first doped semiconductor layer 22 is of a first doping type, and the tunneling passivation contact structure 24 and the first substrate doped layer 25 are of a second doping type, with the first doping type and the second doping type being opposite.

[0117] Furthermore, the first passivation layer 27 at least covers the first doped semiconductor layer 22, the isolation trench 23, and the first sub-surface M3-1. Specifically, the first passivation layer 27 is in contact with the first doped semiconductor layer 22, the isolation trench 23, and the first sub-surface M3-1. In this way, the first passivation layer 27 can passivate the region where the isolation trench 23 is located and the region where the first sub-surface M3-1 is located, thereby improving passivation performance.

[0118] Among them, multiple square tower base structures T1 are provided on the first sub-face M3-1 and the second sub-face M2. The difference between the side length of the largest square tower base structure T1 on the first sub-face M3-1 and the side length of the largest square tower base structure T1 on the second sub-face M2 is a first value, which is less than or equal to 15μm.

[0119] Here, the side length of the square tower base structure T1 refers to the side length of the base of the square tower base structure T1. For example... Figure 2As shown in Figure (a), the side length of the largest square tower base structure T1 on the first sub-face M3-1 is L1, as follows: Figure 2 As shown in Figure (b), the side length of the largest square tower base structure T1 on the second face M2 is L2. It should be noted that in this application, the top view shape of the square tower base structure can be not only a perfect square, but also an approximate square (or near-square). It is understood that an approximate square can be as follows: Figure 2 A square with a notch at the corner, or an approximate square, can also be a rectangle with a small difference between its long and short sides (e.g., the length difference is within 20%). It is understood that other shapes of tower base structures can be set on the first sub-face M3-1 and the second face M2.

[0120] In this embodiment, on the one hand, the isolation trench 23 can serve as an isolation layer to prevent a short circuit caused by the connection between the first doped semiconductor layer 22 on the first surface M1 and the conductive doped layer on the side surface M3; on the other hand, during the etching of the isolation trench 23, the substrate doped layer (inner extension layer) on the side surface M3 is etched simultaneously. This arrangement facilitates control over the etching depth of the isolation trench 23 and the etching depth of the side surface M3 during the process. This not only makes the depth of the isolation trench 23 shallower, reducing the impact of excessively deep isolation trench 23 on battery efficiency, but also makes the side length of the square tower base structure T1 on the first sub-surface M3-1 smaller, i.e. The shallow etching depth of the etching solution on side M3 helps reduce damage to the first semiconductor substrate 21. This not only facilitates carrier collection but also reduces the reflection of external light. Furthermore, compared to related technologies, the difference between the side length of the largest square tower base structure T1 on the first sub-surface M3-1 and the side length of the largest square tower base structure T1 on the second surface M2 is smaller, which also reflects the shallow etching depth of the etching solution on side M3, which helps reduce damage to the first semiconductor substrate 21. In addition, this application can also reduce the etching time in the side M3 region, thereby reducing process time and etching solution costs. Furthermore, compared to related technologies, under the same etching solution, the etching time of this embodiment is shorter, resulting in less damage to the mask layer (such as the second silicon oxide dielectric layer) of the second surface M2, thus providing better protection for the tunneling passivation contact structure 24. Under the same etching time, the solution concentration and etching solution volume selected in this embodiment are lower. The etching depth of the second semiconductor substrate 10 is shallower, resulting in less damage to the second semiconductor substrate 10 and less impact on battery efficiency. In summary, this embodiment can not only reduce etching costs but also improve battery performance.

[0121] In one embodiment, the first difference is less than or equal to 15 μm and greater than or equal to -2 μm.

[0122] In one embodiment, the first difference is less than or equal to 15 μm and greater than 0 μm.

[0123] In one embodiment, the bottom wall of the isolation groove 23 is provided with a plurality of square tower base structures T1, and the side length of the largest square tower base structure T1 on the bottom wall is greater than the side length of the largest square tower base structure T1 on the first sub-face M3-1.

[0124] It should be noted that the interface area of ​​the front M1 is large, so the bubbles generated by the alkali-silicon reaction will quickly form a large bubble and detach from the surface, thus accelerating the reaction. On the other hand, the interface area of ​​the side M3 is small, so the bubbles are difficult to detach. Therefore, the reaction rate of the side M3 is relatively low, which results in a deeper etching depth of the isolation groove 23 and a larger side length of the largest square tower base structure T1.

[0125] In one embodiment, such as Figure 1C As shown, no substrate doping layer is disposed within the first semiconductor substrate 21 connected to the first sub-surface M3-1. It should be noted that the first sub-surface M3-1 can be a part of the side surface M3 or the entire side surface M3.

[0126] In one embodiment, the battery cell 20 includes a first substrate doped layer 25 of a second doping type, which is disposed on at least a portion of the side surface M3. On one hand, the first substrate doped layer 25 enhances the field passivation effect and improves carrier collection efficiency. On the other hand, during the etching of the isolation trench 23, the substrate doped layer (inner extension layer) on the side surface M3 is etched simultaneously. This arrangement facilitates control over the etching depth of the isolation trench 23 and the side surface M3 during the process. This not only makes the isolation trench 23 shallower, reducing the impact of excessively deep isolation trench 23 on battery efficiency, but also allows for the retention of a portion of the substrate doped layer (inner extension layer) on the side surface M3, resulting in the first substrate doped layer 25. Furthermore, compared to related technologies, it is not necessary to completely remove the substrate doped layer (inner extension layer) in the side surface M3 region, reducing the etching time in the side surface M3 region and lowering process time and etching solution costs.

[0127] In one embodiment, a first substrate doped layer 25 is disposed on a first sub-surface M3-1.

[0128] In one embodiment, the first semiconductor substrate 21 is a silicon substrate, the doping type of the first semiconductor substrate 21 is N-type, the doping type of the first doped semiconductor layer 22 is P-type, and the doped film layer of the tunneling passivation contact structure 24 is N-type.

[0129] In one embodiment, along the thickness direction of the first semiconductor substrate 21, the orthographic projection of the first doped semiconductor layer 22 on the first surface M1 does not overlap with the first isolation region Q2; in other words, the orthographic projection of the first doped semiconductor layer 22 is located outside the first isolation region Q2.

[0130] In one embodiment, such as Figure 1B As shown, the tunneling passivation contact structure 24 is only located on the second surface M2. The side surface M3 does not have the tunneling passivation contact structure 24. Furthermore, a second substrate doped layer 26 is provided on the second surface M2.

[0131] In one embodiment, such as Figure 1A As shown, the tunneling passivation contact structure 24 is also located on part of the side surface M3. Along the direction perpendicular to the side surface M3, the orthographic projection of the first substrate doped layer 25 on the side surface M3 does not overlap with the orthographic projection of the tunneling passivation contact structure 24 on the side surface M3. In other words, the tunneling passivation contact structure 24 does not cover the first substrate doped layer 25.

[0132] It is understandable that by providing the tunneling passivation contact structure 24 on the second surface M2 and part of the side surface M3, the carrier collection area can be increased on the one hand, and the passivation performance of the side surface M3 region of the first semiconductor substrate 21 can be improved on the other hand.

[0133] In one embodiment, the solar cell 20 further includes a second substrate doped layer 26, which is disposed on the side of the tunneling passivation contact structure 24 near the first semiconductor substrate 21; in other words, the second substrate doped layer 26 is disposed within the first semiconductor substrate 21 and is located on the side of the tunneling passivation contact structure 24 near the first semiconductor substrate 21, and the second substrate doped layer 26 is connected to the tunneling passivation contact structure 24.

[0134] Furthermore, the first substrate doped layer 25 and the second substrate doped layer 26 have the same doping type; in other words, the second substrate doped layer 26 has a second doping type. By setting the second substrate doped layer 26, the field passivation effect can be further enhanced, and the carrier collection efficiency can be improved. By making the first substrate doped layer 25 and the second substrate doped layer 26 have the same doping type, the first substrate doped layer 25 and the second substrate doped layer 26 can be fabricated in the same process, which helps to reduce fabrication costs.

[0135] In one embodiment, the doping type of the first substrate doped layer 25 is the same as that of the first semiconductor substrate 21. This forms a high-low junction near the side surface M3 of the first semiconductor substrate 21, which is beneficial for improving battery efficiency.

[0136] In one embodiment, the thickness of the first substrate doped layer 25 is less than the thickness of the second substrate doped layer 26. Here, the thickness of the first substrate doped layer 25 refers to the maximum distance between the side of the first substrate doped layer 25 furthest from the center of the first semiconductor substrate 21 and the side of the first substrate doped layer 25 closest to the center of the first semiconductor substrate 21, and the thickness of the second substrate doped layer 26 refers to the minimum distance between the side of the second substrate doped layer 26 furthest from the center of the first semiconductor substrate 21 and the side of the second substrate doped layer 26 closest to the center of the first semiconductor substrate 21. This configuration allows for the formation of a stepped or sloping structure on the side surface M3, which is beneficial for increasing the contact area between the subsequent passivation film layer (such as the first passivation layer 27) and the first semiconductor substrate 21, thereby improving their adhesion.

[0137] In one embodiment, the peak surface doping concentration of the first substrate doped layer 25 is lower than the peak surface doping concentration of the second substrate doped layer 26. This allows for the formation of a substrate doped layer (inner extension layer) with a concentration gradient on the side surface M3, which is beneficial for improving battery efficiency.

[0138] In one embodiment, the total doping amount of the first substrate doped layer 25 is less than the total doping amount of the second substrate doped layer 26.

[0139] In one embodiment, the first substrate doped layer 25 and the second substrate doped layer 26 are connected. This allows the substrate doped layers (inner extension layers) to be continuous on the side surface M3, thereby maximizing the field passivation performance.

[0140] In one embodiment, such as Figure 1A As shown, side surface M3 also includes a second sub-surface M3-2, and the first sub-surface M3-1 is located between the second sub-surface M3-2 and the first isolation region Q2. Figure 1A Taking the orientation as an example, the first sub-surface M3-1 is located above the second sub-surface M3-2. The second substrate doped layer 26, located on the side M3, is disposed on the second sub-surface M3-2; in other words, the second substrate doped layer 26 is disposed within the first semiconductor substrate 21 and connected to the second sub-surface M3-2. Figure 2 As shown, a square tower base structure T1 is provided on the second sub-face M3-2. The side length of the largest square tower base structure T1 on the first sub-face M3-1 is greater than the side length of the square tower base structure T1 on the second sub-face M3-2. In the embodiments of this application, the side length refers to the side length of the bottom surface of the square tower base structure T1.

[0141] like Figure 2 As shown in Figure (a), the side length of the largest square tower base structure T1 on the first sub-face M3-1 is L1, as follows: Figure 2 As shown in Figure (b), the side length of the largest square tower base structure T1 on the second sub-face M3-2 is L2.

[0142] The above configuration can improve the flatness of the first sub-surface M3-1, thereby reflecting the light that is about to be emitted from the first semiconductor substrate 21 back to the first semiconductor substrate 21 and improving the light utilization rate.

[0143] In one embodiment, the roughness of the first sub-face M3-1 is less than the roughness of the second sub-face M3-2.

[0144] In one embodiment, the first sub-face M3-1 and the second sub-face M3-2 are parallel, or the first sub-face M3-1 is inclined relative to the second sub-face M3-2; in other words, the first sub-face M3-1 and the second sub-face M3-2 are not parallel.

[0145] In one embodiment, the bottom wall of the isolation groove 23 is a polished surface or a pyramidal textured surface. Here, the bottom wall of the isolation groove 23 is the groove wall of the isolation groove 23 near the second surface M2.

[0146] In one example, the bottom wall of the isolation groove 23 is polished. This allows the isolation groove 23 and the side wall M3 to be polished in the same process, which helps to reduce the number of processes and lower manufacturing costs.

[0147] In one example, the bottom wall of the isolation groove 23 is made of pyramidal textured material. This reduces light reflection in the area where the isolation groove 23 is located and enhances light absorption in the area where the isolation groove 23 is located, thereby improving light utilization.

[0148] In one embodiment, the central area Q1 of the first face M1 is a pyramidal velvet surface.

[0149] In one embodiment, the depth H of the isolation trench 23 is between 3 μm and 15 μm. Here, the depth H of the isolation trench 23 refers to the maximum distance between the upper surface of the first passivation layer 27 above the first doped semiconductor layer 22 and the lowest point of the isolation trench 23. Exemplarily, the depth H can be 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 15 μm, or between any two of the above values.

[0150] The above configuration ensures that the lowest point of the isolation trench 23 is lower than the lowest point of the first doped semiconductor layer 22, thus guaranteeing the isolation performance of the isolation trench 23. On the other hand, if the isolation trench 23 is too deep, it will have an adverse effect on carrier collection. The above configuration can minimize the impact of the isolation trench 23 on the battery efficiency.

[0151] In one embodiment, such as Figure 1AAs shown, the first semiconductor substrate 21 also includes a diced surface M4. One end of the diced surface M4 is connected to the bottom wall of the isolation groove 23 on the first surface M1, and the other end of the diced surface M4 is connected to the second surface M2. In one example, a first semiconductor substrate 21 has one diced surface M4 and three side surfaces M3. In another example, a first semiconductor substrate 21 has two diced surfaces M4 and two side surfaces M3, wherein the two diced surfaces M4 are opposite to each other, and the two side surfaces M3 are opposite to each other.

[0152] Optionally, the cross-sectional shape of the isolation groove 23 is L-shaped or L-shaped.

[0153] In one embodiment, the tunneling passivation contact structure 24 includes a tunneling layer 241 and a second doped semiconductor layer 242 stacked along a direction away from the first semiconductor substrate 21; the doping type of the second doped semiconductor layer 242 is the same as the doping type of the first substrate doped layer 25, and the second doped semiconductor layer 242 is a second doping type. For example, the tunneling layer 241 is made of silicon oxide. The second doped semiconductor layer 242 is made of doped polycrystalline silicon.

[0154] In one embodiment, the solar cell 20 further includes a second passivation layer 28, a first electrode 291, and a second electrode 292. The second passivation layer 28 at least covers the tunneling passivation contact structure 24. The first electrode 291 is disposed on the first surface M1 and has an ohmic contact with the first doped semiconductor layer 22. The second electrode 292 is disposed on the second surface M2 and has an ohmic contact with the tunneling passivation contact structure 24.

[0155] In one example, the second passivation layer 28 also covers the first passivation layer 27.

[0156] In one example, the first electrode 291 extends through the first passivation layer 27 and makes an ohmic contact with the first doped semiconductor layer 22.

[0157] In one example, the second electrode 292 penetrates the second passivation layer 28 and makes an ohmic contact with the second doped semiconductor layer 242 in the tunnel passivation contact structure 24.

[0158] It should be noted that either the first passivation layer 27 or the second passivation layer 28 can cover the side surface M3, or both can cover the side surface M3. On the side surface M3, the first passivation layer 27 and the second passivation layer 28 can overlap each other. Alternatively, on the side surface M3, the first passivation layer 27 and the second passivation layer 28 can not overlap, but are only connected, thereby enabling full-area passivation of the side surface M3.

[0159] Secondly, such as Figure 3A and Figure 3BAs shown, this application embodiment provides a mother cell 1, which is split into at least two cells 20. Specifically, the mother cell 1 includes a second semiconductor substrate 10, a first doped semiconductor layer 22, a tunneling passivation contact structure 24, and a plurality of isolation trenches 23.

[0160] The second semiconductor substrate 10 includes a first surface M1, a second surface M2, and a side surface M3 connecting the first surface M1 and the second surface M2, which are disposed opposite to each other. The first surface M1 includes a second isolation region Q3, a plurality of central regions Q1, and at least one dicing region Q4. The plurality of central regions Q1 are spaced apart, and a dicing region Q4 is provided between two adjacent central regions Q1. The second isolation region Q3 surrounds the periphery of the plurality of central regions Q1 and the at least one dicing region Q4. Here, the dicing region Q4 is a diced region. A first doped semiconductor layer 22 is disposed in the central region Q1. Among the plurality of isolation trenches 23, each isolation trench 23 is disposed around a corresponding central region Q1 and is located between the second isolation region Q3 and the dicing region Q4. A tunneling passivation contact structure 24 is disposed at least in the second surface M2. The first doped semiconductor layer 22 is of a first doping type, and the tunneling passivation contact structure 24 and the first substrate doped layer 25 are of a second doping type, with the first doping type and the second doping type being opposite. The side surface M3 includes a first sub-surface M3-1, which is connected to the wall of the isolation groove 23 of the second isolation zone Q3.

[0161] Furthermore, the first passivation layer 27 at least covers the first doped semiconductor layer 22, the isolation trench 23, and the first sub-surface M3-1. Specifically, the first passivation layer 27 is in contact with the first doped semiconductor layer 22, the isolation trench 23, and the first sub-surface M3-1. Thus, the first passivation layer 27 can passivate the region where the isolation trench 23 is located and the region where the first substrate doped layer 25 is located, thereby improving passivation performance.

[0162] Furthermore, multiple square tower base structures T1 are provided on both the first sub-face M3-1 and the second sub-face M2. The difference between the side length of the largest square tower base structure T1 on the first sub-face M3-1 and the side length of the largest square tower base structure T1 on the second sub-face M2 is a first value, which is less than or equal to 15μm.

[0163] Here, the side length of the square tower base structure T1 refers to the side length of the base of the square tower base structure T1. For example... Figure 2 As shown in Figure (a), the side length of the largest square tower base structure T1 on the first sub-face M3-1 is L1, as follows: Figure 2As shown in figure (b), the side length of the largest square tower base structure T1 on the second surface M2 is L2. It should be noted that in this application, the top view shape of the square tower base structure can not only be an absolute square, but also an approximate square (or quasi-square). It can be understood that the approximate square can be a square with a notch at the corner as in Figure 2 , or a rectangle with a very small difference between the long side and the short side (such as the length difference is within 20%). It can be understood that other shaped tower base structures can be provided on the first sub-surface M3-1 and the second surface M2.

[0164] It can be understood that each isolation groove 23 is a ring structure, and two adjacent isolation grooves 23 can share a part of the groove section.

[0165] In one example, the first surface M1 includes two central regions Q1 and a cutting region Q4. As Figure 4 shown, the top view shape of the isolation groove 23 is a "day" character shape.

[0166] In another example, the first surface M1 includes three central regions Q1 and two cutting regions Q4. As Figure 5 shown, the top view shape of the isolation groove 23 is an "eye" character shape.

[0167] It should be noted that after裂片 (the text here seems to be incorrect or incomplete, assuming it's "裂片" which might be a misspelling, perhaps "裂片" should be "裂片后"), the second isolation region Q3 and the cutting region Q4 outside the central region Q1 together constitute the first isolation region Q2 in the foregoing embodiment.

[0168] The aforementioned mother cell 1, on the one hand, the isolation trench 23 can serve as an isolation layer to prevent short circuits caused by the connection between the first doped semiconductor layer 22 on the first surface M1 and the conductive doped layer on the side surface M3; on the other hand, during the etching of the isolation trench 23, the substrate doped layer (inner extension layer) on the side surface M3 is etched simultaneously. This arrangement facilitates control over the etching depth of the isolation trench 23 and the etching depth of the side surface M3 during the process. This not only results in a shallower isolation trench 23, reducing the impact of an excessively deep trench 23 on cell efficiency, but also makes the side length of the square tower base structure T1 on the first sub-surface M3-1 smaller, i.e. The shallow etching depth of the etching solution on side M3 helps reduce damage to the first semiconductor substrate 21. This not only facilitates carrier collection but also reduces the reflection of external light. Furthermore, compared to related technologies, the difference between the side length of the largest square tower base structure T1 on the first sub-surface M3-1 and the side length of the largest square tower base structure T1 on the second surface M2 is smaller, which also reflects the shallow etching depth of the etching solution on side M3, which helps reduce damage to the first semiconductor substrate 21. In addition, this application can also reduce the etching time in the side M3 region, thereby reducing process time and etching solution costs. Furthermore, compared to related technologies, under the same etching solution, the etching time of this embodiment is shorter, resulting in less damage to the mask layer (such as the second silicon oxide dielectric layer) of the second surface M2, thus providing better protection for the tunneling passivation contact structure 24. Under the same etching time, the solution concentration and etching solution volume selected in this embodiment are lower. The etching depth of the second semiconductor substrate 10 is shallower, resulting in less damage to the second semiconductor substrate 10 and less impact on battery efficiency. In summary, this embodiment can not only reduce etching costs but also improve battery performance.

[0169] In one embodiment, the first difference is less than or equal to 15 μm and greater than or equal to -2 μm.

[0170] In one embodiment, the first difference is less than or equal to 15 μm and greater than 0 μm.

[0171] In one embodiment, the bottom wall of the isolation groove 23 is provided with a plurality of square tower base structures T1, and the side length of the largest square tower base structure T1 on the bottom wall is greater than the side length of the largest square tower base structure T1 on the first sub-face M3-1.

[0172] It should be noted that the interface area of ​​the front M1 is large, so the bubbles generated by the alkali-silicon reaction will quickly form a large bubble and detach from the surface, thus accelerating the reaction. On the other hand, the interface area of ​​the side M3 is small, so the bubbles are difficult to detach. Therefore, the reaction rate of the side M3 is relatively low, which results in a deeper etching depth of the isolation groove 23 and a larger side length of the largest square tower base structure T1.

[0173] In one embodiment, such as Figure 3C As shown, no substrate doping layer is disposed within the first semiconductor substrate 21 connected to the first sub-surface M3-1. It should be noted that the first sub-surface M3-1 can be a part of the side surface M3 or the entire side surface M3.

[0174] In one embodiment, the mother cell 1 includes a first substrate doped layer 25 of a second doping type, which is disposed on at least a portion of the side surface M3. On one hand, the first substrate doped layer 25 enhances the field passivation effect and improves carrier collection efficiency. On the other hand, during the etching of the isolation trench 23, the substrate doped layer (inner extension layer) on the side surface M3 is etched simultaneously. This arrangement facilitates control over the etching depth of the isolation trench 23 and the side surface M3 during the process. This not only makes the isolation trench 23 shallower, reducing the impact of excessively deep isolation trench 23 on cell efficiency, but also allows for the retention of a portion of the substrate doped layer (inner extension layer) on the side surface M3, resulting in the first substrate doped layer 25. Furthermore, compared to related technologies, it is not necessary to completely remove the substrate doped layer (inner extension layer) in the side surface M3 region, reducing the etching time in the side surface M3 region and lowering process time and etching solution costs.

[0175] In one embodiment, a first substrate doped layer 25 is disposed on a first sub-surface M3-1.

[0176] In one embodiment, along the thickness direction of the first semiconductor substrate 21, the orthographic projection of the first doped semiconductor layer 22 on the first surface M1 does not overlap with the first isolation region Q2; in other words, the orthographic projection of the first doped semiconductor layer 22 is located outside the first isolation region Q2.

[0177] In one embodiment, such as Figure 3B As shown, the tunneling passivation contact structure 24 is only located on the second surface M2. The side surface M3 does not have the tunneling passivation contact structure 24. Furthermore, a second substrate doped layer 26 is provided on the second surface M2.

[0178] In one embodiment, such as Figure 3A As shown, the tunneling passivation contact structure 24 is also located on part of the side surface M3. Along the direction perpendicular to the side surface M3, the orthographic projection of the first substrate doped layer 25 on the side surface M3 does not overlap with the orthographic projection of the tunneling passivation contact structure 24 on the side surface M3. In other words, the tunneling passivation contact structure 24 does not cover the first substrate doped layer 25.

[0179] It is understandable that by providing the tunneling passivation contact structure 24 on the second surface M2 and part of the side surface M3, the carrier collection area can be increased on the one hand, and the passivation performance of the side surface M3 region of the first semiconductor substrate 21 can be improved on the other hand.

[0180] In one embodiment, such as Figure 4 and Figure 5 As shown, the isolation groove 23 includes a first groove segment 231 and a second groove segment 232. The first groove segment 231 is located in the cutting area Q4, and the second groove segment 232 is located in the second isolation area Q3. The width of the first groove segment 231 is greater than the width of the second groove segment 232.

[0181] In a direction perpendicular to the extension direction of the isolation groove 23, the dimension of the first groove segment 231 is the width of the first groove segment 231; in a direction perpendicular to the extension direction of the isolation groove 23, the dimension of the second groove segment 232 is the width of the second groove segment 232.

[0182] The above configuration facilitates cell splitting and minimizes the area occupied by the isolation groove 23, thereby reducing the impact of the isolation groove 23 on battery performance.

[0183] In one example, the width of the first slot 231 is between 300μm and 600μm, and the width of the second slot 232 is between 1μm and 150μm.

[0184] In one embodiment, multiple central regions Q1 are arranged at intervals along a first direction, which is perpendicular to the thickness direction of the second semiconductor substrate 10. It is understood that the number of dicing regions Q4 is one less than the number of central regions Q1, and the number of central regions Q1 can be 2, 3, 4, 5, 6, or more. This arrangement facilitates the dicing of the mother cell 1 to form a relatively regular cell 20.

[0185] In one embodiment, the mother cell 1 further includes a second substrate doped layer 26, which is disposed on the side of the tunneling passivation contact structure 24 near the second semiconductor substrate 10. In other words, the second substrate doped layer 26 is disposed within the second semiconductor substrate 10 and located on the side of the tunneling passivation contact structure 24 near the second semiconductor substrate 10, and the second substrate doped layer 26 is connected to the tunneling passivation contact structure 24.

[0186] Furthermore, the first substrate doped layer 25 and the second substrate doped layer 26 have the same doping type; in other words, the second substrate doped layer 26 has a second doping type. By setting the second substrate doped layer 26, the field passivation effect can be further enhanced, and the carrier collection efficiency can be improved. By making the first substrate doped layer 25 and the second substrate doped layer 26 have the same doping type, the first substrate doped layer 25 and the second substrate doped layer 26 can be fabricated in the same process, which helps to reduce fabrication costs.

[0187] In one embodiment, the doping type of the first substrate doped layer 25 is the same as that of the second semiconductor substrate 10. This forms a high-low junction near the side surface M3 of the second semiconductor substrate 10, which is beneficial for improving battery efficiency.

[0188] In one embodiment, the thickness of the first substrate doped layer 25 is less than the thickness of the second substrate doped layer 26. Here, the thickness of the first substrate doped layer 25 refers to the maximum distance between the side of the first substrate doped layer 25 furthest from the center of the second semiconductor substrate 10 and the side of the first substrate doped layer 25 closest to the center of the second semiconductor substrate 10. The thickness of the second substrate doped layer 26 refers to the minimum distance between the side of the second substrate doped layer 26 furthest from the center of the parent second semiconductor substrate 10 and the side of the second substrate doped layer 26 closest to the center of the second semiconductor substrate 10. This configuration allows for the formation of a stepped or sloping structure on the side surface M3, which is beneficial for increasing the contact area between the subsequent passivation film layer (such as the first passivation layer 27) and the second semiconductor substrate 10, thereby improving their adhesion.

[0189] In one embodiment, the peak surface doping concentration of the first substrate doped layer 25 is lower than the peak surface doping concentration of the second substrate doped layer 26. This allows for the formation of a substrate doped layer (inner extension layer) with a concentration gradient on the side surface M3, which is beneficial for improving battery efficiency.

[0190] In one embodiment, the total doping amount of the first substrate doped layer 25 is less than the total doping amount of the second substrate doped layer 26.

[0191] In one embodiment, the first substrate doped layer 25 and the second substrate doped layer 26 are connected. This allows the substrate doped layers (inner extension layers) to be continuous on the side surface M3, thereby maximizing the field passivation performance.

[0192] In one embodiment, such as Figure 3A As shown, side surface M3 also includes a second sub-surface M3-2, and the first sub-surface M3-1 is located between the second sub-surface M3-2 and the first isolation region Q2. Figure 3A Taking the orientation as an example, the first sub-surface M3-1 is located above the second sub-surface M3-2. The second substrate doped layer 26, located on the side M3, is disposed on the second sub-surface M3-2; in other words, the second substrate doped layer 26 is disposed within the first semiconductor substrate 21 and connected to the second sub-surface M3-2. Figure 2 As shown, a square tower base structure T1 is provided on the second sub-face M3-2. The side length of the largest square tower base structure T1 on the first sub-face M3-1 is greater than the side length of the square tower base structure T1 on the second sub-face M3-2. In the embodiments of this application, the side length refers to the side length of the bottom surface of the square tower base structure T1.

[0193] like Figure 2 As shown in Figure (a), the side length of the largest square tower base structure T1 on the first sub-face M3-1 is L1, as follows: Figure 2 As shown in Figure (b), the side length of the largest square tower base structure T1 on the second sub-face M3-2 is L2.

[0194] The above configuration can improve the flatness of the first sub-surface M3-1, thereby reflecting the light that is about to be emitted from the first semiconductor substrate 21 back to the first semiconductor substrate 21 and improving the light utilization rate.

[0195] In one embodiment, the roughness of the first sub-face M3-1 is less than the roughness of the second sub-face M3-2.

[0196] In one embodiment, the first sub-face M3-1 and the second sub-face M3-2 are parallel, or the first sub-face M3-1 is inclined relative to the second sub-face M3-2; in other words, the first sub-face M3-1 and the second sub-face M3-2 are not parallel.

[0197] In one embodiment, the bottom wall of the isolation groove 23 is a polished surface or a pyramidal textured surface. Here, the bottom wall of the isolation groove 23 is the groove wall of the isolation groove 23 near the second surface M2.

[0198] In one example, the bottom wall of the isolation groove 23 is polished. This allows the isolation groove 23 and the side wall M3 to be polished in the same process, which helps to reduce the number of processes and lower manufacturing costs.

[0199] In one example, the bottom wall of the isolation groove 23 is made of pyramidal textured material. This reduces light reflection in the area where the isolation groove 23 is located, thereby improving light utilization.

[0200] In one embodiment, the central area Q1 of the first face M1 is a pyramidal velvet surface.

[0201] In one embodiment, the depth of the isolation groove 23 is between 3 μm and 15 μm. For example... Figure 3A As shown, the depth H of the isolation trench 23 refers to the distance between the upper surface of the first passivation layer 27 above the first doped semiconductor layer 22 and the lowest point of the isolation trench 23. For example, the depth H can be 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 15μm, or any two of the above values.

[0202] The above configuration ensures that the lowest point of the isolation trench 23 is lower than the lowest point of the first doped semiconductor layer 22, thus guaranteeing the isolation performance of the isolation trench 23. On the other hand, if the isolation trench 23 is too deep, it will have an adverse effect on carrier collection. The above configuration can minimize the impact of the isolation trench 23 on the battery efficiency.

[0203] In one embodiment, the tunneling passivation contact structure 24 includes a tunneling layer 241 and a second doped semiconductor layer 242 stacked along a direction away from the second semiconductor substrate 10; the doping type of the second doped semiconductor layer 242 is the same as the doping type of the first substrate doped layer 25. Exemplarily, the tunneling layer 241 is made of silicon oxide. The second doped semiconductor layer 242 is made of doped polycrystalline silicon.

[0204] Optionally, the cross-sectional shape of the isolation groove 23 located in the second isolation zone Q3 is L-shaped or L-shaped, and the cross-sectional shape of the isolation groove 23 located in the cutting zone Q4 is rectangular, rectangular, trapezoidal or trapezoidal.

[0205] In one embodiment, the mother cell 1 further includes a second passivation layer 28, a first electrode 291, and a second electrode 292. The second passivation layer 28 at least covers the tunneling passivation contact structure 24. The first electrode 291 is disposed on the first surface M1 and has an ohmic contact with the first doped semiconductor layer 22. The second electrode 292 is disposed on the second surface M2 and has an ohmic contact with the tunneling passivation contact structure 24.

[0206] In one example, the second passivation layer 28 also covers the first passivation layer 27.

[0207] In one example, the first electrode 291 extends through the first passivation layer 27 and makes an ohmic contact with the first doped semiconductor layer 22.

[0208] In one example, the second electrode 292 penetrates the second passivation layer 28 and makes an ohmic contact with the second doped semiconductor layer 242 in the tunnel passivation contact structure 24.

[0209] It should be noted that either the first passivation layer 27 or the second passivation layer 28 can cover the side surface M3, or both can cover the side surface M3. On the side surface M3, the first passivation layer 27 and the second passivation layer 28 can overlap each other. Alternatively, on the side surface M3, the first passivation layer 27 and the second passivation layer 28 can not overlap, but are only connected, thereby enabling full-area passivation of the side surface M3.

[0210] Thirdly, embodiments of this application provide a method for preparing a battery cell 20. This method can be used to prepare the battery cell 20 in the first aspect embodiment. Specifically, as shown in... Figure 6 As shown, the preparation method includes the following steps:

[0211] S100: A second semiconductor substrate 10 is provided. The second semiconductor substrate 10 includes a first surface M1, a second surface M2, and a side surface M3 connecting the first surface M1 and the second surface M2, which are disposed opposite to each other. The first surface M1 includes a second isolation region Q3, a plurality of central regions Q1, and at least one dicing region Q4. The plurality of central regions Q1 are spaced apart, and a dicing region Q4 is provided between two adjacent central regions Q1. The second isolation region Q3 surrounds the periphery of the plurality of central regions Q1 and the at least one dicing region Q4. Exemplarily, the second semiconductor substrate 10 may be monocrystalline silicon or polycrystalline silicon. It is understood that in this step, a cleaning solution can be used to remove contaminants on the second semiconductor substrate 10. In one example, the cleaning solution is an alkaline solution. The structure of the second semiconductor substrate 10 is as follows: Figure 7 As shown.

[0212] S200: A first doped semiconductor layer 22 and a plurality of initial isolation trenches 600 are formed on the first surface M1. The first doped semiconductor layer 22 is disposed in the central region Q1, and each initial isolation trench 600 is disposed around a corresponding central region Q1 and located in the second isolation region Q3 and the dicing region Q4. For example, the depth of the initial isolation trenches 600 is between 1 μm and 2 μm.

[0213] S300: A tunneling passivation contact material layer is formed on the second semiconductor substrate 10. It should be noted that this step may also involve forming an initial substrate doped layer 700 on the second semiconductor substrate 10. The tunneling passivation contact material layer covers the second surface M2, the side surface M3, and the initial isolation trench 600. Figure 12 As shown, exemplarily, the tunneling passivation contact material layer includes a tunneling material layer 300 and a second doped semiconductor material layer 400. It is understood that during the fabrication of the tunneling passivation contact material layer, a high-temperature annealing process is employed for crystallization, during which dopant ions diffuse into the second semiconductor substrate 10 to form an initial substrate doped layer 700. It should be noted that a second silicon oxide dielectric layer 500 can also be formed simultaneously in this step; in one example, the second silicon oxide dielectric layer 500 is a phosphosilicate glass layer. It is understood that the tunneling material layer 300 can be fabricated using plasma oxidation or thermal oxidation processes, and the second doped semiconductor material layer 400 and the second silicon oxide dielectric layer 500 can be fabricated using PECVD or LPCVD processes.

[0214] S400: Etch the initial isolation trench 600 and at least part of the tunneling passivation contact material layer on the side surface M3, and further etch the initial isolation trench 600 to obtain the isolation trench 23, and etch the exposed initial substrate doped layer 700 on the side surface M3 to obtain the first sub-surface M3-1 and the tunneling passivation contact structure 24. The first doped semiconductor layer 22 is of the first doping type, and the tunneling passivation contact structure 24 and the first substrate doped layer 25 are of the second doping type, with the first doping type and the second doping type being opposite. Multiple square tower base structures T1 are provided on both the first sub-surface M3-1 and the second surface M2. The difference between the side length of the largest square tower base structure T1 on the first sub-surface M3-1 and the side length of the largest square tower base structure T1 on the second surface M2 is a first value, which is less than or equal to 15 μm.

[0215] S500: A first passivation layer 27 is formed on the second semiconductor substrate 10. In one example, the first passivation layer 27 is formed on the first surface M1 and the side surface M3. The first passivation layer 27 at least covers the first doped semiconductor layer 22, the isolation trench 23, and the first sub-surface M3-1.

[0216] S600: The cutting region Q4 of the second semiconductor substrate 10 is cut to form multiple solar cells 20. In one example, a 300W laser is used to heat the isolation groove 23 along the cutting region Q4, followed by water spraying on the heating line. Due to thermal expansion and contraction of the mother solar cell 1 and the thermal stress caused by the heating spot, the mother solar cell 1 cracks from the isolation groove 23. As the transport fork moves, the mother solar cell 1 gradually cracks from beginning to end.

[0217] The above-described method for fabricating the battery cell 20 has two advantages. First, the isolation trench 23 serves as an isolation layer to prevent short circuits caused by the connection between the first doped semiconductor layer 22 on the first surface M1 and the conductive doped layer on the side surface M3. Second, during the etching of the isolation trench 23, the substrate doped layer (inner extension layer) on the side surface M3 is etched simultaneously. This arrangement facilitates control over the etching depth of the isolation trench 23 and the etching depth of the side surface M3 during the process. This not only results in a shallower isolation trench 23, reducing the impact of an excessively deep isolation trench 23 on battery efficiency, but also makes the side length of the square tower base structure T1 on the first sub-surface M3-1 smaller. In other words, the etching depth of the etching solution on the side M3 is shallower, which helps to reduce damage to the first semiconductor substrate 21. This not only facilitates carrier collection but also reduces the reflection of external light. Furthermore, compared with related technologies, the difference between the side length of the largest square tower base structure T1 on the first sub-surface M3-1 and the side length of the largest square tower base structure T1 on the second surface M2 is smaller, which also reflects that the etching depth of the etching solution on the side M3 is shallower, which helps to reduce damage to the first semiconductor substrate 21. In addition, this application can also reduce the etching time of the side M3 region, thereby reducing the process time and etching solution cost. Furthermore, compared to related technologies, under the same etching solution, the etching time of this embodiment is shorter, resulting in less damage to the mask layer (such as the second silicon oxide dielectric layer) of the second surface M2, thus providing better protection for the tunneling passivation contact structure 24. Under the same etching time, the solution concentration and etching solution volume selected in this embodiment are lower. The etching depth of the second semiconductor substrate 10 is shallower, resulting in less damage to the second semiconductor substrate 10 and less impact on battery efficiency. In summary, this embodiment can not only reduce etching costs but also improve battery performance.

[0218] In one embodiment, S200: forming a first doped semiconductor layer 22 and a plurality of initial isolation trenches 600 on the first surface M1, specifically including the following steps:

[0219] S210: A first doped semiconductor material layer 100 and a first silicon-oxygen dielectric layer 200 are formed on the second semiconductor substrate 10. For example... Figure 8 As shown, the first doped semiconductor material layer 100 and the first silicon oxide dielectric layer 200 are both located on the first surface M1 and the side surface M3. Exemplarily, the first doped semiconductor material layer 100 and the first silicon oxide dielectric layer 200 can be formed using a boron diffusion process, wherein the first silicon oxide dielectric layer 200 is a borosilicate glass layer. It is understood that the first doped semiconductor material layer 100 and the first silicon oxide dielectric layer 200 can also be located on the second surface M2.

[0220] S220: Remove the first silicon-oxide dielectric layer 200 from the second isolation region Q3 and the dicing region Q4. (e.g.) Figure 9 As shown, the etching window of the isolation groove 23 can be defined in this way.

[0221] S230: Remove the first silicon-oxide dielectric layer 200 on the side M3. (e.g.) Figure 10 As shown, exemplarily, the silicon wafer is first pre-cleaned using deionized water or other cleaning solutions to remove surface dust and impurities. Next, the second semiconductor substrate 10 is placed in a chain cleaning machine, and the BSG on the second surface M2 and the side surface M3 is etched using a hydrofluoric acid (HF) solution. The concentration of the HF solution can be 5%-20%. Then, the second semiconductor substrate 10 is rinsed multiple times with deionized water to remove residual HF solution. Finally, nitrogen or compressed air is used to dry the surface of the second semiconductor substrate 10, ensuring the surface is dry.

[0222] S240: Remove the first doped semiconductor material layer 100 exposed by the first silicon oxide dielectric layer 200 to obtain the first doped semiconductor layer 22 and multiple initial isolation trenches 600. Specifically, as shown... Figure 11 As shown, an alkaline solution can be used for polishing to remove the first doped semiconductor material layer 100 on the second surface M2 and the side surface M3, as well as the first doped semiconductor material layer 100 in the exposed area of ​​the first surface M1. In one example, an alkaline solution such as potassium hydroxide (KOH) is used for polishing, with a KOH concentration of approximately 10% and a temperature of 60°C-80°C. After alkaline polishing, a post-alkaline wash can be performed to remove residual alkaline solution and reaction products from the surface.

[0223] In one embodiment, S220: Removing the first silicon oxide dielectric layer 200 from the second isolation region Q3 and the dicing region Q4 specifically includes the following steps:

[0224] S221: The first silicon oxide dielectric layer 200 of the second isolation region Q3 and the cutting region Q4 is removed by laser process. In this way, the first silicon oxide dielectric layer 200 in the area where the isolation trench 23 of the first surface M1 is located can be quickly removed, which facilitates the formation of the isolation trench 23 in subsequent processes.

[0225] In one embodiment, the laser used in the laser process is a Gaussian beam with a power between 10W and 40W. Exemplarily, the laser power can be 10W, 20W, 30W, 40W, or any two of the above values. The spot size is between 30μm and 40μm. Exemplarily, the spot size can be 30μm, 35μm, 38μm, 40μm, or any two of the above values. The frequency is between 500kHz and 1500kHz. Exemplarily, the frequency can be 500kHz, 800kHz, 1000kHz, 1200kHz, 1500kHz, or any two of the above values. The scanning speed is between 10,000 mm / s and 30,000 mm / s. For example, the scanning speed can be 10,000 mm / s, 12,000 mm / s, 16,000 mm / s, 20,000 mm / s, 25,000 mm / s, 28,000 mm / s, 30,000 mm / s, or between any two of the above values.

[0226] By keeping the process parameters of the laser process within the above range, it is beneficial to quickly remove the first silicon oxide dielectric layer 200, and on the other hand, to avoid damage to the second semiconductor substrate 10 by the laser, thereby reducing the battery efficiency.

[0227] In one embodiment, the laser used in the laser process is a flat-top beam with a power between 40W and 100W. Exemplarily, the laser power can be 40W, 50W, 60W, 70W, 80W, 90W, 100W, or any two of the above values. The spot size is between 100μm and 140μm. Exemplarily, the spot size can be 100μm, 110μm, 120μm, 130μm, 140μm, or any two of the above values. The frequency is between 200kHz and 800kHz. Exemplarily, the frequency can be 200kHz, 400kHz, 600kHz, 800kHz, or any two of the above values. The scanning speed is between 35,000 mm / s and 60,000 mm / s. For example, the scanning speed can be 35,000 mm / s, 40,000 mm / s, 45,000 mm / s, 50,000 mm / s, 55,000 mm / s, 60,000 mm / s, or between any two of the above values.

[0228] In one embodiment, in steps S400: etching the initial isolation trench 600 and at least a portion of the tunneling passivation contact material layer on the side surface M3, further etching the initial isolation trench 600 to obtain the isolation trench 23, and etching the exposed initial substrate doped layer 700 on the side surface M3 to obtain the first substrate doped layer 25 and the tunneling passivation contact structure 24, a first alkaline solution is used for etching, and the etching time of the first alkaline solution is between 100s and 400s. Figure 13 This is a schematic diagram of the structure before etching. Figure 14 This is a schematic diagram of the structure after etching.

[0229] It should be noted that in related technologies, it is usually necessary to completely remove the initial substrate doped layer 700 on side M3 to avoid short circuits. In this embodiment, when etching the tunneling passivation contact material layer on the initial isolation trench 600 and the tunneling passivation contact material layer on side M3, due to the rate difference between the first surface M1 and side M3, the interface area of ​​the first surface M1 is large, and the bubbles generated by the alkali-silicon reaction will more quickly form a large bubble and detach from the surface, thereby accelerating the reaction. However, the interface area of ​​side M3 is small, and the bubbles are difficult to detach, so the reaction rate of side M3 is relatively low. Therefore, under the same etching solution, after the tunneling passivation contact material layer on the initial isolation trench 600 and the initial substrate doped layer 700 below the initial isolation trench 600 are removed, a certain thickness of the initial substrate doped layer 700 will remain on side M3, at which point the etching process is stopped. Compared to related technologies, under the same etching solution, the etching time of this application embodiment is shorter, resulting in less damage to the mask layer (such as the second silicon oxide dielectric layer) of the second surface M3, thus providing better protection for the tunneling passivation contact structure 24. Under the same etching time, the solution concentration and etching solution volume selected in this application embodiment are lower. The etching depth of the second semiconductor substrate 10 in this application embodiment is shallower, resulting in less damage to the second semiconductor substrate 10 and less impact on battery efficiency. In summary, this application embodiment can not only reduce etching costs but also improve battery performance.

[0230] In one embodiment, the first alkaline solution comprises potassium hydroxide, and the volume concentration of the alkaline solution in the first alkaline solution is between 1% and 3%. Exemplarily, the volume concentration of potassium hydroxide is 1%, 2.1%, 2.2%, 2.3%, 2.4%, 2.5%, or 3%. In one example, the etching reaction temperature is 65°C to 80°C.

[0231] Please refer to the table below. The inventors have compared related technologies with the embodiments of this application. It can be seen that the etching time of the embodiments of this application is shorter, the amount of material added per batch is smaller, and the solution loss is less, reducing solution loss by approximately 30%. In addition, the isolation trench 23 of the embodiments of this application is shallower, causing less damage to the second semiconductor substrate 10 and having less impact on battery efficiency; the side length of the largest square tower base structure within the isolation trench 23 is smaller, and the side length of the largest square tower base structure on the side is also smaller, resulting in less reflection of external light.

[0232]

[0233] In one embodiment, in steps S400: etching the initial isolation trench 600 and at least a portion of the tunneling passivation contact material layer on the side surface M3, further etching the initial isolation trench 600 to obtain the isolation trench 23, and etching the exposed initial substrate doped layer 700 on the side surface M3 to obtain the first substrate doped layer 25 and the tunneling passivation contact structure 24, after etching with a first alkaline solution, a second alkaline solution is used to remove organic matter, followed by a hydrofluoric acid solution to remove the first silicon oxide dielectric layer 200 and the second silicon oxide dielectric layer 500. The second alkaline solution can be potassium hydroxide and hydrogen peroxide, or ozone water. The structure after removing the first silicon oxide dielectric layer 200 and the second silicon oxide dielectric layer 500 is as follows... Figure 14 As shown.

[0234] In one embodiment, S500: A first passivation layer 27 is formed on the second semiconductor substrate 10. Then, the following steps are included:

[0235] S510: A second passivation layer 28 is formed on the second semiconductor substrate 10. Specifically, the second passivation layer 28 is formed on the second surface M2 and the side surface M3.

[0236] S520: A first electrode 291 and a second electrode 292 are formed on the second semiconductor substrate 10. Specifically, the first electrode 291 and the second electrode 292 can be fabricated using coating and sintering processes.

[0237] Fourthly, embodiments of this application provide a photovoltaic module, which includes the solar cell 20 in any embodiment of the first aspect.

[0238] The individual solar cells can be connected together by string welding, thereby collecting the electrical energy generated by each cell for subsequent transmission. Of course, the solar cells can be arranged at intervals or stacked together in a shingled manner.

[0239] For example, a photovoltaic module also includes an encapsulation layer and a cover plate, the encapsulation layer being used to cover the surface of the battery string and the cover plate being used to cover the surface of the encapsulation layer away from the battery string.

[0240] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0241] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A battery cell, characterized in that, include: A first semiconductor substrate includes a first surface, a second surface, and a side surface connecting the first surface and the second surface, wherein the first surface includes a central region and a first isolation region disposed around the central region; A first doped semiconductor layer is disposed in the central region; the first doped semiconductor layer is of a first doping type. An isolation groove is disposed in the first isolation area and surrounds the central area; wherein, the side surface includes a first sub-surface, and the first sub-surface is connected to the groove wall of the isolation groove; A tunneling passivation contact structure is provided at least on the second surface; the tunneling passivation contact structure is a second doping type, and the first doping type and the second doping type are opposite. The first passivation layer at least covers the first doped semiconductor layer, the isolation trench, and the first sub-surface; The first sub-face and the second face are provided with multiple square tower base structures. The difference between the side length of the largest square tower base structure on the first sub-face and the side length of the largest square tower base structure on the second face is a first value, which is less than or equal to 15 μm.

2. The battery cell according to claim 1, characterized in that, The bottom wall of the isolation trench is provided with multiple square tower base structures, and the side length of the largest square tower base structure on the bottom wall is greater than the side length of the largest square tower base structure on the first sub-surface; And / or, the first difference is less than or equal to 15 μm and greater than or equal to -2 μm.

3. The battery cell according to claim 1, characterized in that, No substrate doping layer is provided in the first semiconductor substrate connected to the first sub-surface.

4. The battery cell according to claim 1, characterized in that, The solar cell includes a first substrate doped layer of a second doping type, the first substrate doped layer being disposed on at least a portion of the side surface.

5. The battery cell according to claim 4, characterized in that, The first substrate doped layer is disposed on the first sub-surface.

6. The battery cell according to claim 5, characterized in that, The tunneling passivation contact structure is also located on a portion of the side surface, and along a direction perpendicular to the side surface, the orthographic projection of the first substrate doped layer on the side surface does not overlap with the orthographic projection of the tunneling passivation contact structure on the side surface.

7. The battery cell according to claim 6, characterized in that, The solar cell further includes a second substrate doped layer, which is disposed on the side of the tunneling passivation contact structure close to the first semiconductor substrate; the second substrate doped layer is a second doping type.

8. The battery cell according to claim 7, characterized in that, The thickness of the first substrate doped layer is less than the thickness of the second substrate doped layer.

9. The battery cell according to claim 7, characterized in that, The surface peak doping concentration of the first substrate doped layer is less than the surface peak doping concentration of the second substrate doped layer; And / or, the total doping amount of the first substrate doped layer is less than the total doping amount of the second substrate doped layer.

10. The battery cell according to claim 7, characterized in that, The first substrate doped layer and the second substrate doped layer are connected.

11. The battery cell according to claim 7, characterized in that, The side surface further includes a second sub-surface, and the first sub-surface is located between the second sub-surface and the first isolation region; the second substrate doped layer located on the side surface is disposed on the second sub-surface; The second sub-surface is provided with multiple square tower base structures, and the side length of the largest square tower base structure on the first sub-surface is greater than the side length of the largest square tower base structure on the second sub-surface.

12. The battery cell according to claim 11, characterized in that, The first sub-face and the second sub-face are parallel, or the first sub-face is inclined relative to the second sub-face.

13. The battery cell according to any one of claims 1-12, characterized in that, The bottom wall of the isolation groove is a polished surface or a pyramidal velvet surface; And / or, the depth of the isolation groove is between 3μm and 15μm.

14. The battery cell according to any one of claims 1-12, characterized in that, The first semiconductor substrate further includes a diced surface, one end of which is connected to the bottom wall of the isolation trench on the first surface, and the other end of which is connected to the second surface.

15. The battery cell according to any one of claims 1-12, characterized in that, The tunneling passivation contact structure includes a tunneling layer and a second doped semiconductor layer stacked along a direction away from the first semiconductor substrate; the second doped semiconductor layer is of a second doping type. and / or The battery cell also includes: A second passivation layer at least covers the tunneling passivation contact structure; The first electrode is disposed on the first surface and is in ohmic contact with the first doped semiconductor layer; The second electrode is disposed on the second surface and is in ohmic contact with the tunneling passivation contact structure.

16. A mother cell, characterized in that, include: The second semiconductor substrate includes a first surface, a second surface, and a side surface connecting the first surface and the second surface, which are disposed opposite to each other. The first surface includes a second isolation region, a plurality of central regions, and at least one dicing region. The plurality of central regions are spaced apart, and a dicing region is provided between two adjacent central regions. The second isolation region surrounds the periphery of the plurality of central regions and the at least one dicing region. A first doped semiconductor layer is disposed in the central region; the first doped semiconductor layer is of a first doping type. Multiple isolation grooves are provided, each of which is arranged around a corresponding central area and is located in the second isolation area and the cutting area; wherein, the side surface includes a first sub-surface, the first sub-surface being connected to the groove wall of the isolation groove in the second isolation area; A tunneling passivation contact structure is provided at least on the second surface; the tunneling passivation contact structure is a second doping type, and the first doping type and the second doping type are opposite. The first passivation layer at least covers the first doped semiconductor layer, the isolation trench, and the first sub-surface; The first sub-face and the second face are provided with multiple square tower base structures. The difference between the side length of the largest square tower base structure on the first sub-face and the side length of the largest square tower base structure on the second face is a first value, which is less than or equal to 15 μm.

17. The mother cell according to claim 16, characterized in that, The plurality of central regions are arranged at intervals along a first direction, which is perpendicular to the thickness direction of the second semiconductor substrate.

18. The mother cell according to claim 16, characterized in that, The bottom wall of the isolation trench is provided with multiple square tower base structures, and the side length of the largest square tower base structure on the bottom wall is greater than the side length of the largest square tower base structure on the first sub-surface; And / or, the first difference is less than or equal to 15 μm and greater than or equal to -2 μm.

19. The mother cell according to claim 16, characterized in that, No substrate doping layer is provided in the second semiconductor substrate connected to the first sub-surface.

20. The mother cell according to claim 16, characterized in that, The isolation groove includes a first groove segment and a second groove segment, the first groove segment being located in the cutting area and the second groove segment being located in the second isolation area; the width of the first groove segment is greater than the width of the second groove segment; In a direction perpendicular to the extension direction of the isolation groove, the size of the first groove segment is the width of the first groove segment; in a direction perpendicular to the extension direction of the isolation groove, the size of the second groove segment is the width of the second groove segment.

21. The battery cell according to claim 16, characterized in that, The mother cell includes a first substrate doped layer of a second doping type, the first substrate doped layer being disposed on at least a portion of the side surface.

22. The mother cell according to claim 21, characterized in that, The first substrate doped layer is disposed on the first sub-surface.

23. The mother cell according to claim 22, characterized in that, The tunneling passivation contact structure is also located on a portion of the side surface, and along a direction perpendicular to the side surface, the orthographic projection of the first substrate doped layer on the side surface does not overlap with the orthographic projection of the tunneling passivation contact structure on the side surface.

24. The mother cell according to claim 23, characterized in that, The mother cell also includes a second substrate doped layer, which is disposed on the side of the tunneling passivation contact structure close to the second semiconductor substrate; the second substrate doped layer is a second doping type.

25. The mother cell according to claim 24, characterized in that, The thickness of the first substrate doped layer is less than the thickness of the second substrate doped layer.

26. The mother cell according to claim 24, characterized in that, The surface peak doping concentration of the first substrate doped layer is less than the surface peak doping concentration of the second substrate doped layer; And / or, the total doping amount of the first substrate doped layer is less than the total doping amount of the second substrate doped layer.

27. The mother cell according to claim 24, characterized in that, The first substrate doped layer and the second substrate doped layer are connected.

28. The mother cell according to claim 24, characterized in that, The side surface further includes a second sub-surface, and the first sub-surface is located between the second sub-surface and the second isolation region; the second substrate doped layer located on the side surface is disposed on the second sub-surface; The second sub-surface is provided with multiple square tower base structures, and the side length of the largest square tower base structure on the first sub-surface is greater than the side length of the largest square tower base structure on the second sub-surface.

29. The mother cell according to claim 28, characterized in that, The first sub-face and the second sub-face are parallel, or the first sub-face is inclined relative to the second sub-face.

30. The mother cell according to any one of claims 16-29, characterized in that, The bottom wall of the isolation groove is a polished surface or a pyramidal velvet surface; And / or, the depth of the isolation groove is between 3μm and 15μm.

31. The mother cell according to any one of claims 16-29, characterized in that, The tunneling passivation contact structure includes a tunneling layer and a second doped semiconductor layer stacked along a direction away from the second semiconductor substrate; the second doped semiconductor layer is of a second doping type. and / or The mother battery also includes: A second passivation layer at least covers the tunneling passivation contact structure; The first electrode is disposed on the first surface and is in ohmic contact with the first doped semiconductor layer; The second electrode is disposed on the second surface and is in ohmic contact with the tunneling passivation contact structure.

32. A method for preparing a battery cell, characterized in that, include: Provide a second semiconductor substrate; The second semiconductor substrate includes a first surface, a second surface, and a side surface connecting the first surface and the second surface, which are disposed opposite to each other. The first surface includes a second isolation region, a plurality of central regions, and at least one dicing region. The plurality of central regions are spaced apart, and a dicing region is provided between two adjacent central regions. The second isolation region surrounds the periphery of the plurality of central regions and the at least one dicing region. A first doped semiconductor layer and a plurality of initial isolation trenches are formed on the first surface; the first doped semiconductor layer is disposed in the central region, and each of the initial isolation trenches is disposed around a corresponding central region and is located in the second isolation region and the dicing region; A tunneling passivation contact material layer is formed on the second semiconductor substrate; the tunneling passivation contact material layer covers the second surface, the side surface, and the initial isolation trench; The initial isolation trench and at least a portion of the tunneling passivation contact material layer on the side surface are etched, and the initial isolation trench is further etched to obtain the isolation trench. The exposed area on the side surface is etched to obtain the first sub-surface and the tunneling passivation contact structure. The first doped semiconductor layer is of a first doping type, and the tunneling passivation contact structure is of a second doping type, with the first doping type and the second doping type being opposite. Multiple square tower base structures are provided on both the first sub-surface and the second surface. The difference between the side length of the largest square tower base structure on the first sub-surface and the side length of the largest square tower base structure on the second surface is a first value, which is less than or equal to 15 μm. A first passivation layer is formed on the second semiconductor substrate; The first passivation layer at least covers the first doped semiconductor layer, the isolation trench, and the first sub-surface; The dicing region of the second semiconductor substrate is diced to form multiple battery cells.

33. The method for preparing a battery cell according to claim 32, characterized in that, The step of forming a first doped semiconductor layer and a plurality of initial isolation trenches on the first surface includes: A first doped semiconductor material layer and a first silicon-oxygen dielectric layer are formed on the second semiconductor substrate; the first doped semiconductor material layer and the first silicon-oxygen dielectric layer are both located on the first surface and the side surface. Remove the first silicon-oxygen dielectric layer from the second isolation region and the cutting region; Remove the first silicon-oxygen dielectric layer on the side; The first doped semiconductor material layer exposed by the first silicon oxide dielectric layer is removed to obtain the first doped semiconductor layer and the plurality of the initial isolation trenches.

34. The method for preparing a battery cell according to claim 33, characterized in that, The step of removing the first silicon oxide dielectric layer from the second isolation region and the dicing region includes: The first silicon oxide dielectric layer in the second isolation region and the cutting region is removed using a laser process.

35. The method for preparing a battery cell according to claim 32, characterized in that, In the steps of etching the initial isolation trench and at least part of the tunneling passivation contact material layer on the side surface, further etching the initial isolation trench to obtain the isolation trench, and etching the exposed area on the side surface to obtain the first sub-surface and the tunneling passivation contact structure, a first alkaline solution is used for etching, and the etching time of the first alkaline solution is between 100s and 400s.

36. The method for preparing a battery cell according to claim 35, characterized in that, The first alkaline solution includes potassium hydroxide, and the volume concentration of the alkaline solution in the first alkaline solution is between 1% and 3%.

37. A photovoltaic module, characterized in that, It includes at least one battery string, the battery string comprising at least two battery cells as claimed in any one of claims 1-15.

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