Semiconductor substrate and method of manufacturing the same, solar cell

Abstract

The application provides a semiconductor substrate, a preparation method thereof and a solar cell. The semiconductor substrate comprises a first surface and a second surface arranged oppositely, the first surface comprises a first region and a second region arranged alternately along a first direction; at least part of the first surface in the first region is a first rough surface; the first surface in the second region is provided with a first groove and a first convex part arranged alternately along the first direction; at least part of the bottom surface of the first groove is a second rough surface; the first convex part comprises two first inclined surfaces connected to each other, the two first inclined surfaces are located on both sides of the first convex part along the first direction; and the first inclined surface is arranged to incline away from the second region in the direction away from the first region. In this way, the light utilization rate can be improved, the short-circuit current and the open-circuit voltage can be improved, and thus the photoelectric conversion efficiency can be improved.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and in particular to a semiconductor substrate, its preparation method, and a solar cell. Background Technology

[0002] Solar cells, also known as photovoltaic cells, are semiconductor devices that directly convert sunlight into electrical energy. Because they are green and environmentally friendly products that do not cause pollution, and because solar energy is a renewable resource, solar cells are a new type of battery with broad development prospects.

[0003] In related technologies, the light-receiving surface of the substrate of a solar cell is provided with a textured structure. However, since the pyramids of the textured structure are at the same height, they are effective in capturing incident light, resulting in a low light absorption rate of the solar cell, which limits the improvement of the photoelectric conversion efficiency of the solar cell. Summary of the Invention

[0004] Based on this, this application provides a semiconductor substrate and its preparation method, as well as a solar cell, which can improve light absorption rate and thus improve photoelectric conversion efficiency.

[0005] In a first aspect, embodiments of this application provide a semiconductor substrate, including a first surface and a second surface disposed opposite to each other, wherein the first surface includes a first region and a second region alternately arranged along a first direction;

[0006] At least a portion of the first surface located in the first region is a first velvet surface;

[0007] The first surface located in the second region is provided with a first groove and a first protrusion arranged alternately along the first direction; at least a portion of the bottom surface of the first groove is a second velvety surface;

[0008] The first protrusion includes two interconnected first inclined surfaces, which are located on both sides of the first protrusion along the first direction; the first inclined surfaces are inclined toward the second region away from the first region.

[0009] In one embodiment, the second velvet surface includes a plurality of second pyramids;

[0010] The ratio of the maximum dimension L1 of the first protrusion along the first direction to the maximum dimension L2 of the second pyramid along the first direction is (3~15):1;

[0011] The ratio of the dimension S1 of the first protrusion along the second direction to the dimension S2 of the second pyramid along the second direction is (3~15):1; the second direction is perpendicular to the first direction and parallel to the thickness direction of the semiconductor substrate.

[0012] In one embodiment, the first velvet surface includes a plurality of first pyramids;

[0013] The ratio of the maximum dimension L1 of the first protrusion along the first direction to the maximum dimension L3 of the first pyramid along the first direction is (3~15):1;

[0014] The ratio of the dimension S1 of the first protrusion along the second direction to the dimension S3 of the first pyramid along the second direction is (3~15):1; the second direction is perpendicular to the first direction and parallel to the thickness direction of the semiconductor substrate.

[0015] In one embodiment, the roughness of the first inclined surface is less than the roughness of the bottom surface of the first groove, and the roughness of the first inclined surface is less than the roughness of the first surface located in the first region.

[0016] In one embodiment, the first groove is disposed adjacent to the first region;

[0017] The first groove includes a second inclined surface, which is inclined toward the second region in a direction close to the first region; the second inclined surface connects the first pile surface and the second pile surface; the first inclined surface connects the second pile surface.

[0018] In one embodiment, the roughness of the second inclined surface is less than the roughness of the bottom surface of the first groove, and the roughness of the second inclined surface is less than the roughness of the first surface located in the first region.

[0019] In one embodiment, a second groove is provided on the first surface of the first region; the bottom surface of the second groove is the first velvet surface;

[0020] The second groove is disposed adjacent to the first protrusion; the first inclined surface adjacent to the second groove is connected to the first velvet surface; the first inclined surface adjacent to the first groove is connected to the second velvet surface.

[0021] In one embodiment, the first protrusion has a mesh structure perpendicular to the second direction; and / or,

[0022] The first region has a mesh structure perpendicular to the second direction;

[0023] The second direction is parallel to the thickness direction of the semiconductor substrate.

[0024] In one embodiment, the dimension S4 of the first groove along the second direction is 5 micrometers to 30 micrometers; and / or,

[0025] The dimension L4 of the first region along the first direction is 80 micrometers to 300 micrometers.

[0026] In one embodiment, the second surface includes a third region and a fourth region that are alternately arranged along the first direction; the roughness of the third region is greater than that of the fourth region.

[0027] In one embodiment, the second surface located in the third region is provided with a plurality of second protrusions; a third groove is defined between adjacent second protrusions; the second protrusion includes a first plane and a third inclined surface connecting the bottom surface of the third groove and the first plane;

[0028] The second surface located in the fourth region is provided with a plurality of third protrusions, and a fourth groove is defined between adjacent third protrusions; the third protrusion includes a second plane and a fourth inclined surface connecting the bottom surface of the fourth groove and the second plane; the outer perimeter of the first plane is smaller than the outer perimeter of the second plane.

[0029] In one embodiment, the outer perimeter of the first plane is 4 micrometers to 40 micrometers;

[0030] The outer perimeter of the second plane is 40 micrometers to 300 micrometers.

[0031] In one embodiment, the acute angle α between the fourth inclined plane and the second plane is between 0 degrees and 23 degrees.

[0032] In one embodiment, the acute angle β between the third inclined plane and the first plane is 24 degrees to 54 degrees.

[0033] Secondly, embodiments of this application provide a method for preparing a semiconductor substrate, comprising:

[0034] A semiconductor substrate is provided, the semiconductor substrate including a first surface and a second surface disposed opposite to each other, the first surface having a first region and a second region alternately arranged along a first direction;

[0035] A first mask layer is formed on the first surface, and the first surface is etched based on the first mask layer, so that the first surface located in the second region has a first groove and a first protrusion arranged alternately along the first direction;

[0036] Remove the first mask layer;

[0037] The bottom surface of the first surface and the first groove are velveted, such that at least a portion of the first surface in the first region is a first velvet surface and at least a portion of the bottom surface of the first groove is a second velvet surface, such that the first protrusion includes two interconnected first inclined surfaces, the two first inclined surfaces being located on both sides of the first protrusion along the first direction; the first inclined surfaces are inclined toward the second region away from the first region.

[0038] In one embodiment, the step of forming a first mask layer on the first surface and etching the first surface based on the first mask layer, such that the first surface located in the second region has first grooves and first protrusions alternately arranged along the first direction, includes:

[0039] A first mask layer is formed on the first surface, the first mask layer including a plurality of first openings extending along the thickness direction of the first mask layer; the plurality of first openings are located in the second region in a direction perpendicular to a second direction; the second direction is parallel to the thickness direction of the semiconductor substrate;

[0040] The first surface exposed by the plurality of first openings is etched such that the first surface located in the second region has first grooves and first protrusions arranged alternately along the first direction.

[0041] In one embodiment, the step of forming a first mask layer on the first surface and etching the first surface based on the first mask layer, such that the first surface located in the second region has first grooves and first protrusions alternately arranged along the first direction, includes:

[0042] A first mask layer is formed on the first surface. The first mask layer includes a plurality of first openings and a second opening that extend along the thickness direction of the first mask layer. The plurality of first openings are located in the second region in a direction perpendicular to the second direction. The second openings are located in the first region in a direction perpendicular to the second direction.

[0043] The first surfaces exposed by the plurality of first openings and second openings are etched such that the first surface located in the second region has first grooves and first protrusions arranged alternately along the first direction, and the first surface located in the first region has second grooves.

[0044] In one embodiment, the step of flocking the bottom surfaces of the first surface and the first groove, such that at least a portion of the first surface in the first region is a first flocked surface and at least a portion of the bottom surface of the first groove is a second flocked surface, and such that the first protrusion includes two interconnected first inclined surfaces, includes:

[0045] The bottom surfaces of the first groove and the second groove are velvetted, such that at least a portion of the bottom surface of the first groove is the second velvet surface and the bottom surface of the second groove is the first velvet surface, such that the first protrusion includes two interconnected first inclined surfaces.

[0046] In one embodiment, the step of forming a first mask layer on the first surface and etching the first surface based on the first mask layer, such that the first surface located in the second region has first grooves and first protrusions alternately arranged along the first direction, includes:

[0047] The first surface is etched using a first preset solution and based on a first mask layer for a first preset duration, such that the first surface located in the second region has a first groove and a first protrusion arranged alternately along the first direction; the first preset solution includes deionized water, an alkaline solution and a texturing additive; the first preset duration is 500 to 2000 seconds.

[0048] In one embodiment, the volume ratio of the alkaline solution in the first preset solution is 2% to 5%; the volume ratio of the texturing additive is 0.2% to 0.6%.

[0049] In one embodiment, the step of flocking the bottom surfaces of the first surface and the first groove, such that at least a portion of the first surface in the first region is a first flocked surface and at least a portion of the bottom surface of the first groove is a second flocked surface, and such that the first protrusion includes two interconnected first inclined surfaces, includes:

[0050] The first surface and the bottom surface of the first groove are texturized using a second preset solution for a second preset duration, such that at least a portion of the first surface in the first region is a first texturized surface and at least a portion of the bottom surface of the first groove is a second texturized surface; such that the first protrusion includes two interconnected first inclined surfaces; the second preset solution includes deionized water, an alkaline solution and a texturizing additive; the second preset duration is 300 to 1000 seconds.

[0051] In one embodiment, in the second preset solution, the volume ratio of the alkaline solution is 0.2% to 2%; and the volume ratio of the texturing additive is 5% to 10%.

[0052] In one embodiment, the second surface includes a third region and a fourth region that are alternately arranged along the first direction;

[0053] The method further includes:

[0054] A second mask layer is formed on the first surface and the second surface respectively;

[0055] A plurality of third openings are formed on the second mask layer located on the second surface, extending along the thickness direction of the second mask layer, and the plurality of third openings are located within the third region perpendicular to the second direction; the second direction is parallel to the thickness direction of the semiconductor substrate;

[0056] The second surface exposed by the plurality of third openings is flocked to obtain a fourth flocked surface including a plurality of fourth pyramids;

[0057] Remove the second mask layer located on the second surface;

[0058] The second surface and the fourth textured surface are polished so that the roughness of the third region is greater than that of the fourth region;

[0059] Remove the second mask layer located on the first surface.

[0060] In one embodiment, the step of polishing the second surface and the fourth textured surface to make the roughness of the third region greater than that of the fourth region further includes:

[0061] The second surface and the fourth textured surface are polished using a third preset solution for a third preset duration, resulting in a plurality of second protrusions on the second surface located in the third region and a plurality of third protrusions on the second surface located in the fourth region; a third groove is defined between adjacent second protrusions; each second protrusion includes a first plane and a third inclined surface connecting the bottom surface of the third groove and the first plane; a fourth groove is defined between adjacent third protrusions; each third protrusion includes a second plane and a fourth inclined surface connecting the bottom surface of the fourth groove and the second plane;

[0062] The outer perimeter of the first plane is smaller than the outer perimeter of the second plane; the third preset solution includes deionized water, alkaline solution and additives; the third preset duration is 30 to 200 seconds.

[0063] In one embodiment, in the third preset solution, the volume ratio of the alkaline solution is 0.6% to 2%; and the volume ratio of the additive is 0.2% to 2%.

[0064] Thirdly, embodiments of this application provide a solar cell, comprising a semiconductor substrate as described in any one of the first aspects or a semiconductor substrate prepared by any one of the second aspects.

[0065] The semiconductor substrate is characterized by having at least a portion of the first surface in the first region being a first textured surface; the first surface in the second region being provided with alternating first grooves and first protrusions along a first direction, and at least a portion of the bottom surface of the first groove being a second textured surface; the first protrusion including two interconnected first inclined surfaces located on both sides of the first protrusion along the first direction; and the first inclined surfaces being inclined toward the second region away from the first region. In this way, on the one hand, the alternating arrangement of the first and second regions along the first direction on the first surface can form a highly differentiated three-dimensional morphology. The first textured surface of the first region retains the basic absorption advantage of traditional textured surfaces for perpendicularly incident light. On the other hand, the alternating arrangement of the first groove and the first protrusion in the second region further expands the spatial dimension of light absorption. The second textured surface on the bottom of the first groove and the first textured surface of the first region form a height difference, which not only significantly increases the effective surface area of ​​the light-receiving surface of the semiconductor substrate, allowing more incident light to come into contact with the substrate surface and reducing the probability of direct reflection and escape of light, but also forms a light trap through the first groove, causing the incident light to undergo multiple reflections within the first groove, thus extending the propagation path of light on the first surface of the semiconductor substrate. Especially for obliquely incident light, the three-dimensional combination of the first protrusion and the first groove can effectively capture light that is difficult to receive by a traditional single textured surface, greatly improving the capture efficiency of light at different incident angles. On the other hand, the first inclined surfaces on both sides of the first convex portion, tilted towards the second region away from the first region, form complementary light reflection angles. This allows incident light, after being reflected by the first inclined surfaces, to be guided to the adjacent first textured surface or first groove, avoiding ineffective light reflection and further improving light utilization. Furthermore, the synergistic effect of the multi-level textured surfaces (first textured surface, second textured surface), the first groove, and the first convex portion significantly extends the optical path of long-wavelength light within the semiconductor substrate, allowing more long-wavelength photons to be absorbed by the semiconductor substrate and converted into charge carriers, effectively reducing transmission loss of long-wavelength light. In addition, the height difference between the second textured surface at the bottom of the first groove and the first textured surface in the first region reduces the overall average thickness of the semiconductor substrate. This avoids the problems of easily bending and processing damage in thin substrates and increases the open-circuit voltage of the semiconductor substrate, thus improving photoelectric conversion efficiency. In summary, this application can improve light utilization, increase short-circuit current and open-circuit voltage, thereby improving photoelectric conversion efficiency. Attached Figure Description

[0066] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0067] Figure 1This is a first partial cross-sectional view of a semiconductor substrate provided for some embodiments of this application.

[0068] Figure 2 A second partial cross-sectional view of a semiconductor substrate provided for some embodiments of this application.

[0069] Figure 3 A third partial cross-sectional view of a semiconductor substrate provided for some embodiments of this application.

[0070] Figure 4 A fourth partial cross-sectional view of a semiconductor substrate provided for some embodiments of this application.

[0071] Figure 5 A fifth partial cross-sectional view of a semiconductor substrate provided for some embodiments of this application.

[0072] Figure 6 This is a first top view of a first surface of a semiconductor substrate provided in some embodiments of this application.

[0073] Figure 7 A second top view of a first side of a semiconductor substrate provided in some embodiments of this application.

[0074] Figure 8 A surface topography diagram of the second surface of a semiconductor substrate located in the third region, provided for some embodiments of this application.

[0075] Figure 9 A scanning electron microscope image of a second protrusion in the third region of a semiconductor substrate provided for some embodiments of this application.

[0076] Figure 10 A surface topography diagram of the second surface of a semiconductor substrate located in the fourth region, provided for some embodiments of this application.

[0077] Figure 11 A scanning electron microscope image of the third convex portion of a semiconductor substrate located in the fourth region, provided for some embodiments of this application.

[0078] Figure 12 This is a schematic flowchart illustrating a method for fabricating a semiconductor substrate according to some embodiments of this application.

[0079] Figure 13 This is another schematic flowchart illustrating a method for fabricating a semiconductor substrate provided in some embodiments of this application.

[0080] Explanation of icon numbers:

[0081] 10. Semiconductor substrate; 11. First surface; 11a. First region; 11b. Second region; 111. First textured surface; 1111. First pyramid; 112. First groove; 1121. Second slope; 113. Second textured surface; 1131. Second pyramid; 114. First convex part; 1141. First slope; 115. Second groove; 12. Second surface; 12a. Third region; 12b. Fourth region; 121. Second convex part; 1211. First plane; 1212. Third slope; 122. Third groove; 123. Third convex part; 1231. Second plane; 1232. Fourth slope; 124. Fourth groove; X. First direction; Z. Second direction. Detailed Implementation

[0082] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0083] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0084] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0085] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0086] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0087] Embodiments of the application are described herein with reference to cross-sectional views illustrating preferred embodiments (and intermediate structures), thus allowing for the anticipation of variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shape of the area shown herein, but should include shape deviations due to, for example, manufacturing techniques.

[0088] Firstly, see Figure 1 As shown, this application embodiment provides a semiconductor substrate 10. The semiconductor substrate 10 includes a first surface 11 and a second surface 12 disposed opposite to each other. The first surface 11 includes a first region 11a and a second region 11b arranged alternately along a first direction X. At least a portion of the first surface 11 located in the first region 11a is a first textured surface 111. The first surface 11 located in the second region 11b is provided with a first groove 112 and a first protrusion 114 arranged alternately along the first direction X. At least a portion of the bottom surface of the first groove 112 is a second textured surface 113. The first protrusion 114 includes two first inclined surfaces 1141 connected to each other, and the two first inclined surfaces 1141 are located on both sides of the first protrusion 114 along the first direction X. The first inclined surfaces 1141 are inclined toward the second region 11b in a direction away from the first region 11a.

[0089] Understandably, the first side 11 can be the light-receiving side, and the second side 12 can be the backlight side.

[0090] In some examples, at least a portion of the first surface 11 in the first region 11a is a first velvet surface 111; the first surface 11 in the second region 11b is provided with a first groove 112 and a first protrusion 114 arranged alternately along the first direction X, and at least a portion of the bottom surface of the first groove 112 is a second velvet surface 113; the first protrusion 114 includes two interconnected first inclined surfaces 1141, the two first inclined surfaces 1141 being located on both sides of the first protrusion 114 along the first direction X; the first inclined surfaces 1141 are inclined toward the second region 11b in a direction away from the first region 11a. In other words, the maximum distance between the first surface 11 and the second surface 12 in the first region 11a is greater than the maximum distance between the bottom surface of the first groove 112 and the second surface 12. A height difference exists between the first region 11a and the bottom surface of the first groove 112, increasing the effective surface area of ​​the first surface 11 of the semiconductor substrate 10. This increases the probability of light contacting the first surface 11 of the semiconductor substrate 10, allowing more incident light to interact with the first textured surface 111, the second textured surface 113, or the first inclined surface 1141 of the first protrusion 114, reducing the proportion of light directly reflected from the first surface 11 of the semiconductor substrate 10, especially for obliquely incident and scattered light. A larger surface area provides more capture sites, further improving light capture efficiency. On the other hand, the increased surface area, combined with the rough structure of the first textured surface 111 and the second textured surface 113, and the three-dimensional morphology formed by the first protrusion 114 and the first groove 112, can further extend the propagation path and reflection times of light on the first surface 11 of the semiconductor substrate 10. This increases the residence time of light within the semiconductor substrate 10, allowing more photons to be absorbed and converted into charge carriers, effectively reducing light transmission loss. Especially for long-wavelength light that is difficult for thin semiconductor substrates 10 to absorb, the extended optical path makes it easier for the semiconductor substrate 10 to capture it, reducing energy waste of long-wavelength light. Furthermore, the three-dimensional structure resulting from the height difference allows the textured and inclined surfaces in different regions to form complementary light absorption angles. Regardless of the direction of incident light, multi-angle reflection and absorption can be achieved through surface structures of different heights, avoiding the absorption blind zone of a single plane or textured surface of the same height at a specific incident angle, significantly widening the effective absorption angle range of light. Furthermore, there is a height difference between the bottom surfaces of the first region 11a and the first groove 112, which means that the local thickness of the semiconductor substrate 10 is reduced, thereby reducing the overall average thickness of the semiconductor substrate 10. This avoids the problems of easy bending and processing damage of thin substrates, and also increases the open-circuit voltage of the semiconductor substrate 10, which is beneficial to improving the photoelectric conversion efficiency.

[0091] The semiconductor substrate 10 provided in this application embodiment has at least a portion of the first surface 11 in the first region 11a as a first textured surface 111; the first surface 11 in the second region 11b is provided with alternating first grooves 112 and first protrusions 114 along the first direction X, at least a portion of the bottom surface of the first grooves 112 is a second textured surface 113; the first protrusions 114 include two interconnected first inclined surfaces 1141, the two first inclined surfaces 1141 are located on both sides of the first protrusions 114 along the first direction X; the first inclined surfaces 1141 are inclined toward the second region 11b away from the first region 11a. In this way, on the one hand, the first region 11a and the second region 11b, which are alternately arranged along the first direction X, can form a highly differentiated three-dimensional morphology. The first textured surface 111 of the first region 11a retains the basic absorption advantage of the traditional textured surface for perpendicularly incident light. On the other hand, the alternating first groove 112 and first protrusion 114 of the second region 11b further expand the spatial dimension of light absorption. The second textured surface 113 on the bottom surface of the first groove 112 and the first textured surface 111 of the first region 11a form a height difference, which not only significantly increases the effective surface area of ​​the light-receiving surface of the semiconductor substrate 10, allowing more incident light to come into contact with the substrate surface and reducing the probability of direct reflection and escape of light, but also forms a light trap through the first groove 112, causing the incident light to undergo multiple reflections within the first groove 112, thus extending the propagation path of light on the first surface 11 of the semiconductor substrate 10. Especially for obliquely incident light, the three-dimensional combination of the first protrusion 114 and the first groove 112 can effectively capture light that is difficult to receive by a traditional single textured surface, greatly improving the capture efficiency of light at different incident angles. On the other hand, the first inclined surfaces 1141 on both sides of the first protrusion 114, which are inclined towards the second region 11b away from the first region 11a, form complementary light reflection angles. This allows the incident light to be guided to the adjacent first textured surface 111 or the first groove 112 after being reflected by the first inclined surface 1141, avoiding ineffective light reflection and further improving light utilization. In addition, the synergistic effect of the multi-level textured surfaces (first textured surface 111, second textured surface 113), the first groove 112, and the first protrusion 114 can significantly extend the optical path of long-wavelength light inside the semiconductor substrate 10, allowing more long-wavelength photons to be absorbed by the semiconductor substrate 10 and converted into charge carriers, effectively reducing the transmission loss of long-wavelength light. Furthermore, the second textured surface 113 on the bottom surface of the first groove 112 and the first textured surface 111 in the first region 11a form a height difference, which can reduce the overall average thickness of the semiconductor substrate 10. This avoids the problems of easy bending and processing damage of thin substrates and increases the open-circuit voltage of the semiconductor substrate 10, which is beneficial to improving photoelectric conversion efficiency. In summary, this application can improve light utilization, increase short-circuit current and open-circuit voltage, thereby improving photoelectric conversion efficiency.

[0092] In one embodiment, see [reference] Figure 1As shown, the second textured surface 113 includes a plurality of second pyramids 1131; the ratio of the maximum dimension L1 of the first protrusion 114 along the first direction X to the maximum dimension L2 of the second pyramid 1131 along the first direction X is (3~15):1; the ratio of the dimension S1 of the first protrusion 114 along the second direction Z to the dimension S2 of the second pyramid 1131 along the second direction Z is (3~15):1; the second direction Z is perpendicular to the first direction X and parallel to the thickness direction of the semiconductor substrate 10.

[0093] In this way, the first protrusion 114 can form a macroscopic three-dimensional support structure, providing reasonable arrangement space for the second pyramid 1131. This not only widens the light capture angle through the first inclined surface 1141 of the first protrusion 114, but also increases the surface roughness, extends the optical path, and reduces reflection by using the microscopic second pyramid 1131. In addition, it can avoid the light absorption blind zone caused by the size conflict between the first protrusion 114 and the second pyramid 1131, ensuring that light rays with different incident angles can be fully captured by the microscopic second pyramid 1131 after being guided by the first inclined surface 1141 of the first protrusion 114. It also adapts to the carrier migration distance, reduces recombination loss, and maximizes the light absorption rate and carrier collection efficiency while ensuring the mechanical properties of the semiconductor substrate 10, thereby improving the photoelectric conversion efficiency.

[0094] In one embodiment, see [reference] Figure 1 As shown, the first textured surface 111 includes a plurality of first pyramids 1111; the ratio of the maximum dimension L1 of the first protrusion 114 along the first direction X to the maximum dimension L3 of the first pyramid 1111 along the first direction X is (3~15):1; the ratio of the dimension S1 of the first protrusion 114 along the second direction Z to the dimension S3 of the first pyramid 1111 along the second direction Z is (3~15):1; the second direction Z is perpendicular to the first direction X and parallel to the thickness direction of the semiconductor substrate 10.

[0095] In this way, the first convex portion 114 located in the second region 11b and the first pyramid 1111 located in the first region 11a can form a complementary structure, which not only avoids the light absorption blind zone caused by the cross-regional structural size conflict, but also widens the capture range of obliquely incident light through the first inclined surface 1141 of the first convex portion 114. At the same time, the rough appearance of the first pyramid 1111 extends the optical path, which can improve the light absorption efficiency at all angles, thereby helping to improve the photoelectric conversion efficiency.

[0096] In one embodiment, the roughness of the first inclined surface 1141 is less than the roughness of the bottom surface of the first groove 112, and the roughness of the first inclined surface 1141 is less than the roughness of the first surface 11 located in the first region 11a.

[0097] In other words, the overall smoothness of the first inclined surface 1141 is higher than that of the bottom surface of the first groove 112 and the smoothness of the first surface 11 located in the first region 11a. Of course, the first inclined surface 1141 may also have small protrusions or depressions, but it does not have a typical pyramid velvet surface structure.

[0098] Thus, by adopting a lower roughness for the first inclined surface 1141, ineffective scattering of incident light on the surface of the first protrusion 114 can be reduced, and more light can be reflected to the high-roughness first textured surface 111 or second textured surface 113 region, thereby improving the secondary capture efficiency of light. The high roughness design of the bottom surface of the first surface 11 and the first groove 112 in the first region 11a can extend the optical path and enhance light absorption. At the same time, the low-roughness first inclined surface 1141 can reduce the surface recombination center density and reduce carrier surface recombination loss. Under the premise of ensuring the all-angle light capture capability, the carrier transport characteristics are optimized, thereby improving the photoelectric conversion efficiency.

[0099] In one embodiment, see [reference] Figure 1 As shown, the first groove 112 is disposed adjacent to the first region 11a; the first groove 112 includes a second inclined surface 1121, which is inclined toward the second region 11b and close to the first region 11a; the second inclined surface 1121 connects the first pile surface 111 and the second pile surface 113; the first inclined surface 1141 connects the second pile surface 113.

[0100] Thus, the second inclined surface 1121 achieves a smooth transition between the first textured surface 111 and the second textured surface 113, and the first inclined surface 1141 is directly connected to the second textured surface 113, constructing a continuous and complementary light transmission path. The second inclined surface 1121 is tilted towards the second region 11b, closer to the first region 11a, which guides the incident light from the first region 11a and the reflected light from the first textured surface 111 to the second textured surface 113, avoiding the formation of a light absorption blind zone in the cross-region structure. The connection between the first inclined surface 1141 and the second textured surface 113 further guides the obliquely incident light to undergo multiple reflections within the first groove 112, extending the optical path and thus improving the light absorption rate. Furthermore, the continuous inclined surface transition reduces surface stress concentration, improves the structural stability of the semiconductor substrate 10, optimizes the carrier migration path, reduces cross-region transport recombination losses, ensures carrier collection efficiency, and improves photoelectric conversion efficiency.

[0101] In one embodiment, the roughness of the second inclined surface 1121 is less than the roughness of the bottom surface of the first groove 112, and the roughness of the second inclined surface 1121 is less than the roughness of the first surface 11 located in the first region 11a.

[0102] In other words, the overall smoothness of the second inclined surface 1121 is higher than that of the bottom surface of the first groove 112 and the first surface 11 located in the first region 11a. Of course, the second inclined surface 1121 may also have small protrusions or depressions, but it does not have a typical pyramid velvet surface structure.

[0103] Thus, the second inclined surface 1121 serves as a connecting channel between the first textured surface 111 and the second textured surface 113. Its lower roughness reduces ineffective scattering of light on the second inclined surface 1121, efficiently guiding the incident light from the first region 11a and the reflected light from the first textured surface 111 to the high-roughness second textured surface 113, thereby improving the directional transmission and secondary capture efficiency of light. Meanwhile, the high roughness of the first surface 11 and the bottom surface of the first groove 112 in the first region 11a ensures optical path extension and enhanced light absorption. At the same time, the low-roughness second inclined surface 1121 reduces the density of surface recombination centers, reducing surface recombination losses during carrier cross-regional transport. In this way, while avoiding light absorption blind zones, the efficiency of light utilization and carrier collection is optimized, which is beneficial to improving photoelectric conversion efficiency.

[0104] In one embodiment, see [reference] Figure 2 As shown, a second groove 115 is provided on the first surface 11 of the first region 11a; the bottom surface of the second groove 115 is a first velvet surface 111; the second groove 115 is disposed adjacent to the first protrusion 114; the first inclined surface 1141 disposed adjacent to the second groove 115 is connected to the first velvet surface 111; the first inclined surface 1141 disposed adjacent to the first groove 112 is connected to the second velvet surface 113.

[0105] Thus, the first textured surface 111 of the second groove 115 and the second textured surface 113 of the first groove 112 form a multi-level light-harvesting unit. Combined with the directional reflection effect of the first inclined surface 1141, the incident light is reflected multiple times between the first groove 112 and the first protrusion 114 and between the second groove 115 and the first protrusion 114, extending the optical path and avoiding absorption blind zones. At the same time, the alternating arrangement of the first groove 112, the second groove 115 and the first protrusion 114 optimizes the surface stress distribution of the semiconductor substrate 10, improves structural stability, and the direct connection between the first inclined surface 1141 and the first textured surface 111, as well as the first inclined surface 1141 and the second textured surface 113, can shorten the carrier migration path and reduce cross-region recombination losses. In this way, while enhancing light absorption, the carrier collection efficiency can be guaranteed, effectively improving the photoelectric conversion efficiency. In addition, by having the first surface 11 in the first region 11a have a second groove 115 and the first surface 11 in the second region 11b have a first groove 112 and a first protrusion 114, the overall average thickness of the semiconductor substrate 10 can be further reduced, and the open-circuit voltage of the semiconductor substrate 10 can be further increased, which is beneficial to improving the photoelectric conversion efficiency.

[0106] In one embodiment, see [reference] Figure 6 and Figure 7 As shown, the first protrusion 114 has a mesh structure perpendicular to the second direction Z; the second direction Z is parallel to the thickness direction of the semiconductor substrate 10.

[0107] In other words, the first protrusion 114 has a mesh structure on the plane of the semiconductor substrate 10. This allows the construction of a three-dimensional light-catching framework, which enables the incident light to be reflected and refracted multiple times in the mesh gaps in different directions, significantly extending the optical path and improving the light-catching efficiency, especially improving the catching efficiency of obliquely incident light and long-wavelength light, thereby increasing the light absorption rate and photoelectric conversion efficiency.

[0108] In one embodiment, see [reference] Figure 6 and Figure 7 As shown, the first region 11a has a mesh structure perpendicular to the second direction Z; the second direction Z is parallel to the thickness direction of the semiconductor substrate 10.

[0109] It should be noted that the first region 11a includes at least the area where the electrode's orthogonal projection onto the semiconductor substrate 10 is located. That is, the area of ​​the electrode's orthogonal projection onto the semiconductor substrate 10 is less than or equal to the area of ​​the first region 11a.

[0110] In one embodiment, see [reference] Figure 4 As shown, the size L4 of the first region 11a along the first direction X is 80 micrometers to 300 micrometers.

[0111] In this way, the size of the first region 11a along the first direction X can be large, which can be greater than the line width of the electrode, thus facilitating the alignment and fabrication of the electrode.

[0112] In one embodiment, see [reference] Figure 4 As shown, the dimension S4 of the first groove 112 along the second direction Z is 5 micrometers to 30 micrometers. That is, the groove depth of the first groove 112 is 5 micrometers to 30 micrometers.

[0113] Thus, by making the size of the first groove 112 along the second direction Z from 5 micrometers to 30 micrometers, the depth of the first groove 112 can be used to construct an effective light trap, extend the reflection path of the incident light in the first groove 112, enhance the capture efficiency of long-wavelength light and obliquely incident light, and make up for the defect of insufficient long-wavelength absorption of the thin semiconductor substrate 10. At the same time, it can avoid the problems of the semiconductor substrate 10 decreasing mechanical strength and increasing processing difficulty due to excessive groove depth, or the inability to form an effective optical path due to insufficient groove depth.

[0114] It should be noted that the dimension S4 of the first groove 112 along the second direction Z can be understood as the distance between the first surface 11 of the first region 11a and the bottom surface of the first groove 112. In other words, the dimension S4 of the first groove 112 along the second direction Z can be understood as the distance between the top of the first pyramid 1111 of the first velvet surface 111 in the first region 11a and the top of the second pyramid 1131 of the second velvet surface 113.

[0115] In one embodiment, see [reference] Figure 3 As shown, the second surface 12 includes a third region 12a and a fourth region 12b arranged alternately along the first direction X; the roughness of the third region 12a is greater than that of the fourth region 12b.

[0116] Understandably, the third region 12a includes at least the area where the electrode is projected onto the semiconductor substrate 10. The area on the second surface 12 other than the third region 12a is the fourth region 12b. The area of ​​the third region 12a is greater than or equal to the area of ​​the electrode projected onto the semiconductor substrate 10.

[0117] The second surface 12 is a backlight surface, which is usually a polished surface. Polishing is beneficial for the uniformity of the deposition thickness of subsequent film layers. However, due to the high flatness of the polished surface, the adhesion between the electrode and the semiconductor substrate 10 is easily poor, resulting in increased contact resistance. Based on this, in this embodiment, by making the roughness of the third region 12a greater than that of the fourth region 12b, that is, by differentiating the flatness of the third region 12a and the fourth region 12b, the surface area of ​​the third region 12a is increased. This increases the adhesion area of ​​the paste, improves the adhesion between the electrode and the semiconductor substrate 10, and thus reduces the contact resistance, which is beneficial for improving the photoelectric conversion efficiency.

[0118] In one embodiment, see [reference] Figure 3 , Figure 8 and Figure 10 As shown, the second surface 12 in the third region 12a is provided with a plurality of second protrusions 121; a third groove 122 is defined between adjacent second protrusions 121; the second protrusion 121 includes a first plane 1211 and a third inclined surface 1212 connecting the bottom surface of the third groove 122 and the first plane 1211; the second surface 12 in the fourth region 12b is provided with a plurality of third protrusions 123, and a fourth groove 124 is defined between adjacent third protrusions 123; the third protrusion 123 includes a second plane 1231 and a fourth inclined surface 1232 connecting the bottom surface of the fourth groove 124 and the second plane 1231; the outer perimeter of the first plane 1211 is smaller than the outer perimeter of the second plane 1231.

[0119] In other words, the second surface 12 located in the third region 12a has a plurality of small and dense second protrusions 121, and the second surface 12 located in the fourth region 12b has a plurality of large and sparse third protrusions 123. In this way, on the one hand, the surface area and roughness of the third region 12a can be further increased, the adhesion and mechanical interlocking force of the electrode paste can be strengthened, and the contact resistance can be significantly reduced; on the other hand, the roughness of the fourth region 12b can be moderately increased while retaining the characteristics of the polished surface, so as to ensure the uniformity of film deposition and the adhesion of the film layer in the fourth region 12b.

[0120] In one embodiment, the outer perimeter of the first plane 1211 is 4 micrometers to 40 micrometers; the outer perimeter of the second plane 1231 is 40 micrometers to 300 micrometers.

[0121] Furthermore, the outer perimeter of the first plane 1211 can be any value between 4 micrometers, 10 micrometers, 15 micrometers, 20 micrometers, 25 micrometers, 30 micrometers, 35 micrometers, 40 micrometers, or 4 micrometers.

[0122] Furthermore, the outer perimeter of the second plane 1231 can be any value between 40 micrometers, 60 micrometers, 80 micrometers, 100 micrometers, 120 micrometers, 140 micrometers, 160 micrometers, 180 micrometers, 200 micrometers, 220 micrometers, 240 micrometers, 260 micrometers, 280 micrometers, 300 micrometers, or between 40 micrometers and 300 micrometers.

[0123] In one embodiment, see [reference] Figure 3 and Figure 9 As shown, the acute angle α between the fourth inclined plane 1232 and the second plane 1231 is 0 degrees to 23 degrees.

[0124] Thus, by limiting the acute angle α between the fourth inclined surface 1232 and the second plane 1231 to the above-mentioned range, the roughness of the fourth region 12b can be improved, enhancing the adhesion and mechanical interlocking force of the electrode paste. At the same time, the excessive angle can be avoided, which would cause severe surface undulations, ensuring uniform and undamaged coverage of the subsequent film layer and guaranteeing the passivation effect.

[0125] In one embodiment, see [reference] Figure 3 and Figure 11 As shown, the acute angle β between the third inclined plane 1212 and the first plane 1211 is 24 degrees to 54 degrees.

[0126] Thus, this angle range creates a moderately inclined three-dimensional structure on the third inclined surface 1212, which significantly increases the surface area and roughness of the third region 12a, strengthens the mechanical bonding force of the electrode paste, and solves the problem of poor adhesion on the polished surface, while avoiding excessive surface undulation caused by an excessively large angle. In addition, the moderately inclined third inclined surface 1212 ensures uniform coverage of the subsequent film layer and smooth paste filling, avoiding film damage or poor contact. Combined with the local flatness of the first plane 1211, it improves the reliability of electrode bonding, reduces contact resistance, ensures stable passivation effect, reduces surface recombination loss, and is conducive to optimizing photoelectric conversion efficiency.

[0127] In one embodiment, see [reference] Figure 4 As shown, in the direction perpendicular to the second direction Z, the first groove 112 and the second protrusion 121 at least partially overlap; the second direction Z is parallel to the thickness direction of the semiconductor substrate 10.

[0128] Thus, the overlap of the first groove 112 and the second protrusion 121 can strengthen the local structural support of the substrate and avoid insufficient strength of the thin semiconductor substrate 10 due to the double-sided groove. In addition, the overlap of the first groove 112 and the second protrusion 121 can form a three-dimensional through light transmission path, extend the reflection path of light inside the semiconductor substrate 10, and improve the light absorption efficiency.

[0129] In one embodiment, see [reference] Figure 4 As shown, in the direction perpendicular to the second direction Z, the first protrusion 114 and the third groove 122 at least partially overlap; the second direction Z is parallel to the thickness direction of the semiconductor substrate 10.

[0130] Thus, the overlap of the first protrusion 114 and the third groove 122 can strengthen the local structural support of the substrate and avoid insufficient strength of the thin semiconductor substrate 10 due to the double-sided groove; the overlap of the first protrusion 114 and the third groove 122 can form a three-dimensional through light transmission path, extend the reflection path of light inside the semiconductor substrate 10, and improve the light absorption efficiency.

[0131] In one embodiment, see [reference] Figure 4 As shown, in the direction perpendicular to the second direction Z, the first groove 112 and the third protrusion 123 at least partially overlap; the second direction Z is parallel to the thickness direction of the semiconductor substrate 10.

[0132] Thus, by making the first groove 112 and the third protrusion 123 at least partially overlap in the direction perpendicular to the second direction Z, the third protrusion 123 strengthens the local mechanical support of the substrate, avoiding insufficient strength of the thin substrate due to double-sided concavity, and the three-dimensional combination of the first groove 112 and the third protrusion 123 extends the reflection path of light inside the substrate, thereby improving the light absorption efficiency.

[0133] In one embodiment, see [reference] Figure 5 As shown, in the direction perpendicular to the second direction Z, the first protrusion 114 and the fourth groove 124 at least partially overlap; the second direction Z is parallel to the thickness direction of the semiconductor substrate 10.

[0134] Thus, by making the first protrusion 114 and the fourth groove 124 at least partially overlap in the direction perpendicular to the second direction Z, the first protrusion 114 strengthens the local mechanical support of the substrate, avoiding insufficient strength of the thin substrate due to double-sided concavity, and the three-dimensional combination of the first protrusion 114 and the fourth groove 124 extends the reflection path of light inside the substrate, thereby improving the light absorption efficiency.

[0135] In one embodiment, see [reference] Figure 5 As shown, in the direction perpendicular to the second direction Z, the second groove 115 and the second protrusion 121 at least partially overlap, and the second direction Z is parallel to the thickness direction of the semiconductor substrate 10.

[0136] Thus, the complementary support structure formed by the overlapping areas can balance the internal stress of the semiconductor substrate 10, avoid the mechanical weakness caused by local depressions in the thin substrate, and improve the bending resistance during processing and use.

[0137] In one embodiment, see [reference] Figure 5 As shown, in a direction perpendicular to the second direction Z, the second groove 115 and the third protrusion 123 at least partially overlap, and the second direction Z is parallel to the thickness direction of the semiconductor substrate 10.

[0138] Thus, the complementary support structure formed by the overlapping areas can balance the internal stress of the semiconductor substrate 10, avoid the mechanical weakness caused by local depressions in the thin substrate, and improve the bending resistance during processing and use.

[0139] Secondly, see Figure 12 As shown, this application embodiment provides a method for fabricating a semiconductor substrate 10, including:

[0140] S10. A semiconductor substrate 10 is provided. The semiconductor substrate 10 includes a first surface 11 and a second surface 12 disposed opposite to each other. The first surface 11 has a first region 11a and a second region 11b arranged alternately along a first direction X.

[0141] S20. A first mask layer is formed on the first surface 11, and the first surface 11 is etched based on the first mask layer, so that the first surface 11 located in the second region 11b has a first groove 112 and a first protrusion 114 arranged alternately along the first direction X.

[0142] Specifically, the first mask layer may include at least one of silicon oxynitride, silicon nitride, and silicon oxide; the first mask layer may be a single-layer structure or a stacked structure.

[0143] S30, Remove the first mask layer;

[0144] S40. The bottom surfaces of the first surface 11 and the first groove 112 are velveted, such that at least a portion of the first surface 11 located in the first region 11a is a first velvet surface 111 and at least a portion of the bottom surface of the first groove 112 is a second velvet surface 113, such that the first protrusion 114 includes two interconnected first inclined surfaces 1141, the two first inclined surfaces 1141 being located on both sides of the first protrusion 114 along the first direction X; the first inclined surfaces 1141 are inclined toward the second region 11b in a direction away from the first region 11a.

[0145] The method for fabricating a semiconductor substrate 10 provided in this application embodiment involves forming a first mask layer on a first surface 11 and etching the first surface 11 based on the first mask layer, such that the first surface 11 located in the second region 11b has first grooves 112 and first protrusions 114 alternately arranged along the first direction X. The first mask layer is then removed, and the bottom surfaces of the first surface 11 and the first grooves 112 are texturized, such that at least a portion of the first surface 11 located in the first region 11a is a first textured surface 111 and at least a portion of the bottom surface of the first grooves 112 is a second textured surface 113. The first protrusion 114 includes two interconnected first inclined surfaces 1141, which are located on both sides of the first protrusion 114 along the first direction X. The first inclined surfaces 1141 are inclined toward the second region 11b in a direction away from the first region 11a. In this way, on the one hand, the first region 11a and the second region 11b, which are alternately arranged along the first direction X, can form a highly differentiated three-dimensional morphology. The first textured surface 111 of the first region 11a retains the basic absorption advantage of the traditional textured surface for perpendicularly incident light. On the other hand, the alternating first groove 112 and first protrusion 114 of the second region 11b further expand the spatial dimension of light absorption. The second textured surface 113 on the bottom surface of the first groove 112 and the first textured surface 111 of the first region 11a form a height difference, which not only significantly increases the effective surface area of ​​the light-receiving surface of the semiconductor substrate 10, allowing more incident light to come into contact with the substrate surface and reducing the probability of direct reflection and escape of light, but also forms a light trap through the first groove 112, causing the incident light to undergo multiple reflections within the first groove 112, thus extending the propagation path of light on the first surface 11 of the semiconductor substrate 10. Especially for obliquely incident light, the three-dimensional combination of the first protrusion 114 and the first groove 112 can effectively capture light that is difficult to receive by a traditional single textured surface, greatly improving the capture efficiency of light at different incident angles. On the other hand, the first inclined surfaces 1141 on both sides of the first protrusion 114, which are inclined towards the second region 11b away from the first region 11a, form complementary light reflection angles. This allows the incident light to be guided to the adjacent first textured surface 111 or the first groove 112 after being reflected by the first inclined surface 1141, avoiding ineffective light reflection and further improving light utilization. In addition, the synergistic effect of the multi-level textured surfaces (first textured surface 111, second textured surface 113), the first groove 112, and the first protrusion 114 can significantly extend the optical path of long-wavelength light inside the semiconductor substrate 10, allowing more long-wavelength photons to be absorbed by the semiconductor substrate 10 and converted into charge carriers, effectively reducing the transmission loss of long-wavelength light. Furthermore, the second textured surface 113 on the bottom surface of the first groove 112 and the first textured surface 111 in the first region 11a form a height difference, which can reduce the overall average thickness of the semiconductor substrate 10. This avoids the problems of easy bending and processing damage of thin substrates and increases the open-circuit voltage of the semiconductor substrate 10, which is beneficial to improving photoelectric conversion efficiency.

[0146] In one embodiment, S20, a first mask layer is formed on the first surface 11, and the first surface 11 is etched based on the first mask layer, such that the first surface 11 located in the second region 11b has first grooves 112 and first protrusions 114 alternately arranged along the first direction X, specifically including:

[0147] A first mask layer is formed on the first surface 11. The first mask layer includes a plurality of first openings extending along the thickness direction of the first mask layer. The plurality of first openings are located in the second region 11b perpendicular to the second direction Z. The second direction Z is parallel to the thickness direction of the semiconductor substrate 10.

[0148] Specifically, a laser can be used to create grooves in the first mask layer, such that the first mask layer includes a plurality of first openings extending along the thickness direction of the first mask layer.

[0149] The first surface 11 exposed by multiple first openings is etched so that the first surface 11 located in the second region 11b has first grooves 112 and first protrusions 114 arranged alternately along the first direction X.

[0150] This creates a height difference between the first surface 11 in the first region 11a and the bottom surface of the first groove 112 in the second region 11b. This significantly increases the effective surface area of ​​the first surface 11 of the semiconductor substrate 10, allowing more incident light to contact the substrate surface and reducing the probability of direct light reflection and escape. Furthermore, the first groove 112 forms a light trap, causing multiple reflections of the incident light within it, thus extending the propagation path of the light on the first surface 11 of the semiconductor substrate 10. Especially for obliquely incident light, the three-dimensional combination of the first protrusion 114 and the first groove 112 effectively captures light that is difficult to receive with a traditional single-height textured surface, greatly improving the capture efficiency of light at different incident angles. In addition, it reduces the overall average thickness of the semiconductor substrate 10, thus avoiding the problems of easy bending and processing damage of thin substrates, and increasing the open-circuit voltage of the semiconductor substrate 10, which is beneficial for improving photoelectric conversion efficiency.

[0151] In one embodiment, S20, a first mask layer is formed on the first surface 11, and the first surface 11 is etched based on the first mask layer, such that the first surface 11 located in the second region 11b has first grooves 112 and first protrusions 114 alternately arranged along the first direction X, specifically including:

[0152] A first mask layer is formed on the first surface 11. The first mask layer includes a plurality of first openings and second openings that extend through the thickness direction of the first mask layer. The plurality of first openings are located in the second region 11b in a direction perpendicular to the second direction Z. The second openings are located in the first region 11a in a direction perpendicular to the second direction Z.

[0153] Specifically, a laser can be used to create grooves in the first mask layer, such that the first mask layer includes a plurality of first openings and second openings extending along the thickness direction of the first mask layer.

[0154] The first surface 11 exposed by the multiple first openings and second openings is etched such that the first surface 11 located in the second region 11b has a first groove 112 and a first protrusion 114 arranged alternately along the first direction X, and the first surface 11 located in the first region 11a has a second groove 115.

[0155] This allows for a further reduction in the overall average thickness of the semiconductor substrate 10, which in turn increases the open-circuit voltage of the semiconductor substrate 10, thus improving the photoelectric conversion efficiency.

[0156] In one embodiment, S40, the bottom surfaces of the first surface 11 and the first groove 112 are flocked, such that at least a portion of the first surface 11 located in the first region 11a is a first flocked surface 111 and at least a portion of the bottom surface of the first groove 112 is a second flocked surface 113, such that the first protrusion 114 includes two interconnected first inclined surfaces 1141, specifically including:

[0157] The bottom surface of the first groove 112 and the bottom surface of the second groove 115 are velvetted, such that at least a portion of the bottom surface of the first groove 112 is the second velvet surface 113 and the bottom surface of the second groove 115 is the first velvet surface 111, such that the first protrusion 114 includes two interconnected first inclined surfaces 1141.

[0158] Thus, the first textured surface 111 of the second groove 115 and the second textured surface 113 of the first groove 112 form a multi-level light-harvesting unit. Combined with the directional reflection effect of the first inclined surface 1141, the incident light is reflected multiple times between different grooves and protrusions, extending the optical path and avoiding absorption blind zones. At the same time, the alternating arrangement of the first groove 112, the second groove 115 and the first protrusion 114 optimizes the surface stress distribution of the semiconductor substrate 10 and improves structural stability. Furthermore, the direct connection between the first inclined surface 1141 and the first textured surface 111, as well as the first inclined surface 1141 and the second textured surface 113, can shorten the carrier migration path and reduce cross-region recombination losses. In this way, while enhancing light absorption, the carrier collection efficiency can be guaranteed, effectively improving the photoelectric conversion efficiency.

[0159] In one embodiment, S20, a first mask layer is formed on the first surface 11, and the first surface 11 is etched based on the first mask layer, such that the first surface 11 located in the second region 11b has first grooves 112 and first protrusions 114 alternately arranged along the first direction X, including...

[0160] The first surface 11 is etched using a first preset solution and based on a first mask layer for a first preset duration, such that the first surface 11 located in the second region 11b has first grooves 112 and first protrusions 114 arranged alternately along the first direction X; the first preset solution includes deionized water, alkaline solution and texturing additive; the first preset duration is 500 to 2000 seconds.

[0161] In other words, by using an alkaline solution and texturing additives to etch the first surface 11 based on the first mask layer and continuing for a first preset time, first grooves 112 and first protrusions 114 alternately arranged along the first direction X are formed on the first surface 11 located in the second region 11b. This creates a height difference between the bottom surfaces of the first surface 11 in the first region 11a and the first grooves 112 in the second region 11b. This not only significantly increases the effective surface area of ​​the light-receiving surface of the semiconductor substrate 10, allowing more incident light to contact the substrate surface and reducing the probability of direct light reflection and escape, but also... The groove 112 forms a light trap, causing the incident light to undergo multiple reflections within the first groove 112, thus extending the propagation path of the light on the first surface 11 of the semiconductor substrate 10. Especially for oblique incident light, the three-dimensional combination of the first protrusion 114 and the first groove 112 can effectively capture light that is difficult to receive by a traditional single textured surface, greatly improving the capture efficiency of light at different incident angles. In addition, it can reduce the overall average thickness of the semiconductor substrate 10, thus avoiding the problems of easy bending and processing damage of thin substrates, and increasing the open-circuit voltage of the semiconductor substrate 10, which is beneficial to improving the photoelectric conversion efficiency.

[0162] In one embodiment, the volume ratio of the alkaline solution in the first preset solution is 2% to 5%, and the volume ratio of the texturing additive is 0.2% to 0.6%.

[0163] Specifically, the alkaline solution can be a potassium hydroxide solution.

[0164] Thus, by keeping the volume ratio of the alkaline solution between 2% and 5%, a suitable etching rate can be provided, which can efficiently form the first groove 112 and the first protrusion 114 of the preset depth, while avoiding excessive etching and uncontrolled morphology due to excessive concentration, or low process efficiency due to excessively low concentration. By keeping the volume ratio of the texturing additive between 0.2% and 0.6%, the etching anisotropy can be controlled, promoting the formation of regular first inclined surfaces 1141 on both sides of the first protrusion 114, while inhibiting excessive corrosion of the sidewalls of the first groove 112, ensuring the stability of the height difference between the first region 11a and the second region 11b.

[0165] In one embodiment, S40, the bottom surfaces of the first surface 11 and the first groove 112 are flocked, such that at least a portion of the first surface 11 located in the first region 11a is a first flocked surface 111 and at least a portion of the bottom surface of the first groove 112 is a second flocked surface 113, such that the first protrusion 114 includes two interconnected first inclined surfaces 1141, specifically including:

[0166] The bottom surfaces of the first surface 11 and the first groove 112 are texturized using a second preset solution for a second preset duration, such that at least a portion of the first surface 11 located in the first region 11a is a first texturized surface 111 and at least a portion of the bottom surface of the first groove 112 is a second texturized surface 113; the first protrusion 114 includes two interconnected first inclined surfaces 1141; the second preset solution includes deionized water, an alkaline solution, and a texturizing additive; the second preset duration is 300 to 1000 seconds.

[0167] In other words, the bottom surfaces of the first surface 11 and the first groove 112 are texturized using an alkaline solution and a texturing additive for a second preset duration. This results in at least a portion of the first surface 11 located in the first region 11a being a first textured surface 111 and at least a portion of the bottom surface of the first groove 112 being a second textured surface 113. The first protrusion 114 includes two interconnected first inclined surfaces 1141. This increases the effective surface area of ​​the first surface 11 of the semiconductor substrate 10. On the one hand, this increases the probability of light contacting the first surface 11 of the semiconductor substrate 10, allowing more incident light to interact with the first textured surface 111, the second textured surface 113, or the first inclined surface 1141 of the first protrusion 114, thus reducing the proportion of light directly reflected from the first surface 11 of the semiconductor substrate 10. Especially for obliquely incident and scattered light, the increased surface area can provide more capture sites, further improving the light capture efficiency. On the other hand, the increased surface area, combined with the rough structure of the first textured surface 111 and the second textured surface 113, as well as the three-dimensional morphology formed by the first protrusion 114 and the first groove 112, can further extend the propagation path and reflection times of light on the first surface 11 of the semiconductor substrate 10, thereby extending the residence time of light inside the semiconductor substrate 10. This allows more photons to be absorbed by the semiconductor substrate 10 and converted into charge carriers, effectively reducing light transmission loss. Especially for long-wavelength light that is difficult for thin semiconductor substrates 10 to absorb, the extended optical path makes it easier for the semiconductor substrate 10 to capture it, reducing energy waste of long-wavelength light, improving light utilization, and enhancing photoelectric conversion efficiency.

[0168] In one embodiment, the volume ratio of the alkaline solution in the second preset solution is 0.2% to 2%, and the volume ratio of the texturing additive is 5% to 10%.

[0169] In other words, the alkaline solution has a lower concentration and the texturing additive has a higher concentration. The low-concentration alkaline solution can be used to gently etch and form the first textured surface 111 and the second textured surface 113, avoiding excessive roughness or structural damage caused by excessively high alkaline solution concentration, thus ensuring light absorption efficiency. The high-concentration texturing additive can enhance etching anisotropy, promote the formation of a regular inclined first slope 1141 in the first protrusion 114, and simultaneously control the uniformity of the size of the first pyramid 1111 of the first textured surface 111 and the second pyramid 1131 of the second textured surface 113. This allows the synergistic effect of the textured surface's reflectivity and the inclined surface's light guiding to be fully utilized, improving light capture efficiency and absorption rate, thereby helping to improve photoelectric conversion efficiency.

[0170] In one embodiment, see [reference] Figure 13 As shown, the second surface 12 includes a third region 12a and a fourth region 12b that are alternately arranged along the first direction X;

[0171] The method also includes:

[0172] S50, a second mask layer is formed on the first surface 11 and the second surface 12 respectively;

[0173] S60. A plurality of third openings are formed on the second mask layer located on the second surface 12, extending along the thickness direction of the second mask layer. The plurality of third openings are located within the third region 12a in a direction perpendicular to the second direction Z. The second direction Z is parallel to the thickness direction of the semiconductor substrate 10.

[0174] S70, The second surface 12 exposed by multiple third openings is velveted to obtain a fourth velvet surface including multiple fourth pyramids;

[0175] S80, Remove the second mask layer located on the second surface 12;

[0176] S90. Polish the second surface 12 and the fourth velvet surface so that the roughness of the third region 12a is greater than that of the fourth region 12b.

[0177] S100, Remove the second mask layer located on the first surface 11.

[0178] In the above process, by texturing the second surface 12 exposed by multiple third openings, a fourth textured surface including multiple fourth pyramids is obtained; the second mask layer located on the second surface 12 is removed; then the second surface 12 and the fourth textured surface are polished so that the roughness of the third region 12a is greater than that of the fourth region 12b. In this way, the surface area of ​​the third region 12a can be increased, thereby increasing the adhesion area of ​​the slurry, improving the bonding force between the electrode and the semiconductor substrate 10, and thus reducing the contact resistance, which is beneficial to improving the photoelectric conversion efficiency.

[0179] In one embodiment, step S90, polishing the second surface 12 and the fourth textured surface to make the roughness of the third region 12a greater than the roughness of the fourth region 12b, further includes:

[0180] The second surface 12 and the fourth textured surface are polished using a third preset solution for a third preset duration, resulting in multiple second protrusions 121 on the second surface 12 located in the third region 12a and multiple third protrusions 123 on the second surface 12 located in the fourth region 12b. A third groove 122 is defined between adjacent second protrusions 121. The second protrusion 121 includes a first plane 1211 and a third inclined plane 1212 connecting the bottom surface of the third groove 122 and the first plane 1211. A fourth groove 124 is defined between adjacent third protrusions 123. The third protrusion 123 includes a second plane 1231 and a fourth inclined plane 1232 connecting the bottom surface of the fourth groove 124 and the second plane 1231. The outer perimeter of the first plane 1211 is smaller than the outer perimeter of the second plane 1231. The third preset solution includes deionized water, an alkaline solution, and additives. The third preset duration is 30 to 200 seconds.

[0181] Thus, by polishing the second surface 12 and the fourth textured surface with an alkaline solution and additives, the second surface 12 in the third region 12a has a plurality of small and dense second protrusions 121, and the second surface 12 in the fourth region 12b has a plurality of large and sparse third protrusions 123. In this way, on the one hand, the surface area and roughness of the third region 12a can be further increased, the adhesion and mechanical interlocking force of the electrode paste can be strengthened, and the contact resistance can be significantly reduced; on the other hand, the roughness of the fourth region 12b can be moderately increased while retaining the characteristics of the polished surface, so as to ensure the uniformity and adhesion of the subsequent film layer in the fourth region 12b.

[0182] In one embodiment, the volume ratio of the alkaline solution in the third preset solution is 0.6% to 2%, and the volume ratio of the additive is 0.2% to 2%.

[0183] Thus, an alkaline solution concentration of 0.6% to 2% can gently polish the fourth textured surface, transforming the fourth pyramid into a second convex portion 121 that combines the first plane 1211 and the third inclined plane 1212. This avoids excessive corrosion of the structure due to excessive concentration or affecting molding efficiency due to insufficient concentration. An additive concentration of 0.2% to 2% can regulate the anisotropy of polishing, ensuring the local flatness of the first plane 1211 and the smooth transition of the third inclined plane 1212. This ensures both the improvement of the roughness and surface area of ​​the third region 12a, strengthening the electrode bonding force to reduce contact resistance, and ensuring the uniformity of subsequent film deposition and passivation effect. Under the premise of balancing process controllability and structural precision, this is conducive to improving photoelectric conversion efficiency.

[0184] Thirdly, embodiments of this application provide a solar cell, including a semiconductor substrate 10 as described in any of the first aspects or a semiconductor substrate 10 prepared using any of the methods in the second aspect. This improves the light absorption rate of the solar cell, increases its short-circuit current and open-circuit voltage, thereby enhancing its photoelectric conversion efficiency.

[0185] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0186] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A semiconductor substrate, characterized in that, It includes a first surface and a second surface that are arranged opposite to each other, wherein the first surface includes a first area and a second area that are alternately arranged along a first direction; At least a portion of the first surface located in the first region is a first velvet surface; The first surface located in the second region is provided with a first groove and a first protrusion arranged alternately along the first direction; at least a portion of the bottom surface of the first groove is a second velvety surface; The first protrusion includes two interconnected first inclined surfaces, which are located on both sides of the first protrusion along the first direction; the first inclined surfaces are inclined toward the second region away from the first region.

2. The semiconductor substrate according to claim 1, characterized in that, The second velvet surface includes multiple second pyramids; The ratio of the maximum dimension L1 of the first protrusion along the first direction to the maximum dimension L2 of the second pyramid along the first direction is (3~15):1; The ratio of the dimension S1 of the first protrusion along the second direction to the dimension S2 of the second pyramid along the second direction is (3~15):1; the second direction is perpendicular to the first direction and parallel to the thickness direction of the semiconductor substrate.

3. The semiconductor substrate according to claim 1, characterized in that, The first velvet surface includes multiple first pyramids; The ratio of the maximum dimension L1 of the first protrusion along the first direction to the maximum dimension L3 of the first pyramid along the first direction is (3~15):1; The ratio of the dimension S1 of the first protrusion along the second direction to the dimension S3 of the first pyramid along the second direction is (3~15):1; the second direction is perpendicular to the first direction and parallel to the thickness direction of the semiconductor substrate.

4. The semiconductor substrate according to claim 1, characterized in that, The roughness of the first inclined surface is less than the roughness of the bottom surface of the first groove, and the roughness of the first inclined surface is less than the roughness of the first surface located in the first region.

5. The semiconductor substrate according to claim 2, characterized in that, The first groove is disposed adjacent to the first area; The first groove includes a second inclined surface, which is inclined toward the second region in a direction close to the first region; the second inclined surface connects the first pile surface and the second pile surface; the first inclined surface connects the second pile surface.

6. The semiconductor substrate according to claim 5, characterized in that, The roughness of the second inclined surface is less than the roughness of the bottom surface of the first groove, and the roughness of the second inclined surface is less than the roughness of the first surface located in the first region.

7. The semiconductor substrate according to claim 1, characterized in that, A second groove is provided on the first surface of the first area; the bottom surface of the second groove is the first velvet surface; The second groove is disposed adjacent to the first protrusion; the first inclined surface adjacent to the second groove is connected to the first velvet surface; the first inclined surface adjacent to the first groove is connected to the second velvet surface.

8. The semiconductor substrate according to any one of claims 1 to 7, characterized in that, The first protrusion has a mesh structure perpendicular to the second direction; and / or, The first region has a mesh structure perpendicular to the second direction; The second direction is parallel to the thickness direction of the semiconductor substrate.

9. The semiconductor substrate according to any one of claims 1 to 7, characterized in that, The dimension S4 of the first groove along the second direction is 5 micrometers to 30 micrometers; the second direction is parallel to the thickness direction of the semiconductor substrate; the first direction is perpendicular to the second direction; And / or, The dimension L4 of the first region along the first direction is 80 micrometers to 300 micrometers.

10. The semiconductor substrate according to claim 1, characterized in that, The second surface includes a third region and a fourth region that are alternately arranged along the first direction; the roughness of the third region is greater than that of the fourth region.

11. The semiconductor substrate according to claim 10, characterized in that, The second surface located in the third region is provided with a plurality of second protrusions; a third groove is defined between adjacent second protrusions; the second protrusion includes a first plane and a third inclined surface connecting the bottom surface of the third groove and the first plane; The second surface located in the fourth region is provided with a plurality of third protrusions, and a fourth groove is defined between adjacent third protrusions; the third protrusion includes a second plane and a fourth inclined surface connecting the bottom surface of the fourth groove and the second plane; the outer perimeter of the first plane is smaller than the outer perimeter of the second plane.

12. The semiconductor substrate according to claim 11, characterized in that, The outer perimeter of the first plane is 4 micrometers to 40 micrometers; The outer perimeter of the second plane is 40 micrometers to 300 micrometers.

13. The semiconductor substrate according to claim 11, characterized in that, The acute angle α between the fourth inclined plane and the second plane is between 0 degrees and 23 degrees.

14. The semiconductor substrate according to claim 11, characterized in that, The acute angle β between the third inclined plane and the first plane 1211 is 24 degrees to 54 degrees.

15. A method for preparing a semiconductor substrate, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a first surface and a second surface disposed opposite to each other, the first surface having a first region and a second region alternately arranged along a first direction; A first mask layer is formed on the first surface, and the first surface is etched based on the first mask layer, so that the first surface located in the second region is provided with a first groove and a first protrusion arranged alternately along the first direction; Remove the first mask layer; The bottom surface of the first surface and the first groove are velveted, such that at least a portion of the first surface in the first region is a first velvet surface and at least a portion of the bottom surface of the first groove is a second velvet surface, such that the first protrusion includes two interconnected first inclined surfaces, the two first inclined surfaces being located on both sides of the first protrusion along the first direction; the first inclined surfaces are inclined toward the second region away from the first region.

16. The method for preparing a semiconductor substrate according to claim 15, characterized in that, The step of forming a first mask layer on the first surface and etching the first surface based on the first mask layer, such that the first surface located in the second region has first grooves and first protrusions alternately arranged along the first direction, includes: A first mask layer is formed on the first surface, the first mask layer including a plurality of first openings extending along the thickness direction of the first mask layer; the plurality of first openings are located in the second region in a direction perpendicular to a second direction; the second direction is parallel to the thickness direction of the semiconductor substrate; The first surface exposed by the plurality of first openings is etched such that the first surface located in the second region has first grooves and first protrusions arranged alternately along the first direction.

17. The method for preparing a semiconductor substrate according to claim 15, characterized in that, The step of forming a first mask layer on the first surface and etching the first surface based on the first mask layer, such that the first surface located in the second region has first grooves and first protrusions alternately arranged along the first direction, includes: A first mask layer is formed on the first surface. The first mask layer includes a plurality of first openings and a second opening that extend along the thickness direction of the first mask layer. The plurality of first openings are located in the second region in a direction perpendicular to the second direction. The second openings are located in the first region in a direction perpendicular to the second direction. The first surfaces exposed by the plurality of first openings and second openings are etched such that the first surface located in the second region has first grooves and first protrusions arranged alternately along the first direction, and the first surface located in the first region has second grooves.

18. The method for preparing a semiconductor substrate according to claim 17, characterized in that, The step of forming a pile on the bottom surface of the first surface and the first groove, such that at least a portion of the first surface in the first region is a first pile surface and at least a portion of the bottom surface of the first groove is a second pile surface, and such that the first protrusion includes two interconnected first inclined surfaces, includes: The bottom surfaces of the first groove and the second groove are velvetted, such that at least a portion of the bottom surface of the first groove is the second velvet surface and the bottom surface of the second groove is the first velvet surface, such that the first protrusion includes two interconnected first inclined surfaces.

19. The method for preparing a semiconductor substrate according to claim 15, characterized in that, The step of forming a first mask layer on the first surface and etching the first surface based on the first mask layer, such that the first surface located in the second region has first grooves and first protrusions alternately arranged along the first direction, includes: The first surface is etched using a first preset solution and based on a first mask layer for a first preset duration, such that the first surface located in the second region has a first groove and a first protrusion arranged alternately along the first direction; the first preset solution includes deionized water, an alkaline solution and a texturing additive; the first preset duration is 500 to 2000 seconds.

20. The method for preparing a semiconductor substrate according to claim 19, characterized in that, In the first preset solution, the volume ratio of the alkaline solution is 2% to 5%; the volume ratio of the texturing additive is 0.2% to 0.6%.

21. The method for preparing a semiconductor substrate according to claim 15, characterized in that, The step of forming a pile on the bottom surface of the first surface and the first groove, such that at least a portion of the first surface in the first region is a first pile surface and at least a portion of the bottom surface of the first groove is a second pile surface, and such that the first protrusion includes two interconnected first inclined surfaces, includes: The first surface and the bottom surface of the first groove are texturized using a second preset solution for a second preset duration, such that at least a portion of the first surface in the first region is a first texturized surface and at least a portion of the bottom surface of the first groove is a second texturized surface; such that the first protrusion includes two interconnected first inclined surfaces; the second preset solution includes deionized water, an alkaline solution and a texturizing additive; the second preset duration is 300 to 1000 seconds.

22. The method for preparing a semiconductor substrate according to claim 21, characterized in that, In the second preset solution, the volume ratio of the alkaline solution is 0.2% to 2%; the volume ratio of the texturing additive is 5% to 10%.

23. The method for preparing a semiconductor substrate according to claim 15, characterized in that, The second surface includes a third region and a fourth region that are alternately arranged along the first direction; The method further includes: A second mask layer is formed on the first surface and the second surface respectively; A plurality of third openings are formed on the second mask layer located on the second surface, extending along the thickness direction of the second mask layer, and the plurality of third openings are located within the third region perpendicular to the second direction; the second direction is parallel to the thickness direction of the semiconductor substrate; The second surface exposed by the plurality of third openings is flocked to obtain a fourth flocked surface including a plurality of fourth pyramids; Remove the second mask layer located on the second surface; The second surface and the fourth textured surface are polished so that the roughness of the third region is greater than that of the fourth region; Remove the second mask layer located on the first surface.

24. The method for preparing a semiconductor substrate according to claim 23, characterized in that, The step of polishing the second surface and the fourth textured surface to make the roughness of the third region greater than that of the fourth region further includes: The second surface and the fourth textured surface are polished using a third preset solution for a third preset duration, resulting in a plurality of second protrusions on the second surface located in the third region and a plurality of third protrusions on the second surface located in the fourth region; a third groove is defined between adjacent second protrusions; each second protrusion includes a first plane and a third inclined surface connecting the bottom surface of the third groove and the first plane; a fourth groove is defined between adjacent third protrusions; each third protrusion includes a second plane and a fourth inclined surface connecting the bottom surface of the fourth groove and the second plane; The outer perimeter of the first plane is smaller than the outer perimeter of the second plane; the third preset solution includes deionized water, alkaline solution and additives; the third preset duration is 30 to 200 seconds.

25. The method for preparing a semiconductor substrate according to claim 24, characterized in that, In the third preset solution, the volume ratio of the alkaline solution is 0.6% to 2%; the volume ratio of the additive is 0.2% to 2%.

26. A solar cell, characterized in that, This includes a semiconductor substrate as described in any one of claims 1 to 14, or a semiconductor substrate prepared by the method described in any one of claims 15 to 25.

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